From 7466e2293c725d3a1e70bd410278865e896e8ca8 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Mon, 5 Sep 2022 11:24:03 +0200 Subject: [PATCH 001/635] samd/dma_manager: Add a DMA manager. Used for allocation of DMA channels. It will be needed for planned modules and methods like adc_timed(), dac_timed(), I2S. It includes management code for DMA IRQ handlers, similar to what was made for Sercom. Signed-off-by: robert-hh --- ports/samd/dma_manager.c | 131 +++++++++++++++++++++++++++++++++++++++ ports/samd/dma_manager.h | 39 ++++++++++++ ports/samd/samd_isr.c | 57 +++++++++++++++-- ports/samd/samd_soc.h | 1 + 4 files changed, 222 insertions(+), 6 deletions(-) create mode 100644 ports/samd/dma_manager.c create mode 100644 ports/samd/dma_manager.h diff --git a/ports/samd/dma_manager.c b/ports/samd/dma_manager.c new file mode 100644 index 00000000000..868606e66b7 --- /dev/null +++ b/ports/samd/dma_manager.c @@ -0,0 +1,131 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022 Robert Hammelrath + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "py/mpconfig.h" +#include "sam.h" +#include "dma_manager.h" +#include "samd_soc.h" + +// Set a number of dma channels managed here. samd21 has 21 dma channels, samd51 +// has 32 channels, as defined by the lib macro DMAC_CH_NUM. +// At first, we use a smaller number here to save RAM. May be increased as needed. + +#ifndef MICROPY_HW_DMA_CHANNELS +#if defined(MCU_SAMD21) +#define MICROPY_HW_DMA_CHANNELS 2 +#elif defined(MCU_SAMD51) +#define MICROPY_HW_DMA_CHANNELS 4 +#endif +#endif + +#if MICROPY_HW_DMA_CHANNELS > DMAC_CH_NUM +#error Number of DMA channels too large +#endif + +volatile DmacDescriptor dma_desc[MICROPY_HW_DMA_CHANNELS] __attribute__ ((aligned(16))); +static volatile DmacDescriptor dma_write_back[MICROPY_HW_DMA_CHANNELS] __attribute__ ((aligned(16))); + +// List of channel flags: true: channel used, false: channel available +static bool channel_list[MICROPY_HW_DMA_CHANNELS]; + +static bool dma_initialized = false; + +// allocate_channel(): retrieve an available channel. Return the number or -1 +int allocate_dma_channel(void) { + for (int i = 0; i < MP_ARRAY_SIZE(channel_list); i++) { + if (channel_list[i] == false) { // Channel available + channel_list[i] = true; + return i; + } + } + mp_raise_ValueError(MP_ERROR_TEXT("no dma channel available")); +} + +// free_channel(n): Declare channel as free +void free_dma_channel(int n) { + if (n >= 0 && n < MP_ARRAY_SIZE(channel_list)) { + channel_list[n] = false; + } +} + +void dma_init(void) { + if (!dma_initialized) { + + // Enable the DMA clock + #if defined(MCU_SAMD21) + PM->AHBMASK.reg |= PM_AHBMASK_DMAC; + PM->APBBMASK.reg |= PM_APBBMASK_DMAC; + #elif defined(MCU_SAMD51) + MCLK->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + #endif + // Setup the initial DMA configuration + DMAC->CTRL.reg = DMAC_CTRL_SWRST; + while (DMAC->CTRL.reg & DMAC_CTRL_SWRST) { + } + // Set the DMA descriptor pointers + DMAC->BASEADDR.reg = (uint32_t)dma_desc; + DMAC->WRBADDR.reg = (uint32_t)dma_write_back; + // Enable the DMA + DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf); + + dma_initialized = true; + } +} + +void dma_deinit(void) { + memset((uint8_t *)dma_desc, 0, sizeof(dma_desc)); + memset((uint8_t *)dma_write_back, 0, sizeof(dma_write_back)); + memset((uint8_t *)channel_list, 0, sizeof(channel_list)); + dma_initialized = false; + // Disable DMA + DMAC->CTRL.reg = 0; + for (int ch = 0; ch < DMAC_CH_NUM; ch++) { + dma_register_irq(ch, NULL); + } +} + +void dac_stop_dma(int dma_channel, bool wait) { + #if defined(MCU_SAMD21) + NVIC_DisableIRQ(DMAC_IRQn); + DMAC->CHID.reg = dma_channel; + DMAC->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_TERR | DMAC_CHINTENSET_SUSP; + DMAC->CHCTRLA.reg = 0; + while (wait && DMAC->CHCTRLA.bit.ENABLE) { + } + #elif defined(MCU_SAMD51) + if (0 <= dma_channel && dma_channel < 4) { + NVIC_DisableIRQ(DMAC_0_IRQn + dma_channel); + } else if (dma_channel >= 4) { + NVIC_DisableIRQ(DMAC_4_IRQn); + } + DMAC->Channel[dma_channel].CHINTENCLR.reg = + DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_TERR | DMAC_CHINTENSET_SUSP; + DMAC->Channel[dma_channel].CHCTRLA.reg = 0; + while (wait && DMAC->Channel[dma_channel].CHCTRLA.bit.ENABLE) { + } + #endif +} diff --git a/ports/samd/dma_manager.h b/ports/samd/dma_manager.h new file mode 100644 index 00000000000..9fd511e3ee2 --- /dev/null +++ b/ports/samd/dma_manager.h @@ -0,0 +1,39 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022 Robert Hammelrath + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_SAMD_DMACHANNEL_H +#define MICROPY_INCLUDED_SAMD_DMACHANNEL_H + +#include "py/runtime.h" + +extern volatile DmacDescriptor dma_desc[]; + +int allocate_dma_channel(void); +void free_dma_channel(int n); +void dma_init(void); +void dma_deinit(void); +void dac_stop_dma(int dma_channel, bool wait); + +#endif // MICROPY_INCLUDED_SAMD_DMACHANNEL_H diff --git a/ports/samd/samd_isr.c b/ports/samd/samd_isr.c index 7c4c1d060f7..6888d8a1dc6 100644 --- a/ports/samd/samd_isr.c +++ b/ports/samd/samd_isr.c @@ -164,6 +164,51 @@ void Sercom7_Handler(void) { } #endif +// DMAC IRQ handler support +#if defined(MCU_SAMD21) +#define DMAC_FIRST_CHANNEL 0 +#else +#define DMAC_FIRST_CHANNEL 4 +#endif + +void (*dma_irq_handler_table[DMAC_CH_NUM])(int num) = {}; + +void dma_register_irq(int dma_channel, void (*dma_irq_handler)) { + if (dma_channel < DMAC_CH_NUM) { + dma_irq_handler_table[dma_channel] = dma_irq_handler; + } +} + +void DMAC0_Handler(void) { + if (dma_irq_handler_table[0]) { + dma_irq_handler_table[0](0); + } +} +void DMAC1_Handler(void) { + if (dma_irq_handler_table[1]) { + dma_irq_handler_table[1](1); + } +} +void DMAC2_Handler(void) { + if (dma_irq_handler_table[2]) { + dma_irq_handler_table[2](2); + } +} +void DMAC3_Handler(void) { + if (dma_irq_handler_table[3]) { + dma_irq_handler_table[3](3); + } +} +void DMACn_Handler(void) { + for (uint32_t mask = 1 << DMAC_FIRST_CHANNEL, dma_channel = DMAC_FIRST_CHANNEL; + dma_channel < DMAC_CH_NUM; + mask <<= 1, dma_channel += 1) { + if ((DMAC->INTSTATUS.reg & mask) && dma_irq_handler_table[dma_channel]) { + dma_irq_handler_table[dma_channel](dma_channel); + } + } +} + #if defined(MCU_SAMD21) const ISR isr_vector[] __attribute__((section(".isr_vector"))) = { (ISR)&_estack, @@ -188,7 +233,7 @@ const ISR isr_vector[] __attribute__((section(".isr_vector"))) = { 0, // 3 Real-Time Counter (RTC) &EIC_Handler, // 4 External Interrupt Controller (EIC) 0, // 5 Non-Volatile Memory Controller (NVMCTRL) - 0, // 6 Direct Memory Access Controller (DMAC) + &DMACn_Handler, // 6 Direct Memory Access Controller (DMAC) USB_Handler_wrapper,// 7 Universal Serial Bus (USB) 0, // 8 Event System Interface (EVSYS) &Sercom0_Handler, // 9 Serial Communication Interface 0 (SERCOM0) @@ -261,11 +306,11 @@ const ISR isr_vector[] __attribute__((section(".isr_vector"))) = { 0, // 28 Frequency Meter (FREQM) 0, // 29 Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0 - _7 0, // 30 Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_8 - _10 - 0, // 31 Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 - 0, // 32 Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 - 0, // 33 Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 - 0, // 34 Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 - 0, // 35 Direct Memory Access Controller (DMAC): DMAC_SUSP_4 - _31, DMAC_TCMPL_4 _31, DMAC_TERR_4- _31 + &DMAC0_Handler, // 31 Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 + &DMAC1_Handler, // 32 Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 + &DMAC2_Handler, // 33 Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 + &DMAC3_Handler, // 34 Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 + &DMACn_Handler, // 35 Direct Memory Access Controller (DMAC): DMAC_SUSP_4 - _31, DMAC_TCMPL_4 _31, DMAC_TERR_4- _31 0, // 36 Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 0, // 37 Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 0, // 38 Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 diff --git a/ports/samd/samd_soc.h b/ports/samd/samd_soc.h index 707d2f8edfa..2477775735c 100644 --- a/ports/samd/samd_soc.h +++ b/ports/samd/samd_soc.h @@ -43,6 +43,7 @@ void USB_Handler_wrapper(void); void sercom_enable(Sercom *spi, int state); void sercom_register_irq(int sercom_id, void (*sercom_irq_handler)); +void dma_register_irq(int dma_channel, void (*dma_irq_handler)); // Each device has a unique 128-bit serial number. The uniqueness of the serial number is // guaranteed only when using all 128 bits. From 6853cfbcee5c1335e771f4ef4914306769ef6d47 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Mon, 5 Sep 2022 11:25:28 +0200 Subject: [PATCH 002/635] samd/tc_manager: Add a tc_manager function set. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These functions are use to allocate, free and configure a set of TC counter instances. The SAMxx MCU have between 3 to 5 (SAMD21) and 4 to 8 (SAMD51) TC instances. Two of them are used for the µs counter, the remaining 1 - 6 instances are administered here for use by various functions, like timed DMA transfers. Signed-off-by: robert-hh --- ports/samd/tc_manager.c | 178 ++++++++++++++++++++++++++++++++++++++++ ports/samd/tc_manager.h | 38 +++++++++ 2 files changed, 216 insertions(+) create mode 100644 ports/samd/tc_manager.c create mode 100644 ports/samd/tc_manager.h diff --git a/ports/samd/tc_manager.c b/ports/samd/tc_manager.c new file mode 100644 index 00000000000..10cad8060ae --- /dev/null +++ b/ports/samd/tc_manager.c @@ -0,0 +1,178 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022 Robert Hammelrath + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "py/mpconfig.h" +#include "sam.h" +#include "tc_manager.h" + +// List of channel flags: true: channel used, false: channel available +// Two Tc instances are used by the usec counter and cannot be assigned. +#if defined(MCU_SAMD21) +static bool instance_flag[TC_INST_NUM] = {false, true, true}; +#elif defined(MCU_SAMD51) +static bool instance_flag[TC_INST_NUM] = {true, true}; +#endif +Tc *tc_instance_list[TC_INST_NUM] = TC_INSTS; +extern const uint16_t prescaler_table[]; + +// allocate_tc_instance(): retrieve an available instance. Return the pointer or NULL +int allocate_tc_instance(void) { + for (int i = 0; i < MP_ARRAY_SIZE(instance_flag); i++) { + if (instance_flag[i] == false) { // available + instance_flag[i] = true; + return i; + } + } + mp_raise_ValueError(MP_ERROR_TEXT("no Timer available")); +} + +// free_tc_instance(n): Declare instance as free +void free_tc_instance(int tc_index) { + if (tc_index >= 0 && tc_index < MP_ARRAY_SIZE(instance_flag)) { + instance_flag[tc_index] = false; + } +} + +int configure_tc(int tc_index, int freq) { + uint32_t clock = DFLL48M_FREQ; // Use the fixed 48M clock + + Tc *tc; + if (tc_index < MP_ARRAY_SIZE(instance_flag)) { + tc = tc_instance_list[tc_index]; + } else { + return -1; + } + // Check for the right prescaler + uint8_t index; + uint32_t period; + + for (index = 0; index < 8; index++) { + period = clock / prescaler_table[index] / freq; + if (period < (1 << 16)) { + break; + } + } + + #if defined(MCU_SAMD21) + + // Set up the clocks + if (tc == TC3) { + PM->APBCMASK.bit.TC3_ = 1; // Enable TC3 clock + GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK5 | GCLK_CLKCTRL_ID_TCC2_TC3; + #if TC_INST_NUM > 3 + } else { + if (tc == TC6) { + PM->APBCMASK.bit.TC6_ = 1; // Enable TC6 clock + } else if (tc == TC7) { + PM->APBCMASK.bit.TC7_ = 1; // Enable TC7 clock + } + // Select multiplexer generic clock source and enable. + GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK5 | GCLK_CLKCTRL_ID_TC6_TC7; + #endif // TC_INST_NUM > 3 + } + // Wait while it updates synchronously. + while (GCLK->STATUS.bit.SYNCBUSY) { + } + // Configure the timer. + tc->COUNT16.CTRLA.reg = TC_CTRLA_SWRST; + while (tc->COUNT16.CTRLA.bit.SWRST || tc->COUNT16.STATUS.bit.SYNCBUSY) { + } + tc->COUNT16.CTRLA.reg = TC_CTRLA_PRESCALER(index) | + TC_CTRLA_MODE_COUNT16 | TC_CTRLA_RUNSTDBY | + TC_CTRLA_WAVEGEN_MFRQ; + tc->COUNT16.CC[0].reg = period; + + tc->COUNT16.CTRLA.bit.ENABLE = 1; + while (tc->COUNT16.STATUS.bit.SYNCBUSY) { + } + + #elif defined(MCU_SAMD51) + + int gclk_id = TC2_GCLK_ID; + // Enable MCLK + switch (tc_index) { + case 2: + MCLK->APBBMASK.bit.TC2_ = 1; // Enable TC2 clock + gclk_id = TC2_GCLK_ID; + break; + case 3: + MCLK->APBBMASK.bit.TC3_ = 1; // Enable TC3 clock + gclk_id = TC3_GCLK_ID; + break; + #if TC_INST_NUM > 4 + case 4: + MCLK->APBCMASK.bit.TC4_ = 1; // Enable TC4 clock + gclk_id = TC4_GCLK_ID; + break; + case 5: + MCLK->APBCMASK.bit.TC5_ = 1; // Enable TC5 clock + gclk_id = TC5_GCLK_ID; + break; + #if TC_INST_NUM > 6 + case 6: + MCLK->APBDMASK.bit.TC6_ = 1; // Enable TC6 clock + gclk_id = TC6_GCLK_ID; + break; + case 7: + MCLK->APBDMASK.bit.TC7_ = 1; // Enable TC7 clock + gclk_id = TC7_GCLK_ID; + break; + #endif // TC_INST_NUM > 6 + #endif // TC_INST_NUM > 4 + } + // Enable the 48Mhz clock. + GCLK->PCHCTRL[gclk_id].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN; + while (GCLK->PCHCTRL[gclk_id].bit.CHEN == 0) { + } + // Configure the timer. + tc->COUNT16.CTRLA.reg = TC_CTRLA_SWRST; + while (tc->COUNT16.SYNCBUSY.bit.SWRST) { + } + tc->COUNT16.CTRLA.reg = TC_CTRLA_PRESCALER(index) | + TC_CTRLA_MODE_COUNT16 | TC_CTRLA_RUNSTDBY | TC_CTRLA_PRESCSYNC_PRESC; + tc->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MFRQ; + tc->COUNT16.CC[0].reg = period; + tc->COUNT16.CTRLA.bit.ENABLE = 1; + while (tc->COUNT16.SYNCBUSY.bit.ENABLE) { + } + + #endif // SAMD21 or SAMD51 + + return 0; +} + +void tc_deinit(void) { + memset((uint8_t *)instance_flag, 0, sizeof(instance_flag)); + // The tc instances used by the us counter have to be locked. + // That's TC4 and TC5 for SAMD21 with the list starting at TC3 + // and TC0 and TC1 for SAMD51, with the list starting at TC0 + #if defined(MCU_SAMD21) + instance_flag[1] = instance_flag[2] = true; + #elif defined(MCU_SAMD51) + instance_flag[0] = instance_flag[1] = true; + #endif +} diff --git a/ports/samd/tc_manager.h b/ports/samd/tc_manager.h new file mode 100644 index 00000000000..9ab1af19b76 --- /dev/null +++ b/ports/samd/tc_manager.h @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022 Robert Hammelrath + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_SAMD_TCINSTANCE_H +#define MICROPY_INCLUDED_SAMD_TCINSTANCE_H + +#include "py/runtime.h" + +extern Tc *tc_instance_list[]; + +int allocate_tc_instance(void); +void free_tc_instance(int tc_index); +int configure_tc(int tc_index, int freq); +void tc_deinit(void); + +#endif // MICROPY_INCLUDED_SAMD_TCINSTANCE_H From f4b3b5802bfc3901630fb1e6c47bfc51152c45ea Mon Sep 17 00:00:00 2001 From: robert-hh Date: Mon, 5 Sep 2022 11:29:08 +0200 Subject: [PATCH 003/635] samd/machine_dac: Add dac.write_timed() method. Used as: dac.write_timed(data, freq [, count]) dac.deinit() Working range for dac_timed(): SAMD21: 1 Hz - 100 kHz (1 MHz clock, 10 bit) SAMD51: 1 Hz - ~500 kHz (8 MHz clock, 12 bit) The buffer has to be a byte array or a halfword array, and the data is sent once. The default for count is 1. If set to a value > 0, the data will be transmitted count times. If set to 0 or < 0, the date will be transmitted until deliberately stopped. The playback can be stopped with dac.deinit(). dac.deinit() just releases the timer and DMA channel needed by dac_timed(). The DAC object itself does not have to be released. Signed-off-by: robert-hh --- ports/samd/Makefile | 2 + ports/samd/machine_dac.c | 254 +++++++++++++++++++++++++++++---------- ports/samd/main.c | 4 + ports/samd/samd_soc.c | 1 - 4 files changed, 199 insertions(+), 62 deletions(-) diff --git a/ports/samd/Makefile b/ports/samd/Makefile index 813aed53678..150fc19958d 100644 --- a/ports/samd/Makefile +++ b/ports/samd/Makefile @@ -112,6 +112,7 @@ MPY_CROSS_FLAGS += -march=$(MPY_CROSS_MCU_ARCH) SRC_C += \ mcu/$(MCU_SERIES_LOWER)/clock_config.c \ + dma_manager.c \ help.c \ machine_bitstream.c \ machine_dac.c \ @@ -130,6 +131,7 @@ SRC_C += \ samd_soc.c \ samd_spiflash.c \ usbd.c \ + tc_manager.c \ SHARED_SRC_C += \ drivers/dht/dht.c \ diff --git a/ports/samd/machine_dac.c b/ports/samd/machine_dac.c index 7dcc654644d..ee49691e715 100644 --- a/ports/samd/machine_dac.c +++ b/ports/samd/machine_dac.c @@ -36,32 +36,41 @@ #include "sam.h" #include "pin_af.h" #include "modmachine.h" +#include "samd_soc.h" +#include "dma_manager.h" +#include "tc_manager.h" typedef struct _dac_obj_t { mp_obj_base_t base; uint8_t id; + bool initialized; mp_hal_pin_obj_t gpio_id; uint8_t vref; + int8_t dma_channel; + int8_t tc_index; + uint32_t count; } dac_obj_t; -static dac_obj_t dac_obj[] = { - #if defined(MCU_SAMD21) - {{&machine_dac_type}, 0, PIN_PA02}, - #elif defined(MCU_SAMD51) - {{&machine_dac_type}, 0, PIN_PA02}, - {{&machine_dac_type}, 1, PIN_PA05}, - #endif -}; Dac *const dac_bases[] = DAC_INSTS; +static void dac_init(dac_obj_t *self, Dac *dac); + #if defined(MCU_SAMD21) +static dac_obj_t dac_obj[] = { + {{&machine_dac_type}, 0, PIN_PA02}, +}; + #define MAX_DAC_VALUE (1023) #define DEFAULT_DAC_VREF (1) #define MAX_DAC_VREF (2) #elif defined(MCU_SAMD51) +static dac_obj_t dac_obj[] = { + {{&machine_dac_type}, 0, PIN_PA02}, + {{&machine_dac_type}, 1, PIN_PA05}, +}; // According to Errata 2.9.2, VDDANA as ref value is not available. However it worked // in tests. So I keep the selection here but set the default to Aref, which is usually // connected at the Board to VDDANA @@ -72,10 +81,36 @@ static uint8_t dac_vref_table[] = { #define MAX_DAC_VALUE (4095) #define DEFAULT_DAC_VREF (2) #define MAX_DAC_VREF (3) -static bool dac_init[2] = {false, false}; -#endif +#endif // defined SAMD21 or SAMD51 +void dac_irq_handler(int dma_channel) { + dac_obj_t *self; + + #if defined(MCU_SAMD21) + DMAC->CHID.reg = dma_channel; + DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; + self = &dac_obj[0]; + if (self->count > 1) { + self->count -= 1; + dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + } + + #elif defined(MCU_SAMD51) + DMAC->Channel[dma_channel].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; + if (dac_obj[0].dma_channel == dma_channel) { + self = &dac_obj[0]; + } else { + self = &dac_obj[1]; + } + if (self->count > 1) { + self->count -= 1; + dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + } + #endif +} static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { @@ -92,10 +127,10 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ uint8_t id = args[ARG_id].u_int; dac_obj_t *self = NULL; - if (0 <= id && id < MP_ARRAY_SIZE(dac_obj)) { + if (0 <= id && id <= MP_ARRAY_SIZE(dac_obj)) { self = &dac_obj[id]; } else { - mp_raise_ValueError(MP_ERROR_TEXT("invalid id for DAC")); + mp_raise_ValueError(MP_ERROR_TEXT("invalid Pin for DAC")); } uint8_t vref = args[ARG_vref].u_int; @@ -103,71 +138,57 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ self->vref = vref; } - Dac *dac = dac_bases[0]; // Just one DAC register block - - // initialize DAC + Dac *dac = dac_bases[0]; // Just one DAC + dac_init(self, dac); + // Set the port as given in self->gpio_id as DAC + mp_hal_set_pin_mux(self->gpio_id, ALT_FCT_DAC); - #if defined(MCU_SAMD21) + return MP_OBJ_FROM_PTR(self); +} - // Configuration SAMD21 - // Enable APBC clocks and PCHCTRL clocks; GCLK3 at 1 MHz - PM->APBCMASK.reg |= PM_APBCMASK_DAC; - GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_DAC; - while (GCLK->STATUS.bit.SYNCBUSY) { - } - // Reset DAC registers - dac->CTRLA.bit.SWRST = 1; - while (dac->CTRLA.bit.SWRST) { - } - dac->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL(self->vref); - // Enable DAC and wait to be ready - dac->CTRLA.bit.ENABLE = 1; - while (dac->STATUS.bit.SYNCBUSY) { - } +static void dac_init(dac_obj_t *self, Dac *dac) { + // Init DAC + if (self->initialized == false) { + #if defined(MCU_SAMD21) - #elif defined(MCU_SAMD51) + // Configuration SAMD21 + // Enable APBC clocks and PCHCTRL clocks; GCLK3 at 1 MHz + PM->APBCMASK.reg |= PM_APBCMASK_DAC; + GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_DAC; + while (GCLK->STATUS.bit.SYNCBUSY) { + } + // Reset DAC registers + dac->CTRLA.bit.SWRST = 1; + while (dac->CTRLA.bit.SWRST) { + } + dac->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL(self->vref); + // Enable DAC and wait to be ready + dac->CTRLA.bit.ENABLE = 1; + while (dac->STATUS.bit.SYNCBUSY) { + } - // Configuration SAMD51 - // Enable APBD clocks and PCHCTRL clocks; GCLK3 at 8 MHz + #elif defined(MCU_SAMD51) - if (!(dac_init[0] | dac_init[1])) { + // Configuration SAMD51 + // Enable APBD clocks and PCHCTRL clocks; GCLK3 at 8 MHz MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC; - GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | \ - GCLK_PCHCTRL_CHEN; + GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN; // Reset DAC registers dac->CTRLA.bit.SWRST = 1; while (dac->CTRLA.bit.SWRST) { } dac->CTRLB.reg = DAC_CTRLB_REFSEL(dac_vref_table[self->vref]); + dac->DACCTRL[self->id].reg = DAC_DACCTRL_ENABLE | DAC_DACCTRL_REFRESH(2) | DAC_DACCTRL_CCTRL_CC12M; - } - - // Modify DAC config - requires disabling see Section 47.6.2.3 of data sheet - if (!dac_init[self->id]) { - // Disable DAC and wait - dac->CTRLA.bit.ENABLE = 0; - while (dac->SYNCBUSY.bit.ENABLE) { - } - - // Modify configuration - dac->DACCTRL[self->id].reg = DAC_DACCTRL_ENABLE | \ - DAC_DACCTRL_REFRESH(2) | DAC_DACCTRL_CCTRL_CC12M; - dac->DATA[self->id].reg = 0; - dac_init[self->id] = true; - - // Enable DAC and wait + // Enable DAC and wait to be ready dac->CTRLA.bit.ENABLE = 1; while (dac->SYNCBUSY.bit.ENABLE) { } - } - #endif - - // Set the port as given in self->gpio_id as DAC - mp_hal_set_pin_mux(self->gpio_id, ALT_FCT_DAC); - - return MP_OBJ_FROM_PTR(self); + #endif // defined SAMD21 or SAMD51 + } + self->initialized = true; } static void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { @@ -177,14 +198,17 @@ static void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) { Dac *dac = dac_bases[0]; // Just one DAC + dac_obj_t *self = self_in; int value = mp_obj_get_int(value_in); + if (value < 0 || value > MAX_DAC_VALUE) { mp_raise_ValueError(MP_ERROR_TEXT("value out of range")); } + // Re-init, if required + dac_init(self, dac); #if defined(MCU_SAMD21) dac->DATA.reg = value; #elif defined(MCU_SAMD51) - dac_obj_t *self = self_in; dac->DATA[self->id].reg = value; #endif @@ -192,8 +216,116 @@ static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) { } MP_DEFINE_CONST_FUN_OBJ_2(dac_write_obj, dac_write); +static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) { + Dac *dac = dac_bases[0]; // Just one DAC used + dac_obj_t *self = args[0]; + mp_buffer_info_t src; + // Re-init, if required + dac_init(self, dac); + + mp_get_buffer_raise(args[1], &src, MP_BUFFER_READ); + if (n_args > 3) { + self->count = mp_obj_get_int(args[3]); + } else { + self->count = 1; + } + if (src.len >= 2) { + int freq = mp_obj_get_int(args[2]); + if (self->dma_channel == -1) { + self->dma_channel = allocate_dma_channel(); + dma_init(); + dma_register_irq(self->dma_channel, dac_irq_handler); + } + if (self->tc_index == -1) { + self->tc_index = allocate_tc_instance(); + } + // Configure TC; no need to check the return value + configure_tc(self->tc_index, freq); + // Configure DMA for halfword output to the DAC + #if defined(MCU_SAMD21) + + dma_desc[self->dma_channel].BTCTRL.reg = + DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT | + DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_SRCINC | DMAC_BTCTRL_STEPSEL | + DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val); + dma_desc[self->dma_channel].BTCNT.reg = src.len / 2; + dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(src.buf) + src.len; + dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(&dac->DATA.reg); + if (self->count >= 1) { + dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT + } else { + dma_desc[self->dma_channel].DESCADDR.reg = (uint32_t)(&dma_desc[self->dma_channel].BTCTRL.reg); + } + + DMAC->CHID.reg = self->dma_channel; + DMAC->CHCTRLA.reg = 0; + while (DMAC->CHCTRLA.bit.ENABLE) { + } + DMAC->CHCTRLB.reg = + DMAC_CHCTRLB_LVL(0) | + DMAC_CHCTRLB_TRIGACT_BEAT | + DMAC_CHCTRLB_TRIGSRC(TC3_DMAC_ID_OVF + 3 * self->tc_index); + DMAC->CHINTENSET.reg = DMAC_CHINTFLAG_TCMPL; + DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + + NVIC_EnableIRQ(DMAC_IRQn); + + #elif defined(MCU_SAMD51) + + dma_desc[self->dma_channel].BTCTRL.reg = + DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT | + DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_SRCINC | DMAC_BTCTRL_STEPSEL | + DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val); + dma_desc[self->dma_channel].BTCNT.reg = src.len / 2; + dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(src.buf) + src.len; + dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(&dac->DATA[self->id].reg); + if (self->count >= 1) { + dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT + } else { + dma_desc[self->dma_channel].DESCADDR.reg = (uint32_t)(&dma_desc[self->dma_channel].BTCTRL.reg); + } + + DMAC->Channel[self->dma_channel].CHCTRLA.reg = + DMAC_CHCTRLA_BURSTLEN(DMAC_CHCTRLA_BURSTLEN_SINGLE_Val) | + DMAC_CHCTRLA_TRIGACT(DMAC_CHCTRLA_TRIGACT_BURST_Val) | + DMAC_CHCTRLA_TRIGSRC(TC0_DMAC_ID_OVF + 3 * self->tc_index); + DMAC->Channel[self->dma_channel].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + + if (self->dma_channel < 4) { + NVIC_EnableIRQ(DMAC_0_IRQn + self->dma_channel); + } else { + NVIC_EnableIRQ(DMAC_4_IRQn); + } + + #endif // defined SAMD21 or SAMD51 + } + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(dac_write_timed_obj, 3, 4, dac_write_timed); + +static mp_obj_t dac_deinit(mp_obj_t self_in) { + dac_obj_t *self = self_in; + self->initialized = false; + // Reset the DAC to lower the current consumption as SAMD21 + dac_bases[0]->CTRLA.bit.SWRST = 1; + if (self->dma_channel >= 0) { + dac_stop_dma(self->dma_channel, true); + free_dma_channel(self->dma_channel); + self->dma_channel = -1; + } + if (self->tc_index >= 0) { + free_tc_instance(self->tc_index); + self->tc_index = -1; + } + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_1(dac_deinit_obj, dac_deinit); + static const mp_rom_map_elem_t dac_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) }, + { MP_ROM_QSTR(MP_QSTR_write_timed), MP_ROM_PTR(&dac_write_timed_obj) }, }; static MP_DEFINE_CONST_DICT(dac_locals_dict, dac_locals_dict_table); diff --git a/ports/samd/main.c b/ports/samd/main.c index d4e991033c4..9f95f6e2668 100644 --- a/ports/samd/main.c +++ b/ports/samd/main.c @@ -36,6 +36,8 @@ #include "shared/runtime/softtimer.h" #include "shared/tinyusb/mp_usbd.h" #include "clock_config.h" +#include "dma_manager.h" +#include "tc_manager.h" extern uint8_t _sstack, _estack, _sheap, _eheap; extern void adc_deinit_all(void); @@ -88,6 +90,8 @@ void samd_main(void) { soft_reset_exit: mp_printf(MP_PYTHON_PRINTER, "MPY: soft reboot\n"); + dma_deinit(); + tc_deinit(); #if MICROPY_PY_MACHINE_ADC adc_deinit_all(); #endif diff --git a/ports/samd/samd_soc.c b/ports/samd/samd_soc.c index 761eb8d1aae..bb7bc076aa9 100644 --- a/ports/samd/samd_soc.c +++ b/ports/samd/samd_soc.c @@ -69,7 +69,6 @@ static void usb_init(void) { void init_us_counter(void) { #if defined(MCU_SAMD21) - PM->APBCMASK.bit.TC3_ = 1; // Enable TC3 clock PM->APBCMASK.bit.TC4_ = 1; // Enable TC4 clock // Select multiplexer generic clock source and enable. GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_TC4_TC5; From 8b4dd110aad69a91a1dd852907370254aba181c6 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Tue, 6 Sep 2022 16:53:45 +0200 Subject: [PATCH 004/635] samd/machine_adc: Add adc.read_timed() method. Used as: adc.read_timed(buffer, freq) Buffer must be preallocated. The size determines the number of 16 bit words to be read. The numeric range of the results is that of the raw ADC. The call returns immediately, and the data transfer is done by DMA. The caller must wait sufficiently long until the data is sampled and can be noticed by a callback. No internal checks are made for a too-high freq value. Read speeds depends on Average and bit length setting: SAMD21: Max. 350kS/s (8 bit, Average 1) SAMD51: Max. 1 MS/s (8 bit, Average 1) Signed-off-by: robert-hh --- ports/samd/machine_adc.c | 147 ++++++++++++++++++++++++++++++++++++--- ports/samd/machine_dac.c | 2 +- ports/samd/tc_manager.c | 5 +- ports/samd/tc_manager.h | 2 +- 4 files changed, 144 insertions(+), 12 deletions(-) diff --git a/ports/samd/machine_adc.c b/ports/samd/machine_adc.c index 665af6f6f27..afd9c5d29a5 100644 --- a/ports/samd/machine_adc.c +++ b/ports/samd/machine_adc.c @@ -31,6 +31,10 @@ #include "py/mphal.h" #include "sam.h" #include "pin_af.h" +#include "modmachine.h" +#include "samd_soc.h" +#include "dma_manager.h" +#include "tc_manager.h" typedef struct _machine_adc_obj_t { mp_obj_base_t base; @@ -39,6 +43,8 @@ typedef struct _machine_adc_obj_t { uint8_t avg; uint8_t bits; uint8_t vref; + int8_t dma_channel; + int8_t tc_index; } machine_adc_obj_t; #define DEFAULT_ADC_BITS 12 @@ -85,6 +91,20 @@ static uint8_t resolution[] = { extern mp_int_t log2i(mp_int_t num); +// Active just for SAMD21, stops the freerun mode +// For SAMD51, just the INT flag is reset. +void adc_irq_handler(int dma_channel) { + + #if defined(MCU_SAMD21) + DMAC->CHID.reg = dma_channel; + DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; + ADC->EVCTRL.bit.STARTEI = 0; + + #elif defined(MCU_SAMD51) + DMAC->Channel[dma_channel].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; + #endif +} + static void mp_machine_adc_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { (void)kind; machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); @@ -116,8 +136,9 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args self->id = id; self->adc_config = adc_config; self->bits = DEFAULT_ADC_BITS; + uint16_t bits = args[ARG_bits].u_int; - if (bits >= 8 && bits <= 12) { + if (8 <= bits && bits <= 12) { self->bits = bits; } uint32_t avg = log2i(args[ARG_average].u_int); @@ -147,6 +168,14 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) { adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel; // set resolution. Scale 8-16 to 0 - 4 for table access. adc->CTRLB.bit.RESSEL = resolution[(self->bits - 8) / 2]; + + #if defined(MCU_SAMD21) + // Stop the ADC sampling by timer + adc->EVCTRL.bit.STARTEI = 0; + #elif defined(MCU_SAMD51) + // Do not restart ADC after data has bee read + adc->DSEQCTRL.reg = 0; + #endif // Measure input voltage adc->SWTRIG.bit.START = 1; while (adc->INTFLAG.bit.RESRDY == 0) { @@ -155,9 +184,107 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) { return adc->RESULT.reg * (65536 / (1 << self->bits)); } +static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t freq_in) { + machine_adc_obj_t *self = self_in; + Adc *adc = adc_bases[self->adc_config.device]; + mp_buffer_info_t src; + mp_get_buffer_raise(values, &src, MP_BUFFER_READ); + if (src.len >= 2) { + int freq = mp_obj_get_int(freq_in); + if (self->dma_channel == -1) { + self->dma_channel = allocate_dma_channel(); + dma_init(); + } + if (self->tc_index == -1) { + self->tc_index = allocate_tc_instance(); + } + // Set Input channel and resolution + // Select the pin as positive input and gnd as negative input reference, non-diff mode by default + adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel; + // set resolution. Scale 8-16 to 0 - 4 for table access. + adc->CTRLB.bit.RESSEL = resolution[(self->bits - 8) / 2]; + + // Configure DMA for halfword output to the DAC + #if defined(MCU_SAMD21) + // dma irq just for SAMD21 to stop the timer based acquisition + dma_register_irq(self->dma_channel, adc_irq_handler); + configure_tc(self->tc_index, freq, TC_EVCTRL_OVFEO); + // Enable APBC clock + PM->APBCMASK.reg |= PM_APBCMASK_EVSYS; + // Set up the EVSYS channel + EVSYS->CTRL.bit.SWRST = 1; + EVSYS->USER.reg = EVSYS_USER_CHANNEL(ADC_EVSYS_CHANNEL + 1) | + EVSYS_USER_USER(EVSYS_ID_USER_ADC_START); + EVSYS->CHANNEL.reg = EVSYS_CHANNEL_CHANNEL(ADC_EVSYS_CHANNEL) | + EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_TC3_OVF + 3 * self->tc_index) | + EVSYS_CHANNEL_PATH_ASYNCHRONOUS; + + dma_desc[self->dma_channel].BTCTRL.reg = + DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT | + DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC | DMAC_BTCTRL_STEPSEL | + DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val); + dma_desc[self->dma_channel].BTCNT.reg = src.len / 2; + dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(&adc->RESULT.reg); + dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(src.buf) + src.len; + dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT + DMAC->CHID.reg = self->dma_channel; + DMAC->CHCTRLA.reg = 0; + while (DMAC->CHCTRLA.bit.ENABLE) { + } + DMAC->CHCTRLB.reg = + DMAC_CHCTRLB_LVL(0) | + DMAC_CHCTRLB_TRIGACT_BEAT | + DMAC_CHCTRLB_TRIGSRC(ADC_DMAC_ID_RESRDY); + + DMAC->CHINTENSET.reg = DMAC_CHINTFLAG_TCMPL; + DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + + NVIC_EnableIRQ(DMAC_IRQn); + adc->EVCTRL.bit.STARTEI = 1; + + #elif defined(MCU_SAMD51) + configure_tc(self->tc_index, freq, 0); + + // Restart ADC after data has bee read + adc->DSEQCTRL.reg = ADC_DSEQCTRL_AUTOSTART; + // Start the first sampling to ensure we get a proper first value. + adc->SWTRIG.bit.START = 1; + while (adc->INTFLAG.bit.RESRDY == 0) { + } + + dma_desc[self->dma_channel].BTCTRL.reg = + DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT | + DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC | DMAC_BTCTRL_STEPSEL | + DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val); + dma_desc[self->dma_channel].BTCNT.reg = src.len / 2; + dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(&adc->RESULT.reg); + dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(src.buf) + src.len; + dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT + + DMAC->Channel[self->dma_channel].CHCTRLA.reg = + DMAC_CHCTRLA_BURSTLEN(DMAC_CHCTRLA_BURSTLEN_SINGLE_Val) | + DMAC_CHCTRLA_TRIGACT(DMAC_CHCTRLA_TRIGACT_BURST_Val) | + DMAC_CHCTRLA_TRIGSRC(TC0_DMAC_ID_OVF + 3 * self->tc_index); + DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + + #endif // defined SAMD21 or SAMD51 + + } + return mp_const_none; +} + // deinit() : release the ADC channel static void mp_machine_adc_deinit(machine_adc_obj_t *self) { busy_flags &= ~((1 << (self->adc_config.device * 16 + self->adc_config.channel))); + if (self->dma_channel >= 0) { + dac_stop_dma(self->dma_channel, true); + free_dma_channel(self->dma_channel); + self->dma_channel = -1; + } + if (self->tc_index >= 0) { + free_tc_instance(self->tc_index); + self->tc_index = -1; + } } void adc_deinit_all(void) { @@ -175,9 +302,9 @@ static void adc_init(machine_adc_obj_t *self) { #if defined(MCU_SAMD21) // Configuration SAMD21 - // Enable APBD clocks and PCHCTRL clocks; GCLK2 at 48 MHz + // Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz PM->APBCMASK.reg |= PM_APBCMASK_ADC; - GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | GCLK_CLKCTRL_ID_ADC; + GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK5 | GCLK_CLKCTRL_ID_ADC; while (GCLK->STATUS.bit.SYNCBUSY) { } // Reset ADC registers @@ -190,7 +317,7 @@ static void adc_init(machine_adc_obj_t *self) { linearity |= ((*((uint32_t *)ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5; /* Write the calibration data. */ ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity); - // Divide 48MHz clock by 32 to obtain 1.5 MHz clock to adc + // Divide a 48MHz clock by 32 to obtain 1.5 MHz clock to adc adc->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV32; // Select external AREFA as reference voltage. adc->REFCTRL.reg = adc_vref_table[self->vref]; @@ -203,12 +330,12 @@ static void adc_init(machine_adc_obj_t *self) { #elif defined(MCU_SAMD51) // Configuration SAMD51 - // Enable APBD clocks and PCHCTRL clocks; GCLK2 at 48 MHz + // Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz if (self->adc_config.device == 0) { - GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; + GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN; MCLK->APBDMASK.bit.ADC0_ = 1; } else { - GCLK->PCHCTRL[ADC1_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; + GCLK->PCHCTRL[ADC1_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN; MCLK->APBDMASK.bit.ADC1_ = 1; } // Reset ADC registers @@ -230,8 +357,10 @@ static void adc_init(machine_adc_obj_t *self) { } /* Write the calibration data. */ adc->CALIB.reg = ADC_CALIB_BIASCOMP(biascomp) | ADC_CALIB_BIASR2R(biasr2r) | ADC_CALIB_BIASREFBUF(biasrefbuf); - // Divide 48MHz clock by 32 to obtain 1.5 MHz clock to adc - adc->CTRLA.reg = ADC_CTRLA_PRESCALER_DIV32; + // Divide 48MHz clock by 4 to obtain 12 MHz clock to adc + adc->CTRLA.reg = ADC_CTRLA_PRESCALER_DIV4; + // Enable the offset compensation + adc->SAMPCTRL.reg = ADC_SAMPCTRL_OFFCOMP; // Set the reference voltage. Default: external AREFA. adc->REFCTRL.reg = adc_vref_table[self->vref]; // Average: Accumulate samples and scale them down accordingly diff --git a/ports/samd/machine_dac.c b/ports/samd/machine_dac.c index ee49691e715..f9d0cccd17a 100644 --- a/ports/samd/machine_dac.c +++ b/ports/samd/machine_dac.c @@ -240,7 +240,7 @@ static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) { self->tc_index = allocate_tc_instance(); } // Configure TC; no need to check the return value - configure_tc(self->tc_index, freq); + configure_tc(self->tc_index, freq, 0); // Configure DMA for halfword output to the DAC #if defined(MCU_SAMD21) diff --git a/ports/samd/tc_manager.c b/ports/samd/tc_manager.c index 10cad8060ae..fb0c3b77ff4 100644 --- a/ports/samd/tc_manager.c +++ b/ports/samd/tc_manager.c @@ -57,7 +57,7 @@ void free_tc_instance(int tc_index) { } } -int configure_tc(int tc_index, int freq) { +int configure_tc(int tc_index, int freq, int event) { uint32_t clock = DFLL48M_FREQ; // Use the fixed 48M clock Tc *tc; @@ -105,6 +105,9 @@ int configure_tc(int tc_index, int freq) { TC_CTRLA_MODE_COUNT16 | TC_CTRLA_RUNSTDBY | TC_CTRLA_WAVEGEN_MFRQ; tc->COUNT16.CC[0].reg = period; + if (event) { + tc->COUNT16.EVCTRL.reg = event; + } tc->COUNT16.CTRLA.bit.ENABLE = 1; while (tc->COUNT16.STATUS.bit.SYNCBUSY) { diff --git a/ports/samd/tc_manager.h b/ports/samd/tc_manager.h index 9ab1af19b76..23957e7be26 100644 --- a/ports/samd/tc_manager.h +++ b/ports/samd/tc_manager.h @@ -32,7 +32,7 @@ extern Tc *tc_instance_list[]; int allocate_tc_instance(void); void free_tc_instance(int tc_index); -int configure_tc(int tc_index, int freq); +int configure_tc(int tc_index, int freq, int event); void tc_deinit(void); #endif // MICROPY_INCLUDED_SAMD_TCINSTANCE_H From ac2f4520d80e9a633add4c4c0c236b15873184b0 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Tue, 13 Sep 2022 18:50:42 +0200 Subject: [PATCH 005/635] samd/machine_dac: Add a callback keyword option to machine.DAC(). The callback is called when a dac_timed() sequence finishes. It will be reset with callback=None or omitting the callback option in the constructor. Side change: Set the clock freq. to 48Mhz. Signed-off-by: robert-hh --- ports/samd/machine_dac.c | 45 +++++++++++++++++++++++++++++++++------- ports/samd/main.c | 4 ++++ 2 files changed, 41 insertions(+), 8 deletions(-) diff --git a/ports/samd/machine_dac.c b/ports/samd/machine_dac.c index f9d0cccd17a..bd61137b293 100644 --- a/ports/samd/machine_dac.c +++ b/ports/samd/machine_dac.c @@ -49,16 +49,18 @@ typedef struct _dac_obj_t { int8_t dma_channel; int8_t tc_index; uint32_t count; + mp_obj_t callback; } dac_obj_t; Dac *const dac_bases[] = DAC_INSTS; static void dac_init(dac_obj_t *self, Dac *dac); +static mp_obj_t dac_deinit(mp_obj_t self_in); #if defined(MCU_SAMD21) static dac_obj_t dac_obj[] = { - {{&machine_dac_type}, 0, PIN_PA02}, + {{&machine_dac_type}, 0, 0, PIN_PA02}, }; #define MAX_DAC_VALUE (1023) @@ -68,8 +70,8 @@ static dac_obj_t dac_obj[] = { #elif defined(MCU_SAMD51) static dac_obj_t dac_obj[] = { - {{&machine_dac_type}, 0, PIN_PA02}, - {{&machine_dac_type}, 1, PIN_PA05}, + {{&machine_dac_type}, 0, 0, PIN_PA02, 2, -1, -1, 1, NULL}, + {{&machine_dac_type}, 1, 0, PIN_PA05, 2, -1, -1, 1, NULL}, }; // According to Errata 2.9.2, VDDANA as ref value is not available. However it worked // in tests. So I keep the selection here but set the default to Aref, which is usually @@ -95,6 +97,10 @@ void dac_irq_handler(int dma_channel) { self->count -= 1; dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID; DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + } else { + if (self->callback != MP_OBJ_NULL) { + mp_sched_schedule(self->callback, self); + } } #elif defined(MCU_SAMD51) @@ -108,6 +114,10 @@ void dac_irq_handler(int dma_channel) { self->count -= 1; dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID; DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + } else { + if (self->callback != MP_OBJ_NULL) { + mp_sched_schedule(self->callback, self); + } } #endif } @@ -115,10 +125,11 @@ void dac_irq_handler(int dma_channel) { static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - enum { ARG_id, ARG_vref }; + enum { ARG_id, ARG_vref, ARG_callback }; static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} }, { MP_QSTR_vref, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_DAC_VREF} }, + { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, }; // Parse the arguments. @@ -138,6 +149,15 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ self->vref = vref; } + self->callback = args[ARG_callback].u_obj; + if (self->callback == mp_const_none) { + self->callback = MP_OBJ_NULL; + } + + self->dma_channel = -1; + self->tc_index = -1; + self->initialized = false; + Dac *dac = dac_bases[0]; // Just one DAC dac_init(self, dac); // Set the port as given in self->gpio_id as DAC @@ -152,9 +172,9 @@ static void dac_init(dac_obj_t *self, Dac *dac) { #if defined(MCU_SAMD21) // Configuration SAMD21 - // Enable APBC clocks and PCHCTRL clocks; GCLK3 at 1 MHz + // Enable APBC clocks and PCHCTRL clocks; GCLK5 at 48 MHz PM->APBCMASK.reg |= PM_APBCMASK_DAC; - GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_DAC; + GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK5 | GCLK_CLKCTRL_ID_DAC; while (GCLK->STATUS.bit.SYNCBUSY) { } // Reset DAC registers @@ -170,9 +190,9 @@ static void dac_init(dac_obj_t *self, Dac *dac) { #elif defined(MCU_SAMD51) // Configuration SAMD51 - // Enable APBD clocks and PCHCTRL clocks; GCLK3 at 8 MHz + // Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC; - GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN; + GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN; // Reset DAC registers dac->CTRLA.bit.SWRST = 1; @@ -318,10 +338,19 @@ static mp_obj_t dac_deinit(mp_obj_t self_in) { free_tc_instance(self->tc_index); self->tc_index = -1; } + self->callback = MP_OBJ_NULL; return mp_const_none; } MP_DEFINE_CONST_FUN_OBJ_1(dac_deinit_obj, dac_deinit); +// Clear the DMA channel entry in the DAC object. +void dac_deinit_channel(void) { + dac_obj[0].dma_channel = -1; + #if defined(MCU_SAMD51) + dac_obj[1].dma_channel = -1; + #endif +} + static const mp_rom_map_elem_t dac_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) }, diff --git a/ports/samd/main.c b/ports/samd/main.c index 9f95f6e2668..0620718d6f1 100644 --- a/ports/samd/main.c +++ b/ports/samd/main.c @@ -41,6 +41,7 @@ extern uint8_t _sstack, _estack, _sheap, _eheap; extern void adc_deinit_all(void); +extern void dac_deinit_channel(void); extern void pin_irq_deinit_all(void); extern void pwm_deinit_all(void); extern void sercom_deinit_all(void); @@ -95,6 +96,9 @@ void samd_main(void) { #if MICROPY_PY_MACHINE_ADC adc_deinit_all(); #endif + #if MICROPY_PY_MACHINE_DAC + dac_deinit_channel(); + #endif pin_irq_deinit_all(); #if MICROPY_PY_MACHINE_PWM pwm_deinit_all(); From 0214d9392d6ace49cc9a1fc61d83fa9f2c32d484 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Tue, 13 Sep 2022 21:26:54 +0200 Subject: [PATCH 006/635] samd/machine_adc: Add a callback keyword option to machine.ADC(). Enabling a callback that will be called when a adc.read_timed_into() run is finished. That's especially useful with slow sampling rates and/or many samples, avoiding to guess the sampling time. Raise an error is adc.read_u16() is called while a read_timed_into() is active. Other ADC changes: - SAMD51: use ADC1 if both ADC1 and ADC0 are available at a Pin. Signed-off-by: robert-hh --- ports/samd/machine_adc.c | 120 ++++++++++++++++++++++++++++++++------- 1 file changed, 101 insertions(+), 19 deletions(-) diff --git a/ports/samd/machine_adc.c b/ports/samd/machine_adc.c index afd9c5d29a5..1833efc6862 100644 --- a/ports/samd/machine_adc.c +++ b/ports/samd/machine_adc.c @@ -28,6 +28,13 @@ // This file is never compiled standalone, it's included directly from // extmod/machine_adc.c via MICROPY_PY_MACHINE_ADC_INCLUDEFILE. +#if MICROPY_PY_MACHINE_ADC + +#include +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mperrno.h" + #include "py/mphal.h" #include "sam.h" #include "pin_af.h" @@ -51,6 +58,7 @@ typedef struct _machine_adc_obj_t { #define DEFAULT_ADC_AVG 16 #if defined(MCU_SAMD21) + static uint8_t adc_vref_table[] = { ADC_REFCTRL_REFSEL_INT1V_Val, ADC_REFCTRL_REFSEL_INTVCC0_Val, ADC_REFCTRL_REFSEL_INTVCC1_Val, ADC_REFCTRL_REFSEL_AREFA_Val, ADC_REFCTRL_REFSEL_AREFB_Val @@ -60,9 +68,19 @@ static uint8_t adc_vref_table[] = { #else #define DEFAULT_ADC_VREF (3) #endif +#define MAX_ADC_VREF (4) #define ADC_EVSYS_CHANNEL 0 +typedef struct _device_mgmt_t { + bool init; + bool busy; + mp_obj_t callback; + mp_obj_t self; +} device_mgmt_t; + +device_mgmt_t device_mgmt[ADC_INST_NUM]; + #elif defined(MCU_SAMD51) static uint8_t adc_vref_table[] = { @@ -75,6 +93,22 @@ static uint8_t adc_vref_table[] = { #else #define DEFAULT_ADC_VREF (3) #endif +#define MAX_ADC_VREF (5) + +typedef struct _device_mgmt_t { + bool init; + #if defined(MCU_SAMD51) + bool busy; + int8_t dma_channel; + mp_obj_t callback; + mp_obj_t self; + #endif +} device_mgmt_t; + +device_mgmt_t device_mgmt[ADC_INST_NUM] = { + { 0, 0, -1, MP_OBJ_NULL, MP_OBJ_NULL}, + { 0, 0, -1, MP_OBJ_NULL, MP_OBJ_NULL} +}; #endif // defined(MCU_SAMD21) @@ -82,12 +116,12 @@ static uint8_t adc_vref_table[] = { #define MICROPY_PY_MACHINE_ADC_CLASS_CONSTANTS Adc *const adc_bases[] = ADC_INSTS; -uint32_t busy_flags = 0; -bool init_flags[2] = {false, false}; -static void adc_init(machine_adc_obj_t *self); +uint32_t ch_busy_flags = 0; + static uint8_t resolution[] = { ADC_CTRLB_RESSEL_8BIT_Val, ADC_CTRLB_RESSEL_10BIT_Val, ADC_CTRLB_RESSEL_12BIT_Val }; +static void adc_init(machine_adc_obj_t *self); extern mp_int_t log2i(mp_int_t num); @@ -97,11 +131,27 @@ void adc_irq_handler(int dma_channel) { #if defined(MCU_SAMD21) DMAC->CHID.reg = dma_channel; - DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; + DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL | DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_SUSP; ADC->EVCTRL.bit.STARTEI = 0; + device_mgmt[0].busy = 0; + if (device_mgmt[0].callback != MP_OBJ_NULL) { + mp_sched_schedule(device_mgmt[0].callback, device_mgmt[0].self); + } #elif defined(MCU_SAMD51) - DMAC->Channel[dma_channel].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; + DMAC->Channel[dma_channel].CHINTFLAG.reg = + DMAC_CHINTFLAG_TCMPL | DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_SUSP; + if (device_mgmt[0].dma_channel == dma_channel) { + device_mgmt[0].busy = 0; + if (device_mgmt[0].callback != MP_OBJ_NULL) { + mp_sched_schedule(device_mgmt[0].callback, device_mgmt[0].self); + } + } else if (device_mgmt[1].dma_channel == dma_channel) { + device_mgmt[1].busy = 0; + if (device_mgmt[1].callback != MP_OBJ_NULL) { + mp_sched_schedule(device_mgmt[1].callback, device_mgmt[1].self); + } + } #endif } @@ -114,13 +164,16 @@ static void mp_machine_adc_print(const mp_print_t *print, mp_obj_t self_in, mp_p self->adc_config.channel, self->bits, 1 << self->avg, self->vref); } -static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { - enum { ARG_id, ARG_bits, ARG_average, ARG_vref }; +static mp_obj_t adc_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, + const mp_obj_t *all_args) { + + enum { ARG_id, ARG_bits, ARG_average, ARG_vref, ARG_callback }; static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ }, { MP_QSTR_bits, MP_ARG_INT, {.u_int = DEFAULT_ADC_BITS} }, { MP_QSTR_average, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_ADC_AVG} }, { MP_QSTR_vref, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_ADC_VREF} }, + { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, }; // Parse the arguments. @@ -129,7 +182,7 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args // Unpack and check, whether the pin has ADC capability int id = mp_hal_get_pin_obj(args[ARG_id].u_obj); - adc_config_t adc_config = get_adc_config(id, busy_flags); + adc_config_t adc_config = get_adc_config(id, ch_busy_flags); // Now that we have a valid device and channel, create and populate the ADC instance machine_adc_obj_t *self = mp_obj_malloc(machine_adc_obj_t, &machine_adc_type); @@ -145,13 +198,20 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args self->avg = (avg <= 10 ? avg : 10); uint8_t vref = args[ARG_vref].u_int; - if (0 <= vref && vref < sizeof(adc_vref_table)) { + if (0 <= vref && vref <= MAX_ADC_VREF) { self->vref = vref; } + device_mgmt[adc_config.device].callback = args[ARG_callback].u_obj; + if (device_mgmt[adc_config.device].callback == mp_const_none) { + device_mgmt[adc_config.device].callback = MP_OBJ_NULL; + } else { + device_mgmt[adc_config.device].self = self; + } // flag the device/channel as being in use. - busy_flags |= (1 << (self->adc_config.device * 16 + self->adc_config.channel)); - init_flags[self->adc_config.device] = false; + ch_busy_flags |= (1 << (self->adc_config.device * 16 + self->adc_config.channel)); + self->dma_channel = -1; + self->tc_index = -1; adc_init(self); @@ -163,6 +223,10 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) { Adc *adc = adc_bases[self->adc_config.device]; // Set the reference voltage. Default: external AREFA. adc->REFCTRL.reg = adc_vref_table[self->vref]; + if (device_mgmt[self->adc_config.device].busy != 0) { + mp_raise_OSError(MP_EBUSY); + } + // Set Input channel and resolution // Select the pin as positive input and gnd as negative input reference, non-diff mode by default adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel; @@ -194,6 +258,7 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f if (self->dma_channel == -1) { self->dma_channel = allocate_dma_channel(); dma_init(); + dma_register_irq(self->dma_channel, adc_irq_handler); } if (self->tc_index == -1) { self->tc_index = allocate_tc_instance(); @@ -206,8 +271,6 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f // Configure DMA for halfword output to the DAC #if defined(MCU_SAMD21) - // dma irq just for SAMD21 to stop the timer based acquisition - dma_register_irq(self->dma_channel, adc_irq_handler); configure_tc(self->tc_index, freq, TC_EVCTRL_OVFEO); // Enable APBC clock PM->APBCMASK.reg |= PM_APBCMASK_EVSYS; @@ -241,9 +304,11 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f NVIC_EnableIRQ(DMAC_IRQn); adc->EVCTRL.bit.STARTEI = 1; + device_mgmt[0].busy = 1; #elif defined(MCU_SAMD51) configure_tc(self->tc_index, freq, 0); + device_mgmt[self->adc_config.device].dma_channel = self->dma_channel; // Restart ADC after data has bee read adc->DSEQCTRL.reg = ADC_DSEQCTRL_AUTOSTART; @@ -265,8 +330,16 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f DMAC_CHCTRLA_BURSTLEN(DMAC_CHCTRLA_BURSTLEN_SINGLE_Val) | DMAC_CHCTRLA_TRIGACT(DMAC_CHCTRLA_TRIGACT_BURST_Val) | DMAC_CHCTRLA_TRIGSRC(TC0_DMAC_ID_OVF + 3 * self->tc_index); + DMAC->Channel[self->dma_channel].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + if (self->dma_channel < 4) { + NVIC_EnableIRQ(DMAC_0_IRQn + self->dma_channel); + } else { + NVIC_EnableIRQ(DMAC_4_IRQn); + } + device_mgmt[self->adc_config.device].busy = 1; + #endif // defined SAMD21 or SAMD51 } @@ -277,6 +350,11 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f static void mp_machine_adc_deinit(machine_adc_obj_t *self) { busy_flags &= ~((1 << (self->adc_config.device * 16 + self->adc_config.channel))); if (self->dma_channel >= 0) { + #if defined(MCU_SAMD51) + if (self->dma_channel == device_mgmt[self->adc_config.device].dma_channel) { + device_mgmt[self->adc_config.device].dma_channel = -1; + } + #endif dac_stop_dma(self->dma_channel, true); free_dma_channel(self->dma_channel); self->dma_channel = -1; @@ -288,17 +366,21 @@ static void mp_machine_adc_deinit(machine_adc_obj_t *self) { } void adc_deinit_all(void) { - busy_flags = 0; - init_flags[0] = 0; - init_flags[1] = 0; + ch_busy_flags = 0; + device_mgmt[0].init = 0; + #if defined(MCU_SAMD51) + device_mgmt[0].dma_channel = -1; + device_mgmt[1].init = 0; + device_mgmt[1].dma_channel = -1; + #endif } static void adc_init(machine_adc_obj_t *self) { // ADC & clock init is done only once per ADC - if (init_flags[self->adc_config.device] == false) { + if (device_mgmt[self->adc_config.device].init == false) { Adc *adc = adc_bases[self->adc_config.device]; - init_flags[self->adc_config.device] = true; + device_mgmt[self->adc_config.device].init = true; #if defined(MCU_SAMD21) // Configuration SAMD21 @@ -320,7 +402,7 @@ static void adc_init(machine_adc_obj_t *self) { // Divide a 48MHz clock by 32 to obtain 1.5 MHz clock to adc adc->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV32; // Select external AREFA as reference voltage. - adc->REFCTRL.reg = adc_vref_table[self->vref]; + adc->REFCTRL.reg = self->vref; // Average: Accumulate samples and scale them down accordingly adc->AVGCTRL.reg = self->avg | ADC_AVGCTRL_ADJRES(self->avg); // Enable ADC and wait to be ready From 490d63aa7ebbfc19d5d797415bf62314a6415578 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Fri, 14 Oct 2022 12:18:28 +0200 Subject: [PATCH 007/635] samd: Add new adc.busy() and dac.busy() methods. These return True, while a timed action is ongoing. Side change: Reorder some code in machine_dac.c and do not reset DAC twice. Signed-off-by: robert-hh --- ports/samd/machine_adc.c | 7 +++++ ports/samd/machine_dac.c | 59 ++++++++++++++++++++++++++++++---------- 2 files changed, 52 insertions(+), 14 deletions(-) diff --git a/ports/samd/machine_adc.c b/ports/samd/machine_adc.c index 1833efc6862..10dbb42c808 100644 --- a/ports/samd/machine_adc.c +++ b/ports/samd/machine_adc.c @@ -353,6 +353,7 @@ static void mp_machine_adc_deinit(machine_adc_obj_t *self) { #if defined(MCU_SAMD51) if (self->dma_channel == device_mgmt[self->adc_config.device].dma_channel) { device_mgmt[self->adc_config.device].dma_channel = -1; + device_mgmt[self->adc_config.device].busy = 0; } #endif dac_stop_dma(self->dma_channel, true); @@ -365,6 +366,12 @@ static void mp_machine_adc_deinit(machine_adc_obj_t *self) { } } +// busy() : Report, if the ADC device is busy +static mp_int_t machine_adc_busy(mp_obj_t self_in) { + machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); + return device_mgmt[self->adc_config.device].busy ? true : false; +} + void adc_deinit_all(void) { ch_busy_flags = 0; device_mgmt[0].init = 0; diff --git a/ports/samd/machine_dac.c b/ports/samd/machine_dac.c index bd61137b293..d0e51bb122e 100644 --- a/ports/samd/machine_dac.c +++ b/ports/samd/machine_dac.c @@ -31,6 +31,8 @@ #include #include "py/obj.h" +#include "py/runtime.h" +#include "py/mperrno.h" #include "py/mphal.h" #include "sam.h" @@ -48,6 +50,7 @@ typedef struct _dac_obj_t { uint8_t vref; int8_t dma_channel; int8_t tc_index; + bool busy; uint32_t count; mp_obj_t callback; } dac_obj_t; @@ -59,20 +62,25 @@ static mp_obj_t dac_deinit(mp_obj_t self_in); #if defined(MCU_SAMD21) -static dac_obj_t dac_obj[] = { - {{&machine_dac_type}, 0, 0, PIN_PA02}, -}; - #define MAX_DAC_VALUE (1023) #define DEFAULT_DAC_VREF (1) #define MAX_DAC_VREF (2) +static dac_obj_t dac_obj[] = { + {{&machine_dac_type}, 0, 0, PIN_PA02, DEFAULT_DAC_VREF, -1, -1, false, 1, NULL}, +}; + #elif defined(MCU_SAMD51) +#define MAX_DAC_VALUE (4095) +#define DEFAULT_DAC_VREF (2) +#define MAX_DAC_VREF (3) + static dac_obj_t dac_obj[] = { - {{&machine_dac_type}, 0, 0, PIN_PA02, 2, -1, -1, 1, NULL}, - {{&machine_dac_type}, 1, 0, PIN_PA05, 2, -1, -1, 1, NULL}, + {{&machine_dac_type}, 0, 0, PIN_PA02, DEFAULT_DAC_VREF, -1, -1, false, 1, NULL}, + {{&machine_dac_type}, 1, 0, PIN_PA05, DEFAULT_DAC_VREF, -1, -1, false, 1, NULL}, }; + // According to Errata 2.9.2, VDDANA as ref value is not available. However it worked // in tests. So I keep the selection here but set the default to Aref, which is usually // connected at the Board to VDDANA @@ -80,9 +88,6 @@ static uint8_t dac_vref_table[] = { DAC_CTRLB_REFSEL_INTREF_Val, DAC_CTRLB_REFSEL_VDDANA_Val, DAC_CTRLB_REFSEL_VREFPU_Val, DAC_CTRLB_REFSEL_VREFPB_Val }; -#define MAX_DAC_VALUE (4095) -#define DEFAULT_DAC_VREF (2) -#define MAX_DAC_VREF (3) #endif // defined SAMD21 or SAMD51 @@ -98,6 +103,7 @@ void dac_irq_handler(int dma_channel) { dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID; DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; } else { + self->busy = false; if (self->callback != MP_OBJ_NULL) { mp_sched_schedule(self->callback, self); } @@ -115,6 +121,7 @@ void dac_irq_handler(int dma_channel) { dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID; DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; } else { + self->busy = false; if (self->callback != MP_OBJ_NULL) { mp_sched_schedule(self->callback, self); } @@ -138,10 +145,10 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ uint8_t id = args[ARG_id].u_int; dac_obj_t *self = NULL; - if (0 <= id && id <= MP_ARRAY_SIZE(dac_obj)) { + if (0 <= id && id < MP_ARRAY_SIZE(dac_obj)) { self = &dac_obj[id]; } else { - mp_raise_ValueError(MP_ERROR_TEXT("invalid Pin for DAC")); + mp_raise_ValueError(MP_ERROR_TEXT("invalid DAC ID")); } uint8_t vref = args[ARG_vref].u_int; @@ -194,9 +201,18 @@ static void dac_init(dac_obj_t *self, Dac *dac) { MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC; GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN; - // Reset DAC registers - dac->CTRLA.bit.SWRST = 1; - while (dac->CTRLA.bit.SWRST) { + // If the DAC is enabled it was already reset + // In that case just disable it. + if (dac->CTRLA.bit.ENABLE) { + // Enable DAC and wait to be ready + dac->CTRLA.bit.ENABLE = 0; + while (dac->SYNCBUSY.bit.ENABLE) { + } + } else { + // Reset DAC registers + dac->CTRLA.bit.SWRST = 1; + while (dac->CTRLA.bit.SWRST) { + } } dac->CTRLB.reg = DAC_CTRLB_REFSEL(dac_vref_table[self->vref]); dac->DACCTRL[self->id].reg = DAC_DACCTRL_ENABLE | DAC_DACCTRL_REFRESH(2) | DAC_DACCTRL_CCTRL_CC12M; @@ -219,6 +235,10 @@ static void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) { Dac *dac = dac_bases[0]; // Just one DAC dac_obj_t *self = self_in; + if (self->busy != false) { + mp_raise_OSError(MP_EBUSY); + } + int value = mp_obj_get_int(value_in); if (value < 0 || value > MAX_DAC_VALUE) { @@ -261,6 +281,8 @@ static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) { } // Configure TC; no need to check the return value configure_tc(self->tc_index, freq, 0); + self->busy = true; + // Configure DMA for halfword output to the DAC #if defined(MCU_SAMD21) @@ -339,10 +361,18 @@ static mp_obj_t dac_deinit(mp_obj_t self_in) { self->tc_index = -1; } self->callback = MP_OBJ_NULL; + self->busy = false; return mp_const_none; } MP_DEFINE_CONST_FUN_OBJ_1(dac_deinit_obj, dac_deinit); +// busy() : Report, if the DAC device is busy +static mp_obj_t machine_dac_busy(mp_obj_t self_in) { + dac_obj_t *self = MP_OBJ_TO_PTR(self_in); + return self->busy ? mp_const_true : mp_const_false; +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_dac_busy_obj, machine_dac_busy); + // Clear the DMA channel entry in the DAC object. void dac_deinit_channel(void) { dac_obj[0].dma_channel = -1; @@ -352,6 +382,7 @@ void dac_deinit_channel(void) { } static const mp_rom_map_elem_t dac_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_busy), MP_ROM_PTR(&machine_dac_busy_obj) }, { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) }, { MP_ROM_QSTR(MP_QSTR_write_timed), MP_ROM_PTR(&dac_write_timed_obj) }, From cc42bf9007ab119e44c74ffcc1adca376bc08dc0 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Wed, 26 Oct 2022 20:39:44 +0200 Subject: [PATCH 008/635] docs/samd: Document the extensions to DAC and ADC. Signed-off-by: robert-hh --- docs/samd/quickref.rst | 154 +++++++++++++++++++++++++++++++++-------- 1 file changed, 124 insertions(+), 30 deletions(-) diff --git a/docs/samd/quickref.rst b/docs/samd/quickref.rst index 781686d2f60..efab6cd4757 100644 --- a/docs/samd/quickref.rst +++ b/docs/samd/quickref.rst @@ -261,30 +261,39 @@ an external ADC. ADC Constructor ``````````````` -.. class:: ADC(dest, *, average=16, vref=n) +.. class:: ADC(dest, *, average=16, bits=12, vref=3, callback=None) :noindex: -Construct and return a new ADC object using the following parameters: - - - *dest* is the Pin object on which the ADC is output. - -Keyword arguments: +On the SAMD21/SAMD51 ADC functionality is available on Pins labelled 'Ann'. - - *average* is used to reduce the noise. With a value of 16 the LSB noise is about 1 digit. - - *vref* sets the reference voltage for the ADC. +Use the :ref:`machine.ADC ` class:: - The default setting is for 3.3V. Other values are: + from machine import ADC - ==== ============================== =============================== - vref SAMD21 SAMD51 - ==== ============================== =============================== - 0 1.0V voltage reference internal bandgap reference (1V) - 1 1/1.48 Analogue voltage supply Analogue voltage supply - 2 1/2 Analogue voltage supply 1/2 Analogue voltage supply - 3 External reference A External reference A - 4 External reference B External reference B - 5 - External reference C - ==== ============================== =============================== + adc0 = ADC(Pin("A0")) # create ADC object on ADC pin, average=16 + adc0.read_u16() # read value, 0-65536 across voltage range 0.0v - 3.3v + adc1 = ADC(Pin("A1"), average=1) # create ADC object on ADC pin, average=1 + +The resolution of the ADC is set by the bits keyword option. The default is 12. +Suitable values are 8, 10 and 12. If you need a higher resolution or better +accuracy, use an external ADC. The default value of average is 16. +Averaging is used to reduce the noise. With a value of 16 the LSB noise is +about 1 digit. The vref=n option sets the reference voltage for the ADC. +The default setting is for 3.3V. Other values are: + +==== ============================== =============================== +vref SAMD21 SAMD51 +==== ============================== =============================== +0 1.0V voltage reference internal bandgap reference (1V) +1 1/1.48 Analogue voltage supply Analogue voltage supply +2 1/2 Analogue voltage supply 1/2 Analogue voltage supply +3 External reference A External reference A +4 External reference B External reference B +5 - External reference C +==== ============================== =============================== + +The callback keyword option is used for timed ADC sampling. The callback is executed +when all data has been sampled. ADC Methods ``````````` @@ -294,27 +303,66 @@ ADC Methods Read a single ADC value as unsigned 16 bit quantity. The voltage range is defined by the vref option of the constructor, the resolutions by the bits option. -DAC (digital to analog conversion) ----------------------------------- +.. method:: read_timed(data, freq) -The DAC class provides a fast digital to analog conversion. Usage example:: +Read ADC values into the data buffer at a supplied frequency. The buffer +must be preallocated. Values are stored as 16 bit quantities in the binary +range given by the bits option. If bits=12, the value range is 0-4095. +The voltage range is defined by the vref option. +The sampling frequency range depends on the bits and average setting. At bits=8 +and average=1, the largest rate is >1 MHz for SAMD51 and 350kHz for SAMD21. +the lowest sampling rate is 1 Hz. The call to the method returns immediately, +The data transfer is done by DMA in the background, controlled by a hardware timer. +If in the constructor a callback was defined, it will be called after all data has been +read. Alternatively, the method busy() can be used to tell, if the capture has finished. - from machine import DAC +Example for a call to adc.read_timed() and a callback:: - dac0 = DAC(0) # create DAC object on DAC pin A0 - dac0.write(1023) # write value, 0-4095 across voltage range 0.0v - 3.3v - dac1 = DAC(1) # create DAC object on DAC pin A1 - dac1.write(2000) # write value, 0-4095 across voltage range 0.0v - 3.3v + from machine import ADC + from array import array -The resolution of the DAC is 12 bit for SAMD51 and 10 bit for SAMD21. SAMD21 devices -have 1 DAC channel at GPIO PA02, SAMD51 devices have 2 DAC channels at GPIO PA02 and PA05. + def finished(adc_o): + print("Sampling finished on ADC", adc_o) + + # create ADC object on ADC pin A0, average=1 + adc = ADC(Pin("A0"), average=1, callback=finished) + buffer = array("H", bytearray(512)) # create an array for 256 ADC values + adc.read_timed(buffer, 10000) # read 256 12 bit values at a frequency of + # 10 kHz and call finished() when done. + +.. method:: busy() + +busy() returns `True` while the data acquisition using read_timed() is ongoing, `False` +otherwise. + +.. method deinit() + +Deinitialize an ADC object and release the resources used by it, especially the ADC +channel and the timer used for read_timed(). + + +DAC (digital to analogue conversion) +------------------------------------ DAC Constructor ``````````````` -.. class:: DAC(id, *, vref=3) +.. class:: DAC(id, *, vref=3, callback=None) :noindex: + +The DAC class provides a fast digital to analogue conversion. Usage example:: + + from machine import DAC + + dac0 = DAC(0) # create DAC object on DAC pin A0 + dac0.write(1023) # write value, 0-4095 across voltage range 0.0V - 3.3V + dac1 = DAC(1) # create DAC object on DAC pin A1 + dac1.write(2000) # write value, 0-4095 across voltage range 0.0V - 3.3V + +The resolution of the DAC is 12 bit for SAMD51 and 10 bit for SAMD21. SAMD21 devices +have 1 DAC channel at GPIO PA02, accepting only 0 as id. SAMD51 devices have +2 DAC channels at GPIO PA02 and PA05 with values 0 and 1 for the id. The vref arguments defines the output voltage range, the callback option is used for dac_timed(). Suitable values for vref are: @@ -327,6 +375,7 @@ vref SAMD21 SAMD51 3 - Buffered external reference ==== ============================ ================================ + DAC Methods ``````````` @@ -335,6 +384,51 @@ DAC Methods Write a single value to the selected DAC output. The value range is 0-1023 for SAMD21 and 0-4095 for SAMD51. The voltage range depends on the vref setting. +.. method:: write_timed(data, freq [, count=1]) + +The call to dac_timed() allows to output a series of analogue values at a given rate. +data must be a buffer with 16 bit values in the range of the DAC (10 bit of 12 bit). +freq may have a range of 1Hz to ~200kHz for SAMD21 and 1 Hz to ~500kHz for SAMD51. +The optional argument count specifies, how often data output will be repeated. The +range is 1 - (2**32 - 1). If count == 0, the data output will be repeated until stopped +by a call to deinit(). If the data has been output count times, a callback will +be called, if given. + +Example:: + + from machine import DAC + from array import array + + data = array("H", [i for i in range(0, 4096, 256)]) # create a step sequence + + def done(dac_o): + print("Sequence done at", dac_o) + + dac = DAC(0, callback=done) + dac.write_timed(data, 1000, 10) # output data 10 times at a rate of 1000 values/s + # and call done() when finished. + +The data transfer is done by DMA and not affected by python code execution. +It is possible to restart dac.write_timed() in the callback function with changed +parameters. + + +.. method:: busy() + :noindex: + +Tell, whether a write_timed() activity is ongoing. It returns `True` if yes, `False` +otherwise. + + +.. method:: deinit() + +Deinitialize the DAC and release the resources used by it, especially the DMA channel +and the Timer. On most SAMD21 boards, there is just one timer available for +dac.write_timed() and adc.read_timed(). So they cannot run both at the same time, +and releasing the timer may be important. The DAC driver consumes a substantial amount +of current. deinit() will reduce that as well. + + Software SPI bus ---------------- From e4a06097a4a233283b4206d4113c83490e3e531c Mon Sep 17 00:00:00 2001 From: robert-hh Date: Fri, 24 Mar 2023 11:52:11 +0100 Subject: [PATCH 009/635] samd/machine_dac: Rework the DAC deinit() semantics. Since the two channels of a SAMD51 are not completely independent, dac.deinit() now clears both channels, and both channels have to be re-instantiated after a deinit(). Side change: - rearrange some code lines. Signed-off-by: robert-hh --- docs/samd/quickref.rst | 3 +- ports/samd/machine_dac.c | 65 +++++++++++++++++++++++----------------- ports/samd/main.c | 4 +-- 3 files changed, 41 insertions(+), 31 deletions(-) diff --git a/docs/samd/quickref.rst b/docs/samd/quickref.rst index efab6cd4757..4d6894eac17 100644 --- a/docs/samd/quickref.rst +++ b/docs/samd/quickref.rst @@ -426,7 +426,8 @@ Deinitialize the DAC and release the resources used by it, especially the DMA ch and the Timer. On most SAMD21 boards, there is just one timer available for dac.write_timed() and adc.read_timed(). So they cannot run both at the same time, and releasing the timer may be important. The DAC driver consumes a substantial amount -of current. deinit() will reduce that as well. +of current. deinit() will reduce that as well. After calling deinit(), the +DAC objects cannot be used any more and must be recreated. Software SPI bus diff --git a/ports/samd/machine_dac.c b/ports/samd/machine_dac.c index d0e51bb122e..a76aef4a916 100644 --- a/ports/samd/machine_dac.c +++ b/ports/samd/machine_dac.c @@ -46,8 +46,8 @@ typedef struct _dac_obj_t { mp_obj_base_t base; uint8_t id; bool initialized; - mp_hal_pin_obj_t gpio_id; uint8_t vref; + mp_hal_pin_obj_t gpio_id; int8_t dma_channel; int8_t tc_index; bool busy; @@ -57,7 +57,7 @@ typedef struct _dac_obj_t { Dac *const dac_bases[] = DAC_INSTS; -static void dac_init(dac_obj_t *self, Dac *dac); +static void dac_init(dac_obj_t *self); static mp_obj_t dac_deinit(mp_obj_t self_in); #if defined(MCU_SAMD21) @@ -67,7 +67,7 @@ static mp_obj_t dac_deinit(mp_obj_t self_in); #define MAX_DAC_VREF (2) static dac_obj_t dac_obj[] = { - {{&machine_dac_type}, 0, 0, PIN_PA02, DEFAULT_DAC_VREF, -1, -1, false, 1, NULL}, + {{&machine_dac_type}, 0, 0, DEFAULT_DAC_VREF, PIN_PA02}, }; #elif defined(MCU_SAMD51) @@ -77,8 +77,8 @@ static dac_obj_t dac_obj[] = { #define MAX_DAC_VREF (3) static dac_obj_t dac_obj[] = { - {{&machine_dac_type}, 0, 0, PIN_PA02, DEFAULT_DAC_VREF, -1, -1, false, 1, NULL}, - {{&machine_dac_type}, 1, 0, PIN_PA05, DEFAULT_DAC_VREF, -1, -1, false, 1, NULL}, + {{&machine_dac_type}, 0, 0, DEFAULT_DAC_VREF, PIN_PA02}, + {{&machine_dac_type}, 1, 0, DEFAULT_DAC_VREF, PIN_PA05}, }; // According to Errata 2.9.2, VDDANA as ref value is not available. However it worked @@ -164,18 +164,20 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ self->dma_channel = -1; self->tc_index = -1; self->initialized = false; + self->busy = false; - Dac *dac = dac_bases[0]; // Just one DAC - dac_init(self, dac); + dac_init(self); // Set the port as given in self->gpio_id as DAC mp_hal_set_pin_mux(self->gpio_id, ALT_FCT_DAC); return MP_OBJ_FROM_PTR(self); } -static void dac_init(dac_obj_t *self, Dac *dac) { +static void dac_init(dac_obj_t *self) { // Init DAC if (self->initialized == false) { + Dac *dac = dac_bases[0]; // Just one DAC + #if defined(MCU_SAMD21) // Configuration SAMD21 @@ -197,9 +199,6 @@ static void dac_init(dac_obj_t *self, Dac *dac) { #elif defined(MCU_SAMD51) // Configuration SAMD51 - // Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz - MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC; - GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN; // If the DAC is enabled it was already reset // In that case just disable it. @@ -209,6 +208,9 @@ static void dac_init(dac_obj_t *self, Dac *dac) { while (dac->SYNCBUSY.bit.ENABLE) { } } else { + // Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz + MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC; + GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN; // Reset DAC registers dac->CTRLA.bit.SWRST = 1; while (dac->CTRLA.bit.SWRST) { @@ -235,6 +237,10 @@ static void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) { Dac *dac = dac_bases[0]; // Just one DAC dac_obj_t *self = self_in; + + if (self->initialized == false) { + mp_raise_OSError(MP_ENODEV); + } if (self->busy != false) { mp_raise_OSError(MP_EBUSY); } @@ -244,8 +250,6 @@ static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) { if (value < 0 || value > MAX_DAC_VALUE) { mp_raise_ValueError(MP_ERROR_TEXT("value out of range")); } - // Re-init, if required - dac_init(self, dac); #if defined(MCU_SAMD21) dac->DATA.reg = value; #elif defined(MCU_SAMD51) @@ -260,8 +264,10 @@ static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) { Dac *dac = dac_bases[0]; // Just one DAC used dac_obj_t *self = args[0]; mp_buffer_info_t src; - // Re-init, if required - dac_init(self, dac); + + if (self->initialized == false) { + mp_raise_OSError(MP_ENODEV); + } mp_get_buffer_raise(args[1], &src, MP_BUFFER_READ); if (n_args > 3) { @@ -346,11 +352,8 @@ static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) { } static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(dac_write_timed_obj, 3, 4, dac_write_timed); -static mp_obj_t dac_deinit(mp_obj_t self_in) { - dac_obj_t *self = self_in; +static void dac_deinit_channel(dac_obj_t *self) { self->initialized = false; - // Reset the DAC to lower the current consumption as SAMD21 - dac_bases[0]->CTRLA.bit.SWRST = 1; if (self->dma_channel >= 0) { dac_stop_dma(self->dma_channel, true); free_dma_channel(self->dma_channel); @@ -362,6 +365,20 @@ static mp_obj_t dac_deinit(mp_obj_t self_in) { } self->callback = MP_OBJ_NULL; self->busy = false; +} + +// Reset DAC and clear the DMA channel entries in the DAC objects. +void dac_deinit_all(void) { + // Reset the DAC to lower the current consumption as SAMD21 + dac_bases[0]->CTRLA.bit.SWRST = 1; + dac_deinit_channel(&dac_obj[0]); + #if defined(MCU_SAMD51) + dac_deinit_channel(&dac_obj[1]); + #endif +} + +static mp_obj_t dac_deinit(mp_obj_t self_in) { + dac_deinit_all(); return mp_const_none; } MP_DEFINE_CONST_FUN_OBJ_1(dac_deinit_obj, dac_deinit); @@ -373,18 +390,10 @@ static mp_obj_t machine_dac_busy(mp_obj_t self_in) { } static MP_DEFINE_CONST_FUN_OBJ_1(machine_dac_busy_obj, machine_dac_busy); -// Clear the DMA channel entry in the DAC object. -void dac_deinit_channel(void) { - dac_obj[0].dma_channel = -1; - #if defined(MCU_SAMD51) - dac_obj[1].dma_channel = -1; - #endif -} - static const mp_rom_map_elem_t dac_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) }, { MP_ROM_QSTR(MP_QSTR_busy), MP_ROM_PTR(&machine_dac_busy_obj) }, { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) }, - { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) }, { MP_ROM_QSTR(MP_QSTR_write_timed), MP_ROM_PTR(&dac_write_timed_obj) }, }; diff --git a/ports/samd/main.c b/ports/samd/main.c index 0620718d6f1..b0ee334db25 100644 --- a/ports/samd/main.c +++ b/ports/samd/main.c @@ -41,7 +41,7 @@ extern uint8_t _sstack, _estack, _sheap, _eheap; extern void adc_deinit_all(void); -extern void dac_deinit_channel(void); +extern void dac_deinit_all(void); extern void pin_irq_deinit_all(void); extern void pwm_deinit_all(void); extern void sercom_deinit_all(void); @@ -97,7 +97,7 @@ void samd_main(void) { adc_deinit_all(); #endif #if MICROPY_PY_MACHINE_DAC - dac_deinit_channel(); + dac_deinit_all(); #endif pin_irq_deinit_all(); #if MICROPY_PY_MACHINE_PWM From e029a9a0717b1f6be7acd1784db3dc46db408809 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Sat, 25 Mar 2023 16:41:21 +0100 Subject: [PATCH 010/635] samd: Make adc.read_timed() and dac.write_timed() configurable. Both together require ~1.9k of flash space, including the DMA-manager and the TC-manager. adc.read_timed() uses ~700 bytes, dac.write_timed() ~600 bytes. Signed-off-by: robert-hh --- ports/samd/dma_manager.c | 4 ++++ ports/samd/machine_adc.c | 35 +++++++++++++++++++++++++++++++---- ports/samd/machine_dac.c | 34 +++++++++++++++++++++++++++++++--- ports/samd/main.c | 4 ++++ ports/samd/mpconfigport.h | 11 +++++++++++ ports/samd/tc_manager.c | 4 ++++ 6 files changed, 85 insertions(+), 7 deletions(-) diff --git a/ports/samd/dma_manager.c b/ports/samd/dma_manager.c index 868606e66b7..2ca7f7ba106 100644 --- a/ports/samd/dma_manager.c +++ b/ports/samd/dma_manager.c @@ -30,6 +30,8 @@ #include "dma_manager.h" #include "samd_soc.h" +#if MICROPY_HW_DMA_MANAGER + // Set a number of dma channels managed here. samd21 has 21 dma channels, samd51 // has 32 channels, as defined by the lib macro DMAC_CH_NUM. // At first, we use a smaller number here to save RAM. May be increased as needed. @@ -129,3 +131,5 @@ void dac_stop_dma(int dma_channel, bool wait) { } #endif } + +#endif diff --git a/ports/samd/machine_adc.c b/ports/samd/machine_adc.c index 10dbb42c808..f497623a54a 100644 --- a/ports/samd/machine_adc.c +++ b/ports/samd/machine_adc.c @@ -50,8 +50,10 @@ typedef struct _machine_adc_obj_t { uint8_t avg; uint8_t bits; uint8_t vref; + #if MICROPY_PY_MACHINE_ADC_READ_TIMED int8_t dma_channel; int8_t tc_index; + #endif } machine_adc_obj_t; #define DEFAULT_ADC_BITS 12 @@ -74,9 +76,11 @@ static uint8_t adc_vref_table[] = { typedef struct _device_mgmt_t { bool init; + #if MICROPY_PY_MACHINE_ADC_READ_TIMED bool busy; mp_obj_t callback; mp_obj_t self; + #endif } device_mgmt_t; device_mgmt_t device_mgmt[ADC_INST_NUM]; @@ -105,10 +109,7 @@ typedef struct _device_mgmt_t { #endif } device_mgmt_t; -device_mgmt_t device_mgmt[ADC_INST_NUM] = { - { 0, 0, -1, MP_OBJ_NULL, MP_OBJ_NULL}, - { 0, 0, -1, MP_OBJ_NULL, MP_OBJ_NULL} -}; +device_mgmt_t device_mgmt[ADC_INST_NUM]; #endif // defined(MCU_SAMD21) @@ -125,6 +126,8 @@ static void adc_init(machine_adc_obj_t *self); extern mp_int_t log2i(mp_int_t num); +#if MICROPY_PY_MACHINE_ADC_READ_TIMED + // Active just for SAMD21, stops the freerun mode // For SAMD51, just the INT flag is reset. void adc_irq_handler(int dma_channel) { @@ -154,6 +157,7 @@ void adc_irq_handler(int dma_channel) { } #endif } +#endif static void mp_machine_adc_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { (void)kind; @@ -173,7 +177,9 @@ static mp_obj_t adc_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_ { MP_QSTR_bits, MP_ARG_INT, {.u_int = DEFAULT_ADC_BITS} }, { MP_QSTR_average, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_ADC_AVG} }, { MP_QSTR_vref, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_ADC_VREF} }, + #if MICROPY_PY_MACHINE_ADC_READ_TIMED { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + #endif }; // Parse the arguments. @@ -201,6 +207,11 @@ static mp_obj_t adc_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_ if (0 <= vref && vref <= MAX_ADC_VREF) { self->vref = vref; } + // flag the device/channel as being in use. + ch_busy_flags |= (1 << (self->adc_config.device * 16 + self->adc_config.channel)); + device_mgmt[self->adc_config.device].init = false; + + #if MICROPY_PY_MACHINE_ADC_READ_TIMED device_mgmt[adc_config.device].callback = args[ARG_callback].u_obj; if (device_mgmt[adc_config.device].callback == mp_const_none) { device_mgmt[adc_config.device].callback = MP_OBJ_NULL; @@ -212,6 +223,7 @@ static mp_obj_t adc_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_ ch_busy_flags |= (1 << (self->adc_config.device * 16 + self->adc_config.channel)); self->dma_channel = -1; self->tc_index = -1; + #endif adc_init(self); @@ -223,9 +235,12 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) { Adc *adc = adc_bases[self->adc_config.device]; // Set the reference voltage. Default: external AREFA. adc->REFCTRL.reg = adc_vref_table[self->vref]; + + #if MICROPY_PY_MACHINE_ADC_READ_TIMED if (device_mgmt[self->adc_config.device].busy != 0) { mp_raise_OSError(MP_EBUSY); } + #endif // Set Input channel and resolution // Select the pin as positive input and gnd as negative input reference, non-diff mode by default @@ -372,6 +387,9 @@ static mp_int_t machine_adc_busy(mp_obj_t self_in) { return device_mgmt[self->adc_config.device].busy ? true : false; } +#endif + +#if MICROPY_PY_MACHINE_ADC_READ_TIMED void adc_deinit_all(void) { ch_busy_flags = 0; device_mgmt[0].init = 0; @@ -381,6 +399,15 @@ void adc_deinit_all(void) { device_mgmt[1].dma_channel = -1; #endif } +#else +void adc_deinit_all(void) { + ch_busy_flags = 0; + device_mgmt[0].init = 0; + #if defined(MCU_SAMD51) + device_mgmt[1].init = 0; + #endif +} +#endif static void adc_init(machine_adc_obj_t *self) { // ADC & clock init is done only once per ADC diff --git a/ports/samd/machine_dac.c b/ports/samd/machine_dac.c index a76aef4a916..dcb6c020d56 100644 --- a/ports/samd/machine_dac.c +++ b/ports/samd/machine_dac.c @@ -48,17 +48,18 @@ typedef struct _dac_obj_t { bool initialized; uint8_t vref; mp_hal_pin_obj_t gpio_id; + #if MICROPY_PY_MACHINE_DAC_WRITE_TIMED int8_t dma_channel; int8_t tc_index; bool busy; uint32_t count; mp_obj_t callback; + #endif } dac_obj_t; Dac *const dac_bases[] = DAC_INSTS; static void dac_init(dac_obj_t *self); -static mp_obj_t dac_deinit(mp_obj_t self_in); #if defined(MCU_SAMD21) @@ -91,6 +92,8 @@ static uint8_t dac_vref_table[] = { #endif // defined SAMD21 or SAMD51 +#if MICROPY_PY_MACHINE_DAC_WRITE_TIMED + void dac_irq_handler(int dma_channel) { dac_obj_t *self; @@ -129,6 +132,8 @@ void dac_irq_handler(int dma_channel) { #endif } +#endif + static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { @@ -136,7 +141,9 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} }, { MP_QSTR_vref, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_DAC_VREF} }, + #if MICROPY_PY_MACHINE_DAC_WRITE_TIMED { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + #endif }; // Parse the arguments. @@ -156,15 +163,17 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ self->vref = vref; } + #if MICROPY_PY_MACHINE_DAC_WRITE_TIMED self->callback = args[ARG_callback].u_obj; if (self->callback == mp_const_none) { self->callback = MP_OBJ_NULL; } - self->dma_channel = -1; self->tc_index = -1; - self->initialized = false; self->busy = false; + #endif + + self->initialized = false; dac_init(self); // Set the port as given in self->gpio_id as DAC @@ -241,9 +250,11 @@ static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) { if (self->initialized == false) { mp_raise_OSError(MP_ENODEV); } + #if MICROPY_PY_MACHINE_DAC_WRITE_TIMED if (self->busy != false) { mp_raise_OSError(MP_EBUSY); } + #endif int value = mp_obj_get_int(value_in); @@ -260,6 +271,8 @@ static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) { } MP_DEFINE_CONST_FUN_OBJ_2(dac_write_obj, dac_write); +#if MICROPY_PY_MACHINE_DAC_WRITE_TIMED + static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) { Dac *dac = dac_bases[0]; // Just one DAC used dac_obj_t *self = args[0]; @@ -390,11 +403,26 @@ static mp_obj_t machine_dac_busy(mp_obj_t self_in) { } static MP_DEFINE_CONST_FUN_OBJ_1(machine_dac_busy_obj, machine_dac_busy); +#else + +void dac_deinit_all(void) { + // Reset the DAC to lower the current consumption as SAMD21 + dac_bases[0]->CTRLA.bit.SWRST = 1; + dac_obj[0].initialized = false; + #if defined(MCU_SAMD51) + dac_obj[1].initialized = false; + #endif +} + +#endif + static const mp_rom_map_elem_t dac_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) }, + #if MICROPY_PY_MACHINE_DAC_WRITE_TIMED { MP_ROM_QSTR(MP_QSTR_busy), MP_ROM_PTR(&machine_dac_busy_obj) }, { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_write_timed), MP_ROM_PTR(&dac_write_timed_obj) }, + #endif }; static MP_DEFINE_CONST_DICT(dac_locals_dict, dac_locals_dict_table); diff --git a/ports/samd/main.c b/ports/samd/main.c index b0ee334db25..7ea59a02c2b 100644 --- a/ports/samd/main.c +++ b/ports/samd/main.c @@ -91,8 +91,12 @@ void samd_main(void) { soft_reset_exit: mp_printf(MP_PYTHON_PRINTER, "MPY: soft reboot\n"); + #if MICROPY_HW_DMA_MANAGER dma_deinit(); + #endif + #if MICROPY_HW_TC_MANAGER tc_deinit(); + #endif #if MICROPY_PY_MACHINE_ADC adc_deinit_all(); #endif diff --git a/ports/samd/mpconfigport.h b/ports/samd/mpconfigport.h index 74b694ac80a..faa0b6f446f 100644 --- a/ports/samd/mpconfigport.h +++ b/ports/samd/mpconfigport.h @@ -136,6 +136,17 @@ #define MICROPY_PY_MACHINE_I2C_TARGET_HARD_IRQ (1) #define MICROPY_PY_MACHINE_I2C_TARGET_FINALISER (1) +#ifndef MICROPY_PY_MACHINE_DAC_WRITE_TIMED +#define MICROPY_PY_MACHINE_DAC_WRITE_TIMED (1) +#endif +#ifndef MICROPY_PY_MACHINE_ADC_READ_TIMED +#define MICROPY_PY_MACHINE_ADC_READ_TIMED (1) +#endif +#if MICROPY_PY_MACHINE_DAC_WRITE_TIMED || MICROPY_PY_MACHINE_ADC_READ_TIMED +#define MICROPY_HW_DMA_MANAGER (1) +#define MICROPY_HW_TC_MANAGER (1) +#endif + #define MP_STATE_PORT MP_STATE_VM // Miscellaneous settings diff --git a/ports/samd/tc_manager.c b/ports/samd/tc_manager.c index fb0c3b77ff4..b6b981087c4 100644 --- a/ports/samd/tc_manager.c +++ b/ports/samd/tc_manager.c @@ -29,6 +29,8 @@ #include "sam.h" #include "tc_manager.h" +#if MICROPY_HW_TC_MANAGER + // List of channel flags: true: channel used, false: channel available // Two Tc instances are used by the usec counter and cannot be assigned. #if defined(MCU_SAMD21) @@ -179,3 +181,5 @@ void tc_deinit(void) { instance_flag[0] = instance_flag[1] = true; #endif } + +#endif From 285b737e4466bbd27ddf78949541278445f51ab1 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Sat, 26 Aug 2023 10:43:09 +0200 Subject: [PATCH 011/635] samd: Fix init and deinit for adc_timed() and dac_timed(). Fixes: - Leave no half-initialized device if init fails. - Fix dac_deinit_channel(). Perform deinit only for channels that had been initilized. Signed-off-by: robert-hh --- ports/samd/machine_adc.c | 5 +++++ ports/samd/machine_dac.c | 31 +++++++++++++++++-------------- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/ports/samd/machine_adc.c b/ports/samd/machine_adc.c index f497623a54a..0674f318fea 100644 --- a/ports/samd/machine_adc.c +++ b/ports/samd/machine_adc.c @@ -270,6 +270,9 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f mp_get_buffer_raise(values, &src, MP_BUFFER_READ); if (src.len >= 2) { int freq = mp_obj_get_int(freq_in); + if (self->tc_index == -1) { + self->tc_index = allocate_tc_instance(); + } if (self->dma_channel == -1) { self->dma_channel = allocate_dma_channel(); dma_init(); @@ -331,6 +334,8 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f adc->SWTRIG.bit.START = 1; while (adc->INTFLAG.bit.RESRDY == 0) { } + // Wait a little bit allowing the ADC to settle. + mp_hal_delay_us(15); dma_desc[self->dma_channel].BTCTRL.reg = DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT | diff --git a/ports/samd/machine_dac.c b/ports/samd/machine_dac.c index dcb6c020d56..f19566f61b1 100644 --- a/ports/samd/machine_dac.c +++ b/ports/samd/machine_dac.c @@ -290,14 +290,14 @@ static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) { } if (src.len >= 2) { int freq = mp_obj_get_int(args[2]); + if (self->tc_index == -1) { + self->tc_index = allocate_tc_instance(); + } if (self->dma_channel == -1) { self->dma_channel = allocate_dma_channel(); dma_init(); dma_register_irq(self->dma_channel, dac_irq_handler); } - if (self->tc_index == -1) { - self->tc_index = allocate_tc_instance(); - } // Configure TC; no need to check the return value configure_tc(self->tc_index, freq, 0); self->busy = true; @@ -366,18 +366,21 @@ static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) { static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(dac_write_timed_obj, 3, 4, dac_write_timed); static void dac_deinit_channel(dac_obj_t *self) { - self->initialized = false; - if (self->dma_channel >= 0) { - dac_stop_dma(self->dma_channel, true); - free_dma_channel(self->dma_channel); - self->dma_channel = -1; - } - if (self->tc_index >= 0) { - free_tc_instance(self->tc_index); - self->tc_index = -1; + if (self->initialized) { + self->initialized = false; + + if (self->dma_channel >= 0) { + dac_stop_dma(self->dma_channel, true); + free_dma_channel(self->dma_channel); + self->dma_channel = -1; + } + if (self->tc_index >= 0) { + free_tc_instance(self->tc_index); + self->tc_index = -1; + } + self->callback = MP_OBJ_NULL; + self->busy = false; } - self->callback = MP_OBJ_NULL; - self->busy = false; } // Reset DAC and clear the DMA channel entries in the DAC objects. From 92201f8e92738397e974803d2930081d8772c9f9 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Tue, 24 Oct 2023 10:01:25 +0200 Subject: [PATCH 012/635] samd/machine_adc: Factor out machine.adc_timed() to extmod code. After machine.ADC has been moved to extmod/machine_adc.c. Adding adc.read_timed() and adc.busy() to extmod/machine_adc.c with a corresponding flag to enable them. ADC/DAC timed are by default enabled only at all SAMD51 devices and at SAMD21 devices with an external flash for the file system. Add class constants for the reference voltage source. As far as possible the STM32 names are used, except where they should match common board silkscreen labels. Signed-off-by: robert-hh --- docs/samd/quickref.rst | 38 ++++++++++----------- extmod/machine_adc.c | 22 ++++++++++++ ports/samd/machine_adc.c | 52 +++++++++++++++++------------ ports/samd/machine_dac.c | 6 ++++ ports/samd/mcu/samd21/mpconfigmcu.h | 7 ++++ ports/samd/mcu/samd51/mpconfigmcu.h | 6 ++++ ports/samd/mpconfigport.h | 6 ---- 7 files changed, 90 insertions(+), 47 deletions(-) diff --git a/docs/samd/quickref.rst b/docs/samd/quickref.rst index 4d6894eac17..4998646ef38 100644 --- a/docs/samd/quickref.rst +++ b/docs/samd/quickref.rst @@ -261,7 +261,7 @@ an external ADC. ADC Constructor ``````````````` -.. class:: ADC(dest, *, average=16, bits=12, vref=3, callback=None) +.. class:: ADC(dest, *, average=16, bits=12, vref=ADC.AREF, callback=None) :noindex: On the SAMD21/SAMD51 ADC functionality is available on Pins labelled 'Ann'. @@ -281,16 +281,16 @@ Averaging is used to reduce the noise. With a value of 16 the LSB noise is about 1 digit. The vref=n option sets the reference voltage for the ADC. The default setting is for 3.3V. Other values are: -==== ============================== =============================== -vref SAMD21 SAMD51 -==== ============================== =============================== -0 1.0V voltage reference internal bandgap reference (1V) -1 1/1.48 Analogue voltage supply Analogue voltage supply -2 1/2 Analogue voltage supply 1/2 Analogue voltage supply -3 External reference A External reference A -4 External reference B External reference B -5 - External reference C -==== ============================== =============================== +========= ===== ============================== ============================= +Symbol Value SAMD21 SAMD51 +========= ===== ============================== ============================= +INT_VREF 0 1.0V voltage reference 1V internal bandgap reference +VDDA 1 1/1.48 Analogue voltage supply Analogue voltage supply +VDDA2 2 1/2 Analogue voltage supply 1/2 Analogue voltage supply +AREF 3 External reference A (PA03) External reference A (PA03) +AREFB 4 External reference B (PA04) External reference B (PA04) +AREFC 5 External reference C (PA06) +========= ===== ============================== ============================= The callback keyword option is used for timed ADC sampling. The callback is executed when all data has been sampled. @@ -366,14 +366,14 @@ have 1 DAC channel at GPIO PA02, accepting only 0 as id. SAMD51 devices have The vref arguments defines the output voltage range, the callback option is used for dac_timed(). Suitable values for vref are: -==== ============================ ================================ -vref SAMD21 SAMD51 -==== ============================ ================================ -0 Internal voltage reference Internal bandgap reference (~1V) -1 Analogue voltage supply Analogue voltage supply -2 External reference Unbuffered external reference -3 - Buffered external reference -==== ============================ ================================ +========= ===== ============================ ================================ +Symbol Value SAMD21 SAMD51 +========= ===== ============================ ================================ +INT_VREF 0 Internal voltage reference Internal bandgap reference (~1V) +VDDA 1 Analogue voltage supply Analogue voltage supply +AREF 2 External reference Unbuffered external reference +AREFB 3 Buffered external reference +========= ===== ============================ ================================ DAC Methods diff --git a/extmod/machine_adc.c b/extmod/machine_adc.c index 11f1123dc79..47bc7e10dc5 100644 --- a/extmod/machine_adc.c +++ b/extmod/machine_adc.c @@ -140,6 +140,24 @@ static mp_obj_t machine_adc_read(mp_obj_t self_in) { static MP_DEFINE_CONST_FUN_OBJ_1(machine_adc_read_obj, machine_adc_read); #endif +#if MICROPY_PY_MACHINE_ADC_READ_TIMED +// ADC.read_timed(buf, freq) +static mp_obj_t machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t freq_in) { + machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_int_t freq = mp_obj_get_int(freq_in); + mp_machine_adc_read_timed(self, values, freq); + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_3(machine_adc_read_timed_obj, machine_adc_read_timed); + +// ADC.busy() +static mp_obj_t machine_adc_busy(mp_obj_t self_in) { + machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); + return mp_machine_adc_busy(self); +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_adc_busy_obj, machine_adc_busy); +#endif + static const mp_rom_map_elem_t machine_adc_locals_dict_table[] = { #if MICROPY_PY_MACHINE_ADC_INIT { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_adc_init_obj) }, @@ -164,6 +182,10 @@ static const mp_rom_map_elem_t machine_adc_locals_dict_table[] = { #if MICROPY_PY_MACHINE_ADC_READ { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&machine_adc_read_obj) }, #endif + #if MICROPY_PY_MACHINE_ADC_READ_TIMED + { MP_ROM_QSTR(MP_QSTR_read_timed), MP_ROM_PTR(&machine_adc_read_timed_obj) }, + { MP_ROM_QSTR(MP_QSTR_busy), MP_ROM_PTR(&machine_adc_busy_obj) }, + #endif // A port must add ADC class constants defining the following macro. // It can be defined to nothing if there are no constants. diff --git a/ports/samd/machine_adc.c b/ports/samd/machine_adc.c index 0674f318fea..815c36acaa6 100644 --- a/ports/samd/machine_adc.c +++ b/ports/samd/machine_adc.c @@ -28,17 +28,13 @@ // This file is never compiled standalone, it's included directly from // extmod/machine_adc.c via MICROPY_PY_MACHINE_ADC_INCLUDEFILE. -#if MICROPY_PY_MACHINE_ADC - #include #include "py/obj.h" -#include "py/runtime.h" #include "py/mperrno.h" -#include "py/mphal.h" +#include "mphalport.h" #include "sam.h" #include "pin_af.h" -#include "modmachine.h" #include "samd_soc.h" #include "dma_manager.h" #include "tc_manager.h" @@ -113,8 +109,21 @@ device_mgmt_t device_mgmt[ADC_INST_NUM]; #endif // defined(MCU_SAMD21) -// The ADC class doesn't have any constants for this port. -#define MICROPY_PY_MACHINE_ADC_CLASS_CONSTANTS +#if defined(MCU_SAMD51) +#define MICROPY_PY_MACHINE_SAMD51_ADC_CLASS_CONSTANTS \ + { MP_ROM_QSTR(MP_QSTR_AREFC), MP_ROM_INT(5) }, +#else +#define MICROPY_PY_MACHINE_SAMD51_ADC_CLASS_CONSTANTS +#endif + +// Class constants for the ADC reference sources.. +#define MICROPY_PY_MACHINE_ADC_CLASS_CONSTANTS \ + { MP_ROM_QSTR(MP_QSTR_INT_VREF), MP_ROM_INT(0) }, \ + { MP_ROM_QSTR(MP_QSTR_VDDA), MP_ROM_INT(1) }, \ + { MP_ROM_QSTR(MP_QSTR_VDDA2), MP_ROM_INT(2) }, \ + { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_INT(3) }, \ + { MP_ROM_QSTR(MP_QSTR_AREFB), MP_ROM_INT(4) }, \ + MICROPY_PY_MACHINE_SAMD51_ADC_CLASS_CONSTANTS \ Adc *const adc_bases[] = ADC_INSTS; uint32_t ch_busy_flags = 0; @@ -168,8 +177,7 @@ static void mp_machine_adc_print(const mp_print_t *print, mp_obj_t self_in, mp_p self->adc_config.channel, self->bits, 1 << self->avg, self->vref); } -static mp_obj_t adc_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, - const mp_obj_t *all_args) { +static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { enum { ARG_id, ARG_bits, ARG_average, ARG_vref, ARG_callback }; static const mp_arg_t allowed_args[] = { @@ -263,13 +271,13 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) { return adc->RESULT.reg * (65536 / (1 << self->bits)); } -static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t freq_in) { - machine_adc_obj_t *self = self_in; +#if MICROPY_PY_MACHINE_ADC_READ_TIMED + +static void mp_machine_adc_read_timed(machine_adc_obj_t *self, mp_obj_t values, mp_int_t freq) { Adc *adc = adc_bases[self->adc_config.device]; mp_buffer_info_t src; mp_get_buffer_raise(values, &src, MP_BUFFER_READ); if (src.len >= 2) { - int freq = mp_obj_get_int(freq_in); if (self->tc_index == -1) { self->tc_index = allocate_tc_instance(); } @@ -363,12 +371,19 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f #endif // defined SAMD21 or SAMD51 } - return mp_const_none; } +// busy() : Report, if the ADC device is busy +static mp_obj_t mp_machine_adc_busy(machine_adc_obj_t *self) { + return device_mgmt[self->adc_config.device].busy ? mp_const_true : mp_const_false; +} + +#endif + // deinit() : release the ADC channel static void mp_machine_adc_deinit(machine_adc_obj_t *self) { - busy_flags &= ~((1 << (self->adc_config.device * 16 + self->adc_config.channel))); + ch_busy_flags &= ~((1 << (self->adc_config.device * 16 + self->adc_config.channel))); + #if MICROPY_PY_MACHINE_ADC_READ_TIMED if (self->dma_channel >= 0) { #if defined(MCU_SAMD51) if (self->dma_channel == device_mgmt[self->adc_config.device].dma_channel) { @@ -384,16 +399,9 @@ static void mp_machine_adc_deinit(machine_adc_obj_t *self) { free_tc_instance(self->tc_index); self->tc_index = -1; } + #endif } -// busy() : Report, if the ADC device is busy -static mp_int_t machine_adc_busy(mp_obj_t self_in) { - machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); - return device_mgmt[self->adc_config.device].busy ? true : false; -} - -#endif - #if MICROPY_PY_MACHINE_ADC_READ_TIMED void adc_deinit_all(void) { ch_busy_flags = 0; diff --git a/ports/samd/machine_dac.c b/ports/samd/machine_dac.c index f19566f61b1..2772162f9f9 100644 --- a/ports/samd/machine_dac.c +++ b/ports/samd/machine_dac.c @@ -425,6 +425,12 @@ static const mp_rom_map_elem_t dac_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_busy), MP_ROM_PTR(&machine_dac_busy_obj) }, { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_write_timed), MP_ROM_PTR(&dac_write_timed_obj) }, + { MP_ROM_QSTR(MP_QSTR_INT_VREF), MP_ROM_INT(0) }, + { MP_ROM_QSTR(MP_QSTR_VDDA), MP_ROM_INT(1) }, + { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_INT(2) }, + #if defined(MCU_SAMD51) + { MP_ROM_QSTR(MP_QSTR_AREFB), MP_ROM_INT(3) }, + #endif #endif }; diff --git a/ports/samd/mcu/samd21/mpconfigmcu.h b/ports/samd/mcu/samd21/mpconfigmcu.h index a6be13b2420..ff5b2d5e4a3 100644 --- a/ports/samd/mcu/samd21/mpconfigmcu.h +++ b/ports/samd/mcu/samd21/mpconfigmcu.h @@ -76,6 +76,13 @@ unsigned long trng_random_u32(int delay); #define MICROPY_PY_MACHINE_I2C_TARGET (SAMD21_EXTRA_FEATURES) #endif +#ifndef MICROPY_PY_MACHINE_ADC_READ_TIMED +#define MICROPY_PY_MACHINE_ADC_READ_TIMED (SAMD21_EXTRA_FEATURES) +#endif +#ifndef MICROPY_PY_MACHINE_DAC_WRITE_TIMED +#define MICROPY_PY_MACHINE_DAC_WRITE_TIMED (SAMD21_EXTRA_FEATURES) +#endif + #ifndef MICROPY_PY_MACHINE_PIN_BOARD_CPU #define MICROPY_PY_MACHINE_PIN_BOARD_CPU (1) #endif diff --git a/ports/samd/mcu/samd51/mpconfigmcu.h b/ports/samd/mcu/samd51/mpconfigmcu.h index 974a40f7aa7..e5709d6cdd6 100644 --- a/ports/samd/mcu/samd51/mpconfigmcu.h +++ b/ports/samd/mcu/samd51/mpconfigmcu.h @@ -34,6 +34,12 @@ unsigned long trng_random_u32(void); #ifndef MICROPY_HW_UART_RTSCTS #define MICROPY_HW_UART_RTSCTS (1) #endif +#ifndef MICROPY_PY_MACHINE_ADC_READ_TIMED +#define MICROPY_PY_MACHINE_ADC_READ_TIMED (1) +#endif +#ifndef MICROPY_PY_MACHINE_DAC_WRITE_TIMED +#define MICROPY_PY_MACHINE_DAC_WRITE_TIMED (1) +#endif #define CPU_FREQ (120000000) #define DFLL48M_FREQ (48000000) diff --git a/ports/samd/mpconfigport.h b/ports/samd/mpconfigport.h index faa0b6f446f..fa6b1541224 100644 --- a/ports/samd/mpconfigport.h +++ b/ports/samd/mpconfigport.h @@ -136,12 +136,6 @@ #define MICROPY_PY_MACHINE_I2C_TARGET_HARD_IRQ (1) #define MICROPY_PY_MACHINE_I2C_TARGET_FINALISER (1) -#ifndef MICROPY_PY_MACHINE_DAC_WRITE_TIMED -#define MICROPY_PY_MACHINE_DAC_WRITE_TIMED (1) -#endif -#ifndef MICROPY_PY_MACHINE_ADC_READ_TIMED -#define MICROPY_PY_MACHINE_ADC_READ_TIMED (1) -#endif #if MICROPY_PY_MACHINE_DAC_WRITE_TIMED || MICROPY_PY_MACHINE_ADC_READ_TIMED #define MICROPY_HW_DMA_MANAGER (1) #define MICROPY_HW_TC_MANAGER (1) From 21b3a51aae4603f7cf81843ee55631a2127a9d15 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Fri, 17 Apr 2026 09:18:41 +0200 Subject: [PATCH 013/635] samd/machine_adc: Fix the configuration with averaging enabled. When averaging is selected, the resolution is fixed to 12 bit. The configuration has to be changed to cater for the result shifts. Side change: Remove a duplicated code line in init(). Signed-off-by: robert-hh --- docs/samd/quickref.rst | 3 ++- ports/samd/machine_adc.c | 40 +++++++++++++++++++--------------------- 2 files changed, 21 insertions(+), 22 deletions(-) diff --git a/docs/samd/quickref.rst b/docs/samd/quickref.rst index 4998646ef38..31a91640a5d 100644 --- a/docs/samd/quickref.rst +++ b/docs/samd/quickref.rst @@ -278,7 +278,8 @@ The resolution of the ADC is set by the bits keyword option. The default is 12. Suitable values are 8, 10 and 12. If you need a higher resolution or better accuracy, use an external ADC. The default value of average is 16. Averaging is used to reduce the noise. With a value of 16 the LSB noise is -about 1 digit. The vref=n option sets the reference voltage for the ADC. +about 1 digit. When averaging is enabled, the resolution is forced to +12 bits. The vref=n option sets the reference voltage for the ADC. The default setting is for 3.3V. Other values are: ========= ===== ============================== ============================= diff --git a/ports/samd/machine_adc.c b/ports/samd/machine_adc.c index 815c36acaa6..848b3502088 100644 --- a/ports/samd/machine_adc.c +++ b/ports/samd/machine_adc.c @@ -211,6 +211,11 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args uint32_t avg = log2i(args[ARG_average].u_int); self->avg = (avg <= 10 ? avg : 10); + // Enforce 12 bits with averaging. Maybe raise an exception. + if (self->avg != 0) { + self->bits = 12; + } + uint8_t vref = args[ARG_vref].u_int; if (0 <= vref && vref <= MAX_ADC_VREF) { self->vref = vref; @@ -227,8 +232,6 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args device_mgmt[adc_config.device].self = self; } - // flag the device/channel as being in use. - ch_busy_flags |= (1 << (self->adc_config.device * 16 + self->adc_config.channel)); self->dma_channel = -1; self->tc_index = -1; #endif @@ -241,8 +244,6 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args // read_u16() static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) { Adc *adc = adc_bases[self->adc_config.device]; - // Set the reference voltage. Default: external AREFA. - adc->REFCTRL.reg = adc_vref_table[self->vref]; #if MICROPY_PY_MACHINE_ADC_READ_TIMED if (device_mgmt[self->adc_config.device].busy != 0) { @@ -250,11 +251,15 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) { } #endif + // Set the reference voltage. Default: external AREFA. + adc->REFCTRL.reg = adc_vref_table[self->vref]; + // Average: Accumulate samples and scale them down accordingly + adc->AVGCTRL.reg = self->avg | ADC_AVGCTRL_ADJRES(self->avg < 4 ? self->avg : 4); // Set Input channel and resolution // Select the pin as positive input and gnd as negative input reference, non-diff mode by default adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel; - // set resolution. Scale 8-16 to 0 - 4 for table access. - adc->CTRLB.bit.RESSEL = resolution[(self->bits - 8) / 2]; + // Set the resolution to 16 bit with AVG enabled or to 8-12 bit w/o average. + adc->CTRLB.bit.RESSEL = (self->avg != 0 ? ADC_CTRLB_RESSEL_16BIT_Val : resolution[(self->bits - 8) / 2]); #if defined(MCU_SAMD21) // Stop the ADC sampling by timer @@ -267,8 +272,8 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) { adc->SWTRIG.bit.START = 1; while (adc->INTFLAG.bit.RESRDY == 0) { } - // Get and return the result - return adc->RESULT.reg * (65536 / (1 << self->bits)); + // Get and return the result. When averaging is enabled, the result size is always 12 bit. + return adc->RESULT.reg << (16 - self->bits); } #if MICROPY_PY_MACHINE_ADC_READ_TIMED @@ -286,14 +291,15 @@ static void mp_machine_adc_read_timed(machine_adc_obj_t *self, mp_obj_t values, dma_init(); dma_register_irq(self->dma_channel, adc_irq_handler); } - if (self->tc_index == -1) { - self->tc_index = allocate_tc_instance(); - } + // Set the reference voltage. Default: external AREFA. + adc->REFCTRL.reg = adc_vref_table[self->vref]; + // Average: Accumulate samples and scale them down accordingly + adc->AVGCTRL.reg = self->avg | ADC_AVGCTRL_ADJRES(self->avg < 4 ? self->avg : 4); // Set Input channel and resolution // Select the pin as positive input and gnd as negative input reference, non-diff mode by default adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel; - // set resolution. Scale 8-16 to 0 - 4 for table access. - adc->CTRLB.bit.RESSEL = resolution[(self->bits - 8) / 2]; + // Set the resolution to 16 bit with AVG enabled or to 8-12 bit w/o average. + adc->CTRLB.bit.RESSEL = (self->avg != 0 ? ADC_CTRLB_RESSEL_16BIT_Val : resolution[(self->bits - 8) / 2]); // Configure DMA for halfword output to the DAC #if defined(MCU_SAMD21) @@ -448,10 +454,6 @@ static void adc_init(machine_adc_obj_t *self) { ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity); // Divide a 48MHz clock by 32 to obtain 1.5 MHz clock to adc adc->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV32; - // Select external AREFA as reference voltage. - adc->REFCTRL.reg = self->vref; - // Average: Accumulate samples and scale them down accordingly - adc->AVGCTRL.reg = self->avg | ADC_AVGCTRL_ADJRES(self->avg); // Enable ADC and wait to be ready adc->CTRLA.bit.ENABLE = 1; while (adc->STATUS.bit.SYNCBUSY) { @@ -490,10 +492,6 @@ static void adc_init(machine_adc_obj_t *self) { adc->CTRLA.reg = ADC_CTRLA_PRESCALER_DIV4; // Enable the offset compensation adc->SAMPCTRL.reg = ADC_SAMPCTRL_OFFCOMP; - // Set the reference voltage. Default: external AREFA. - adc->REFCTRL.reg = adc_vref_table[self->vref]; - // Average: Accumulate samples and scale them down accordingly - adc->AVGCTRL.reg = self->avg | ADC_AVGCTRL_ADJRES(self->avg); // Enable ADC and wait to be ready adc->CTRLA.bit.ENABLE = 1; while (adc->SYNCBUSY.bit.ENABLE) { From f5af52985cb26e731a8437061c403e904ea5a287 Mon Sep 17 00:00:00 2001 From: Jim Mussared Date: Fri, 26 May 2023 17:53:00 +1000 Subject: [PATCH 014/635] py/objstr: Add support for bytes.find(int). This adds support for `bytes.find(x)` where x is an integer value. It also extends to `bytearray` as well as the methods `.rfind()`, `.index()` and `.rindex()`. This allows existing Python code that uses integers like this to "just work" (i.e. CPython compatibility is always good). The Python alternative is a bit awkward, i.e. given a byte value, to use find/index you have to make it into a single-element bytes, e.g. `b.find(chr(n).encode())`. Signed-off-by: Jim Mussared --- py/objstr.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/py/objstr.c b/py/objstr.c index e8b2512a246..06afb91fc7f 100644 --- a/py/objstr.c +++ b/py/objstr.c @@ -770,11 +770,29 @@ static mp_obj_t str_finder(size_t n_args, const mp_obj_t *args, int direction, b const mp_obj_type_t *self_type = mp_obj_get_type(args[0]); check_is_str_or_bytes(args[0]); - // check argument type - str_check_arg_type(self_type, args[1]); - GET_STR_DATA_LEN(args[0], haystack, haystack_len); - GET_STR_DATA_LEN(args[1], needle, needle_len); + + mp_int_t val; + byte needle_data; + const byte *needle; + size_t needle_len; + if (self_type != &mp_type_str && mp_obj_get_int_maybe(args[1], &val)) { + // Allow {bytes/bytearray}.{find,index}(int). + #if MICROPY_FULL_CHECKS + if (val < 0 || val > 255) { + mp_raise_ValueError(MP_ERROR_TEXT("bytes value out of range")); + } + #endif + needle_data = val; + needle = &needle_data; + needle_len = 1; + } else { + // check argument type + str_check_arg_type(self_type, args[1]); + GET_STR_DATA_LEN(args[1], needle_tmp, needle_len_tmp); + needle = needle_tmp; + needle_len = needle_len_tmp; + } const byte *start = haystack; const byte *end = haystack + haystack_len; From b7e32206b1449f64c4fcd6ba3c76417e515df21c Mon Sep 17 00:00:00 2001 From: Jim Mussared Date: Fri, 26 May 2023 21:54:20 +1000 Subject: [PATCH 015/635] tests/basics: Add tests for bytes/bytearray.find/index(int). Signed-off-by: Jim Mussared --- tests/basics/bytearray_byte_operations.py | 17 +++- tests/basics/bytes_find.py | 28 +++++++ tests/basics/bytes_index.py | 99 +++++++++++++++++++++++ tests/basics/string_find.py | 1 + tests/basics/string_index.py | 6 ++ 5 files changed, 147 insertions(+), 4 deletions(-) create mode 100644 tests/basics/bytes_index.py diff --git a/tests/basics/bytearray_byte_operations.py b/tests/basics/bytearray_byte_operations.py index 48b08ab2619..794fe8cafa2 100644 --- a/tests/basics/bytearray_byte_operations.py +++ b/tests/basics/bytearray_byte_operations.py @@ -2,6 +2,7 @@ print(bytearray(b"hello world").find(b"ll")) print(bytearray(b"hello\x00world").rfind(b"l")) +print(bytearray(b"hello world").find(ord(b"l"))) print(bytearray(b"abc efg ").strip(b"g a")) print(bytearray(b" spacious ").lstrip()) @@ -14,10 +15,18 @@ print(bytearray(b"asdfasdf").replace(b"a", b"b")) -print("00\x0000".index("0", 0)) -print("00\x0000".index("0", 3)) -print("00\x0000".rindex("0", 0)) -print("00\x0000".rindex("0", 3)) +print(b"00\x0000".index(b"0", 0)) +print(b"00\x0000".index(b"0", 3)) +print(b"00\x0000".index(ord("0"), 0)) +print(b"00\x0000".index(ord("0"), 3)) +print(b"00\x0000".index(0, 0)) +try: + print(b"00\x0000".index(0, 3)) +except ValueError: + print("ValueError") +print(b"00\x0000".index(b"0", 3)) +print(b"00\x0000".rindex(b"0", 0)) +print(b"00\x0000".rindex(b"0", 3)) print(bytearray(b"foobar").endswith(b"bar")) print(bytearray(b"1foo").startswith(b"foo", 1)) diff --git a/tests/basics/bytes_find.py b/tests/basics/bytes_find.py index 75ef9796cd1..4a2707cc531 100644 --- a/tests/basics/bytes_find.py +++ b/tests/basics/bytes_find.py @@ -21,6 +21,34 @@ print(b"0000".find(b'1', 3)) print(b"0000".find(b'1', 4)) print(b"0000".find(b'1', 5)) +print(b"0000".find(ord(b'0'))) +print(b"0000".find(ord(b'0'), 0)) +print(b"0000".find(ord(b'0'), 1)) +print(b"0000".find(ord(b'0'), 2)) +print(b"0000".find(ord(b'0'), 3)) +print(b"0000".find(ord(b'0'), 4)) +print(b"0000".find(ord(b'0'), 5)) +print(b"0000".find(ord(b'x'), 3)) +print(b"0000".find(ord(b'1'), 3)) +print(b"0000".find(ord(b'1'), 4)) +print(b"0000".find(ord(b'1'), 5)) # Non-ascii values (make sure not treated as unicode-like) print(b"\x80abc".find(b"a", 1)) + +# Int-like conversion. +print(b"00\x0000".find(b'0', True)) + +# Out of bounds int. +try: + print(b"0000".find(b'0', -1)) +except ValueError: + print("ValueError") +try: + print(b"0000".find(b'0', 256)) +except ValueError: + print("ValueError") +try: + print(b"0000".find(b'0', 91273611)) +except ValueError: + print("ValueError") diff --git a/tests/basics/bytes_index.py b/tests/basics/bytes_index.py new file mode 100644 index 00000000000..08ed46e4a9c --- /dev/null +++ b/tests/basics/bytes_index.py @@ -0,0 +1,99 @@ +print(b"hello world".index(b"ll")) +print(b"hello world".index(b"ll", None)) +print(b"hello world".index(b"ll", 1)) +print(b"hello world".index(b"ll", 1, None)) +print(b"hello world".index(b"ll", None, None)) +print(b"hello world".index(b"ll", 1, -1)) +try: + print(b"hello world".index(b"ll", 1, 1)) +except ValueError: + print("ValueError") +try: + print(b"hello world".index(b"ll", 1, 2)) +except ValueError: + print("ValueError") +try: + print(b"hello world".index(b"ll", 1, 3)) +except ValueError: + print("ValueError") +print(b"hello world".index(b"ll", 1, 4)) +print(b"hello world".index(b"ll", 1, 5)) +print(b"hello world".index(b"ll", -100)) +print(b"0000".index(b'0')) +print(b"0000".index(b'0', 0)) +print(b"0000".index(b'0', 1)) +print(b"0000".index(b'0', 2)) +print(b"0000".index(b'0', 3)) +try: + print(b"0000".index(b'0', 4)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(b'0', 5)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(b'-1', 3)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(b'1', 3)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(b'1', 4)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(b'1', 5)) +except ValueError: + print("ValueError") +print(b"0000".index(ord(b'0'))) +print(b"0000".index(ord(b'0'), 0)) +print(b"0000".index(ord(b'0'), 1)) +print(b"0000".index(ord(b'0'), 2)) +print(b"0000".index(ord(b'0'), 3)) +try: + print(b"0000".index(ord(b'0'), 4)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(ord(b'0'), 5)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(ord(b'x'), 3)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(ord(b'1'), 3)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(ord(b'1'), 4)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(ord(b'1'), 5)) +except ValueError: + print("ValueError") + +# Non-ascii values (make sure not treated as unicode-like) +print(b"\x80abc".index(b"a", 1)) + +# Int-like conversion. +print(b"00\x0000".index(b'0', True)) + +# Out of bounds int. +try: + print(b"0000".index(b'0', -1)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(b'0', 256)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(b'0', 91273611)) +except ValueError: + print("ValueError") diff --git a/tests/basics/string_find.py b/tests/basics/string_find.py index f9fcad3e579..f37064ad291 100644 --- a/tests/basics/string_find.py +++ b/tests/basics/string_find.py @@ -24,6 +24,7 @@ print("aaaaaaaaaaa".find("bbb", 9, 2)) try: + # Only works on bytes/bytearray. 'abc'.find(1) except TypeError: print('TypeError') diff --git a/tests/basics/string_index.py b/tests/basics/string_index.py index 31f6900e6c1..328f2dff54c 100644 --- a/tests/basics/string_index.py +++ b/tests/basics/string_index.py @@ -76,3 +76,9 @@ print("Raised ValueError") else: print("Did not raise ValueError") + +try: + # Only works on bytes/bytearray. + 'abc'.index(1) +except TypeError: + print('TypeError') From 05fcc8c580c7ddb604c730458f7080b024cab07b Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 23 Apr 2026 23:26:04 +1000 Subject: [PATCH 016/635] tests/basics: Add coverage for bytes find/index with out-of-bounds arg. Signed-off-by: Damien George --- tests/basics/bytes_find.py | 10 ++++++++++ tests/basics/bytes_index.py | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/tests/basics/bytes_find.py b/tests/basics/bytes_find.py index 4a2707cc531..1ecbf13b0cf 100644 --- a/tests/basics/bytes_find.py +++ b/tests/basics/bytes_find.py @@ -52,3 +52,13 @@ print(b"0000".find(b'0', 91273611)) except ValueError: print("ValueError") + +# Out of bounds search argument. +try: + print(b"0000".find(-1)) +except ValueError: + print("ValueError") +try: + print(b"0000".find(256)) +except ValueError: + print("ValueError") diff --git a/tests/basics/bytes_index.py b/tests/basics/bytes_index.py index 08ed46e4a9c..d99b325192e 100644 --- a/tests/basics/bytes_index.py +++ b/tests/basics/bytes_index.py @@ -97,3 +97,13 @@ print(b"0000".index(b'0', 91273611)) except ValueError: print("ValueError") + +# Out of bounds search argument. +try: + print(b"0000".index(-1)) +except ValueError: + print("ValueError") +try: + print(b"0000".index(256)) +except ValueError: + print("ValueError") From 01df5a1f0512fdabd8d40e465b07eb12f0573744 Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Mon, 3 Nov 2025 10:01:34 -0700 Subject: [PATCH 017/635] py/py.mk: Add LIBS_USERMOD to LIBS. This enables C++ modules to correctly postion -l linker flags at the end of the flags instead of at the start. Updated the example C++ micropython.mk accordingly. Signed-off-by: Dryw Wade --- examples/usercmodule/cppexample/micropython.mk | 5 ++++- py/py.mk | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/examples/usercmodule/cppexample/micropython.mk b/examples/usercmodule/cppexample/micropython.mk index 0071d4fcc72..cf4c6bd9b3a 100644 --- a/examples/usercmodule/cppexample/micropython.mk +++ b/examples/usercmodule/cppexample/micropython.mk @@ -8,5 +8,8 @@ SRC_USERMOD_CXX += $(CPPEXAMPLE_MOD_DIR)/example.cpp CFLAGS_USERMOD += -I$(CPPEXAMPLE_MOD_DIR) CXXFLAGS_USERMOD += -I$(CPPEXAMPLE_MOD_DIR) -std=c++11 +# Add any necessary paths to library files. +# LDFLAGS_USERMOD += -Lpath/to/libs + # We use C++ features so have to link against the standard library. -LDFLAGS_USERMOD += -lstdc++ +LIBS_USERMOD += -lstdc++ diff --git a/py/py.mk b/py/py.mk index 932c47ef177..b37e3cf5798 100644 --- a/py/py.mk +++ b/py/py.mk @@ -47,6 +47,7 @@ SRC_USERMOD_LIB_ASM := CFLAGS_USERMOD := CXXFLAGS_USERMOD := LDFLAGS_USERMOD := +LIBS_USERMOD := # Backwards compatibility with older user c modules that set SRC_USERMOD # added to SRC_USERMOD_C below @@ -69,6 +70,7 @@ SRC_USERMOD_PATHFIX_LIB_ASM += $(patsubst $(USER_C_MODULES)/%.S,%.S,$(SRC_USERMO CFLAGS += $(CFLAGS_USERMOD) CXXFLAGS += $(CXXFLAGS_USERMOD) LDFLAGS += $(LDFLAGS_USERMOD) +LIBS += $(LIBS_USERMOD) SRC_QSTR += $(SRC_USERMOD_PATHFIX_C) $(SRC_USERMOD_PATHFIX_CXX) PY_O += $(addprefix $(BUILD)/, $(SRC_USERMOD_PATHFIX_C:.c=.o)) From 234bac45d33f410fb3b56a87cf56266e96a71c66 Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Tue, 4 Nov 2025 10:38:50 -0700 Subject: [PATCH 018/635] py/mkrules.mk: Change LIB to LIBS. Same in ports/windows/Makefile to be consistent with other ports. Signed-off-by: Dryw Wade --- ports/windows/Makefile | 2 +- py/mkrules.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/windows/Makefile b/ports/windows/Makefile index 8d371ed8ac3..6e206e7f23c 100644 --- a/ports/windows/Makefile +++ b/ports/windows/Makefile @@ -86,7 +86,7 @@ SRC_C += shared/readline/readline.c SRC_C += shared/runtime/pyexec.c endif -LIB += -lws2_32 +LIBS += -lws2_32 # List of sources for qstr extraction SRC_QSTR += $(SRC_C) $(SRC_CXX) $(SHARED_SRC_C) diff --git a/py/mkrules.mk b/py/mkrules.mk index 6ac731b368b..f94bcea2ae1 100644 --- a/py/mkrules.mk +++ b/py/mkrules.mk @@ -259,7 +259,7 @@ $(BUILD)/$(PROG): $(OBJ) $(ECHO) "LINK $@" # Do not pass COPT here - it's *C* compiler optimizations. For example, # we may want to compile using Thumb, but link with non-Thumb libc. - $(Q)$(CC) -o $@ $^ $(LIB) $(LDFLAGS) + $(Q)$(CC) -o $@ $^ $(LIBS) $(LDFLAGS) ifndef DEBUG ifdef STRIP $(Q)$(STRIP) $(STRIPFLAGS_EXTRA) $@ From 416eadf9627398467cd1aea4eecf17ddedb8dbe3 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 8 Apr 2026 11:43:41 +1000 Subject: [PATCH 019/635] ports: Use mp_obj_is_float instead of mp_obj_is_type. `mp_obj_is_float` must be used in case the object representation is C or D. Signed-off-by: Damien George --- ports/renesas-ra/timer.c | 2 +- ports/stm32/timer.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ports/renesas-ra/timer.c b/ports/renesas-ra/timer.c index 286bc4d0fb5..5038936a833 100644 --- a/ports/renesas-ra/timer.c +++ b/ports/renesas-ra/timer.c @@ -339,7 +339,7 @@ static mp_obj_t pyb_timer_freq(size_t n_args, const mp_obj_t *args) { uint32_t freq; if (0) { #if MICROPY_PY_BUILTINS_FLOAT - } else if (mp_obj_is_type(args[1], &mp_type_float)) { + } else if (mp_obj_is_float(args[1])) { freq = (int)mp_obj_get_float(args[1]); #endif } else { diff --git a/ports/stm32/timer.c b/ports/stm32/timer.c index a2f48139ee4..d70878267e1 100644 --- a/ports/stm32/timer.c +++ b/ports/stm32/timer.c @@ -450,7 +450,7 @@ static uint32_t compute_prescaler_period_from_freq(pyb_timer_obj_t *self, mp_obj uint32_t period; if (0) { #if MICROPY_PY_BUILTINS_FLOAT - } else if (mp_obj_is_type(freq_in, &mp_type_float)) { + } else if (mp_obj_is_float(freq_in)) { float freq = mp_obj_get_float_to_f(freq_in); if (freq <= 0) { goto bad_freq; @@ -545,7 +545,7 @@ static uint32_t compute_pwm_value_from_percent(uint32_t period, mp_obj_t percent uint32_t cmp; if (0) { #if MICROPY_PY_BUILTINS_FLOAT - } else if (mp_obj_is_type(percent_in, &mp_type_float)) { + } else if (mp_obj_is_float(percent_in)) { mp_float_t percent = mp_obj_get_float(percent_in); if (percent <= 0.0) { cmp = 0; From d6a1d371567ef264dfff1ae7154e4773ab2ab09d Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 8 Apr 2026 11:44:18 +1000 Subject: [PATCH 020/635] py/obj: Add assert that float isn't used with mp_obj_is_type. Some object representations have floats as literal objects (ie not heap allocated) and in such a case using `mp_obj_is_type(t, &mp_type_float)` will always return false. So add a compile-time assertion to force the correct usage. Signed-off-by: Damien George --- py/obj.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/py/obj.h b/py/obj.h index 4683f8a719f..c7933cd867c 100644 --- a/py/obj.h +++ b/py/obj.h @@ -117,7 +117,7 @@ extern const struct _mp_obj_float_t mp_const_float_inf_obj; extern const struct _mp_obj_float_t mp_const_float_nan_obj; #endif -#define mp_obj_is_float(o) mp_obj_is_type((o), &mp_type_float) +#define mp_obj_is_float(o) mp_obj_is_exact_type((o), &mp_type_float) mp_float_t mp_obj_float_get(mp_obj_t self_in); mp_obj_t mp_obj_new_float(mp_float_t value); #endif @@ -162,7 +162,7 @@ extern const struct _mp_obj_float_t mp_const_float_inf_obj; extern const struct _mp_obj_float_t mp_const_float_nan_obj; #endif -#define mp_obj_is_float(o) mp_obj_is_type((o), &mp_type_float) +#define mp_obj_is_float(o) mp_obj_is_exact_type((o), &mp_type_float) mp_float_t mp_obj_float_get(mp_obj_t self_in); mp_obj_t mp_obj_new_float(mp_float_t value); #endif @@ -986,8 +986,13 @@ void *mp_obj_malloc_with_finaliser_helper(size_t num_bytes, const mp_obj_type_t MP_STATIC_ASSERT_NONCONSTEXPR((t) != &mp_type_str), assert((t) != &mp_type_str), \ MP_STATIC_ASSERT_NONCONSTEXPR((t) != &mp_type_NoneType), assert((t) != &mp_type_NoneType), \ 1) +#if MICROPY_PY_BUILTINS_FLOAT +#define mp_type_assert_not_float(t) (MP_STATIC_ASSERT_NONCONSTEXPR((t) != &mp_type_float), assert((t) != &mp_type_float), 1) +#else +#define mp_type_assert_not_float(t) (1) +#endif -#define mp_obj_is_type(o, t) (mp_type_assert_not_bool_int_str_nonetype(t) && mp_obj_is_exact_type(o, t)) +#define mp_obj_is_type(o, t) (mp_type_assert_not_bool_int_str_nonetype(t) && mp_type_assert_not_float(t) && mp_obj_is_exact_type(o, t)) #if MICROPY_OBJ_IMMEDIATE_OBJS // bool's are immediates, not real objects, so test for the 2 possible values. #define mp_obj_is_bool(o) ((o) == mp_const_false || (o) == mp_const_true) From a254bbca791007f15be4e5a6abda307cc526af26 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Thu, 16 Apr 2026 13:48:08 -0500 Subject: [PATCH 021/635] py/nlrx86: Fix nlr_push to build with Clang 19. This version is believed to work from Clang 3.0 to 22.1.0 (all versions on godbolt at the time of writing). Clang rejects the `(void)x;` notation for a used variable in a naked asm function, so do this only conditionally. Introduces use of `__builtin_unreachable()` with gcc. This saves 1 byte by causing gcc not to emit an `ud2` opcode at the end. However, the unreachable sanitizer (enabled by default(!) on Ubuntu 24.04 with gcc version 13.3.0) corrupts the ebx register, so it must be disabled. Clang does not accept `__builtin_unreachable` or `return 0;` here, UNREACHABLE must expand to nothing. Closes: #17415 Signed-off-by: Jeff Epler --- py/nlrx86.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/py/nlrx86.c b/py/nlrx86.c index 26bf0dc6ccb..82e139dd8e8 100644 --- a/py/nlrx86.c +++ b/py/nlrx86.c @@ -40,23 +40,35 @@ __attribute__((used)) unsigned int nlr_push_tail(nlr_buf_t *nlr); #endif #if !defined(__clang__) && defined(__GNUC__) && __GNUC__ >= 8 -// Since gcc 8.0 the naked attribute is supported -#define USE_NAKED (1) -#define UNDO_PRELUDE (0) +// Since gcc 8.0 the naked and no-sanitize attributes are supported + #define NLR_PUSH_ATTRIBUTE __attribute__((naked, no_sanitize("unreachable"))) + #define UNDO_PRELUDE (0) + #define ARG_USED(x) (void)x; + #define NLR_UNREACHABLE __builtin_unreachable(); #elif defined(__ZEPHYR__) || defined(__ANDROID__) // Zephyr and Android use a different calling convention by default -#define USE_NAKED (0) -#define UNDO_PRELUDE (0) + #define NLR_PUSH_ATTRIBUTE /* NOTHING */ + #define UNDO_PRELUDE (0) + #define ARG_USED(x) (void)x; + #define NLR_UNREACHABLE return 0; +#elif defined(__clang__) +// clang on Ubuntu 24.04 enables -fsanitize=unreachable by default, but this +// destroys the content of the ebx register. + #define NLR_PUSH_ATTRIBUTE __attribute__((naked, no_sanitize("unreachable"))) + #define UNDO_PRELUDE (0) + #define ARG_USED(x) /* NOTHING */ + #define NLR_UNREACHABLE /* NOTHING */ #else -#define USE_NAKED (0) -#define UNDO_PRELUDE (1) +// gcc before 8 unavoidably emits a 'push %ebp' prologue instruction + #define NLR_PUSH_ATTRIBUTE /* NOTHING */ + #define UNDO_PRELUDE (1) + #define ARG_USED(x) (void)x; + #define NLR_UNREACHABLE return 0; #endif -#if USE_NAKED -__attribute__((naked)) -#endif +NLR_PUSH_ATTRIBUTE unsigned int nlr_push(nlr_buf_t *nlr) { - (void)nlr; + ARG_USED(nlr) __asm volatile ( #if UNDO_PRELUDE @@ -73,9 +85,7 @@ unsigned int nlr_push(nlr_buf_t *nlr) { "jmp nlr_push_tail \n" // do the rest in C ); - #if !USE_NAKED - return 0; // needed to silence compiler warning - #endif + NLR_UNREACHABLE } MP_NORETURN void nlr_jump(void *val) { From 5e94df1e5d2eed090742d1f1a569d6758bc108ca Mon Sep 17 00:00:00 2001 From: Jeongseop Lim Date: Sat, 25 Apr 2026 16:29:13 +0900 Subject: [PATCH 022/635] py/modbuiltins: Treat pow(x, y, None) as pow(x, y). CPython's _PyNumber_PowerNoMod normalises a None modulus to "no modulus" and dispatches to the 2-argument power path, so e.g. pow(2, -3, None) returns 0.125. MicroPython previously fell through to the integer-only 3-arg path and raised TypeError. Handle args[2] == mp_const_none at the entry of mp_builtin_pow so the existing MP_BINARY_OP_POWER handlers decide the result type. Signed-off-by: Jeongseop Lim --- py/modbuiltins.c | 25 ++++++++++++++----------- tests/basics/builtin_pow3.py | 6 ++++++ 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/py/modbuiltins.c b/py/modbuiltins.c index 6f085f2df38..9617b8fcdae 100644 --- a/py/modbuiltins.c +++ b/py/modbuiltins.c @@ -364,18 +364,21 @@ static mp_obj_t mp_builtin_ord(mp_obj_t o_in) { MP_DEFINE_CONST_FUN_OBJ_1(mp_builtin_ord_obj, mp_builtin_ord); static mp_obj_t mp_builtin_pow(size_t n_args, const mp_obj_t *args) { - switch (n_args) { - case 2: - return mp_binary_op(MP_BINARY_OP_POWER, args[0], args[1]); - default: - #if !MICROPY_PY_BUILTINS_POW3 - mp_raise_NotImplementedError(MP_ERROR_TEXT("3-arg pow() not supported")); - #elif MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_MPZ - return mp_binary_op(MP_BINARY_OP_MODULO, mp_binary_op(MP_BINARY_OP_POWER, args[0], args[1]), args[2]); - #else - return mp_obj_int_pow3(args[0], args[1], args[2]); - #endif + // Treat pow(x, y, None) as pow(x, y), matching CPython. + if (n_args == 2 + #if MICROPY_PY_BUILTINS_POW3 + || args[2] == mp_const_none + #endif + ) { + return mp_binary_op(MP_BINARY_OP_POWER, args[0], args[1]); } + #if !MICROPY_PY_BUILTINS_POW3 + mp_raise_NotImplementedError(MP_ERROR_TEXT("3-arg pow() not supported")); + #elif MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_MPZ + return mp_binary_op(MP_BINARY_OP_MODULO, mp_binary_op(MP_BINARY_OP_POWER, args[0], args[1]), args[2]); + #else + return mp_obj_int_pow3(args[0], args[1], args[2]); + #endif } MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_builtin_pow_obj, 2, 3, mp_builtin_pow); diff --git a/tests/basics/builtin_pow3.py b/tests/basics/builtin_pow3.py index 94e657bc441..2dbe0d33e4b 100644 --- a/tests/basics/builtin_pow3.py +++ b/tests/basics/builtin_pow3.py @@ -28,3 +28,9 @@ print(pow(4, 5, "z")) except TypeError: print("TypeError expected") + +# pow(x, y, None) is equivalent to pow(x, y) +print(pow(0, 1, None)) +print(pow(1, 0, None)) +print(pow(-2, 3, None)) +print(pow(3, 8, None)) From 72d4c4df45aac2cf62a8c72b458c5a5ada7402ef Mon Sep 17 00:00:00 2001 From: radiofan Date: Wed, 28 Jan 2026 16:02:51 +0700 Subject: [PATCH 023/635] py/builtinhelp: Add options for changing help('modules') format. This commit allow to change count and width of columns for help('modules') output by mpconfigport.h. Signed-off-by: radiofan --- py/builtinhelp.c | 16 +++++++++++----- py/mpconfig.h | 10 ++++++++++ 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/py/builtinhelp.c b/py/builtinhelp.c index 59d7e26ac66..ccbbbf91629 100644 --- a/py/builtinhelp.c +++ b/py/builtinhelp.c @@ -33,6 +33,14 @@ #if MICROPY_PY_BUILTINS_HELP +#if MICROPY_PY_BUILTINS_HELP_NUM_COLUMNS <= 0 +#error "MICROPY_PY_BUILTINS_HELP_NUM_COLUMNS must be more than 0" +#endif + +#if MICROPY_PY_BUILTINS_HELP_COLUMN_WIDTH <= 0 +#error "MICROPY_PY_BUILTINS_HELP_COLUMN_WIDTH must be more than 0" +#endif + const char mp_help_default_text[] = "Welcome to MicroPython!\n" "\n" @@ -93,12 +101,10 @@ static void mp_help_print_modules(void) { mp_obj_list_sort(1, &list, (mp_map_t *)&mp_const_empty_map); // print the list of modules in a column-first order - #define NUM_COLUMNS (4) - #define COLUMN_WIDTH (18) size_t len; mp_obj_t *items; mp_obj_list_get(list, &len, &items); - unsigned int num_rows = (len + NUM_COLUMNS - 1) / NUM_COLUMNS; + unsigned int num_rows = (len + MICROPY_PY_BUILTINS_HELP_NUM_COLUMNS - 1) / MICROPY_PY_BUILTINS_HELP_NUM_COLUMNS; for (unsigned int i = 0; i < num_rows; ++i) { unsigned int j = i; for (;;) { @@ -107,9 +113,9 @@ static void mp_help_print_modules(void) { if (j >= len) { break; } - int gap = COLUMN_WIDTH - l; + int gap = MICROPY_PY_BUILTINS_HELP_COLUMN_WIDTH - l; while (gap < 1) { - gap += COLUMN_WIDTH; + gap += MICROPY_PY_BUILTINS_HELP_COLUMN_WIDTH; } while (gap--) { mp_print_str(MP_PYTHON_PRINTER, " "); diff --git a/py/mpconfig.h b/py/mpconfig.h index 0d81898537a..f46e79911ed 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -1569,6 +1569,16 @@ typedef time_t mp_timestamp_t; #define MICROPY_PY_BUILTINS_HELP_MODULES (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_EXTRA_FEATURES) #endif +// Use this to configure output of help('modules') +#ifndef MICROPY_PY_BUILTINS_HELP_NUM_COLUMNS +#define MICROPY_PY_BUILTINS_HELP_NUM_COLUMNS (4) +#endif + +// Use this to configure output of help('modules') +#ifndef MICROPY_PY_BUILTINS_HELP_COLUMN_WIDTH +#define MICROPY_PY_BUILTINS_HELP_COLUMN_WIDTH (18) +#endif + // Whether to provide mem-info related functions in micropython module #ifndef MICROPY_PY_MICROPYTHON_MEM_INFO #define MICROPY_PY_MICROPYTHON_MEM_INFO (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_EXTRA_FEATURES) From 88007335ff51fd74b8e47d8f3a36ca9b46597fb6 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Apr 2026 07:29:45 +1000 Subject: [PATCH 024/635] lib/nrfx: Update submodule to v3.14.0. Signed-off-by: Andrew Leech --- lib/nrfx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/nrfx b/lib/nrfx index 7a4c9d946cf..11f57e578c7 160000 --- a/lib/nrfx +++ b/lib/nrfx @@ -1 +1 @@ -Subproject commit 7a4c9d946cf1801771fc180acdbf7b878f270093 +Subproject commit 11f57e578c7feea13f21c79ea0efab2630ac68c7 From a6f90f38a62c4201cd35c03ed9e28b46cfb25456 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Apr 2026 07:29:54 +1000 Subject: [PATCH 025/635] nrf: Adapt port configuration and startup for nrfx v3. Add API version macros, convert NRFX_CHECK config to literal 0/1, add NRF_GPIOTE0 compat alias, implement required nrfx_glue.h macros (atomics, CLZ/CTZ, cache, event readback, IRQ pending), add haly/helpers include paths and new source files, and update startup_nrf52840.c IRQ handler names to match the nrfx v3 MDK renames in nrf52840_name_change.h. Signed-off-by: Andrew Leech --- ports/nrf/Makefile | 7 ++ ports/nrf/device/startup_nrf52840.c | 48 ++++---- ports/nrf/nrfx_config.h | 175 ++++++++++++++++++++++------ ports/nrf/nrfx_glue.h | 36 ++++++ 4 files changed, 208 insertions(+), 58 deletions(-) diff --git a/ports/nrf/Makefile b/ports/nrf/Makefile index dc46ab1ec46..546c17709e5 100644 --- a/ports/nrf/Makefile +++ b/ports/nrf/Makefile @@ -88,6 +88,8 @@ INC += -I../../lib/nrfx/drivers INC += -I../../lib/nrfx/drivers/include INC += -I../../lib/nrfx/mdk INC += -I../../lib/nrfx/hal +INC += -I../../lib/nrfx/haly +INC += -I../../lib/nrfx/helpers INC += -I../../lib/nrfx/drivers/src/ INC += -I../../shared/readline @@ -99,6 +101,7 @@ SYSTEM_C_SRC := ifeq ($(MCU_SUB_VARIANT),nrf51822) SYSTEM_C_SRC += $(addprefix lib/nrfx/mdk/, system_nrf51.c) NRF_DEFINES += -D$(MCU_VARIANT_UPPER) + NRF_DEFINES += -DNRF51822_XXAA else ifeq ($(MCU_SUB_VARIANT),nrf52832) SYSTEM_C_SRC += $(addprefix lib/nrfx/mdk/, system_nrf52.c) NRF_DEFINES += -D$(MCU_VARIANT_UPPER) @@ -224,6 +227,10 @@ SRC_NRFX += $(addprefix lib/nrfx/drivers/src/,\ nrfx_clock.c \ ) +SRC_NRFX += \ + lib/nrfx/soc/nrfx_atomic.c \ + lib/nrfx/helpers/nrfx_flag32_allocator.c + SRC_C += \ main.c \ mphalport.c \ diff --git a/ports/nrf/device/startup_nrf52840.c b/ports/nrf/device/startup_nrf52840.c index 288b13820f5..f7696346e74 100644 --- a/ports/nrf/device/startup_nrf52840.c +++ b/ports/nrf/device/startup_nrf52840.c @@ -70,11 +70,11 @@ void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Han void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CLOCK_POWER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void RADIO_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTE0_UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_UARTE0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void NFCT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void GPIOTE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void SAADC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); @@ -85,17 +85,17 @@ void RTC0_IRQHandler (void) __attribute__ ((weak, alias("Default_Han void TEMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void ECB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void CCM_AAR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AAR_CCM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void RTC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void QDEC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void COMP_LPCOMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI0_EGU0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI1_EGU1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI2_EGU2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI3_EGU3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI4_EGU4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI5_EGU5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EGU0_SWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EGU1_SWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EGU2_SWI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EGU3_SWI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EGU4_SWI4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EGU5_SWI5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void TIMER3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void TIMER4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void PWM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); @@ -103,7 +103,7 @@ void PDM_IRQHandler (void) __attribute__ ((weak, alias("Default_Han void MWU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void PWM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void PWM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_SPIM2_SPIS2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void RTC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void I2S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); @@ -133,11 +133,11 @@ const func __Vectors[] __attribute__ ((section(".isr_vector"),used)) = { SysTick_Handler, /* External Interrupts */ - POWER_CLOCK_IRQHandler, + CLOCK_POWER_IRQHandler, RADIO_IRQHandler, - UARTE0_UART0_IRQHandler, - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, + UART0_UARTE0_IRQHandler, + SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0_IRQHandler, + SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1_IRQHandler, NFCT_IRQHandler, GPIOTE_IRQHandler, SAADC_IRQHandler, @@ -148,17 +148,17 @@ const func __Vectors[] __attribute__ ((section(".isr_vector"),used)) = { TEMP_IRQHandler, RNG_IRQHandler, ECB_IRQHandler, - CCM_AAR_IRQHandler, + AAR_CCM_IRQHandler, WDT_IRQHandler, RTC1_IRQHandler, QDEC_IRQHandler, COMP_LPCOMP_IRQHandler, - SWI0_EGU0_IRQHandler, - SWI1_EGU1_IRQHandler, - SWI2_EGU2_IRQHandler, - SWI3_EGU3_IRQHandler, - SWI4_EGU4_IRQHandler, - SWI5_EGU5_IRQHandler, + EGU0_SWI0_IRQHandler, + EGU1_SWI1_IRQHandler, + EGU2_SWI2_IRQHandler, + EGU3_SWI3_IRQHandler, + EGU4_SWI4_IRQHandler, + EGU5_SWI5_IRQHandler, TIMER3_IRQHandler, TIMER4_IRQHandler, PWM0_IRQHandler, @@ -168,7 +168,7 @@ const func __Vectors[] __attribute__ ((section(".isr_vector"),used)) = { MWU_IRQHandler, PWM1_IRQHandler, PWM2_IRQHandler, - SPIM2_SPIS2_SPI2_IRQHandler, + SPI2_SPIM2_SPIS2_IRQHandler, RTC2_IRQHandler, I2S_IRQHandler, FPU_IRQHandler, diff --git a/ports/nrf/nrfx_config.h b/ports/nrf/nrfx_config.h index c38af62145f..29e32e21c14 100644 --- a/ports/nrf/nrfx_config.h +++ b/ports/nrf/nrfx_config.h @@ -31,6 +31,11 @@ #include "py/mpconfig.h" #include "nrf.h" +// nrfx v3 API version selection +#define NRFX_CONFIG_API_VER_MAJOR 3 +#define NRFX_CONFIG_API_VER_MINOR 14 +#define NRFX_CONFIG_API_VER_MICRO 0 + // Port specific defines #ifndef NRFX_LOG_ENABLED #define NRFX_LOG_ENABLED 0 @@ -49,6 +54,12 @@ #define GPIO_COUNT 1 #endif +// nrfx v3 instance macros expect NRF_GPIOTE0 but nrf51/nrf52 MDK +// only defines NRF_GPIOTE (single instance, no numeric suffix). +#if defined(NRF51) || defined(NRF52_SERIES) +#define NRF_GPIOTE0 NRF_GPIOTE +#endif + #if defined(NRF52840) // for tinyusb // #define NRFX_IRQ_IS_ENABLED 1 @@ -58,6 +69,9 @@ #endif #define NRFX_GPIOTE_ENABLED 1 +#if !defined(NRF9160_XXAA) +#define NRFX_GPIOTE0_ENABLED 1 +#endif #define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 #if NRF51 #define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 3 @@ -92,18 +106,32 @@ #define NRFX_UARTE3_ENABLED 1 #endif +// nrfx v3 NRFX_CHECK() requires literal 0/1 values, not C expressions. + #if defined(NRF51) || defined(NRF52_SERIES) - #define NRFX_TWI_ENABLED (MICROPY_PY_MACHINE_I2C) + #if MICROPY_PY_MACHINE_I2C + #define NRFX_TWI_ENABLED 1 + #else + #define NRFX_TWI_ENABLED 0 + #endif #define NRFX_TWI0_ENABLED 1 #define NRFX_TWI1_ENABLED 1 #elif defined(NRF9160_XXAA) - #define NRFX_TWIM_ENABLED (MICROPY_PY_MACHINE_I2C) + #if MICROPY_PY_MACHINE_I2C + #define NRFX_TWIM_ENABLED 1 + #else + #define NRFX_TWIM_ENABLED 0 + #endif #define NRFX_TWIM0_ENABLED 1 #define NRFX_TWIM1_ENABLED 1 #endif #if defined(NRF51) || defined(NRF52832) - #define NRFX_SPI_ENABLED (MICROPY_PY_MACHINE_SPI) + #if MICROPY_PY_MACHINE_SPI + #define NRFX_SPI_ENABLED 1 + #else + #define NRFX_SPI_ENABLED 0 + #endif #define NRFX_SPI0_ENABLED 1 #define NRFX_SPI1_ENABLED 1 @@ -111,20 +139,23 @@ #define NRFX_SPI2_ENABLED 1 #endif #elif defined(NRF52840) - #define NRFX_SPIM_ENABLED (MICROPY_PY_MACHINE_SPI) + #if MICROPY_PY_MACHINE_SPI + #define NRFX_SPIM_ENABLED 1 + #else + #define NRFX_SPIM_ENABLED 0 + #endif #define NRFX_SPIM0_ENABLED 1 #define NRFX_SPIM1_ENABLED 1 #define NRFX_SPIM2_ENABLED 1 - #define NRFX_SPIM3_ENABLED (NRF52840) + #define NRFX_SPIM3_ENABLED 1 #elif defined(NRF9160_XXAA) - #define NRFX_SPIM_ENABLED (MICROPY_PY_MACHINE_SPI) + #if MICROPY_PY_MACHINE_SPI + #define NRFX_SPIM_ENABLED 1 + #else + #define NRFX_SPIM_ENABLED 0 + #endif #define NRFX_SPIM0_ENABLED 1 #define NRFX_SPIM1_ENABLED 1 - -// 0 NRF_GPIO_PIN_NOPULL -// 1 NRF_GPIO_PIN_PULLDOWN -// 3 NRF_GPIO_PIN_PULLUP - #define NRFX_SPIM_MISO_PULL_CFG 1 #endif // NRF51 // 0 NRF_GPIO_PIN_NOPULL @@ -133,49 +164,123 @@ #define NRFX_SPI_MISO_PULL_CFG 1 #define NRFX_SPIM_MISO_PULL_CFG 1 -#define NRFX_RTC_ENABLED (MICROPY_PY_MACHINE_RTCOUNTER) +#if MICROPY_PY_MACHINE_RTCOUNTER + #define NRFX_RTC_ENABLED 1 +#else + #define NRFX_RTC_ENABLED 0 +#endif #define NRFX_RTC0_ENABLED 1 #define NRFX_RTC1_ENABLED 1 -#define NRFX_RTC2_ENABLED (!NRF51) && (!NRF9160_XXAA) +#if !defined(NRF51) && !defined(NRF9160_XXAA) + #define NRFX_RTC2_ENABLED 1 +#else + #define NRFX_RTC2_ENABLED 0 +#endif -#define NRFX_TIMER_ENABLED (MICROPY_PY_MACHINE_TIMER_NRF) +#if MICROPY_PY_MACHINE_TIMER_NRF + #define NRFX_TIMER_ENABLED 1 +#else + #define NRFX_TIMER_ENABLED 0 +#endif #define NRFX_TIMER0_ENABLED 1 -#define NRFX_TIMER1_ENABLED (!MICROPY_PY_MACHINE_SOFT_PWM) +#if MICROPY_PY_MACHINE_SOFT_PWM + #define NRFX_TIMER1_ENABLED 0 +#else + #define NRFX_TIMER1_ENABLED 1 +#endif #define NRFX_TIMER2_ENABLED 1 -#define NRFX_TIMER3_ENABLED (!NRF51) && (!NRF9160_XXAA) -#define NRFX_TIMER4_ENABLED (!NRF51) && (!NRF9160_XXAA) - +#if !defined(NRF51) && !defined(NRF9160_XXAA) + #define NRFX_TIMER3_ENABLED 1 + #define NRFX_TIMER4_ENABLED 1 +#else + #define NRFX_TIMER3_ENABLED 0 + #define NRFX_TIMER4_ENABLED 0 +#endif -#define NRFX_PWM_ENABLED (!NRF51) && MICROPY_PY_MACHINE_HW_PWM +#if !defined(NRF51) && MICROPY_PY_MACHINE_HW_PWM + #define NRFX_PWM_ENABLED 1 +#else + #define NRFX_PWM_ENABLED 0 +#endif #define NRFX_PWM0_ENABLED 1 #define NRFX_PWM1_ENABLED 1 #define NRFX_PWM2_ENABLED 1 -#define NRFX_PWM3_ENABLED (NRF52840) +#if defined(NRF52840) + #define NRFX_PWM3_ENABLED 1 +#else + #define NRFX_PWM3_ENABLED 0 +#endif #define NRFX_NVMC_ENABLED 1 // Peripheral Resource Sharing #if defined(NRF51) || defined(NRF52832) - #define NRFX_PRS_BOX_0_ENABLED (NRFX_TWI_ENABLED && NRFX_TWI0_ENABLED && NRFX_SPI_ENABLED && NRFX_SPI0_ENABLED) - #define NRFX_PRS_BOX_1_ENABLED (NRFX_TWI_ENABLED && NRFX_TWI1_ENABLED && NRFX_SPI_ENABLED && NRFX_SPI1_ENABLED) - - #if defined(NRF52832) - #define NRFX_PRS_BOX_2_ENABLED (NRFX_TWI_ENABLED && NRFX_TWI1_ENABLED && NRFX_SPI_ENABLED && NRFX_SPI1_ENABLED) + #if NRFX_TWI_ENABLED && NRFX_TWI0_ENABLED && NRFX_SPI_ENABLED && NRFX_SPI0_ENABLED + #define NRFX_PRS_BOX_0_ENABLED 1 + #else + #define NRFX_PRS_BOX_0_ENABLED 0 + #endif + #if NRFX_TWI_ENABLED && NRFX_TWI1_ENABLED && NRFX_SPI_ENABLED && NRFX_SPI1_ENABLED + #define NRFX_PRS_BOX_1_ENABLED 1 + #else + #define NRFX_PRS_BOX_1_ENABLED 0 + #endif + #if defined(NRF52832) && NRFX_TWI_ENABLED && NRFX_TWI1_ENABLED && NRFX_SPI_ENABLED && NRFX_SPI1_ENABLED + #define NRFX_PRS_BOX_2_ENABLED 1 + #else + #define NRFX_PRS_BOX_2_ENABLED 0 #endif #elif defined(NRF52840) - #define NRFX_PRS_BOX_0_ENABLED (NRFX_TWI_ENABLED && NRFX_TWI0_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM0_ENABLED) - #define NRFX_PRS_BOX_1_ENABLED (NRFX_TWI_ENABLED && NRFX_TWI1_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM1_ENABLED) - #define NRFX_PRS_BOX_2_ENABLED (NRFX_TWI_ENABLED && NRFX_TWI2_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM2_ENABLED) + #if NRFX_TWI_ENABLED && NRFX_TWI0_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM0_ENABLED + #define NRFX_PRS_BOX_0_ENABLED 1 + #else + #define NRFX_PRS_BOX_0_ENABLED 0 + #endif + #if NRFX_TWI_ENABLED && NRFX_TWI1_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM1_ENABLED + #define NRFX_PRS_BOX_1_ENABLED 1 + #else + #define NRFX_PRS_BOX_1_ENABLED 0 + #endif +// nRF52840 has no TWI2, so BOX_2 PRS is not applicable. + #define NRFX_PRS_BOX_2_ENABLED 0 #elif defined(NRF9160_XXAA) - #define NRFX_PRS_BOX_0_ENABLED (NRFX_TWIM_ENABLED && NRFX_TWIM0_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM0_ENABLED) - #define NRFX_PRS_BOX_1_ENABLED (NRFX_TWIM_ENABLED && NRFX_TWIM1_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM1_ENABLED) - #define NRFX_PRS_BOX_2_ENABLED (NRFX_TWIM_ENABLED && NRFX_TWIM2_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM2_ENABLED) + #if NRFX_TWIM_ENABLED && NRFX_TWIM0_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM0_ENABLED + #define NRFX_PRS_BOX_0_ENABLED 1 + #else + #define NRFX_PRS_BOX_0_ENABLED 0 + #endif + #if NRFX_TWIM_ENABLED && NRFX_TWIM1_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM1_ENABLED + #define NRFX_PRS_BOX_1_ENABLED 1 + #else + #define NRFX_PRS_BOX_1_ENABLED 0 + #endif + #if NRFX_TWIM_ENABLED && NRFX_TWIM2_ENABLED && NRFX_SPIM_ENABLED && NRFX_SPIM2_ENABLED + #define NRFX_PRS_BOX_2_ENABLED 1 + #else + #define NRFX_PRS_BOX_2_ENABLED 0 + #endif +#else + #define NRFX_PRS_BOX_0_ENABLED 0 + #define NRFX_PRS_BOX_1_ENABLED 0 + #define NRFX_PRS_BOX_2_ENABLED 0 #endif -#define NRFX_PRS_ENABLED (NRFX_PRS_BOX_0_ENABLED || NRFX_PRS_BOX_1_ENABLED || NRFX_PRS_BOX_2_ENABLED) +#if NRFX_PRS_BOX_0_ENABLED || NRFX_PRS_BOX_1_ENABLED || NRFX_PRS_BOX_2_ENABLED + #define NRFX_PRS_ENABLED 1 +#else + #define NRFX_PRS_ENABLED 0 +#endif -#define NRFX_SAADC_ENABLED !(NRF51) && (MICROPY_PY_MACHINE_ADC) -#define NRFX_ADC_ENABLED (NRF51) && (MICROPY_PY_MACHINE_ADC) +#if !defined(NRF51) && MICROPY_PY_MACHINE_ADC + #define NRFX_SAADC_ENABLED 1 +#else + #define NRFX_SAADC_ENABLED 0 +#endif +#if defined(NRF51) && MICROPY_PY_MACHINE_ADC + #define NRFX_ADC_ENABLED 1 +#else + #define NRFX_ADC_ENABLED 0 +#endif #if defined(NRF9160_XXAA) @@ -240,6 +345,8 @@ #define GPIOTE_IRQn GPIOTE1_IRQn #define GPIOTE_IRQHandler GPIOTE1_IRQHandler +#define NRFX_GPIOTE1_ENABLED 1 + #endif #endif // NRFX_CONFIG_H diff --git a/ports/nrf/nrfx_glue.h b/ports/nrf/nrfx_glue.h index 56e1f719dae..af3d30d2dad 100644 --- a/ports/nrf/nrfx_glue.h +++ b/ports/nrf/nrfx_glue.h @@ -31,6 +31,7 @@ #include "py/misc.h" #include +#include #ifndef ARRAY_SIZE #define ARRAY_SIZE MP_ARRAY_SIZE @@ -43,6 +44,39 @@ void mp_hal_delay_us(mp_uint_t us); #define NRFX_DELAY_US mp_hal_delay_us +// Atomic operations (required by nrfx v3+) +#define nrfx_atomic_t nrfx_atomic_u32_t +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value) +#define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value) +#define NRFX_ATOMIC_FETCH_AND(p_data, value) nrfx_atomic_u32_fetch_and(p_data, value) +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) nrfx_atomic_u32_fetch_xor(p_data, value) +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) nrfx_atomic_u32_fetch_add(p_data, value) +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) nrfx_atomic_u32_fetch_sub(p_data, value) +#define NRFX_ATOMIC_CAS(p_data, old_value, new_value) \ + nrfx_atomic_u32_cmp_exch(p_data, &(old_value), new_value) + +// CLZ/CTZ intrinsics +#define NRFX_CLZ(value) __CLZ(value) +#define NRFX_CTZ(value) __CLZ(__RBIT(value)) + +// Event readback is required on all nRF51/nRF52 devices +#define NRFX_EVENT_READBACK_ENABLED 1 + +// Override NRFY_CACHE_INV to suppress unused variable warnings +// on targets without data cache (nRF51/nRF52). +#define NRFY_CACHE_INV(p_buffer, size) do { (void)(p_buffer); (void)(size); } while (0) +#define NRFY_CACHE_WB(p_buffer, size) do { (void)(p_buffer); (void)(size); } while (0) +#define NRFY_CACHE_WBINV(p_buffer, size) do { (void)(p_buffer); (void)(size); } while (0) + +// Resource usage tracking +#define NRFX_DPPI_CHANNELS_USED 0 +#define NRFX_DPPI_GROUPS_USED 0 +#define NRFX_PPI_CHANNELS_USED 0 +#define NRFX_PPI_GROUPS_USED 0 +#define NRFX_EGUS_USED 0 +#define NRFX_GPIOTE_CHANNELS_USED 0 +#define NRFX_TIMERS_USED 0 + #if BLUETOOTH_SD #if NRF51 @@ -149,4 +183,6 @@ void mp_hal_delay_us(mp_uint_t us); #define NRFX_IRQ_IS_ENABLED(irq_number) (0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)))) +#define NRFX_IRQ_IS_PENDING(irq_number) (0 != (NVIC->ISPR[irq_number / 32] & (1UL << (irq_number % 32)))) + #endif // NRFX_GLUE_H From 7ac25f70740214288dcc30c188cd5c16af6ce52c Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Apr 2026 07:34:45 +1000 Subject: [PATCH 026/635] nrf: Rewrite GPIOTE pin IRQ handling for nrfx v3 API. Replace removed nrfx_gpiote_in_init/uninit/event_enable with the v3 instance-based API: channel allocation, input_configure, and trigger_enable. Allocates a hardware GPIOTE channel per pin to preserve high-accuracy edge detection. Falls back to PORT SENSE if all channels are in use. Signed-off-by: Andrew Leech --- ports/nrf/modules/machine/pin.c | 86 +++++++++++++++++++++++++-------- ports/nrf/nrfx_glue.h | 3 -- 2 files changed, 66 insertions(+), 23 deletions(-) diff --git a/ports/nrf/modules/machine/pin.c b/ports/nrf/modules/machine/pin.c index f46394d769c..7dbf88bab53 100644 --- a/ports/nrf/modules/machine/pin.c +++ b/ports/nrf/modules/machine/pin.c @@ -38,12 +38,30 @@ #include "nrf_gpio.h" #include "nrfx_gpiote.h" +#if defined(NRF9160_XXAA) +static const nrfx_gpiote_t gpiote_inst = NRFX_GPIOTE_INSTANCE(1); +#else +static const nrfx_gpiote_t gpiote_inst = NRFX_GPIOTE_INSTANCE(0); +#endif + #if defined(NRF52840_XXAA) #define NUM_OF_PINS 48 #else #define NUM_OF_PINS 32 #endif +static uint8_t pin_gpiote_ch[NUM_OF_PINS]; + +#define PIN_GPIOTE_CH_NONE UINT8_MAX + +static void pin_gpiote_release(nrfx_gpiote_pin_t pin) { + nrfx_gpiote_pin_uninit(&gpiote_inst, pin); + if (pin_gpiote_ch[pin] != PIN_GPIOTE_CH_NONE) { + nrfx_gpiote_channel_free(&gpiote_inst, pin_gpiote_ch[pin]); + pin_gpiote_ch[pin] = PIN_GPIOTE_CH_NONE; + } +} + extern const pin_obj_t machine_board_pin_obj[]; extern const uint8_t machine_pin_num_of_board_pins; @@ -119,10 +137,17 @@ void pin_init0(void) { for (int i = 0; i < NUM_OF_PINS; i++) { MP_STATE_PORT(pin_irq_handlers)[i] = mp_const_none; } - // Initialize GPIOTE if not done yet. - if (!nrfx_gpiote_is_init()) { - nrfx_gpiote_init(NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY); + if (!nrfx_gpiote_init_check(&gpiote_inst)) { + nrfx_gpiote_init(&gpiote_inst, NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY); + } else { + // Soft reset: free GPIOTE channels from the previous cycle. + for (int i = 0; i < NUM_OF_PINS; i++) { + if (pin_gpiote_ch[i] != PIN_GPIOTE_CH_NONE) { + pin_gpiote_release(i); + } + } } + memset(pin_gpiote_ch, PIN_GPIOTE_CH_NONE, sizeof(pin_gpiote_ch)); #if PIN_DEBUG pin_class_debug = false; @@ -494,7 +519,8 @@ static mp_obj_t pin_af(mp_obj_t self_in) { static MP_DEFINE_CONST_FUN_OBJ_1(pin_af_obj, pin_af); -static void pin_common_irq_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { +static void pin_common_irq_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t action, void *p_context) { + (void)p_context; mp_obj_t pin_handler = MP_STATE_PORT(pin_irq_handlers)[pin]; mp_obj_t pin_number = MP_OBJ_NEW_SMALL_INT(pin); const pin_obj_t *pin_obj = pin_find(pin_number); @@ -513,7 +539,7 @@ static void pin_common_irq_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t } else { // Uncaught exception; disable the callback so it doesn't run again. MP_STATE_PORT(pin_irq_handlers)[pin] = mp_const_none; - nrfx_gpiote_in_uninit(pin); + pin_gpiote_release(pin); mp_printf(MICROPY_ERROR_PRINTER, "uncaught exception in interrupt handler for Pin('%q')\n", pin_obj->name); mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(nlr.ret_val)); } @@ -537,30 +563,50 @@ static mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar nrfx_gpiote_pin_t pin = self->pin; + pin_gpiote_release(pin); + if (args[ARG_handler].u_obj != mp_const_none) { - nrfx_gpiote_in_config_t config = NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE(true); + nrfx_gpiote_trigger_t trigger = NRFX_GPIOTE_TRIGGER_TOGGLE; if (args[ARG_trigger].u_int == NRF_GPIOTE_POLARITY_LOTOHI) { - config.sense = NRF_GPIOTE_POLARITY_LOTOHI; + trigger = NRFX_GPIOTE_TRIGGER_LOTOHI; } else if (args[ARG_trigger].u_int == NRF_GPIOTE_POLARITY_HITOLO) { - config.sense = NRF_GPIOTE_POLARITY_HITOLO; + trigger = NRFX_GPIOTE_TRIGGER_HITOLO; } - config.pull = NRF_GPIO_PIN_PULLUP; - config.skip_gpio_setup = true; - - nrfx_err_t err_code = nrfx_gpiote_in_init(pin, &config, pin_common_irq_handler); - if (err_code == NRFX_ERROR_INVALID_STATE) { - // Re-init if already configured. - nrfx_gpiote_in_uninit(pin); - nrfx_gpiote_in_init(pin, &config, pin_common_irq_handler); + + uint8_t gpiote_ch; + nrfx_err_t err = nrfx_gpiote_channel_alloc(&gpiote_inst, &gpiote_ch); + + nrfx_gpiote_trigger_config_t trigger_config = { + .trigger = trigger, + .p_in_channel = (err == NRFX_SUCCESS) ? &gpiote_ch : NULL, + }; + nrfx_gpiote_handler_config_t handler_config = { + .handler = pin_common_irq_handler, + .p_context = NULL, + }; + nrfx_gpiote_input_pin_config_t input_config = { + .p_pull_config = NULL, + .p_trigger_config = &trigger_config, + .p_handler_config = &handler_config, + }; + + nrfx_err_t cfg_err = nrfx_gpiote_input_configure(&gpiote_inst, pin, &input_config); + if (cfg_err != NRFX_SUCCESS) { + if (err == NRFX_SUCCESS) { + nrfx_gpiote_channel_free(&gpiote_inst, gpiote_ch); + } + mp_raise_ValueError(MP_ERROR_TEXT("pin IRQ config failed")); } - } else { - nrfx_gpiote_in_uninit(pin); + + if (err == NRFX_SUCCESS) { + pin_gpiote_ch[pin] = gpiote_ch; + } + + nrfx_gpiote_trigger_enable(&gpiote_inst, pin, true); } MP_STATE_PORT(pin_irq_handlers)[pin] = args[ARG_handler].u_obj; - nrfx_gpiote_in_event_enable(pin, true); - // return the irq object return mp_const_none; } diff --git a/ports/nrf/nrfx_glue.h b/ports/nrf/nrfx_glue.h index af3d30d2dad..04881868527 100644 --- a/ports/nrf/nrfx_glue.h +++ b/ports/nrf/nrfx_glue.h @@ -44,7 +44,6 @@ void mp_hal_delay_us(mp_uint_t us); #define NRFX_DELAY_US mp_hal_delay_us -// Atomic operations (required by nrfx v3+) #define nrfx_atomic_t nrfx_atomic_u32_t #define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value) #define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value) @@ -55,7 +54,6 @@ void mp_hal_delay_us(mp_uint_t us); #define NRFX_ATOMIC_CAS(p_data, old_value, new_value) \ nrfx_atomic_u32_cmp_exch(p_data, &(old_value), new_value) -// CLZ/CTZ intrinsics #define NRFX_CLZ(value) __CLZ(value) #define NRFX_CTZ(value) __CLZ(__RBIT(value)) @@ -68,7 +66,6 @@ void mp_hal_delay_us(mp_uint_t us); #define NRFY_CACHE_WB(p_buffer, size) do { (void)(p_buffer); (void)(size); } while (0) #define NRFY_CACHE_WBINV(p_buffer, size) do { (void)(p_buffer); (void)(size); } while (0) -// Resource usage tracking #define NRFX_DPPI_CHANNELS_USED 0 #define NRFX_DPPI_GROUPS_USED 0 #define NRFX_PPI_CHANNELS_USED 0 From a9fc9e44583435dda79552c8e0d26ddaad51ed11 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Apr 2026 07:34:55 +1000 Subject: [PATCH 027/635] nrf: Update peripheral drivers for nrfx v3 API. Adapt UART, ADC, PWM, SPI, I2C, and RTC drivers for nrfx v3 renamed structs, constants, and function signatures. Notably: UARTE config members renamed and conditional on UART vs UARTE for nRF51 compatibility, SAADC value type changed to int16_t, pin-not-connected constants renamed, TWI vs TWIM pin config split, and RTC prescaler macro renamed. Signed-off-by: Andrew Leech --- ports/nrf/modules/machine/adc.c | 4 ++-- ports/nrf/modules/machine/i2c.c | 6 ++++++ ports/nrf/modules/machine/pwm.c | 9 +++++---- ports/nrf/modules/machine/rtcounter.c | 2 +- ports/nrf/modules/machine/spi.c | 2 +- ports/nrf/modules/machine/timer.c | 2 +- ports/nrf/modules/machine/uart.c | 29 ++++++++++++++++++++++++--- 7 files changed, 42 insertions(+), 12 deletions(-) diff --git a/ports/nrf/modules/machine/adc.c b/ports/nrf/modules/machine/adc.c index 9fa8005a228..c5acc0d77f0 100644 --- a/ports/nrf/modules/machine/adc.c +++ b/ports/nrf/modules/machine/adc.c @@ -161,7 +161,7 @@ int16_t machine_adc_value_read(machine_adc_obj_t *adc_obj) { nrfx_adc_sample_convert(&channel_config, &value); #else // NRF52 - nrf_saadc_value_t value = 0; + int16_t value = 0; nrfx_saadc_simple_mode_set((1 << adc_obj->id), NRF_SAADC_RESOLUTION_8BIT, NRF_SAADC_INPUT_DISABLED, NULL); nrfx_saadc_buffer_set(&value, 1); @@ -248,7 +248,7 @@ mp_obj_t machine_adc_battery_level(void) { nrfx_adc_sample_convert(&channel_config, &value); #else // NRF52 - nrf_saadc_value_t value = 0; + int16_t value = 0; const nrfx_saadc_channel_t config = { \ .channel_config = diff --git a/ports/nrf/modules/machine/i2c.c b/ports/nrf/modules/machine/i2c.c index 6c2b3e94838..ced53346414 100644 --- a/ports/nrf/modules/machine/i2c.c +++ b/ports/nrf/modules/machine/i2c.c @@ -116,8 +116,14 @@ mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, siz const machine_hard_i2c_obj_t *self = &machine_hard_i2c_obj[i2c_id]; nrfx_twi_config_t config; + memset(&config, 0, sizeof(config)); + #if NRFX_TWI_ENABLED config.scl = mp_hal_get_pin_obj(args[ARG_scl].u_obj)->pin; config.sda = mp_hal_get_pin_obj(args[ARG_sda].u_obj)->pin; + #else + config.scl_pin = mp_hal_get_pin_obj(args[ARG_scl].u_obj)->pin; + config.sda_pin = mp_hal_get_pin_obj(args[ARG_sda].u_obj)->pin; + #endif int freq = NRF_TWI_FREQ_400K; if (args[ARG_freq].u_int != -1) { diff --git a/ports/nrf/modules/machine/pwm.c b/ports/nrf/modules/machine/pwm.c index 13d824e8667..4a6bfa86108 100644 --- a/ports/nrf/modules/machine/pwm.c +++ b/ports/nrf/modules/machine/pwm.c @@ -332,6 +332,7 @@ static void mp_machine_pwm_duty_set_ns(machine_pwm_obj_t *self, mp_int_t duty) { static void machine_hard_pwm_start(const machine_pwm_obj_t *self) { nrfx_pwm_config_t config; + memset(&config, 0, sizeof(config)); // check if ready to go if (self->p_config->defer_start == true || self->p_config->freq_div < 0 || self->p_config->duty_mode[self->channel] == DUTY_NOT_SET) { @@ -340,10 +341,10 @@ static void machine_hard_pwm_start(const machine_pwm_obj_t *self) { self->p_config->active = RUNNING; - config.output_pins[0] = self->p_config->duty_mode[0] != DUTY_NOT_SET ? self->p_config->pwm_pin[0] : NRFX_PWM_PIN_NOT_USED; - config.output_pins[1] = self->p_config->duty_mode[1] != DUTY_NOT_SET ? self->p_config->pwm_pin[1] : NRFX_PWM_PIN_NOT_USED; - config.output_pins[2] = self->p_config->duty_mode[2] != DUTY_NOT_SET ? self->p_config->pwm_pin[2] : NRFX_PWM_PIN_NOT_USED; - config.output_pins[3] = self->p_config->duty_mode[3] != DUTY_NOT_SET ? self->p_config->pwm_pin[3] : NRFX_PWM_PIN_NOT_USED; + config.output_pins[0] = self->p_config->duty_mode[0] != DUTY_NOT_SET ? self->p_config->pwm_pin[0] : NRF_PWM_PIN_NOT_CONNECTED; + config.output_pins[1] = self->p_config->duty_mode[1] != DUTY_NOT_SET ? self->p_config->pwm_pin[1] : NRF_PWM_PIN_NOT_CONNECTED; + config.output_pins[2] = self->p_config->duty_mode[2] != DUTY_NOT_SET ? self->p_config->pwm_pin[2] : NRF_PWM_PIN_NOT_CONNECTED; + config.output_pins[3] = self->p_config->duty_mode[3] != DUTY_NOT_SET ? self->p_config->pwm_pin[3] : NRF_PWM_PIN_NOT_CONNECTED; uint32_t tick_freq = PWM_MAX_BASE_FREQ / (1 << self->p_config->freq_div); uint32_t period = tick_freq / self->p_config->freq; diff --git a/ports/nrf/modules/machine/rtcounter.c b/ports/nrf/modules/machine/rtcounter.c index a66a635a05d..66a57145d23 100644 --- a/ports/nrf/modules/machine/rtcounter.c +++ b/ports/nrf/modules/machine/rtcounter.c @@ -128,7 +128,7 @@ static void rtc_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t /* MicroPython bindings for machine API */ const nrfx_rtc_config_t machine_rtc_config = { - .prescaler = RTC_FREQ_TO_PRESCALER(RTC_FREQUENCY), + .prescaler = NRF_RTC_FREQ_TO_PRESCALER(RTC_FREQUENCY), .reliable = 0, .tick_latency = 0, // ignored when reliable == 0 #ifdef NRF51 diff --git a/ports/nrf/modules/machine/spi.c b/ports/nrf/modules/machine/spi.c index f474c88715c..e3f72cba385 100644 --- a/ports/nrf/modules/machine/spi.c +++ b/ports/nrf/modules/machine/spi.c @@ -75,7 +75,7 @@ #define nrfx_spi_config_t nrfx_spim_config_t #define nrfx_spi_xfer_desc_t nrfx_spim_xfer_desc_t -#define NRFX_SPI_PIN_NOT_USED NRFX_SPIM_PIN_NOT_USED +#define NRFX_SPI_PIN_NOT_USED NRF_SPIM_PIN_NOT_CONNECTED #define NRFX_SPI_INSTANCE NRFX_SPIM_INSTANCE #define NRF_SPI_BIT_ORDER_LSB_FIRST NRF_SPIM_BIT_ORDER_LSB_FIRST #define NRF_SPI_BIT_ORDER_MSB_FIRST NRF_SPIM_BIT_ORDER_MSB_FIRST diff --git a/ports/nrf/modules/machine/timer.c b/ports/nrf/modules/machine/timer.c index 42a40ad2f26..48fefec99cd 100644 --- a/ports/nrf/modules/machine/timer.c +++ b/ports/nrf/modules/machine/timer.c @@ -143,7 +143,7 @@ static mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, // shortcut) and channel 1 for capturing the current time. const nrfx_timer_config_t config = { - .frequency = NRF_TIMER_FREQ_1MHz, + .frequency = 1000000, .mode = NRF_TIMER_MODE_TIMER, .bit_width = NRF_TIMER_BIT_WIDTH_24, #ifdef NRF51 diff --git a/ports/nrf/modules/machine/uart.c b/ports/nrf/modules/machine/uart.c index 4c75bf82098..e46ece7dfb4 100644 --- a/ports/nrf/modules/machine/uart.c +++ b/ports/nrf/modules/machine/uart.c @@ -64,7 +64,7 @@ typedef struct _machine_uart_buf_t { #define nrfx_uart_config_t nrfx_uarte_config_t #define nrfx_uart_rx nrfx_uarte_rx -#define nrfx_uart_tx nrfx_uarte_tx +#define nrfx_uart_tx(inst, buf, len) nrfx_uarte_tx(inst, buf, len, 0) #define nrfx_uart_tx_in_progress nrfx_uarte_tx_in_progress #define nrfx_uart_init nrfx_uarte_init #define nrfx_uart_uninit nrfx_uarte_uninit @@ -258,15 +258,24 @@ static mp_obj_t mp_machine_uart_make_new(const mp_obj_type_t *type, size_t n_arg machine_uart_obj_t *self = &machine_uart_obj[uart_id]; nrfx_uart_config_t config; + memset(&config, 0, sizeof(config)); // flow control + #if NRFX_UART_ENABLED #if MICROPY_HW_UART1_HWFC config.hal_cfg.hwfc = NRF_UART_HWFC_ENABLED; #else config.hal_cfg.hwfc = NRF_UART_HWFC_DISABLED; #endif - config.hal_cfg.parity = NRF_UART_PARITY_EXCLUDED; + #else + #if MICROPY_HW_UART1_HWFC + config.config.hwfc = NRF_UART_HWFC_ENABLED; + #else + config.config.hwfc = NRF_UART_HWFC_DISABLED; + #endif + config.config.parity = NRF_UART_PARITY_EXCLUDED; + #endif // Higher priority than pin interrupts, otherwise printing exceptions from // interrupt handlers gets stuck. @@ -288,12 +297,26 @@ static mp_obj_t mp_machine_uart_make_new(const mp_obj_type_t *type, size_t n_arg config.baudrate = args[ARG_baudrate].u_int / 400 * (uint32_t)(400ULL * (uint64_t)UINT32_MAX / 16000000ULL); config.baudrate = (config.baudrate + 0x800) & 0xffffff000; // rounding + #if NRFX_UART_ENABLED config.pseltxd = MICROPY_HW_UART1_TX; config.pselrxd = MICROPY_HW_UART1_RX; - #if MICROPY_HW_UART1_HWFC config.pselrts = MICROPY_HW_UART1_RTS; config.pselcts = MICROPY_HW_UART1_CTS; + #else + config.pselrts = NRF_UART_PSEL_DISCONNECTED; + config.pselcts = NRF_UART_PSEL_DISCONNECTED; + #endif + #else + config.txd_pin = MICROPY_HW_UART1_TX; + config.rxd_pin = MICROPY_HW_UART1_RX; + #if MICROPY_HW_UART1_HWFC + config.rts_pin = MICROPY_HW_UART1_RTS; + config.cts_pin = MICROPY_HW_UART1_CTS; + #else + config.rts_pin = NRF_UARTE_PSEL_DISCONNECTED; + config.cts_pin = NRF_UARTE_PSEL_DISCONNECTED; + #endif #endif self->timeout = args[ARG_timeout].u_int; self->timeout_char = args[ARG_timeout_char].u_int; From 77a9f3e6244babc771926af73d6257e11be39e63 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Apr 2026 07:35:01 +1000 Subject: [PATCH 028/635] nrf: Fix nRF9160 secureboot build for nrfx v3. Add fallback define for NRF_FPU_S which was removed from the nRF9160 device headers in nrfx v3. Signed-off-by: Andrew Leech --- .../nrf/drivers/secureboot/secureboot_main.c | 35 ++++++++++--------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/ports/nrf/drivers/secureboot/secureboot_main.c b/ports/nrf/drivers/secureboot/secureboot_main.c index 8362852cd79..7870fc7ecc4 100644 --- a/ports/nrf/drivers/secureboot/secureboot_main.c +++ b/ports/nrf/drivers/secureboot/secureboot_main.c @@ -27,6 +27,12 @@ #include #include +// NRF_FPU_S was removed from the nRF9160 device headers in nrfx v3. +// Define it here using the known secure-domain base address. +#ifndef NRF_FPU_S +#define NRF_FPU_S ((NRF_FPU_Type *)0x5002C000UL) +#endif + // Secure flash 32K. #define SECURE_32K_FLASH_PAGE_START (0) #define SECURE_32K_FLASH_PAGE_END (0) @@ -53,19 +59,19 @@ static void configure_flash(void) { for (uint8_t i = SECURE_32K_FLASH_PAGE_START; i <= SECURE_32K_FLASH_PAGE_END; i++) { uint32_t perm = 0; perm |= (SPU_FLASHREGION_PERM_EXECUTE_Enable << SPU_FLASHREGION_PERM_EXECUTE_Pos); - perm |= (SPU_FLASHREGION_PERM_WRITE_Enable << SPU_FLASHREGION_PERM_WRITE_Pos); - perm |= (SPU_FLASHREGION_PERM_READ_Enable << SPU_FLASHREGION_PERM_READ_Pos); - perm |= (SPU_FLASHREGION_PERM_LOCK_Locked << SPU_FLASHREGION_PERM_LOCK_Pos); + perm |= (SPU_FLASHREGION_PERM_WRITE_Enable << SPU_FLASHREGION_PERM_WRITE_Pos); + perm |= (SPU_FLASHREGION_PERM_READ_Enable << SPU_FLASHREGION_PERM_READ_Pos); + perm |= (SPU_FLASHREGION_PERM_LOCK_Locked << SPU_FLASHREGION_PERM_LOCK_Pos); perm |= (SPU_FLASHREGION_PERM_SECATTR_Secure << SPU_FLASHREGION_PERM_SECATTR_Pos); NRF_SPU_S->FLASHREGION[i].PERM = perm; } for (uint8_t i = NONSECURE_32K_FLASH_PAGE_START; i <= NONSECURE_32K_FLASH_PAGE_END; i++) { uint32_t perm = 0; - perm |= (SPU_FLASHREGION_PERM_EXECUTE_Enable << SPU_FLASHREGION_PERM_EXECUTE_Pos); - perm |= (SPU_FLASHREGION_PERM_WRITE_Enable << SPU_FLASHREGION_PERM_WRITE_Pos); - perm |= (SPU_FLASHREGION_PERM_READ_Enable << SPU_FLASHREGION_PERM_READ_Pos); - perm |= (SPU_FLASHREGION_PERM_LOCK_Locked << SPU_FLASHREGION_PERM_LOCK_Pos); + perm |= (SPU_FLASHREGION_PERM_EXECUTE_Enable << SPU_FLASHREGION_PERM_EXECUTE_Pos); + perm |= (SPU_FLASHREGION_PERM_WRITE_Enable << SPU_FLASHREGION_PERM_WRITE_Pos); + perm |= (SPU_FLASHREGION_PERM_READ_Enable << SPU_FLASHREGION_PERM_READ_Pos); + perm |= (SPU_FLASHREGION_PERM_LOCK_Locked << SPU_FLASHREGION_PERM_LOCK_Pos); perm |= (SPU_FLASHREGION_PERM_SECATTR_Non_Secure << SPU_FLASHREGION_PERM_SECATTR_Pos); NRF_SPU_S->FLASHREGION[i].PERM = perm; } @@ -93,8 +99,7 @@ static void configure_ram(void) { } } -static void peripheral_setup(uint8_t peripheral_id) -{ +static void peripheral_setup(uint8_t peripheral_id) { NVIC_DisableIRQ(peripheral_id); uint32_t perm = 0; perm |= (SPU_PERIPHID_PERM_PRESENT_IsPresent << SPU_PERIPHID_PERM_PRESENT_Pos); @@ -105,8 +110,7 @@ static void peripheral_setup(uint8_t peripheral_id) NVIC_SetTargetState(peripheral_id); } -static void configure_peripherals(void) -{ +static void configure_peripherals(void) { NRF_SPU_S->GPIOPORT[0].PERM = 0; peripheral_setup(PERIPHERAL_ID_GET(NRF_REGULATORS_S)); peripheral_setup(PERIPHERAL_ID_GET(NRF_CLOCK_S)); @@ -143,13 +147,12 @@ static void configure_peripherals(void) typedef void __attribute__((cmse_nonsecure_call)) nsfunc(void); -static void jump_to_non_secure(void) -{ +static void jump_to_non_secure(void) { TZ_SAU_Disable(); SAU->CTRL |= SAU_CTRL_ALLNS_Msk; // Set NS vector table. - uint32_t * vtor_ns = (uint32_t *)0x8000; + uint32_t *vtor_ns = (uint32_t *)0x8000; SCB_NS->VTOR = (uint32_t)vtor_ns; // Allow for FPU to be used by NS. @@ -165,7 +168,7 @@ static void jump_to_non_secure(void) // Cast NS Reset_Handler to a non-secure function. nsfunc *fp = (nsfunc *)vtor_ns[1]; - fp = (nsfunc *)((intptr_t)(fp) & ~1); + fp = (nsfunc *)((intptr_t)(fp) & ~1); if (cmse_is_nsfptr(fp)) { __DSB(); @@ -184,6 +187,6 @@ void _start(void) { jump_to_non_secure(); while (1) { - ; + ; } } From 5a60aa2f00d7c1666c56d6cefc4633bc9cb9e7f6 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Apr 2026 15:19:20 +1000 Subject: [PATCH 029/635] nrf: Modernize Pin.irq to use shared mp_irq infrastructure. Replace the nrf port's custom Pin.irq implementation with the shared mp_irq_obj_t pattern used by rp2 and alif ports. Adds support for the hard kwarg (soft IRQs via mp_sched_schedule when hard=False), makes handler optional, and returns a proper IRQ object with flags() and trigger() methods. Boards without MICROPY_ENABLE_SCHEDULER retain the direct ISR-only path. Signed-off-by: Andrew Leech --- ports/nrf/modules/machine/pin.c | 226 ++++++++++++++++++++++++-------- 1 file changed, 170 insertions(+), 56 deletions(-) diff --git a/ports/nrf/modules/machine/pin.c b/ports/nrf/modules/machine/pin.c index 7dbf88bab53..a3cbff44c43 100644 --- a/ports/nrf/modules/machine/pin.c +++ b/ports/nrf/modules/machine/pin.c @@ -34,6 +34,7 @@ #include "py/runtime.h" #include "py/mphal.h" #include "py/gc.h" +#include "shared/runtime/mpirq.h" #include "pin.h" #include "nrf_gpio.h" #include "nrfx_gpiote.h" @@ -50,6 +51,16 @@ static const nrfx_gpiote_t gpiote_inst = NRFX_GPIOTE_INSTANCE(0); #define NUM_OF_PINS 32 #endif +#if MICROPY_ENABLE_SCHEDULER +typedef struct _machine_pin_irq_obj_t { + mp_irq_obj_t base; + uint32_t flags; + uint32_t trigger; +} machine_pin_irq_obj_t; + +static const mp_irq_methods_t machine_pin_irq_methods; +#endif + static uint8_t pin_gpiote_ch[NUM_OF_PINS]; #define PIN_GPIOTE_CH_NONE UINT8_MAX @@ -62,6 +73,54 @@ static void pin_gpiote_release(nrfx_gpiote_pin_t pin) { } } +static void pin_common_irq_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t action, void *p_context); + +static mp_uint_t machine_pin_irq_trigger_set(nrfx_gpiote_pin_t pin, mp_uint_t new_trigger) { + pin_gpiote_release(pin); + + if (new_trigger) { + nrfx_gpiote_trigger_t trigger = NRFX_GPIOTE_TRIGGER_TOGGLE; + if (new_trigger == NRF_GPIOTE_POLARITY_LOTOHI) { + trigger = NRFX_GPIOTE_TRIGGER_LOTOHI; + } else if (new_trigger == NRF_GPIOTE_POLARITY_HITOLO) { + trigger = NRFX_GPIOTE_TRIGGER_HITOLO; + } + + uint8_t gpiote_ch; + nrfx_err_t err = nrfx_gpiote_channel_alloc(&gpiote_inst, &gpiote_ch); + + nrfx_gpiote_trigger_config_t trigger_config = { + .trigger = trigger, + .p_in_channel = (err == NRFX_SUCCESS) ? &gpiote_ch : NULL, + }; + nrfx_gpiote_handler_config_t handler_config = { + .handler = pin_common_irq_handler, + .p_context = NULL, + }; + nrfx_gpiote_input_pin_config_t input_config = { + .p_pull_config = NULL, + .p_trigger_config = &trigger_config, + .p_handler_config = &handler_config, + }; + + nrfx_err_t cfg_err = nrfx_gpiote_input_configure(&gpiote_inst, pin, &input_config); + if (cfg_err != NRFX_SUCCESS) { + if (err == NRFX_SUCCESS) { + nrfx_gpiote_channel_free(&gpiote_inst, gpiote_ch); + } + mp_raise_ValueError(MP_ERROR_TEXT("pin IRQ config failed")); + } + + if (err == NRFX_SUCCESS) { + pin_gpiote_ch[pin] = gpiote_ch; + } + + nrfx_gpiote_trigger_enable(&gpiote_inst, pin, true); + } + + return 0; +} + extern const pin_obj_t machine_board_pin_obj[]; extern const uint8_t machine_pin_num_of_board_pins; @@ -134,9 +193,13 @@ static bool pin_class_debug; void pin_init0(void) { MP_STATE_PORT(pin_class_mapper) = mp_const_none; MP_STATE_PORT(pin_class_map_dict) = mp_const_none; + #if MICROPY_ENABLE_SCHEDULER + memset(MP_STATE_PORT(machine_pin_irq_obj), 0, sizeof(MP_STATE_PORT(machine_pin_irq_obj))); + #else for (int i = 0; i < NUM_OF_PINS; i++) { MP_STATE_PORT(pin_irq_handlers)[i] = mp_const_none; } + #endif if (!nrfx_gpiote_init_check(&gpiote_inst)) { nrfx_gpiote_init(&gpiote_inst, NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY); } else { @@ -519,6 +582,75 @@ static mp_obj_t pin_af(mp_obj_t self_in) { static MP_DEFINE_CONST_FUN_OBJ_1(pin_af_obj, pin_af); +#if MICROPY_ENABLE_SCHEDULER + +static void pin_common_irq_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t action, void *p_context) { + (void)p_context; + machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_obj[pin]); + if (irq != NULL) { + irq->flags = action; + mp_irq_handler(&irq->base); + } +} + +static machine_pin_irq_obj_t *machine_pin_get_irq(nrfx_gpiote_pin_t pin) { + machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_obj[pin]); + if (irq == NULL) { + irq = m_new_obj(machine_pin_irq_obj_t); + irq->base.base.type = &mp_irq_type; + irq->base.methods = (mp_irq_methods_t *)&machine_pin_irq_methods; + mp_obj_t pin_number = MP_OBJ_NEW_SMALL_INT(pin); + irq->base.parent = (mp_obj_t)pin_find(pin_number); + irq->base.handler = mp_const_none; + irq->base.ishard = false; + irq->flags = 0; + irq->trigger = 0; + MP_STATE_PORT(machine_pin_irq_obj[pin]) = irq; + } + return irq; +} + +static mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + enum { ARG_handler, ARG_trigger, ARG_hard }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_handler, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_trigger, MP_ARG_INT, {.u_int = NRF_GPIOTE_POLARITY_LOTOHI | NRF_GPIOTE_POLARITY_HITOLO} }, + { MP_QSTR_hard, MP_ARG_BOOL, {.u_bool = false} }, + }; + pin_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + machine_pin_irq_obj_t *irq = machine_pin_get_irq(self->pin); + + if (n_args > 1 || kw_args->used != 0) { + mp_obj_t handler = args[ARG_handler].u_obj; + mp_uint_t trigger = args[ARG_trigger].u_int; + bool hard = args[ARG_hard].u_bool; + + irq->base.handler = handler; + irq->base.ishard = hard; + irq->flags = 0; + irq->trigger = trigger; + + if (handler != mp_const_none) { + machine_pin_irq_trigger_set(self->pin, trigger); + } else { + machine_pin_irq_trigger_set(self->pin, 0); + } + } + + return MP_OBJ_FROM_PTR(irq); +} +static MP_DEFINE_CONST_FUN_OBJ_KW(pin_irq_obj, 1, pin_irq); + +#else // !MICROPY_ENABLE_SCHEDULER +// Note: this path is dead code on the nrf port (MICROPY_ENABLE_SCHEDULER is +// always 1). It is retained for custom board configurations that may disable +// the scheduler. Limitations vs the scheduler-enabled path: +// - The "hard" parameter is accepted but ignored; handler always runs in ISR. +// - Returns mp_const_none instead of an mp_irq_obj_t. + static void pin_common_irq_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t action, void *p_context) { (void)p_context; mp_obj_t pin_handler = MP_STATE_PORT(pin_irq_handlers)[pin]; @@ -526,92 +658,44 @@ static void pin_common_irq_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t const pin_obj_t *pin_obj = pin_find(pin_number); if (pin_handler != mp_const_none) { - #if MICROPY_ENABLE_SCHEDULER - mp_sched_lock(); - #endif - // When executing code within a handler we must lock the GC to prevent - // any memory allocations. We must also catch any exceptions. gc_lock(); nlr_buf_t nlr; if (nlr_push(&nlr) == 0) { mp_call_function_1(pin_handler, (mp_obj_t)pin_obj); nlr_pop(); } else { - // Uncaught exception; disable the callback so it doesn't run again. MP_STATE_PORT(pin_irq_handlers)[pin] = mp_const_none; pin_gpiote_release(pin); mp_printf(MICROPY_ERROR_PRINTER, "uncaught exception in interrupt handler for Pin('%q')\n", pin_obj->name); mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(nlr.ret_val)); } gc_unlock(); - #if MICROPY_ENABLE_SCHEDULER - mp_sched_unlock(); - #endif } } static mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { - enum {ARG_handler, ARG_trigger, ARG_wake}; + enum { ARG_handler, ARG_trigger, ARG_hard }; static const mp_arg_t allowed_args[] = { - { MP_QSTR_handler, MP_ARG_OBJ | MP_ARG_REQUIRED, {.u_obj = mp_const_none} }, - { MP_QSTR_trigger, MP_ARG_INT, {.u_int = NRF_GPIOTE_POLARITY_LOTOHI | NRF_GPIOTE_POLARITY_HITOLO} }, - { MP_QSTR_wake, MP_ARG_BOOL, {.u_bool = false} }, + { MP_QSTR_handler, MP_ARG_OBJ | MP_ARG_REQUIRED, {.u_obj = mp_const_none} }, + { MP_QSTR_trigger, MP_ARG_INT, {.u_int = NRF_GPIOTE_POLARITY_LOTOHI | NRF_GPIOTE_POLARITY_HITOLO} }, + { MP_QSTR_hard, MP_ARG_BOOL, {.u_bool = false} }, }; pin_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); nrfx_gpiote_pin_t pin = self->pin; - - pin_gpiote_release(pin); - - if (args[ARG_handler].u_obj != mp_const_none) { - nrfx_gpiote_trigger_t trigger = NRFX_GPIOTE_TRIGGER_TOGGLE; - if (args[ARG_trigger].u_int == NRF_GPIOTE_POLARITY_LOTOHI) { - trigger = NRFX_GPIOTE_TRIGGER_LOTOHI; - } else if (args[ARG_trigger].u_int == NRF_GPIOTE_POLARITY_HITOLO) { - trigger = NRFX_GPIOTE_TRIGGER_HITOLO; - } - - uint8_t gpiote_ch; - nrfx_err_t err = nrfx_gpiote_channel_alloc(&gpiote_inst, &gpiote_ch); - - nrfx_gpiote_trigger_config_t trigger_config = { - .trigger = trigger, - .p_in_channel = (err == NRFX_SUCCESS) ? &gpiote_ch : NULL, - }; - nrfx_gpiote_handler_config_t handler_config = { - .handler = pin_common_irq_handler, - .p_context = NULL, - }; - nrfx_gpiote_input_pin_config_t input_config = { - .p_pull_config = NULL, - .p_trigger_config = &trigger_config, - .p_handler_config = &handler_config, - }; - - nrfx_err_t cfg_err = nrfx_gpiote_input_configure(&gpiote_inst, pin, &input_config); - if (cfg_err != NRFX_SUCCESS) { - if (err == NRFX_SUCCESS) { - nrfx_gpiote_channel_free(&gpiote_inst, gpiote_ch); - } - mp_raise_ValueError(MP_ERROR_TEXT("pin IRQ config failed")); - } - - if (err == NRFX_SUCCESS) { - pin_gpiote_ch[pin] = gpiote_ch; - } - - nrfx_gpiote_trigger_enable(&gpiote_inst, pin, true); - } + mp_uint_t trigger = args[ARG_handler].u_obj != mp_const_none ? args[ARG_trigger].u_int : 0; + machine_pin_irq_trigger_set(pin, trigger); MP_STATE_PORT(pin_irq_handlers)[pin] = args[ARG_handler].u_obj; - // return the irq object return mp_const_none; } static MP_DEFINE_CONST_FUN_OBJ_KW(pin_irq_obj, 1, pin_irq); +#endif // MICROPY_ENABLE_SCHEDULER + static const mp_rom_map_elem_t pin_locals_dict_table[] = { // instance methods { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pin_init_obj) }, @@ -754,6 +838,36 @@ MP_DEFINE_CONST_OBJ_TYPE( locals_dict, &pin_af_locals_dict ); +#if MICROPY_ENABLE_SCHEDULER +static mp_uint_t machine_pin_irq_trigger(mp_obj_t self_in, mp_uint_t new_trigger) { + pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_obj[self->pin]); + irq->flags = 0; + irq->trigger = new_trigger; + return machine_pin_irq_trigger_set(self->pin, new_trigger); +} + +static mp_uint_t machine_pin_irq_info(mp_obj_t self_in, mp_uint_t info_type) { + pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_obj[self->pin]); + if (info_type == MP_IRQ_INFO_FLAGS) { + return irq->flags; + } else if (info_type == MP_IRQ_INFO_TRIGGERS) { + return irq->trigger; + } + return 0; +} + +static const mp_irq_methods_t machine_pin_irq_methods = { + .trigger = machine_pin_irq_trigger, + .info = machine_pin_irq_info, +}; +#endif + MP_REGISTER_ROOT_POINTER(mp_obj_t pin_class_mapper); MP_REGISTER_ROOT_POINTER(mp_obj_t pin_class_map_dict); +#if MICROPY_ENABLE_SCHEDULER +MP_REGISTER_ROOT_POINTER(void *machine_pin_irq_obj[NUM_OF_PINS]); +#else MP_REGISTER_ROOT_POINTER(mp_obj_t pin_irq_handlers[NUM_OF_PINS]); +#endif From 080e2ed1626f5d8d10a72b38d6cbcf7aa9deeb51 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Apr 2026 15:19:28 +1000 Subject: [PATCH 030/635] nrf: Preserve SPI config across init calls. Use -1 sentinels for SPI init parameters so that calling spi.init(baudrate=X) no longer resets polarity, phase, and other settings to defaults. Matches the rp2 port behavior. Signed-off-by: Andrew Leech --- ports/nrf/modules/machine/spi.c | 126 ++++++++++++++++++-------------- 1 file changed, 72 insertions(+), 54 deletions(-) diff --git a/ports/nrf/modules/machine/spi.c b/ports/nrf/modules/machine/spi.c index e3f72cba385..9ed24bd9b90 100644 --- a/ports/nrf/modules/machine/spi.c +++ b/ports/nrf/modules/machine/spi.c @@ -188,6 +188,9 @@ enum { }; static inline uint32_t machine_hard_spi_get_baudrate(const machine_hard_spi_obj_t *self) { + #if NRFX_SPIM_ENABLED + return self->p_config->frequency; + #else MP_STATIC_ASSERT(NRF_SPI_FREQ_125K == (2 << 24)); MP_STATIC_ASSERT(NRF_SPI_FREQ_250K == (4 << 24)); MP_STATIC_ASSERT(NRF_SPI_FREQ_500K == (8 << 24)); @@ -195,15 +198,8 @@ static inline uint32_t machine_hard_spi_get_baudrate(const machine_hard_spi_obj_ MP_STATIC_ASSERT(NRF_SPI_FREQ_2M == (32 << 24)); MP_STATIC_ASSERT(NRF_SPI_FREQ_4M == (64 << 24)); MP_STATIC_ASSERT(NRF_SPI_FREQ_8M == (128 << 24)); - #if defined(NRF52840_XXAA) && NRFX_SPIM_ENABLED - if (self->p_config->frequency == NRF_SPIM_FREQ_16M) { - return 16000000; - } - if (self->p_config->frequency == NRF_SPIM_FREQ_32M) { - return 32000000; - } - #endif return 125000 * (self->p_config->frequency >> 25); + #endif } static void machine_hard_spi_init_helper(const machine_hard_spi_obj_t *self, mp_arg_val_t *args); @@ -266,54 +262,76 @@ static mp_obj_t machine_hard_spi_make_new(const mp_obj_type_t *type, size_t n_ar } static void machine_hard_spi_init_helper(const machine_hard_spi_obj_t *self, mp_arg_val_t *args) { - int baudrate = args[ARG_INIT_baudrate].u_int; - - if (baudrate <= 125000) { - self->p_config->frequency = NRF_SPI_FREQ_125K; - } else if (baudrate <= 250000) { - self->p_config->frequency = NRF_SPI_FREQ_250K; - } else if (baudrate <= 500000) { - self->p_config->frequency = NRF_SPI_FREQ_500K; - } else if (baudrate <= 1000000) { - self->p_config->frequency = NRF_SPI_FREQ_1M; - } else if (baudrate <= 2000000) { - self->p_config->frequency = NRF_SPI_FREQ_2M; - } else if (baudrate <= 4000000) { - self->p_config->frequency = NRF_SPI_FREQ_4M; - } else if (baudrate <= 8000000) { - self->p_config->frequency = NRF_SPI_FREQ_8M; - #if defined(NRF52840_XXAA) && NRFX_SPIM_ENABLED - } else if (baudrate <= 16000000) { - self->p_config->frequency = NRF_SPIM_FREQ_16M; - } else if (baudrate <= 32000000) { - self->p_config->frequency = NRF_SPIM_FREQ_32M; - #endif // NRF52840_XXAA && NRFX_SPIM_ENABLED - } else { // Default - self->p_config->frequency = NRF_SPI_FREQ_1M; + if (args[ARG_INIT_baudrate].u_int != -1) { + int baudrate = args[ARG_INIT_baudrate].u_int; + #if NRFX_SPIM_ENABLED + // nrfx v3 SPIM takes frequency in Hz but only supports specific values. + if (baudrate <= 125000) { + self->p_config->frequency = 125000; + } else if (baudrate <= 250000) { + self->p_config->frequency = 250000; + } else if (baudrate <= 500000) { + self->p_config->frequency = 500000; + } else if (baudrate <= 1000000) { + self->p_config->frequency = 1000000; + } else if (baudrate <= 2000000) { + self->p_config->frequency = 2000000; + } else if (baudrate <= 4000000) { + self->p_config->frequency = 4000000; + } else if (baudrate <= 8000000) { + self->p_config->frequency = 8000000; + #if NRF_SPIM_HAS_16_MHZ_FREQ + } else if (baudrate <= 16000000) { + self->p_config->frequency = 16000000; + #endif + #if NRF_SPIM_HAS_32_MHZ_FREQ + } else if (baudrate <= 32000000) { + self->p_config->frequency = 32000000; + #endif + } else { + self->p_config->frequency = 1000000; + } + #else + if (baudrate <= 125000) { + self->p_config->frequency = NRF_SPI_FREQ_125K; + } else if (baudrate <= 250000) { + self->p_config->frequency = NRF_SPI_FREQ_250K; + } else if (baudrate <= 500000) { + self->p_config->frequency = NRF_SPI_FREQ_500K; + } else if (baudrate <= 1000000) { + self->p_config->frequency = NRF_SPI_FREQ_1M; + } else if (baudrate <= 2000000) { + self->p_config->frequency = NRF_SPI_FREQ_2M; + } else if (baudrate <= 4000000) { + self->p_config->frequency = NRF_SPI_FREQ_4M; + } else if (baudrate <= 8000000) { + self->p_config->frequency = NRF_SPI_FREQ_8M; + } else { + self->p_config->frequency = NRF_SPI_FREQ_1M; + } + #endif } - if (args[ARG_INIT_polarity].u_int == 0) { - // Active high - if (args[ARG_INIT_phase].u_int == 0) { - // First clock edge - self->p_config->mode = NRF_SPI_MODE_0; - } else { - // Second clock edge - self->p_config->mode = NRF_SPI_MODE_1; + int polarity = args[ARG_INIT_polarity].u_int; + int phase = args[ARG_INIT_phase].u_int; + if (polarity != -1 || phase != -1) { + if (polarity == -1) { + polarity = (self->p_config->mode == NRF_SPI_MODE_2 || self->p_config->mode == NRF_SPI_MODE_3) ? 1 : 0; } - } else { - // Active low - if (args[ARG_INIT_phase].u_int == 0) { - // First clock edge - self->p_config->mode = NRF_SPI_MODE_2; + if (phase == -1) { + phase = (self->p_config->mode == NRF_SPI_MODE_1 || self->p_config->mode == NRF_SPI_MODE_3) ? 1 : 0; + } + if (polarity == 0) { + self->p_config->mode = (phase == 0) ? NRF_SPI_MODE_0 : NRF_SPI_MODE_1; } else { - // Second clock edge - self->p_config->mode = NRF_SPI_MODE_3; + self->p_config->mode = (phase == 0) ? NRF_SPI_MODE_2 : NRF_SPI_MODE_3; } } - self->p_config->orc = 0xFF; // Overrun character - self->p_config->bit_order = (args[ARG_INIT_firstbit].u_int == 0) ? NRF_SPI_BIT_ORDER_MSB_FIRST : NRF_SPI_BIT_ORDER_LSB_FIRST; + self->p_config->orc = 0xFF; + if (args[ARG_INIT_firstbit].u_int != -1) { + self->p_config->bit_order = (args[ARG_INIT_firstbit].u_int == 0) ? NRF_SPI_BIT_ORDER_MSB_FIRST : NRF_SPI_BIT_ORDER_LSB_FIRST; + } // Set context to this instance of SPI nrfx_err_t err_code = nrfx_spi_init(self->p_spi, self->p_config, NULL, (void *)self); @@ -328,11 +346,11 @@ static void machine_hard_spi_init_helper(const machine_hard_spi_obj_t *self, mp_ static void machine_hard_spi_init(mp_obj_base_t *self_in, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { static const mp_arg_t allowed_args[] = { - { MP_QSTR_baudrate, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000000} }, - { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, - { MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, - { MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} }, - { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_baudrate, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, }; // parse args From ac0af105a9d770ff667aa14595ab07d37dafad33 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Apr 2026 15:19:36 +1000 Subject: [PATCH 031/635] nrf: Add I2C timeout parameter and fix disable on error. Accept the timeout kwarg (default 50ms) for compatibility with rp2 and alif ports. Also fix TWI peripheral not being disabled on the transfer error path. Signed-off-by: Andrew Leech --- ports/nrf/modules/machine/i2c.c | 59 +++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 6 deletions(-) diff --git a/ports/nrf/modules/machine/i2c.c b/ports/nrf/modules/machine/i2c.c index ced53346414..e2b7a19a27d 100644 --- a/ports/nrf/modules/machine/i2c.c +++ b/ports/nrf/modules/machine/i2c.c @@ -55,11 +55,20 @@ #define nrfx_twi_xfer_desc_t nrfx_twim_xfer_desc_t +#define nrfx_twi_evt_handler_t nrfx_twim_evt_handler_t +#define nrfx_twi_evt_t nrfx_twim_evt_t +#define nrfx_twi_evt_type_t nrfx_twim_evt_type_t + #define NRFX_TWI_XFER_DESC_RX NRFX_TWIM_XFER_DESC_RX #define NRFX_TWI_XFER_DESC_TX NRFX_TWIM_XFER_DESC_TX #define NRFX_TWI_INSTANCE NRFX_TWIM_INSTANCE +#define NRFX_TWI_EVT_DONE NRFX_TWIM_EVT_DONE +#define NRFX_TWI_EVT_ADDRESS_NACK NRFX_TWIM_EVT_ADDRESS_NACK +#define NRFX_TWI_EVT_DATA_NACK NRFX_TWIM_EVT_DATA_NACK +#define NRFX_TWI_EVT_BUS_ERROR NRFX_TWIM_EVT_BUS_ERROR + #define NRF_TWI_FREQ_100K NRF_TWIM_FREQ_100K #define NRF_TWI_FREQ_250K NRF_TWIM_FREQ_250K #define NRF_TWI_FREQ_400K NRF_TWIM_FREQ_400K @@ -69,9 +78,12 @@ typedef struct _machine_hard_i2c_obj_t { mp_obj_base_t base; nrfx_twi_t p_twi; // Driver instance + uint32_t timeout; + volatile bool xfer_done; + volatile nrfx_twi_evt_type_t xfer_evt; } machine_hard_i2c_obj_t; -static const machine_hard_i2c_obj_t machine_hard_i2c_obj[] = { +static machine_hard_i2c_obj_t machine_hard_i2c_obj[] = { {{&machine_i2c_type}, .p_twi = NRFX_TWI_INSTANCE(0)}, {{&machine_i2c_type}, .p_twi = NRFX_TWI_INSTANCE(1)}, }; @@ -79,6 +91,12 @@ static const machine_hard_i2c_obj_t machine_hard_i2c_obj[] = { void i2c_init0(void) { } +static void twi_event_handler(nrfx_twi_evt_t const *p_event, void *p_context) { + machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t *)p_context; + self->xfer_evt = p_event->type; + self->xfer_done = true; +} + static int i2c_find(mp_obj_t id) { // given an integer id int i2c_id = mp_obj_get_int(id); @@ -90,7 +108,7 @@ static int i2c_find(mp_obj_t id) { static void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { machine_hard_i2c_obj_t *self = self_in; - mp_printf(print, "I2C(%u)", self->p_twi.drv_inst_idx); + mp_printf(print, "I2C(%u, timeout=%u)", self->p_twi.drv_inst_idx, self->timeout); } /******************************************************************************/ @@ -99,12 +117,13 @@ static void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { MP_MACHINE_I2C_CHECK_FOR_LEGACY_SOFTI2C_CONSTRUCTION(n_args, n_kw, all_args); - enum { ARG_id, ARG_scl, ARG_sda, ARG_freq }; + enum { ARG_id, ARG_scl, ARG_sda, ARG_freq, ARG_timeout }; static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ }, { MP_QSTR_scl, MP_ARG_REQUIRED | MP_ARG_OBJ }, { MP_QSTR_sda, MP_ARG_REQUIRED | MP_ARG_OBJ }, { MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 50000} }, }; // parse args @@ -113,7 +132,9 @@ mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, siz // get static peripheral object int i2c_id = i2c_find(args[ARG_id].u_obj); - const machine_hard_i2c_obj_t *self = &machine_hard_i2c_obj[i2c_id]; + machine_hard_i2c_obj_t *self = &machine_hard_i2c_obj[i2c_id]; + + self->timeout = args[ARG_timeout].u_int; nrfx_twi_config_t config; memset(&config, 0, sizeof(config)); @@ -140,8 +161,8 @@ mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, siz // First reset the TWI nrfx_twi_uninit(&self->p_twi); - // Set context to this object. - nrfx_twi_init(&self->p_twi, &config, NULL, (void *)self); + // Set context to this object, use non-blocking mode with event handler. + nrfx_twi_init(&self->p_twi, &config, twi_event_handler, (void *)self); return MP_OBJ_FROM_PTR(self); } @@ -151,6 +172,9 @@ int machine_hard_i2c_transfer_single(mp_obj_base_t *self_in, uint16_t addr, size nrfx_twi_enable(&self->p_twi); + self->xfer_done = false; + self->xfer_evt = NRFX_TWI_EVT_DONE; + nrfx_err_t err_code; int transfer_ret = 0; if (flags & MP_MACHINE_I2C_FLAG_READ) { @@ -162,7 +186,10 @@ int machine_hard_i2c_transfer_single(mp_obj_base_t *self_in, uint16_t addr, size transfer_ret = len; } + // In non-blocking mode, ANACK/DNACK are delivered via the event handler. + // These checks handle transfer start failures (e.g. bus busy). if (err_code != NRFX_SUCCESS) { + nrfx_twi_disable(&self->p_twi); if (err_code == NRFX_ERROR_DRV_TWI_ERR_ANACK) { return -MP_ENODEV; } else if (err_code == NRFX_ERROR_DRV_TWI_ERR_DNACK) { @@ -171,8 +198,28 @@ int machine_hard_i2c_transfer_single(mp_obj_base_t *self_in, uint16_t addr, size return -MP_ETIMEDOUT; } + // Poll for transfer completion with timeout (timeout=0 means no timeout, + // the loop relies on MICROPY_EVENT_POLL_HOOK for Ctrl-C). + mp_uint_t start = mp_hal_ticks_us(); + while (!self->xfer_done) { + if (self->timeout > 0 && (mp_hal_ticks_us() - start) >= self->timeout) { + nrfx_twi_disable(&self->p_twi); + nrfx_twi_enable(&self->p_twi); + return -MP_ETIMEDOUT; + } + MICROPY_EVENT_POLL_HOOK; + } + nrfx_twi_disable(&self->p_twi); + if (self->xfer_evt == NRFX_TWI_EVT_ADDRESS_NACK) { + return -MP_ENODEV; + } else if (self->xfer_evt == NRFX_TWI_EVT_DATA_NACK) { + return -MP_EIO; + } else if (self->xfer_evt != NRFX_TWI_EVT_DONE) { + return -MP_EIO; + } + return transfer_ret; } From 7d3cf417d1c54a142705be088a32e9d84519ce7f Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 22 Apr 2026 14:57:05 +1000 Subject: [PATCH 032/635] nrf/Makefile: Update nrfutil deploy rules for latest nrfutil. The old `nrfutil` runs only under CPython 2.x and has been replaced by a new stand-alone `nrfutil` executable, available directly from Nordic. Update the Makefile to work with this new version, and also update the README to describe how to install it. Signed-off-by: Damien George --- ports/nrf/Makefile | 8 ++++---- ports/nrf/README.md | 10 ++++++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/ports/nrf/Makefile b/ports/nrf/Makefile index 546c17709e5..e39bf9639b8 100644 --- a/ports/nrf/Makefile +++ b/ports/nrf/Makefile @@ -449,12 +449,12 @@ sd: nrfutil_dfu_sd nrfutil_dfu_deploy nrfutil_dfu_sd: $(BUILD)/$(OUTPUT_FILENAME).hex $(Q)hexmerge.py -o $(BUILD)/stripped_sd.hex --range=0x1000: $(SOFTDEV_HEX) - $(Q)nrfutil pkg generate --hw-version 52 --sd-req 0x00 --sd-id 0x00 --softdevice $(BUILD)/stripped_sd.hex $(BUILD)/stripped_sd.zip - $(Q)nrfutil dfu usb-serial -pkg $(BUILD)/stripped_sd.zip -p $(NRFUTIL_PORT) -t 0 + $(Q)nrfutil nrf5sdk-tools pkg generate --hw-version 52 --sd-req 0x00 --sd-id 0x00 --softdevice $(BUILD)/stripped_sd.hex $(BUILD)/stripped_sd.zip + $(Q)nrfutil nrf5sdk-tools dfu usb-serial -pkg $(BUILD)/stripped_sd.zip -p $(NRFUTIL_PORT) -t 0 nrfutil_dfu_deploy: $(BUILD)/$(OUTPUT_FILENAME).hex - $(Q)nrfutil pkg generate --hw-version 52 --sd-req $(NRFUTIL_SD_REQ) --application-version 1 --application $(BUILD)/$(OUTPUT_FILENAME).hex $(BUILD)/$(OUTPUT_FILENAME)_dfu.zip - $(Q)nrfutil dfu usb-serial -pkg $(BUILD)/$(OUTPUT_FILENAME)_dfu.zip -p $(NRFUTIL_PORT) -t 0 + $(Q)nrfutil nrf5sdk-tools pkg generate --hw-version 52 --sd-req $(NRFUTIL_SD_REQ) --application-version 1 --application $(BUILD)/$(OUTPUT_FILENAME).hex $(BUILD)/$(OUTPUT_FILENAME)_dfu.zip + $(Q)nrfutil nrf5sdk-tools dfu usb-serial -pkg $(BUILD)/$(OUTPUT_FILENAME)_dfu.zip -p $(NRFUTIL_PORT) -t 0 deploy: nrfutil_dfu_deploy diff --git a/ports/nrf/README.md b/ports/nrf/README.md index 889ead5d4d7..b65683712c7 100644 --- a/ports/nrf/README.md +++ b/ports/nrf/README.md @@ -207,9 +207,15 @@ for more tips about using the BMP with GDB. ## nRFUtil Targets -Install the necessary Python packages that will be used for flashing using the bootloader: +First install the base `nrfutil` CLI tool from +[Nordic Semiconductor](https://www.nordicsemi.com/Products/Development-tools/nRF-Util). +Then install the SDK sub-package of that tool in order to get access to the `pkg` +and `dfu` commands: + + nrfutil install nrf5sdk-tools + +Then install the necessary Python packages: - sudo pip install nrfutil sudo pip install intelhex The `intelhex` provides the `hexmerge.py` utility which is used by the Makefile From 18e83d19c9b8847e9754518d5dbf6f6cfb80aa14 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 22 Apr 2026 15:03:24 +1000 Subject: [PATCH 033/635] nrf/boards: Change all boards to use "nrf" for sys.platform value. The `sys.platform` variable on bare-metal ports is uniformly the port name (except for stm32 which uses "pyboard" for `sys.platform`), regardless of the board. Change the nrf port to follow this convention. Among other things, this gets the test auto-detection working properly on nrf boards, which relies on the value of `sys.platform` (eg for target wiring selection). Signed-off-by: Damien George --- ports/nrf/boards/ACTINIUS_ICARUS/mpconfigboard.h | 1 - ports/nrf/boards/ARDUINO_PRIMO/mpconfigboard.h | 1 - ports/nrf/boards/BLUEIO_TAG_EVIM/mpconfigboard.h | 1 - ports/nrf/boards/DVK_BL652/mpconfigboard.h | 1 - ports/nrf/boards/EVK_NINA_B1/mpconfigboard.h | 1 - ports/nrf/boards/EVK_NINA_B3/mpconfigboard.h | 1 - ports/nrf/boards/FEATHER52/mpconfigboard.h | 1 - ports/nrf/boards/IBK_BLYST_NANO/mpconfigboard.h | 1 - ports/nrf/boards/IDK_BLYST_NANO/mpconfigboard.h | 1 - ports/nrf/boards/MICROBIT/mpconfigboard.h | 1 - ports/nrf/boards/NRF52840_MDK_USB_DONGLE/mpconfigboard.h | 1 - ports/nrf/boards/PARTICLE_XENON/mpconfigboard.h | 1 - ports/nrf/boards/PCA10000/mpconfigboard.h | 1 - ports/nrf/boards/PCA10001/mpconfigboard.h | 1 - ports/nrf/boards/PCA10028/mpconfigboard.h | 1 - ports/nrf/boards/PCA10031/mpconfigboard.h | 1 - ports/nrf/boards/PCA10040/mpconfigboard.h | 1 - ports/nrf/boards/PCA10056/mpconfigboard.h | 1 - ports/nrf/boards/PCA10059/mpconfigboard.h | 1 - ports/nrf/boards/PCA10090/mpconfigboard.h | 1 - ports/nrf/boards/SEEED_XIAO_NRF52/mpconfigboard.h | 1 - ports/nrf/boards/WT51822_S4AT/mpconfigboard.h | 1 - ports/nrf/mpconfigport.h | 2 -- 23 files changed, 24 deletions(-) diff --git a/ports/nrf/boards/ACTINIUS_ICARUS/mpconfigboard.h b/ports/nrf/boards/ACTINIUS_ICARUS/mpconfigboard.h index 87e9f8ed2e6..2d91456299f 100644 --- a/ports/nrf/boards/ACTINIUS_ICARUS/mpconfigboard.h +++ b/ports/nrf/boards/ACTINIUS_ICARUS/mpconfigboard.h @@ -28,7 +28,6 @@ #define MICROPY_HW_BOARD_NAME "Actinius Icarus" #define MICROPY_HW_MCU_NAME "NRF9160" -#define MICROPY_PY_SYS_PLATFORM "nrf9160" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_RTCOUNTER (1) diff --git a/ports/nrf/boards/ARDUINO_PRIMO/mpconfigboard.h b/ports/nrf/boards/ARDUINO_PRIMO/mpconfigboard.h index 6b1b4e0074c..d199c44fe3b 100644 --- a/ports/nrf/boards/ARDUINO_PRIMO/mpconfigboard.h +++ b/ports/nrf/boards/ARDUINO_PRIMO/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "Arduino Primo" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "nrf52" #define MICROPY_PY_MACHINE_SOFT_PWM (1) #define MICROPY_PY_MUSIC (1) diff --git a/ports/nrf/boards/BLUEIO_TAG_EVIM/mpconfigboard.h b/ports/nrf/boards/BLUEIO_TAG_EVIM/mpconfigboard.h index 417b49fce61..b667043d359 100644 --- a/ports/nrf/boards/BLUEIO_TAG_EVIM/mpconfigboard.h +++ b/ports/nrf/boards/BLUEIO_TAG_EVIM/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "BLUEIO-TAG-EVIM" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "BLYST Nano" #define MICROPY_PY_MACHINE_SOFT_PWM (1) #define MICROPY_PY_MUSIC (1) diff --git a/ports/nrf/boards/DVK_BL652/mpconfigboard.h b/ports/nrf/boards/DVK_BL652/mpconfigboard.h index fe77fe19574..7193bb9cb3e 100644 --- a/ports/nrf/boards/DVK_BL652/mpconfigboard.h +++ b/ports/nrf/boards/DVK_BL652/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "DVK-BL652" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "bl652" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_HW_PWM (1) diff --git a/ports/nrf/boards/EVK_NINA_B1/mpconfigboard.h b/ports/nrf/boards/EVK_NINA_B1/mpconfigboard.h index dd64ffb8b7f..f9a3be59337 100644 --- a/ports/nrf/boards/EVK_NINA_B1/mpconfigboard.h +++ b/ports/nrf/boards/EVK_NINA_B1/mpconfigboard.h @@ -28,7 +28,6 @@ // https://www.u-blox.com/sites/default/files/EVK-NINA-B1_UserGuide_%28UBX-15028120%29.pdf #define MICROPY_HW_BOARD_NAME "EVK_NINA_B1" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "nrf52" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_HW_PWM (1) diff --git a/ports/nrf/boards/EVK_NINA_B3/mpconfigboard.h b/ports/nrf/boards/EVK_NINA_B3/mpconfigboard.h index 98bd71eec87..d50250ed1f8 100644 --- a/ports/nrf/boards/EVK_NINA_B3/mpconfigboard.h +++ b/ports/nrf/boards/EVK_NINA_B3/mpconfigboard.h @@ -34,7 +34,6 @@ // Board data #define MICROPY_HW_BOARD_NAME "EVK_NINA_B3" #define MICROPY_HW_MCU_NAME "NRF52840" -#define MICROPY_PY_SYS_PLATFORM "nrf52" // Enable @viper and @native #define MICROPY_EMIT_THUMB (1) diff --git a/ports/nrf/boards/FEATHER52/mpconfigboard.h b/ports/nrf/boards/FEATHER52/mpconfigboard.h index 7dcc7357a69..1207c9b06c2 100644 --- a/ports/nrf/boards/FEATHER52/mpconfigboard.h +++ b/ports/nrf/boards/FEATHER52/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "Bluefruit nRF52 Feather" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "nrf52" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_HW_PWM (1) diff --git a/ports/nrf/boards/IBK_BLYST_NANO/mpconfigboard.h b/ports/nrf/boards/IBK_BLYST_NANO/mpconfigboard.h index 6d1c5364b53..d5121391c22 100644 --- a/ports/nrf/boards/IBK_BLYST_NANO/mpconfigboard.h +++ b/ports/nrf/boards/IBK_BLYST_NANO/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "IBK-BLYST-NANO" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "BLYST Nano" #define MICROPY_PY_MACHINE_SOFT_PWM (1) #define MICROPY_PY_MUSIC (1) diff --git a/ports/nrf/boards/IDK_BLYST_NANO/mpconfigboard.h b/ports/nrf/boards/IDK_BLYST_NANO/mpconfigboard.h index aacb49e7150..1f614fa4712 100644 --- a/ports/nrf/boards/IDK_BLYST_NANO/mpconfigboard.h +++ b/ports/nrf/boards/IDK_BLYST_NANO/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "IDK-BLYST-NANO" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "BLYST Nano" #define MICROPY_PY_MACHINE_SOFT_PWM (1) #define MICROPY_PY_MUSIC (1) diff --git a/ports/nrf/boards/MICROBIT/mpconfigboard.h b/ports/nrf/boards/MICROBIT/mpconfigboard.h index 3f9f873ff7d..1306aa4e361 100644 --- a/ports/nrf/boards/MICROBIT/mpconfigboard.h +++ b/ports/nrf/boards/MICROBIT/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "micro:bit" #define MICROPY_HW_MCU_NAME "NRF51822" -#define MICROPY_PY_SYS_PLATFORM "nrf51" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MUSIC (1) diff --git a/ports/nrf/boards/NRF52840_MDK_USB_DONGLE/mpconfigboard.h b/ports/nrf/boards/NRF52840_MDK_USB_DONGLE/mpconfigboard.h index 499abbc4efc..dc155a7ff2a 100644 --- a/ports/nrf/boards/NRF52840_MDK_USB_DONGLE/mpconfigboard.h +++ b/ports/nrf/boards/NRF52840_MDK_USB_DONGLE/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "MDK-USB-DONGLE" #define MICROPY_HW_MCU_NAME "NRF52840" -#define MICROPY_PY_SYS_PLATFORM "nrf52840-MDK-USB-Dongle" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_HW_PWM (1) diff --git a/ports/nrf/boards/PARTICLE_XENON/mpconfigboard.h b/ports/nrf/boards/PARTICLE_XENON/mpconfigboard.h index 35b70d61290..7d2c1c0db81 100644 --- a/ports/nrf/boards/PARTICLE_XENON/mpconfigboard.h +++ b/ports/nrf/boards/PARTICLE_XENON/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "XENON" #define MICROPY_HW_MCU_NAME "NRF52840" -#define MICROPY_PY_SYS_PLATFORM "PARTICLE-XENON" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_HW_PWM (1) diff --git a/ports/nrf/boards/PCA10000/mpconfigboard.h b/ports/nrf/boards/PCA10000/mpconfigboard.h index a450c3c36e4..630515d3da2 100644 --- a/ports/nrf/boards/PCA10000/mpconfigboard.h +++ b/ports/nrf/boards/PCA10000/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "PCA10000" #define MICROPY_HW_MCU_NAME "NRF51822" -#define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_SOFT_PWM (1) diff --git a/ports/nrf/boards/PCA10001/mpconfigboard.h b/ports/nrf/boards/PCA10001/mpconfigboard.h index 929189188ec..47a8c5e94e7 100644 --- a/ports/nrf/boards/PCA10001/mpconfigboard.h +++ b/ports/nrf/boards/PCA10001/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "PCA10001" #define MICROPY_HW_MCU_NAME "NRF51822" -#define MICROPY_PY_SYS_PLATFORM "nrf51-DK" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_SOFT_PWM (1) diff --git a/ports/nrf/boards/PCA10028/mpconfigboard.h b/ports/nrf/boards/PCA10028/mpconfigboard.h index df2e4e85d93..b05a2a477d4 100644 --- a/ports/nrf/boards/PCA10028/mpconfigboard.h +++ b/ports/nrf/boards/PCA10028/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "PCA10028" #define MICROPY_HW_MCU_NAME "NRF51822" -#define MICROPY_PY_SYS_PLATFORM "nrf51-DK" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_SOFT_PWM (1) diff --git a/ports/nrf/boards/PCA10031/mpconfigboard.h b/ports/nrf/boards/PCA10031/mpconfigboard.h index e74e83c663e..02add73b2cc 100644 --- a/ports/nrf/boards/PCA10031/mpconfigboard.h +++ b/ports/nrf/boards/PCA10031/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "PCA10031" #define MICROPY_HW_MCU_NAME "NRF51822" -#define MICROPY_PY_SYS_PLATFORM "nrf51-dongle" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_SOFT_PWM (1) diff --git a/ports/nrf/boards/PCA10040/mpconfigboard.h b/ports/nrf/boards/PCA10040/mpconfigboard.h index 2b1c4c7ef5c..7f8064fb99d 100644 --- a/ports/nrf/boards/PCA10040/mpconfigboard.h +++ b/ports/nrf/boards/PCA10040/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "PCA10040" #define MICROPY_HW_MCU_NAME "NRF52832" -#define MICROPY_PY_SYS_PLATFORM "nrf52-DK" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_HW_PWM (1) diff --git a/ports/nrf/boards/PCA10056/mpconfigboard.h b/ports/nrf/boards/PCA10056/mpconfigboard.h index b3ad76a7f44..7923f343582 100644 --- a/ports/nrf/boards/PCA10056/mpconfigboard.h +++ b/ports/nrf/boards/PCA10056/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "PCA10056" #define MICROPY_HW_MCU_NAME "NRF52840" -#define MICROPY_PY_SYS_PLATFORM "nrf52840-PDK" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_HW_PWM (1) diff --git a/ports/nrf/boards/PCA10059/mpconfigboard.h b/ports/nrf/boards/PCA10059/mpconfigboard.h index 97f6ccb9410..95494a963e2 100644 --- a/ports/nrf/boards/PCA10059/mpconfigboard.h +++ b/ports/nrf/boards/PCA10059/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "PCA10059" #define MICROPY_HW_MCU_NAME "NRF52840" -#define MICROPY_PY_SYS_PLATFORM "nrf52840-Dongle" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_HW_PWM (1) diff --git a/ports/nrf/boards/PCA10090/mpconfigboard.h b/ports/nrf/boards/PCA10090/mpconfigboard.h index 1989fd04764..ea25720a70d 100644 --- a/ports/nrf/boards/PCA10090/mpconfigboard.h +++ b/ports/nrf/boards/PCA10090/mpconfigboard.h @@ -28,7 +28,6 @@ #define MICROPY_HW_BOARD_NAME "PCA10090" #define MICROPY_HW_MCU_NAME "NRF9160" -#define MICROPY_PY_SYS_PLATFORM "nrf9160-DK" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_TIMER_NRF (0) diff --git a/ports/nrf/boards/SEEED_XIAO_NRF52/mpconfigboard.h b/ports/nrf/boards/SEEED_XIAO_NRF52/mpconfigboard.h index 1faa256d80b..ca90cd0b13c 100644 --- a/ports/nrf/boards/SEEED_XIAO_NRF52/mpconfigboard.h +++ b/ports/nrf/boards/SEEED_XIAO_NRF52/mpconfigboard.h @@ -26,7 +26,6 @@ #define MICROPY_HW_BOARD_NAME "XIAO nRF52840 Sense" #define MICROPY_HW_MCU_NAME "NRF52840" -#define MICROPY_PY_SYS_PLATFORM "nrf52" #define MICROPY_BOARD_EARLY_INIT XIAO_board_early_init #define MICROPY_BOARD_DEINIT XIAO_board_deinit diff --git a/ports/nrf/boards/WT51822_S4AT/mpconfigboard.h b/ports/nrf/boards/WT51822_S4AT/mpconfigboard.h index e9865cb4d66..0419ed72e0d 100644 --- a/ports/nrf/boards/WT51822_S4AT/mpconfigboard.h +++ b/ports/nrf/boards/WT51822_S4AT/mpconfigboard.h @@ -28,7 +28,6 @@ // https://4tronix.co.uk/picobot2/WT51822-S4AT.pdf #define MICROPY_HW_BOARD_NAME "WT51822-S4AT" #define MICROPY_HW_MCU_NAME "NRF51822" -#define MICROPY_PY_SYS_PLATFORM "nrf51" #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_RTCOUNTER (1) diff --git a/ports/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h index cad839d0e90..946c7f42d70 100644 --- a/ports/nrf/mpconfigport.h +++ b/ports/nrf/mpconfigport.h @@ -87,9 +87,7 @@ #define MICROPY_PY_ARRAY_SLICE_ASSIGN (CORE_FEAT) #endif -#ifndef MICROPY_PY_SYS_PLATFORM #define MICROPY_PY_SYS_PLATFORM "nrf" -#endif #ifndef MICROPY_PY_SYS_STDFILES #define MICROPY_PY_SYS_STDFILES (CORE_FEAT) From 6bbd7bcc60f6b258f2b35eca61a3a0a90484edff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Fri, 1 May 2026 17:24:09 +0200 Subject: [PATCH 034/635] nrf/boards: Use 64 byte raw-paste buffer on PCA10031. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apply the same workaround as added in cc7eb1a5351c0d7d60f084dc79ccd0fa047b259e for other boards to the NRF51-Dongle, since it also suffers from the same limitation. This change makes it possible to run unit tests against it. Signed-off-by: Daniël van de Giessen --- ports/nrf/boards/PCA10031/mpconfigboard.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/ports/nrf/boards/PCA10031/mpconfigboard.h b/ports/nrf/boards/PCA10031/mpconfigboard.h index 02add73b2cc..9711b1ea40b 100644 --- a/ports/nrf/boards/PCA10031/mpconfigboard.h +++ b/ports/nrf/boards/PCA10031/mpconfigboard.h @@ -58,3 +58,8 @@ #define MICROPY_HW_SPI0_MISO (17) #define HELP_TEXT_BOARD_LED "1,2,3" + +// The JLink CDC on the PCA10031 cannot accept more than 64 incoming bytes at a time. +// That makes the UART REPL unreliable in general. But it can be improved to some +// extent by setting the raw-paste buffer size to that limit of 64. +#define MICROPY_REPL_STDIN_BUFFER_MAX (64) From a876a2acedb4fe51cc73c082081676949662f2d4 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Fri, 17 Apr 2026 22:30:49 +1000 Subject: [PATCH 035/635] unix/unix_mphal: Use TCSANOW for terminal mode switching. Change tcsetattr from TCSAFLUSH to TCSANOW in mp_hal_stdio_mode_raw and mp_hal_stdio_mode_orig. The TCSAFLUSH flag calls tcdrain() before applying terminal settings, which blocks indefinitely on macOS when used with PTY devices if the master side has not read all pending output. This is a known macOS kernel behavior (XNU ttywait loops until the output queue is consumed by the master). The drain serves no practical purpose on the unix port since output is written via write() syscalls that complete before tcsetattr is called. The input flush is also unnecessary since MicroPython's readline handles stale input gracefully. Two repl_ test .exp files are updated to account for the newline after Ctrl-D (end paste mode) no longer being discarded by the input flush; it produces an extra empty prompt line. Signed-off-by: Andrew Leech --- ports/unix/unix_mphal.c | 4 ++-- tests/cmdline/repl_autocomplete_underscore.py.exp | 1 + tests/cmdline/repl_paste.py.exp | 7 +++++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/ports/unix/unix_mphal.c b/ports/unix/unix_mphal.c index b0861aaa774..d04e0b96e7e 100644 --- a/ports/unix/unix_mphal.c +++ b/ports/unix/unix_mphal.c @@ -111,12 +111,12 @@ void mp_hal_stdio_mode_raw(void) { termios.c_lflag = 0; termios.c_cc[VMIN] = 1; termios.c_cc[VTIME] = 0; - tcsetattr(0, TCSAFLUSH, &termios); + tcsetattr(0, TCSANOW, &termios); } void mp_hal_stdio_mode_orig(void) { // restore terminal settings - tcsetattr(0, TCSAFLUSH, &orig_termios); + tcsetattr(0, TCSANOW, &orig_termios); } #endif diff --git a/tests/cmdline/repl_autocomplete_underscore.py.exp b/tests/cmdline/repl_autocomplete_underscore.py.exp index f2d3a44c9ad..54882267d9b 100644 --- a/tests/cmdline/repl_autocomplete_underscore.py.exp +++ b/tests/cmdline/repl_autocomplete_underscore.py.exp @@ -26,6 +26,7 @@ paste mode; Ctrl-C to cancel, Ctrl-D to finish === def _private_property(self): === return 99 === \$ +>>> \$ >>> # Paste executed >>> \$ >>> # Create an instance diff --git a/tests/cmdline/repl_paste.py.exp b/tests/cmdline/repl_paste.py.exp index 3165b863052..a95d9fd2f7b 100644 --- a/tests/cmdline/repl_paste.py.exp +++ b/tests/cmdline/repl_paste.py.exp @@ -12,6 +12,7 @@ paste mode; Ctrl-C to cancel, Ctrl-D to finish === \$ Hello from paste mode! >>> \$ +>>> \$ >>> # Paste mode with multiple indentation levels >>> \$ paste mode; Ctrl-C to cancel, Ctrl-D to finish @@ -34,6 +35,7 @@ Even: 2 Odd: 3 Even: 4 >>> \$ +>>> \$ >>> # Paste mode with blank lines >>> \$ paste mode; Ctrl-C to cancel, Ctrl-D to finish @@ -52,6 +54,7 @@ First line After blank line After two blank lines >>> \$ +>>> \$ >>> # Paste mode with class definition and multiple methods >>> \$ paste mode; Ctrl-C to cancel, Ctrl-D to finish @@ -76,6 +79,7 @@ Value is: 21 Doubled: 42 Value is: 42 >>> \$ +>>> \$ >>> # Paste mode with exception handling >>> \$ paste mode; Ctrl-C to cancel, Ctrl-D to finish @@ -90,6 +94,7 @@ paste mode; Ctrl-C to cancel, Ctrl-D to finish Caught division by zero Finally block executed >>> \$ +>>> \$ >>> # Cancel paste mode with Ctrl-C >>> \$ paste mode; Ctrl-C to cancel, Ctrl-D to finish @@ -113,6 +118,7 @@ Traceback (most recent call last): File "", line 2 SyntaxError: invalid syntax >>> \$ +>>> \$ >>> # Paste mode with runtime error >>> \$ paste mode; Ctrl-C to cancel, Ctrl-D to finish @@ -127,6 +133,7 @@ Traceback (most recent call last): File "", line 3, in will_error NameError: name 'undefined_variable' isn't defined >>> \$ +>>> \$ >>> # Final test to show REPL is still functioning >>> 1 + 2 + 3 6 From 30781dce0a13b8e10d76bf02eb683fc0b2f38560 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Fri, 17 Apr 2026 22:31:03 +1000 Subject: [PATCH 036/635] tests/cmdline: Add Ctrl-C interrupt test for the repl_ test framework. Adds a "# sigint:" directive for repl_ tests that need Ctrl-C to generate SIGINT via the PTY terminal driver. When present, the child process is set up with the PTY as its controlling terminal (via setsid/TIOCSCTTY/tcsetpgrp) so that \x03 written to the PTY master generates SIGINT for the child's process group. This works because MicroPython's REPL restores original terminal settings (with ISIG enabled) before executing user code, allowing the terminal driver to convert \x03 into SIGINT during blocking operations. Test added: - repl_ctrl_c_interrupt_execution.py: Verifies Ctrl-C interrupts a blocking time.sleep() call and the REPL remains functional afterward. Also wraps PTY fd handling in try/finally for all repl_ tests. Signed-off-by: Andrew Leech --- pyproject.toml | 1 + .../repl_ctrl_c_interrupt_execution.py | 8 ++ .../repl_ctrl_c_interrupt_execution.py.exp | 15 +++ tests/run-tests.py | 96 +++++++++++++++---- 4 files changed, 99 insertions(+), 21 deletions(-) create mode 100644 tests/cmdline/repl_ctrl_c_interrupt_execution.py create mode 100644 tests/cmdline/repl_ctrl_c_interrupt_execution.py.exp diff --git a/pyproject.toml b/pyproject.toml index 55763552fa8..f528961b2c8 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -51,6 +51,7 @@ exclude = [ # Ruff finds Python SyntaxError in these files "tests/cmdline/repl_autoindent.py", "tests/cmdline/repl_basic.py", "tests/cmdline/repl_cont.py", + "tests/cmdline/repl_ctrl_c_interrupt_execution.py", "tests/cmdline/repl_emacs_keys.py", "tests/cmdline/repl_paste.py", "tests/cmdline/repl_words_move.py", diff --git a/tests/cmdline/repl_ctrl_c_interrupt_execution.py b/tests/cmdline/repl_ctrl_c_interrupt_execution.py new file mode 100644 index 00000000000..b125e2c16b4 --- /dev/null +++ b/tests/cmdline/repl_ctrl_c_interrupt_execution.py @@ -0,0 +1,8 @@ +# sigint: deliver via controlling terminal +# Test that Ctrl-C (SIGINT) interrupts blocking code execution. +# MicroPython restores original terminal mode (ISIG on) during +# execution, so the PTY terminal driver generates SIGINT from \x03. +import time +time.sleep(10) +{\x03} +print('repl still responds') diff --git a/tests/cmdline/repl_ctrl_c_interrupt_execution.py.exp b/tests/cmdline/repl_ctrl_c_interrupt_execution.py.exp new file mode 100644 index 00000000000..48baad0193a --- /dev/null +++ b/tests/cmdline/repl_ctrl_c_interrupt_execution.py.exp @@ -0,0 +1,15 @@ +MicroPython \.\+ version +Type "help()" for more information. +>>> # sigint: deliver via controlling terminal +>>> # Test that Ctrl-C (SIGINT) interrupts blocking code execution. +>>> # MicroPython restores original terminal mode (ISIG on) during +>>> # execution, so the PTY terminal driver generates SIGINT from \x03. +>>> import time +>>> time.sleep(10) +######## +\.\*Traceback (most recent call last): + File "", line 1, in +KeyboardInterrupt: \$ +>>> print('repl still responds') +repl still responds +>>> \$ diff --git a/tests/run-tests.py b/tests/run-tests.py index ba6197acf3e..eb6f9d6f9cb 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -460,11 +460,16 @@ def run_micropython(pyb, args, test_file, test_file_abspath, is_special=False): if is_special: # check for any cmdline options needed for this test cmdlist = [MICROPYTHON] + send_sigint = False with open(test_file, "rb") as f: - line = f.readline() - if line.startswith(b"# cmdline:"): - # subprocess.check_output on Windows only accepts strings, not bytes - cmdlist += [str(c, "utf-8") for c in line[10:].strip().split()] + for line in f: + if line.startswith(b"# cmdline:"): + # subprocess.check_output on Windows only accepts strings, not bytes + cmdlist += [str(c, "utf-8") for c in line[10:].strip().split()] + elif line.startswith(b"# sigint:"): + send_sigint = True + elif not line.startswith(b"#"): + break # run the test, possibly with redirected input try: @@ -499,27 +504,76 @@ def send_get(what): os.write(master, what) return get() + def send_ctrl_c(): + # Send \x03 without trailing newline and wait for + # the full response (traceback + new prompt). + os.write(master, b"\x03") + return get(True) + with open(test_file, "rb") as f: # instead of: output_mupy = subprocess.check_output(cmdlist, stdin=f) master, slave = pty.openpty() - p = subprocess.Popen( - cmdlist, stdin=slave, stdout=slave, stderr=subprocess.STDOUT, bufsize=0 - ) - banner = get(True) - output_mupy = banner + b"".join(send_get(line) for line in f) - send_get(b"\x04") # exit the REPL, so coverage info is saved - # At this point the process might have exited already, but trying to - # kill it 'again' normally doesn't result in exceptions as Python and/or - # the OS seem to try to handle this nicely. When running Linux on WSL - # though, the situation differs and calling Popen.kill after the process - # terminated results in a ProcessLookupError. Just catch that one here - # since we just want the process to be gone and that's the case. try: - p.kill() - except ProcessLookupError: - pass - os.close(master) - os.close(slave) + preexec_fn = None + use_sigint_kill = False + # Tests with "# sigint:" need Ctrl-C (\x03) to + # generate SIGINT. MicroPython restores original + # terminal mode (ISIG on) during code execution, + # so on Linux we set up the PTY as a controlling + # terminal for proper signal delivery. On macOS, + # setsid/TIOCSCTTY breaks PTY I/O, so we fall + # back to os.kill(). + if send_sigint: + if sys.platform == "darwin": + use_sigint_kill = True + else: + import fcntl + import termios + + def preexec_fn(): + os.setsid() + fcntl.ioctl(0, termios.TIOCSCTTY, 0) + os.tcsetpgrp(0, os.getpid()) + + p = subprocess.Popen( + cmdlist, + stdin=slave, + stdout=slave, + stderr=subprocess.STDOUT, + bufsize=0, + preexec_fn=preexec_fn, + ) + banner = get(True) + if send_sigint: + import signal + + parts = [] + for line in f: + if b"{\\x03}" in line: + if use_sigint_kill: + os.kill(p.pid, signal.SIGINT) + parts.append(get(True)) + else: + parts.append(send_ctrl_c()) + else: + parts.append(send_get(line)) + output_mupy = banner + b"".join(parts) + else: + output_mupy = banner + b"".join(send_get(line) for line in f) + send_get(b"\x04") # exit the REPL, so coverage info is saved + # At this point the process might have exited already, but trying to + # kill it 'again' normally doesn't result in exceptions as Python and/or + # the OS seem to try to handle this nicely. When running Linux on WSL + # though, the situation differs and calling Popen.kill after the process + # terminated results in a ProcessLookupError. Just catch that one here + # since we just want the process to be gone and that's the case. + try: + p.kill() + except ProcessLookupError: + pass + finally: + os.close(master) + os.close(slave) else: output_mupy = subprocess.check_output( cmdlist + [test_file], stderr=subprocess.STDOUT From 72222a63ca6e9cf9f0cd6b7edb219e386f6e9f7c Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 8 Apr 2026 16:56:34 +1000 Subject: [PATCH 037/635] tests/extmod: Don't require constructor to raise for bad socket type. Some socket implementations (eg `extmod/modsocket.c`) don't (and can't easily) raise an exception for an invalid socket type. So just test that passing such a value doesn't crash the device. Signed-off-by: Damien George --- tests/extmod/socket_badconstructor.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/extmod/socket_badconstructor.py b/tests/extmod/socket_badconstructor.py index 1ea5d750b3e..25d981f70a7 100644 --- a/tests/extmod/socket_badconstructor.py +++ b/tests/extmod/socket_badconstructor.py @@ -16,10 +16,12 @@ except TypeError: print("TypeError") +# This may or may not raise an exception, depending on the socket implementation. +# The test is here for coverage. try: s = socket.socket(socket.AF_INET, 123456) except OSError: - print("OSError") + pass try: s = socket.socket(socket.AF_INET, socket.SOCK_RAW, None) From c8b71b0e6cb6b198994117af41bb05d81d81cc50 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 31 Jul 2025 13:34:02 +1000 Subject: [PATCH 038/635] tests/perf_bench: Skip import tests when vfs module doesn't exist. For example, the ESP8266_GENERIC FLASH_512K variant doesn't have the `vfs` module. Signed-off-by: Damien George --- tests/perf_bench/core_import_mpy_multi.py | 9 +++++---- tests/perf_bench/core_import_mpy_single.py | 9 +++++---- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/tests/perf_bench/core_import_mpy_multi.py b/tests/perf_bench/core_import_mpy_multi.py index 67deec05088..55aa379e2bf 100644 --- a/tests/perf_bench/core_import_mpy_multi.py +++ b/tests/perf_bench/core_import_mpy_multi.py @@ -1,8 +1,9 @@ # Test performance of importing an .mpy file many times. -import sys, io, vfs - -if not hasattr(io, "IOBase"): +try: + import sys, vfs + from io import IOBase +except ImportError: print("SKIP") raise SystemExit @@ -26,7 +27,7 @@ def f(): file_data = b'M\x06\x00\x1e\x14\x03\x0etest.py\x00\x0f\x02A\x00\x02f\x00\x0cresult\x00/-5#\x82I\x81{\x81w\x82/\x81\x05\x81\x17Iom\x82\x13\x06arg\x00\x05\x1cthis will be a string object\x00\x06\x1bthis will be a bytes object\x00\n\x07\x05\x0bconst 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\x12\x81!\x12\x81\"\x12\x81#\x12\x81$*\x0bY\x12\x81%\x12\x81&*\x02Y\x12\x81'\x12\x81(\x12\x81)\x12\x81*\x12\x81+\x12\x81,\x12\x81-\x12\x81.\x12\x81/\x12\x810*\nY\x12\x811\x12\x812\x12\x813\x12\x814*\x04Y\x12\x815\x12\x816\x12\x817\x12\x818*\x04Y\x12\x819\x12\x81:\x12\x81;\x12\x81<*\x04YQc\x87p\x08@\x05\x80###############################\x00\xc0#\x01\xc0#\x02\xc0#\x03\xc0#\x04\xc0#\x05\xc0#\x06\xc0#\x07\xc0#\x08\xc0#\t\xc0#\n\xc0#\x0b\xc0#\x0c\xc0#\r\xc0#\x0e\xc0#\x0f\xc0#\x10\xc0#\x11\xc0#\x12\xc0#\x13\xc0#\x14\xc0#\x15\xc0#\x16\xc0#\x17\xc0#\x18\xc0#\x19\xc0#\x1a\xc0#\x1b\xc0#\x1c\xc0#\x1d\xc0Qc" -class File(io.IOBase): +class File(IOBase): def __init__(self): self.off = 0 From 551a5680f0c0bfd64fa04ea5c052e46e16231ea0 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 5 Aug 2025 10:09:29 +1000 Subject: [PATCH 039/635] tests/run-perfbench.py: Skip misc_mandel if target doesn't have complex. Eg running this on `ADAFRUIT_ITSYBITSY_M0_EXPRESS` would previously crash with "NameError: name not defined" due to the lookup of `complex` as a global. With the change here, that test is skipped automatically. Also, provide better skip messages with the reason for the skip. Signed-off-by: Damien George --- tests/run-perfbench.py | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/tests/run-perfbench.py b/tests/run-perfbench.py index 16182bc8a9f..686c3da7ae4 100755 --- a/tests/run-perfbench.py +++ b/tests/run-perfbench.py @@ -101,15 +101,14 @@ def run_benchmarks(args, target, param_n, param_m, n_average, test_list): print(test_file + ": ", end="") # Check if test should be skipped - skip = ( - skip_complex - and test_file.find("bm_fft") != -1 - or skip_native - and test_file.find("viper_") != -1 - ) - if skip: - test_results.append((test_file, "skip", "")) - print("SKIP") + skip_reason = None + if skip_complex and test_file.endswith(("bm_fft.py", "misc_mandel.py")): + skip_reason = "complex not supported" + elif skip_native and test_file.find("viper_") != -1: + skip_reason = "native not supported" + if skip_reason: + test_results.append((test_file, "skip", skip_reason)) + print("SKIP:", skip_reason) continue # Create test script From fc8857a4aeac719497ba9642738007404d8cbea7 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 5 Aug 2025 10:01:04 +1000 Subject: [PATCH 040/635] tests/multi_net/udp_data_multi.py: Reduce number of UDP groups to 4. This test is unreliable with 5 UDP groups because on bare-metal lwIP targets there's only enough buffer space for 4 groups, see `extmod/modlwip.c`: // Total queue length for buffered UDP/raw incoming packets. #define LWIP_INCOMING_PACKET_QUEUE_LEN (4) Signed-off-by: Damien George --- tests/multi_net/udp_data_multi.py | 2 +- tests/multi_net/udp_data_multi.py.exp | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/multi_net/udp_data_multi.py b/tests/multi_net/udp_data_multi.py index 5d7b13e5188..a2ed33d292d 100644 --- a/tests/multi_net/udp_data_multi.py +++ b/tests/multi_net/udp_data_multi.py @@ -5,7 +5,7 @@ NUM_NEW_SOCKETS = 4 NUM_PACKET_BURSTS = 6 -NUM_PACKET_GROUPS = 5 +NUM_PACKET_GROUPS = 4 TOTAL_PACKET_BURSTS = NUM_NEW_SOCKETS * NUM_PACKET_BURSTS # The tast passes if more than 75% of packets are received in each group. PACKET_RECV_THRESH = 0.75 * TOTAL_PACKET_BURSTS diff --git a/tests/multi_net/udp_data_multi.py.exp b/tests/multi_net/udp_data_multi.py.exp index bc67c6ab0cf..a74ef42b730 100644 --- a/tests/multi_net/udp_data_multi.py.exp +++ b/tests/multi_net/udp_data_multi.py.exp @@ -7,7 +7,6 @@ pass group=0 pass group=1 pass group=2 pass group=3 -pass group=4 --- instance1 --- test socket 0 test socket 1 From 722aacfd581c03b7bdda8bd114414e32275576c2 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 26 Sep 2025 22:37:40 +1000 Subject: [PATCH 041/635] tests/extmod/machine_soft_timer.py: Skip test on nrf boards. The nrf port doesn't implement the `freq` argument. Signed-off-by: Damien George --- tests/extmod/machine_soft_timer.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/extmod/machine_soft_timer.py b/tests/extmod/machine_soft_timer.py index aa19becd8eb..4c0611caedf 100644 --- a/tests/extmod/machine_soft_timer.py +++ b/tests/extmod/machine_soft_timer.py @@ -9,8 +9,8 @@ print("SKIP") raise SystemExit -if sys.platform in ("esp32", "esp8266"): - print("SKIP") # TODO: Implement soft timers for esp32/esp8266 ports +if sys.platform in ("esp32", "esp8266", "nrf"): + print("SKIP") # TODO: Implement soft timers for esp32/esp8266/nrf ports raise SystemExit # create and deinit From 0b8fbe3f9b6db99b9c12c7b4c67f3f699bb30eb8 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 26 Sep 2025 22:38:01 +1000 Subject: [PATCH 042/635] tests/micropython/ringio_big.py: Improve running on low-memory targets. Two changes here to improve running this test on targets with low memory: - Print the results at end of test, so if a MemoryError occurs part-way- through then the SKIP works correctly. - Reorganise the order of the sub-tests and preallocate the large buffer so it can be reused. This gets the test running and passing on ESP32_GENERIC with the native emitter (and also still works with the bytecode emitter). Signed-off-by: Damien George --- tests/micropython/ringio_big.py | 27 +++++++++++++++++++-------- tests/run-tests.py | 1 + 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/tests/micropython/ringio_big.py b/tests/micropython/ringio_big.py index ddbbae12a63..88d5d2cc165 100644 --- a/tests/micropython/ringio_big.py +++ b/tests/micropython/ringio_big.py @@ -8,22 +8,33 @@ print("SKIP") raise SystemExit +results = [] + try: - # The maximum possible size - micropython.RingIO(bytearray(65535)) + # The maximum possible size passed as an integer. micropython.RingIO(65534) try: - # Buffer may not be too big - micropython.RingIO(bytearray(65536)) + # Size may not be too big + micropython.RingIO(65535) except ValueError as ex: - print(type(ex)) + results.append(type(ex)) + + # Allocate a buffer for use below. + buf_64k = memoryview(bytearray(65536)) + + # The maximum possible size passed as a buffer. + micropython.RingIO(buf_64k[:-1]) try: - # Size may not be too big - micropython.RingIO(65535) + # Buffer may not be too big + micropython.RingIO(buf_64k) except ValueError as ex: - print(type(ex)) + results.append(type(ex)) + except MemoryError: print("SKIP") raise SystemExit + +for result in results: + print(result) diff --git a/tests/run-tests.py b/tests/run-tests.py index eb6f9d6f9cb..8585b1cc7e8 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -286,6 +286,7 @@ "micropython/import_mpy_invalid.py", "micropython/import_mpy_native.py", "micropython/import_mpy_native_gc.py", + "micropython/ringio_big.py", "misc/non_compliant.py", "misc/rge_sm.py", ) From 1d9b8b456eaa5ecbb552f135094365701ee2d2b3 Mon Sep 17 00:00:00 2001 From: Damien George Date: Sun, 8 Feb 2026 23:02:36 +1100 Subject: [PATCH 043/635] tests/extmod/machine_uart_tx.py: Make string longer for more accuracy. This decreases the variation in the time taken to send, making the test more reliable. Without this change the nrf port is flaky at 2400 baud, eg the `ARDUINO_NANO_33_BLE_SENSE` board fails this test more often than not. Signed-off-by: Damien George --- tests/extmod/machine_uart_tx.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/extmod/machine_uart_tx.py b/tests/extmod/machine_uart_tx.py index 1ff9af64bd4..4e0ff37a8b1 100644 --- a/tests/extmod/machine_uart_tx.py +++ b/tests/extmod/machine_uart_tx.py @@ -37,7 +37,7 @@ # Test that write+flush takes the expected amount of time to execute. for bits_per_s in (2400, 9600, 115200): - text = "Hello World" + text = "Hello World from MicroPython" uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs) time.sleep_ms(initial_delay_ms) From 0ead9671b1bfe7fc1b0b087b867940aa75290596 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 10 Feb 2026 02:10:48 +1100 Subject: [PATCH 044/635] tests/extmod/framebuf_polygon.py: Skip test if buf can't be allocated. Prior to this change this test fails on `ADAFRUIT_ITSYBITSY_M0_EXPRESS` with the native emitter, because it doesn't have enough heap to allocate the backing buffer. Signed-off-by: Damien George --- tests/extmod/framebuf_polygon.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tests/extmod/framebuf_polygon.py b/tests/extmod/framebuf_polygon.py index da05be2c4db..91a64d74c30 100644 --- a/tests/extmod/framebuf_polygon.py +++ b/tests/extmod/framebuf_polygon.py @@ -11,6 +11,12 @@ print("SKIP") raise SystemExit +try: + buf = bytearray(70 * 70) +except MemoryError: + print("SKIP") + raise SystemExit + def print_buffer(buffer, width, height): for row in range(height): @@ -20,8 +26,6 @@ def print_buffer(buffer, width, height): print() -buf = bytearray(70 * 70) - w = 30 h = 25 fbuf = framebuf.FrameBuffer(buf, w, h, framebuf.GS8) From 98c76a9cbd518739402684cd53b4ef68d1af8a01 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 10 Feb 2026 02:11:21 +1100 Subject: [PATCH 045/635] tests/extmod/machine_spi_rate.py: Skip test if bufs can't be allocated. Prior to this change this test fails on `ADAFRUIT_ITSYBITSY_M0_EXPRESS` with the native emitter, because it doesn't have enough heap to allocate the read/write buffers. Signed-off-by: Damien George --- tests/extmod/machine_spi_rate.py | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/tests/extmod/machine_spi_rate.py b/tests/extmod/machine_spi_rate.py index c41bf3ac2f7..27174bf95e7 100644 --- a/tests/extmod/machine_spi_rate.py +++ b/tests/extmod/machine_spi_rate.py @@ -6,6 +6,15 @@ print("SKIP") raise SystemExit +try: + wr_short = b"abcdefghijklmnop" * 10 + rd_short = bytearray(len(wr_short)) + wr_long = wr_short * 20 + rd_long = bytearray(len(wr_long)) +except MemoryError: + print("SKIP") + raise SystemExit + import time, sys from target_wiring import spi_standalone_args_list @@ -56,13 +65,6 @@ def test_instances(): print_results = False -wr_short = b"abcdefghijklmnop" * 10 -rd_short = bytearray(len(wr_short)) - -wr_long = wr_short * 20 -rd_long = bytearray(len(wr_long)) - - def test_spi(spi_args, baudrate, polarity, phase, print_results): s = SPI(*spi_args, baudrate=baudrate, polarity=polarity, phase=phase) From 9ecdeb626185f92584ec98c5cf62f98eedd7cc28 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 10 Feb 2026 01:33:31 +1100 Subject: [PATCH 046/635] tests/run-tests.py: Skip tests depending on error reporting capability. Detect the target's error reporting capabilities, and skip tests as appropriate. For example, all samd boards are configured with `MICROPY_ERROR_REPORTING_TERSE` so need to skip these four tests. Signed-off-by: Damien George --- tests/feature_check/target_info.py | 8 +++++++- tests/run-tests.py | 19 ++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/tests/feature_check/target_info.py b/tests/feature_check/target_info.py index e95530023d7..ed91b27b775 100644 --- a/tests/feature_check/target_info.py +++ b/tests/feature_check/target_info.py @@ -36,4 +36,10 @@ except NameError: float_prec = 0 -print(platform, arch, arch_flags, build, thread, float_prec, len("α") == 1) +# Detect the error reporting level (based on the length of the raised exception message). +try: + (lambda: 0)(0) +except TypeError as er: + error_reporting = {0: "none", 27: "terse", 54: "normal", 56: "detailed"}[len(er.value)] + +print(platform, arch, arch_flags, build, thread, float_prec, len("α") == 1, error_reporting) diff --git a/tests/run-tests.py b/tests/run-tests.py index 8585b1cc7e8..f6a4a33adee 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -198,6 +198,19 @@ ), } +# Tests to skip when MICROPY_ERROR_REPORTING is at a certain level. +error_reporting_tests_to_skip = { + # Skip at level MICROPY_ERROR_REPORTING_NONE. + "none": ( + "micropython/heapalloc_exc_compressed.py", + "micropython/heapalloc_exc_compressed_emg_exc.py", + "micropython/opt_level_lineno.py", + "misc/print_exception.py", + ), +} +# Skip at level MICROPY_ERROR_REPORTING_TERSE. +error_reporting_tests_to_skip["terse"] = error_reporting_tests_to_skip["none"] + # Tests with known intermittent failures. These tests still run, but failures # are reclassified as "ignored" instead of "fail" so they don't affect the CI # exit code. Paths are relative to the tests/ directory (must match test_file @@ -353,7 +366,7 @@ def detect_test_platform(pyb, args): output = run_feature_check(pyb, args, "target_info.py") if output.endswith(b"CRASH"): raise ValueError("cannot detect platform: {}".format(output)) - platform, arch, arch_flags, build, thread, float_prec, unicode = ( + platform, arch, arch_flags, build, thread, float_prec, unicode, error_reporting = ( str(output, "ascii").strip().split() ) if arch == "None": @@ -380,6 +393,7 @@ def detect_test_platform(pyb, args): args.thread = thread args.float_prec = float_prec args.unicode = unicode + args.error_reporting = error_reporting # Print the detected information about the target. print("platform={}".format(platform), end="") @@ -922,6 +936,9 @@ def run_tests(pyb, tests, args, result_dir, num_threads=1): # Skip platform-specific tests. skip_tests.update(platform_tests_to_skip.get(args.platform, ())) + # Skip error-reporting-specific tests. + skip_tests.update(error_reporting_tests_to_skip.get(args.error_reporting, ())) + # Some tests are known to fail on 64-bit machines if pyb is None and platform.architecture()[0] == "64bit": pass From 0a55311be5cad0e7a00f0e7a4f4c34115ddf4938 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 9 Apr 2026 21:56:12 +1000 Subject: [PATCH 047/635] tests/micropython: Remove dependence on exact exception message. Allows running with terse error reporting (and normal and detailed). Signed-off-by: Damien George --- tests/micropython/native_with.py | 1 + tests/micropython/native_with.py.exp | 2 +- tests/micropython/viper_with.py | 1 + tests/micropython/viper_with.py.exp | 2 +- 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/micropython/native_with.py b/tests/micropython/native_with.py index 9c0b98af903..37c385a42f9 100644 --- a/tests/micropython/native_with.py +++ b/tests/micropython/native_with.py @@ -9,6 +9,7 @@ def __enter__(self): print("__enter__") def __exit__(self, a, b, c): + b = repr(b)[:10] # shorten exception to "NameError(" prefix for target compatibility print("__exit__", a, b, c) diff --git a/tests/micropython/native_with.py.exp b/tests/micropython/native_with.py.exp index 7e28663f6fc..b8083a4c66b 100644 --- a/tests/micropython/native_with.py.exp +++ b/tests/micropython/native_with.py.exp @@ -5,5 +5,5 @@ __exit__ None None None __init__ __enter__ 1 -__exit__ name 'fail' isn't defined None +__exit__ NameError( None NameError diff --git a/tests/micropython/viper_with.py b/tests/micropython/viper_with.py index 40fbf6fb315..833a6babe7d 100644 --- a/tests/micropython/viper_with.py +++ b/tests/micropython/viper_with.py @@ -9,6 +9,7 @@ def __enter__(self): print("__enter__") def __exit__(self, a, b, c): + b = repr(b)[:10] # shorten exception to "NameError(" prefix for target compatibility print("__exit__", a, b, c) diff --git a/tests/micropython/viper_with.py.exp b/tests/micropython/viper_with.py.exp index 7e28663f6fc..b8083a4c66b 100644 --- a/tests/micropython/viper_with.py.exp +++ b/tests/micropython/viper_with.py.exp @@ -5,5 +5,5 @@ __exit__ None None None __init__ __enter__ 1 -__exit__ name 'fail' isn't defined None +__exit__ NameError( None NameError From 2cebe9f04f290b6c3d9373ea17d5f7e75962bb40 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 9 Apr 2026 21:56:46 +1000 Subject: [PATCH 048/635] tests/misc/rge_sm.py: Skip test if target doesn't have enough memory. For example, `ADAFRUIT_ITSYBITSY_M0_EXPRESS` only has about 20k heap and runs out of memory part way through the integration loop. Signed-off-by: Damien George --- tests/misc/rge_sm.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/misc/rge_sm.py b/tests/misc/rge_sm.py index 56dad574977..9e74c3b7a79 100644 --- a/tests/misc/rge_sm.py +++ b/tests/misc/rge_sm.py @@ -78,7 +78,11 @@ def singleTraj(system, trajStart, h=0.02, tend=1.0): # compute the trajectory rk = RungeKutta(system, trajStart, tstart, h) - rk.solve(tend) + try: + rk.solve(tend) + except MemoryError: + print("SKIP") + raise SystemExit # print out trajectory From 10b624751edff9f31ecd0844d8fd918c2634add4 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Wed, 29 Apr 2026 12:15:28 -0500 Subject: [PATCH 049/635] tests/float/float_format_ints.py: Add another valid alternative result. Clang -m32 rounds some floating point reprs differently, likely due to x87 temporary excess precision. Accept this value in addition to the other values that are accepted. Closes: #19120 Signed-off-by: Jeff Epler --- tests/float/float_format_ints.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/float/float_format_ints.py b/tests/float/float_format_ints.py index 7b7b30c4b34..1f221bd5e79 100644 --- a/tests/float/float_format_ints.py +++ b/tests/float/float_format_ints.py @@ -46,6 +46,13 @@ if is_REPR_C and val_str == "2147483200.000000": val_str = "2147483520.000000" +# When using REPR_C, x86 and clang, 2147483520.0 is the same +# as 2147483100.0, the second being "simple" but rounded differently +# due to x87 extra precision on intermediates. +# Both representations are valid. +if is_REPR_C and val_str == "2147483100.000000": + val_str = "2147483520.000000" + print(val_str) # Very large positive integers can be a test for precision and resolution. From 9ee7ac8224a525d38814820d0f895e6868b70012 Mon Sep 17 00:00:00 2001 From: Jeongseop Lim Date: Mon, 4 May 2026 22:11:29 +0900 Subject: [PATCH 050/635] tests/cpydiff: Document dir() not post-processing __dir__ result. CPython's dir() converts the result of __dir__ to a list and sorts it; MicroPython returns the value as-is. Document the difference with a class whose __dir__ returns a non-list iterable. Signed-off-by: Jeongseop Lim --- tests/cpydiff/core_class_dir.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 tests/cpydiff/core_class_dir.py diff --git a/tests/cpydiff/core_class_dir.py b/tests/cpydiff/core_class_dir.py new file mode 100644 index 00000000000..e2b0e877cdc --- /dev/null +++ b/tests/cpydiff/core_class_dir.py @@ -0,0 +1,14 @@ +""" +categories: Core,Classes +description: dir() does not convert __dir__ return value to a sorted list +cause: MicroPython's dir() returns the value from __dir__ as-is, without iterating it into a list or sorting it. +workaround: Have __dir__ return a sorted list directly. +""" + + +class C: + def __dir__(self): + return "cba" + + +print(dir(C())) From 14b26b99c26a783712249ed692c02c4992a6c597 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sun, 19 Oct 2025 14:34:37 +1100 Subject: [PATCH 051/635] stm32/tinyusb_port: Add High Speed USB controller support with TinyUSB. Implements mapping from MICROPY_HW_USB_MAIN_DEV to TinyUSB RHPORT configuration, enabling board-specific USB PHY selection for TinyUSB stack. Adds support for HS-in-FS mode (High Speed controller running at Full Speed) which is the default for STM32 boards without external ULPI PHY. Thi STM32F4/F7/H7 high-speed RHPORT mode selection is placed in ports/stm32/tinyusb_port/tusb_config.h, following the alif/nrf pattern. Includes py/mpconfig.h to ensure board config macros are available when TinyUSB processes the header. Signed-off-by: Andrew Leech --- ports/stm32/Makefile | 1 + ports/stm32/stm32_it.c | 2 +- ports/stm32/tinyusb_port/tusb_config.h | 51 ++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 ports/stm32/tinyusb_port/tusb_config.h diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 63ed974b9b5..ae78649041f 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -111,6 +111,7 @@ INC += -I$(STM32LIB_HAL_ABS)/Inc INC += -I$(USBDEV_DIR)/core/inc -I$(USBDEV_DIR)/class/inc #INC += -I$(USBHOST_DIR) INC += -I$(TOP)/lib/tinyusb/src +INC += -Itinyusb_port INC += -I$(TOP)/shared/tinyusb/ INC += -Ilwip_inc diff --git a/ports/stm32/stm32_it.c b/ports/stm32/stm32_it.c index 3ae1980f8fe..f528314a5e0 100644 --- a/ports/stm32/stm32_it.c +++ b/ports/stm32/stm32_it.c @@ -384,7 +384,7 @@ void USB1_OTG_HS_IRQHandler(void) { void OTG_HS_IRQHandler(void) { IRQ_ENTER(OTG_HS_IRQn); #if MICROPY_HW_TINYUSB_STACK - tud_int_handler(0); + tud_int_handler(1); // OTG_HS is always RHPORT1 on F4/F7/H7 (not N6, which uses USB1_OTG_HS_IRQHandler) #else HAL_PCD_IRQHandler(&pcd_hs_handle); #endif diff --git a/ports/stm32/tinyusb_port/tusb_config.h b/ports/stm32/tinyusb_port/tusb_config.h new file mode 100644 index 00000000000..4d74eec9b37 --- /dev/null +++ b/ports/stm32/tinyusb_port/tusb_config.h @@ -0,0 +1,51 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_STM32_TINYUSB_PORT_TUSB_CONFIG_H +#define MICROPY_INCLUDED_STM32_TINYUSB_PORT_TUSB_CONFIG_H + +#include "py/mpconfig.h" + +// STM32F4/F7/H7 boards with USB_HS use OTG_HS on RHPORT1, not RHPORT0. +// Disable RHPORT0 and put RHPORT1 in device mode (HS, or FS when the +// HS controller uses the internal FS PHY via MICROPY_HW_USB_HS_IN_FS). +// Other configs are handled either by the board (e.g. N6 sets RHPORT0 +// to HS in mpconfigboard_common.h) or by the shared default in +// shared/tinyusb/tusb_config.h (RHPORT0 in FS device mode). + +// These families place OTG_HS on RHPORT1. Extend the list if a new family +// also uses OTG_HS on RHPORT1 rather than RHPORT0. +#if MICROPY_HW_USB_HS && (defined(STM32F4) || defined(STM32F7) || defined(STM32H7)) +#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_NONE) +#if MICROPY_HW_USB_HS_IN_FS +#define CFG_TUSB_RHPORT1_MODE (OPT_MODE_DEVICE | OPT_MODE_FULL_SPEED) +#else +#define CFG_TUSB_RHPORT1_MODE (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED) +#endif +#endif + +#include "shared/tinyusb/tusb_config.h" + +#endif // MICROPY_INCLUDED_STM32_TINYUSB_PORT_TUSB_CONFIG_H From b001b71959b0d9ac03b9259ee9bbf4eb08e699d0 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 28 Oct 2025 14:30:25 +1100 Subject: [PATCH 052/635] stm32/factoryreset: Add TinyUSB-specific boot.py examples. Signed-off-by: Andrew Leech --- ports/stm32/factoryreset.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/ports/stm32/factoryreset.c b/ports/stm32/factoryreset.c index 50854a908b1..1811ca1186f 100644 --- a/ports/stm32/factoryreset.c +++ b/ports/stm32/factoryreset.c @@ -44,9 +44,15 @@ static const char fresh_boot_py[] = "import pyb\r\n" "#pyb.main('main.py') # main script to run after this one\r\n" #if MICROPY_HW_ENABLE_USB +#if MICROPY_HW_TINYUSB_STACK + "#usb = machine.USBDevice()\r\n" + "#usb.builtin_driver = machine.USBDevice.BUILTIN_DEFAULT # CDC + MSC\r\n" + "#usb.active(True)\r\n" +#else "#pyb.usb_mode('VCP+MSC') # act as a serial and a storage device\r\n" "#pyb.usb_mode('VCP+HID') # act as a serial device and a mouse\r\n" #endif +#endif #if MICROPY_PY_NETWORK "#import network\r\n" "#network.country('US') # ISO 3166-1 Alpha-2 code, eg US, GB, DE, AU or XX for worldwide\r\n" From 8d3597ca50bbf58b794c8585ea333ca941957d30 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 7 Mar 2026 07:46:16 +1100 Subject: [PATCH 053/635] shared/tinyusb: Fix CDC reconnect stall and TX FIFO. When a host closes and reopens the CDC serial port, the IN endpoint may remain stalled from a prior runtime USB disconnect (e.g. mpremote connect/disconnect cycles). Clear the stall on DTR high so the connection recovers without requiring a device reset. On DTR low (host close), flush the TX FIFO so stale data does not accumulate and block writes on the next connection. Signed-off-by: Andrew Leech --- shared/tinyusb/mp_usbd_cdc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/shared/tinyusb/mp_usbd_cdc.c b/shared/tinyusb/mp_usbd_cdc.c index 961bdf89896..8018032d36c 100644 --- a/shared/tinyusb/mp_usbd_cdc.c +++ b/shared/tinyusb/mp_usbd_cdc.c @@ -34,6 +34,11 @@ #if MICROPY_HW_USB_CDC && MICROPY_HW_ENABLE_USBDEV && !MICROPY_EXCLUDE_SHARED_TINYUSB_USBD_CDC +// TinyUSB has no public API for endpoint stall detection/clearing; this +// private header is the intended interface for class drivers (all built-in +// TinyUSB class drivers include it for the same purpose). +#include "device/usbd_pvt.h" + static uint8_t cdc_itf_pending; // keep track of cdc interfaces which need attention to poll static int8_t cdc_connected_flush_delay = 0; @@ -176,10 +181,18 @@ void MICROPY_WRAP_TUD_CDC_LINE_STATE_CB(tud_cdc_line_state_cb)(uint8_t itf, bool #if MICROPY_HW_USB_CDC && !MICROPY_EXCLUDE_SHARED_TINYUSB_USBD_CDC if (dtr) { // A host application has started to open the cdc serial port. + // USBD_CDC_EP_IN is the IN endpoint for itf 0; only clear stall for itf 0. + if (itf == 0 && usbd_edpt_stalled(TUD_OPT_RHPORT, USBD_CDC_EP_IN)) { + usbd_edpt_clear_stall(TUD_OPT_RHPORT, USBD_CDC_EP_IN); + } // Wait a few ms for host to be ready then send tx buffer. // High speed connection SOF fires at 125us, full speed at 1ms. cdc_connected_flush_delay = (tud_speed_get() == TUSB_SPEED_HIGH) ? 128 : 16; tud_sof_cb_enable(true); + } else { + // Host has closed the cdc serial port. Discard pending TX data to + // avoid a full FIFO blocking writes on the next connection. + tud_cdc_n_write_clear(itf); } #endif #if MICROPY_HW_USB_CDC_DTR_RTS_BOOTLOADER From 693f33aa42bb09f7a6beec8646a9f3312983dca5 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 10 Mar 2026 21:33:01 +1100 Subject: [PATCH 054/635] stm32/usbd: Match ST DFU bootloader serial number in TinyUSB. The TinyUSB serial descriptor used a raw hex dump of all 12 UID bytes in sequential order (24-char lowercase), while the legacy USB stack and ST's onboard DFU bootloader use a condensed algorithm that selects 6 bytes with two additions (12-char uppercase). This mismatch caused the device to report a different serial number depending on which USB stack was active, breaking tools that identify devices by serial (e.g. udev rules, mpremote, dfu-util). Use the ST DFU bootloader algorithm for consistency. Signed-off-by: Andrew Leech --- ports/stm32/usbd.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/ports/stm32/usbd.c b/ports/stm32/usbd.c index 35275cd1bd0..fec87c90147 100644 --- a/ports/stm32/usbd.c +++ b/ports/stm32/usbd.c @@ -28,15 +28,25 @@ #if MICROPY_HW_ENABLE_USBDEV && MICROPY_HW_TINYUSB_STACK +#include #include "mp_usbd.h" -#include "py/mpconfig.h" -#include "string.h" #include "mphalport.h" void mp_usbd_port_get_serial_number(char *serial_buf) { + // Use the same algorithm as the ST DFU bootloader so that the serial + // number is consistent across all USB modes. + MP_STATIC_ASSERT(12 <= MICROPY_HW_USB_DESC_STR_MAX); // 6 derived bytes x 2 hex digits + NUL + static const char hexdig[] = "0123456789ABCDEF"; uint8_t *id = (uint8_t *)MP_HAL_UNIQUE_ID_ADDRESS; - MP_STATIC_ASSERT(12 * 2 <= MICROPY_HW_USB_DESC_STR_MAX); - mp_usbd_hex_str(serial_buf, id, 12); + uint8_t bytes[] = { + id[11], (uint8_t)(id[10] + id[2]), id[9], + (uint8_t)(id[8] + id[0]), id[7], id[6], + }; + for (int i = 0; i < 6; i++) { + serial_buf[i * 2] = hexdig[bytes[i] >> 4]; + serial_buf[i * 2 + 1] = hexdig[bytes[i] & 0x0f]; + } + serial_buf[12] = '\0'; } #endif From d2e0d20f824a3477121b1e1fe34b61e5579f44ed Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Thu, 30 Apr 2026 20:26:30 +1000 Subject: [PATCH 055/635] stm32,extmod: Use full path for shared/tinyusb/mp_usbd.h include. Removes the need for -I$(TOP)/shared/tinyusb/ in the stm32 Makefile by using an explicit path in the two files that include mp_usbd.h outside of the shared/tinyusb/ directory itself. Signed-off-by: Andrew Leech --- extmod/machine_usb_device.c | 2 +- ports/stm32/Makefile | 1 - ports/stm32/usbd.c | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/extmod/machine_usb_device.c b/extmod/machine_usb_device.c index f6e97f42054..e8303ef84f7 100644 --- a/extmod/machine_usb_device.c +++ b/extmod/machine_usb_device.c @@ -28,7 +28,7 @@ #if MICROPY_HW_ENABLE_USB_RUNTIME_DEVICE -#include "mp_usbd.h" +#include "shared/tinyusb/mp_usbd.h" #include "py/mperrno.h" #include "py/objstr.h" diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index ae78649041f..7597d23d0a3 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -112,7 +112,6 @@ INC += -I$(USBDEV_DIR)/core/inc -I$(USBDEV_DIR)/class/inc #INC += -I$(USBHOST_DIR) INC += -I$(TOP)/lib/tinyusb/src INC += -Itinyusb_port -INC += -I$(TOP)/shared/tinyusb/ INC += -Ilwip_inc CFLAGS += $(INC) -Wall -Wpointer-arith -Werror -Wdouble-promotion -Wfloat-conversion -std=gnu99 $(CFLAGS_EXTRA) diff --git a/ports/stm32/usbd.c b/ports/stm32/usbd.c index fec87c90147..d8f8b3dd551 100644 --- a/ports/stm32/usbd.c +++ b/ports/stm32/usbd.c @@ -29,7 +29,7 @@ #if MICROPY_HW_ENABLE_USBDEV && MICROPY_HW_TINYUSB_STACK #include -#include "mp_usbd.h" +#include "shared/tinyusb/mp_usbd.h" #include "mphalport.h" void mp_usbd_port_get_serial_number(char *serial_buf) { From c5df9543f74b54feeab32e4bc4bbed5d87e6251e Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 13 Apr 2026 15:30:13 +1000 Subject: [PATCH 056/635] stm32/Makefile: Provide definitions of CFLAGS_MCU & MPY_CROSS_MCU_ARCH. Selected for the specific MCU series, to reduce code duplication when referring to them. Signed-off-by: Damien George --- ports/stm32/Makefile | 6 +++--- ports/stm32/stm32.mk | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 7597d23d0a3..31c8a500c9b 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -116,7 +116,7 @@ INC += -Ilwip_inc CFLAGS += $(INC) -Wall -Wpointer-arith -Werror -Wdouble-promotion -Wfloat-conversion -std=gnu99 $(CFLAGS_EXTRA) CFLAGS += -D$(CMSIS_MCU) -DUSE_FULL_LL_DRIVER -CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES)) +CFLAGS += $(CFLAGS_MCU) CFLAGS += $(COPT) CFLAGS += -I$(BOARD_DIR) CFLAGS += -DSTM32_HAL_H='' @@ -130,7 +130,7 @@ endif # as doesn't recognise -mcpu=cortex-m55 AFLAGS += -march=armv8.1-m.main else -AFLAGS += $(filter -mcpu=%,$(CFLAGS_MCU_$(MCU_SERIES))) +AFLAGS += $(filter -mcpu=%,$(CFLAGS_MCU)) endif # Configure for nan-boxing object model if requested @@ -190,7 +190,7 @@ COPT ?= -Os -DNDEBUG endif # Options for mpy-cross -MPY_CROSS_FLAGS += -march=$(MPY_CROSS_MCU_ARCH_$(MCU_SERIES)) +MPY_CROSS_FLAGS += -march=$(MPY_CROSS_MCU_ARCH) SHARED_SRC_C += $(addprefix shared/,\ libc/string0.c \ diff --git a/ports/stm32/stm32.mk b/ports/stm32/stm32.mk index a1532d2776d..ba052974d6f 100644 --- a/ports/stm32/stm32.mk +++ b/ports/stm32/stm32.mk @@ -86,6 +86,10 @@ MPY_CROSS_MCU_ARCH_u5 = armv7m MPY_CROSS_MCU_ARCH_wb = armv7m MPY_CROSS_MCU_ARCH_wl = armv7m +# Select the correct flags for the given MCU series. +CFLAGS_MCU = $(CFLAGS_MCU_$(MCU_SERIES)) +MPY_CROSS_MCU_ARCH = $(MPY_CROSS_MCU_ARCH_$(MCU_SERIES)) + # gcc up to 14.2.0 have a known loop-optimisation bug: # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116799 # This bug manifests for Cortex M55 targets, so require a newer compiler on such targets. From a6144fb2335e5dbb01152fcbf408038cf65c19f8 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 13 Apr 2026 15:32:14 +1000 Subject: [PATCH 057/635] stm32/make-stmconst.py: Point periph reg defns to S/NS on CM33/CM55. Cortex-M33 and Cortex-M55 CPUs have both secure and non-secure addresses for most peripherals. Prior to this commit, the `stm` module was not taking this into account and instead of providing standard constants like `stm.RTC` it was providing both the _S and _NS set of peripherals, like `stm.RTC_S` and `stm.RTC_NS`. This makes it hard to write portable code which expectes things like `stm.RTC` to exist. Furthermore, Python code doesn't really have a way to know whether it's running in secure or non-secure mode, so doesn't know which peripheral registers to use (either _S or _NS). This commit addresses this issue by removing the constants ending in _S and _NS, and providing standard peripheral constants without any suffix. The address of the peripheral is chosen as the _S or _NS peripheral address depending on whether the firmware is built in secure or non-secure mode, respectively. The information about secure/non-secure mode is provide to `make-stmconst.py` by passing through the MCU CFLAGS. Signed-off-by: Damien George --- ports/stm32/Makefile | 2 +- ports/stm32/make-stmconst.py | 44 ++++++++++++++++++++++++++++++++++-- 2 files changed, 43 insertions(+), 3 deletions(-) diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 31c8a500c9b..b212abae621 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -711,7 +711,7 @@ $(GEN_PLLI2STABLE_HDR): $(PLLI2SVALUES) | $(HEADER_BUILD)/qstr.i.last $(BUILD)/modstm.o: $(GEN_STMCONST_HDR) $(HEADER_BUILD)/modstm_const.h: $(CMSIS_MCU_HDR) make-stmconst.py | $(HEADER_BUILD) $(ECHO) "GEN stmconst $@" - $(Q)$(PYTHON) make-stmconst.py --mpz $(GEN_STMCONST_MPZ) $(CMSIS_MCU_HDR) > $(GEN_STMCONST_HDR) + $(Q)$(PYTHON) make-stmconst.py --mpz $(GEN_STMCONST_MPZ) $(CMSIS_MCU_HDR) $(CFLAGS_MCU) > $(GEN_STMCONST_HDR) $(GEN_CDCINF_HEADER): $(GEN_CDCINF_FILE) $(FILE2H) | $(HEADER_BUILD) $(ECHO) "GEN $@" diff --git a/ports/stm32/make-stmconst.py b/ports/stm32/make-stmconst.py index 5601eb0af42..c1394657c34 100644 --- a/ports/stm32/make-stmconst.py +++ b/ports/stm32/make-stmconst.py @@ -119,12 +119,25 @@ def parse_file(filename): m = lexer.next_match() if m[0] == "EOF": break - elif m[0] == "#define hex": + + # If the CPU is secure, skip definitions for opposite security mode. + if m[0].startswith("#define"): + id_lhs = m[1]["id"] + if ( + security_mode + and id_lhs.endswith(("_NS", "_S")) + and not id_lhs.endswith(security_mode) + ): + continue + + if m[0] == "#define hex": d = m[1].groupdict() consts[d["id"]] = int(d["hex"], base=16) elif m[0] == "#define X": d = m[1].groupdict() if d["id2"] in consts: + if d["id"] in consts: + raise Exception(f"macro {d['id']} redefined") consts[d["id"]] = consts[d["id2"]] elif m[0] == "#define X+hex": d = m[1].groupdict() @@ -133,7 +146,11 @@ def parse_file(filename): elif m[0] == "#define typedef": d = m[1].groupdict() if d["id2"] in consts: - periphs.append((d["id"], consts[d["id2"]])) + periph_reg = d["id"] + if security_mode: + # Make, eg, "RTC_S"/"RTC_NS" available as "RTC". + periph_reg = periph_reg.removesuffix(security_mode) + periphs.append((periph_reg, consts[d["id2"]])) elif m[0] == "typedef struct": lexer.must_match("{") m = lexer.next_match() @@ -230,7 +247,20 @@ def print_regs_as_submodules(reg_name, reg_defs, modules): def main(): + global security_mode + cmd_parser = argparse.ArgumentParser(description="Extract ST constants from a C header file.") + + # Options used by gcc to control CPU architecture. + cmd_parser.add_argument("-mcmse", action="store_true") + cmd_parser.add_argument("-mcpu") + cmd_parser.add_argument("-mfloat-abi") + cmd_parser.add_argument("-mfp16-format") + cmd_parser.add_argument("-mfpu") + cmd_parser.add_argument("-msoft-float", action="store_true") + cmd_parser.add_argument("-mthumb", action="store_true") + cmd_parser.add_argument("-mtune") + cmd_parser.add_argument("file", nargs=1, help="input file") cmd_parser.add_argument( "--mpz", @@ -240,6 +270,16 @@ def main(): ) args = cmd_parser.parse_args() + # Determine the security mode of the CPU. + if args.mcpu in ("cortex-m33", "cortex-m55"): + if args.mcmse: + security_mode = "_S" + else: + security_mode = "_NS" + else: + security_mode = None + + # Parse the input CMSIS file with the register definitions. periphs, reg_defs = parse_file(args.file[0]) # add legacy GPIO constants that were removed when upgrading CMSIS From a7555039cd4ac053452030799c775e512e553a82 Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Mon, 13 Apr 2026 10:05:37 +0200 Subject: [PATCH 058/635] stm32/boards: Allow overriding USB PID for Arduino boards. Arduino boards are assigned different USB PIDs based on the MicroPython "variant" they're running. Enable overriding the USB pid at build time. Signed-off-by: iabdalkader --- ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h | 2 ++ ports/stm32/boards/ARDUINO_NICLA_VISION/mpconfigboard.h | 2 ++ ports/stm32/boards/ARDUINO_OPTA/mpconfigboard.h | 2 ++ ports/stm32/boards/ARDUINO_PORTENTA_H7/mpconfigboard.h | 2 ++ 4 files changed, 8 insertions(+) diff --git a/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h b/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h index 71097406b43..06a8442d445 100644 --- a/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h +++ b/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h @@ -302,7 +302,9 @@ extern struct _spi_bdev_t spi_bdev; #define MICROPY_HW_FMC_D15 (pin_D10) #define MICROPY_HW_USB_VID 0x2341 +#ifndef MICROPY_HW_USB_PID #define MICROPY_HW_USB_PID 0x0566 +#endif #define MICROPY_HW_USB_PID_CDC_MSC (MICROPY_HW_USB_PID) #define MICROPY_HW_USB_PID_CDC_HID (MICROPY_HW_USB_PID) #define MICROPY_HW_USB_PID_CDC (MICROPY_HW_USB_PID) diff --git a/ports/stm32/boards/ARDUINO_NICLA_VISION/mpconfigboard.h b/ports/stm32/boards/ARDUINO_NICLA_VISION/mpconfigboard.h index e15d07dcb3c..46e2e43a05b 100644 --- a/ports/stm32/boards/ARDUINO_NICLA_VISION/mpconfigboard.h +++ b/ports/stm32/boards/ARDUINO_NICLA_VISION/mpconfigboard.h @@ -227,7 +227,9 @@ extern struct _spi_bdev_t spi_bdev; #define MICROPY_HW_BLE_UART_BAUDRATE_DOWNLOAD_FIRMWARE (3000000) #define MICROPY_HW_USB_VID 0x2341 +#ifndef MICROPY_HW_USB_PID #define MICROPY_HW_USB_PID 0x055F +#endif #define MICROPY_HW_USB_PID_CDC_MSC (MICROPY_HW_USB_PID) #define MICROPY_HW_USB_PID_CDC_HID (MICROPY_HW_USB_PID) #define MICROPY_HW_USB_PID_CDC (MICROPY_HW_USB_PID) diff --git a/ports/stm32/boards/ARDUINO_OPTA/mpconfigboard.h b/ports/stm32/boards/ARDUINO_OPTA/mpconfigboard.h index 851b9f9d2f8..2f9a8f02704 100644 --- a/ports/stm32/boards/ARDUINO_OPTA/mpconfigboard.h +++ b/ports/stm32/boards/ARDUINO_OPTA/mpconfigboard.h @@ -212,7 +212,9 @@ extern struct _spi_bdev_t spi_bdev; // USB config #define MICROPY_HW_USB_FS (1) #define MICROPY_HW_USB_VID 0x2341 +#ifndef MICROPY_HW_USB_PID #define MICROPY_HW_USB_PID 0x0564 +#endif #define MICROPY_HW_USB_PID_CDC_MSC (MICROPY_HW_USB_PID) #define MICROPY_HW_USB_PID_CDC_HID (MICROPY_HW_USB_PID) #define MICROPY_HW_USB_PID_CDC (MICROPY_HW_USB_PID) diff --git a/ports/stm32/boards/ARDUINO_PORTENTA_H7/mpconfigboard.h b/ports/stm32/boards/ARDUINO_PORTENTA_H7/mpconfigboard.h index 1c1a804c5ec..f4dc8d7111b 100644 --- a/ports/stm32/boards/ARDUINO_PORTENTA_H7/mpconfigboard.h +++ b/ports/stm32/boards/ARDUINO_PORTENTA_H7/mpconfigboard.h @@ -326,7 +326,9 @@ extern struct _spi_bdev_t spi_bdev; #define MICROPY_HW_ETH_RMII_TXD1 (pin_G12) #define MICROPY_HW_USB_VID 0x2341 +#ifndef MICROPY_HW_USB_PID #define MICROPY_HW_USB_PID 0x055B +#endif #define MICROPY_HW_USB_PID_CDC_MSC (MICROPY_HW_USB_PID) #define MICROPY_HW_USB_PID_CDC_HID (MICROPY_HW_USB_PID) #define MICROPY_HW_USB_PID_CDC (MICROPY_HW_USB_PID) From 2c57e9df65ff8f240341bc365b066ec16b3a02a0 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 23 Apr 2026 13:55:03 +1000 Subject: [PATCH 059/635] stm32: Conditionally disable USB interrupts during SD operations. - This is necessary if the USB MSC device is exposing the SD Card, as a USB operation might read/write SD. - However, rather than disabling USB interrupts (and all lower interrupts) unconditionally, we can check if MSC is enabled & SDCard is configured as one of the USB MSC LUNs. This happens to be necessary to reliably trigger SDCard DMA alignment bugs from hard ISRs. However, it's good to do anyhow - allows interrupt processing to continue while the CPU is blocked waiting for the SD operation. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/stm32/sdcard.c | 41 +++++++++++++++++++++++++++----- ports/stm32/usbd_msc_interface.c | 9 +++++++ ports/stm32/usbd_msc_interface.h | 7 +++++- 3 files changed, 50 insertions(+), 7 deletions(-) diff --git a/ports/stm32/sdcard.c b/ports/stm32/sdcard.c index 3e755bf9f26..98bfe090f38 100644 --- a/ports/stm32/sdcard.c +++ b/ports/stm32/sdcard.c @@ -38,6 +38,15 @@ #include "dma.h" #include "irq.h" +#if !BUILDING_MBOOT +#include "usbd_msc_interface.h" +#else +// For mboot, act like the SDCard is always exposed via USB MSC +inline static bool usbd_msc_lu_includes_sdcard(void) { + return true; +} +#endif // !BUILDING_MBOOT + #if MICROPY_HW_ENABLE_SDCARD || MICROPY_HW_ENABLE_MMCARD #if defined(STM32F7) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4) || defined(STM32N6) @@ -541,8 +550,14 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo } if (query_irq() == IRQ_STATE_ENABLED) { - // we must disable USB irqs to prevent MSC contention with SD card - uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS); + #if MICROPY_HW_USB_MSC + uint32_t basepri; + bool usb_msc_sdcard = usbd_msc_lu_includes_sdcard(); + if (usb_msc_sdcard) { + // we must disable USB irqs to prevent MSC contention with SD card + basepri = raise_irq_pri(IRQ_PRI_OTG_FS); + } + #endif #if SDIO_USE_GPDMA DMA_HandleTypeDef sd_dma; @@ -586,7 +601,11 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo } #endif - restore_irq_pri(basepri); + #if MICROPY_HW_USB_MSC + if (usb_msc_sdcard) { + restore_irq_pri(basepri); + } + #endif } else { #if MICROPY_HW_ENABLE_MMCARD if (pyb_sdmmc_flags & PYB_SDMMC_FLAG_MMC) { @@ -635,8 +654,14 @@ mp_uint_t sdcard_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t n } if (query_irq() == IRQ_STATE_ENABLED) { - // we must disable USB irqs to prevent MSC contention with SD card - uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS); + #if MICROPY_HW_USB_MSC + uint32_t basepri; + bool usb_msc_sdcard = usbd_msc_lu_includes_sdcard(); + if (usb_msc_sdcard) { + // we must disable USB irqs to prevent MSC contention with SD card + basepri = raise_irq_pri(IRQ_PRI_OTG_FS); + } + #endif #if SDIO_USE_GPDMA DMA_HandleTypeDef sd_dma; @@ -679,7 +704,11 @@ mp_uint_t sdcard_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t n } #endif - restore_irq_pri(basepri); + #if MICROPY_HW_USB_MSC + if (usb_msc_sdcard) { + restore_irq_pri(basepri); + } + #endif } else { #if MICROPY_HW_ENABLE_MMCARD if (pyb_sdmmc_flags & PYB_SDMMC_FLAG_MMC) { diff --git a/ports/stm32/usbd_msc_interface.c b/ports/stm32/usbd_msc_interface.c index 68236e5c512..29bf46aaa66 100644 --- a/ports/stm32/usbd_msc_interface.c +++ b/ports/stm32/usbd_msc_interface.c @@ -109,6 +109,15 @@ void usbd_msc_init_lu(size_t lu_n, const void *lu_data) { usbd_msc_lu_flags = 0; } +bool usbd_msc_lu_includes_sdcard(void) { + for (int i = 0; i < usbd_msc_lu_num; i++) { + if (usbd_msc_lu_data[i] == &pyb_sdcard_type) { + return true; + } + } + return false; +} + // Helper function to perform an ioctl on a logical unit static int lu_ioctl(uint8_t lun, int op, uint32_t *data) { if (lun >= usbd_msc_lu_num) { diff --git a/ports/stm32/usbd_msc_interface.h b/ports/stm32/usbd_msc_interface.h index 9d25a72a3a4..4980bb7b7e6 100644 --- a/ports/stm32/usbd_msc_interface.h +++ b/ports/stm32/usbd_msc_interface.h @@ -26,8 +26,13 @@ #ifndef MICROPY_INCLUDED_STM32_USBD_MSC_INTERFACE_H #define MICROPY_INCLUDED_STM32_USBD_MSC_INTERFACE_H -extern const USBD_StorageTypeDef usbd_msc_fops; +#include +#include + +extern const struct _USBD_STORAGE usbd_msc_fops; void usbd_msc_init_lu(size_t lu_n, const void *lu_data); +bool usbd_msc_lu_includes_sdcard(void); + #endif // MICROPY_INCLUDED_STM32_USBD_MSC_INTERFACE_H From 7a5eae80dfb8d6ed953cbb5b7e5302fd9d040c54 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 23 Apr 2026 13:54:09 +1000 Subject: [PATCH 060/635] tests/ports/stm32: Add DMA alignment test for SDCard driver. Rename the existing dma_alignment test to spi_dma_align, as this one uses the SPI driver. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- .../ports/stm32_hardware/sdcard_dma_align.py | 188 ++++++++++++++++++ .../{dma_alignment.py => spi_dma_align.py} | 0 2 files changed, 188 insertions(+) create mode 100644 tests/ports/stm32_hardware/sdcard_dma_align.py rename tests/ports/stm32_hardware/{dma_alignment.py => spi_dma_align.py} (100%) diff --git a/tests/ports/stm32_hardware/sdcard_dma_align.py b/tests/ports/stm32_hardware/sdcard_dma_align.py new file mode 100644 index 00000000000..4af1ef543e4 --- /dev/null +++ b/tests/ports/stm32_hardware/sdcard_dma_align.py @@ -0,0 +1,188 @@ +# Test DMA read operations when the buffer alignment in RAM varies. +# +# Test requirements: +# A mostly empty FAT formatted SDCard installed in SD socket +import errno +import os +import pyb +import machine +import micropython +import vfs +import unittest + +from micropython import const + +_BLOCK_SZ = const(512) +_OFFS_WIDTH = const(64) # Should be at least the cache line size plus the GC block size +_TEST_BUF_SZ = const(_BLOCK_SZ + _OFFS_WIDTH) + +# More repeats = longer test run, more chance of triggering a cache coherence issue +_REPEATS = const(8) + +MOUNT_POINT = "/sd" +FILE_PATH = "/sd/stm32_align.blk" + +# Skip the whole test if there isn't a mountable SDCard +try: + sd = pyb.SDCard() + vfs.mount(sd, MOUNT_POINT) + vfs.umount(MOUNT_POINT) + del sd +except (OSError, AttributeError): + print("SKIP") + raise SystemExit + + +def verify_contents(buf, silent=False): + # Verify that each byte in 'buf' has the value of its index in the buffer + bad_pos = [] + for i in range(_BLOCK_SZ): + bi = buf[i] + if bi != i & 0xFF: + if silent: + return False + bad_pos.append((i, bi)) + if not bad_pos: + return True + + assert not silent + + print("{} bad readback values in sector:".format(len(bad_pos)), end="") + for i, v in bad_pos: + print(" {:#x}={:#x}".format(i, v), end="") + print() + return False + + +class TestSDAlign(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.sd = pyb.SDCard() + vfs.mount(cls.sd, MOUNT_POINT) + buf = bytearray(_BLOCK_SZ) + try: + with open(FILE_PATH, "rb") as f: + rlen = f.readinto(buf) + if rlen != _BLOCK_SZ: + raise RuntimeError("Unexpected length of temporary file ", FILE_PATH, rlen) + if not verify_contents(buf): + raise RuntimeError("Corrupt test block in temporary file ", FILE_PATH) + except OSError as e: + if e.errno != errno.ENOENT: + raise + + print("Creating new temp file...") + with open(FILE_PATH, "wb") as f: + f.write(bytes(i & 0xFF for i in range(_BLOCK_SZ))) + + # Now look for the sector which holds the temporary file + # (assume is in the first 20MB of the SD Card) + for b in range(1, 40960): + if not cls.sd.readblocks(b, buf): + raise RuntimeError("Failed to call readblocks on SDCard. block:", b) + if verify_contents(buf, True): + print("Temporary file contents found in block {}".format(b)) + cls.block = b + return + + raise RuntimeError( + "Contents of temporary file not found near start of SDCard. Too many files?" + ) + + @classmethod + def tearDownClass(cls): + try: + os.unlink(FILE_PATH) + print("Deleted temp file") + except OSError: + pass + vfs.umount(MOUNT_POINT) + del cls.sd + + def setUp(self): + self.offs = 0 + + @micropython.native + def _test_reads_inner(self, buf, repeats=_REPEATS): + for offs in range(_OFFS_WIDTH): + with self.subTest(offs=offs): + self.offs = offs + slice = memoryview(buf)[offs : offs + _BLOCK_SZ] + assert len(slice) == _BLOCK_SZ + for r in range(repeats): + self.assertTrue( + self.sd.readblocks(self.block, slice), + "Read failed for block {} offs {} repeat {}/{}".format( + self.block, offs, r, repeats + ), + ) + self.assertTrue( + verify_contents(slice), + "Verify failed for block {} offs {} repeat {}/{}".format( + self.block, offs, r, repeats + ), + ) + + def test_reads(self): + # Test reading at all available offsets in a buffer + buf = bytearray(_TEST_BUF_SZ) + # This test is the most random as any failure depends on speculative reads while + # the DMA operation is in progress. We run the test more times to increase the chance + # of hitting one of these cases, but even if the issue is present the test only fails + # once per ~250 iterations. The other tests inject explicit reads and writes so they fail + # more or less immediately. + self._test_reads_inner(buf, repeats=_REPEATS * 4) + + def test_interrupted_reads(self): + # Test reading at all available offsets in a buffer, while an interrupt is + # scanning through the whole buffer + buf = bytearray(_TEST_BUF_SZ) + t = None + self.scan = 0 + self.val = None + try: + + @micropython.native + def timer_cb(_): + # Arbitrary read from somewhere in the buffer + self.val = buf[self.scan % _TEST_BUF_SZ] + self.scan += 1 + + t = pyb.Timer(1, freq=30_000, callback=timer_cb, hard=True) + self._test_reads_inner(buf) + finally: + if t: + t.deinit() + # print("scan count", self.scan, self.val) + + def test_interrupted_read_write(self): + # Test reading at all available offsets in a buffer, while an interrupt is + # writing before & after the DMA buffer + buf = bytearray(_TEST_BUF_SZ) + t = None + try: + + @micropython.native + def timer_cb(t): + # Arbitrary CPU write just before and after the buffer, trying to dirty a DMA cache line + # + # Note: we never write into a word overlapping the DMA buffer, because if the buffer is not 4-byte aligned + # sdcard_read_blocks() will do a trick to align it temporarily, and this will race with that trick and + # corrupt the memory. + offs = self.offs + if offs > 3: + buf[offs - 4] = 0x55 + offs += _BLOCK_SZ + if offs < _TEST_BUF_SZ - 3: + buf[offs] = 0x56 + + # pybd SF2 at default CPU frequency can manage >30kHz <40kHz + t = pyb.Timer(1, freq=35_000, callback=timer_cb, hard=True) + self._test_reads_inner(buf) + finally: + if t: + t.deinit() + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/ports/stm32_hardware/dma_alignment.py b/tests/ports/stm32_hardware/spi_dma_align.py similarity index 100% rename from tests/ports/stm32_hardware/dma_alignment.py rename to tests/ports/stm32_hardware/spi_dma_align.py From d2e87fd16cce187836f9d918b11ab73081435f8c Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 15 Apr 2026 10:45:06 +1000 Subject: [PATCH 061/635] stm32/sdcard: Use dma_protect_rx_region on read operations. Will avoid corruption for unaligned reads, unless a SPI DMA operation is in progress at the same time (to be fixed separately). This fixes the unit test added in the parent commit. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/stm32/sdcard.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ports/stm32/sdcard.c b/ports/stm32/sdcard.c index 98bfe090f38..f2714ab5865 100644 --- a/ports/stm32/sdcard.c +++ b/ports/stm32/sdcard.c @@ -574,7 +574,7 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo // make sure cache is flushed and invalidated so when DMA updates the RAM // from reading the peripheral the CPU then reads the new data - MP_HAL_CLEANINVALIDATE_DCACHE(dest, num_blocks * SDCARD_BLOCK_SIZE); + dma_protect_rx_region(dest, num_blocks * SDCARD_BLOCK_SIZE); sdcard_reset_periph(); #if MICROPY_HW_ENABLE_MMCARD @@ -589,6 +589,8 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo err = sdcard_wait_finished(); } + dma_unprotect_rx_region(dest, num_blocks * SDCARD_BLOCK_SIZE); + #if SDIO_USE_GPDMA dma_deinit(&SDMMC_DMA); #if MICROPY_HW_ENABLE_MMCARD From e496000efc95894b62696c77863fd5566208ecdd Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 7 May 2026 17:50:35 +1000 Subject: [PATCH 062/635] esp8266: Remove obsolete --verify option from ESP8266. Has been the default forever (or, at least, for a decade) and was removed entirely in a recent esptool release. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/esp8266/Makefile | 2 +- ports/esp8266/README.md | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/ports/esp8266/Makefile b/ports/esp8266/Makefile index b961c76fdaf..699d174f69d 100644 --- a/ports/esp8266/Makefile +++ b/ports/esp8266/Makefile @@ -196,7 +196,7 @@ FROZEN_EXTRA_DEPS = $(CONFVARS_FILE) deploy: $(FWBIN) $(ECHO) "Writing $< to the board" - $(Q)$(ESPTOOL) --port $(PORT) --baud $(BAUD) write_flash --verify --flash_size=$(FLASH_SIZE) --flash_mode=$(FLASH_MODE) 0 $< + $(Q)$(ESPTOOL) --port $(PORT) --baud $(BAUD) write_flash --flash_size=$(FLASH_SIZE) --flash_mode=$(FLASH_MODE) 0 $< erase: $(ECHO) "Erase flash" diff --git a/ports/esp8266/README.md b/ports/esp8266/README.md index 561c7714032..33a5eea275d 100644 --- a/ports/esp8266/README.md +++ b/ports/esp8266/README.md @@ -240,8 +240,7 @@ While the port is in beta, it's known to be generally stable. If you experience strange bootloops, crashes, lockups, here's a list to check against: - You didn't erase flash before programming MicroPython firmware. -- Firmware can be occasionally flashed incorrectly. Just retry. Recent - esptool.py versions have --verify option. +- Firmware can be occasionally flashed incorrectly. Just retry. - Power supply you use doesn't provide enough power for ESP8266 or isn't stable enough. - A module/flash may be defective (not unheard of for cheap modules). From cc502abae9cdd02241b9f89db8b97ccab4c913c2 Mon Sep 17 00:00:00 2001 From: IhorNehrutsa Date: Mon, 19 Aug 2024 17:06:34 +0300 Subject: [PATCH 063/635] esp32/machine_pin: Add mode, pull and drive to machine_pin_print(). This commit adds mode, pull, drive parameters to the Pin repr function. This allows to serialize Pin object to str and restore the Pin object from the string. Signed-off-by: IhorNehrutsa --- ports/esp32/machine_pin.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) mode change 100644 => 100755 ports/esp32/machine_pin.c diff --git a/ports/esp32/machine_pin.c b/ports/esp32/machine_pin.c old mode 100644 new mode 100755 index efe6733194c..5eb13a48ce5 --- a/ports/esp32/machine_pin.c +++ b/ports/esp32/machine_pin.c @@ -129,7 +129,35 @@ gpio_num_t machine_pin_get_id(mp_obj_t pin_in) { static void machine_pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { machine_pin_obj_t *self = self_in; - mp_printf(print, "Pin(%u)", PIN_OBJ_PTR_INDEX(self)); + gpio_num_t gpio_num = PIN_OBJ_PTR_INDEX(self); + + mp_printf(print, "Pin(%u", gpio_num); + #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) + gpio_io_config_t gpio_io_config; + gpio_get_io_config(gpio_num, &gpio_io_config); + qstr mode; + if (gpio_io_config.oe) { + mode = MP_QSTR_OUT; + } else if (gpio_io_config.od) { + mode = MP_QSTR_OPEN_DRAIN; + } else { // if (gpio_io_config.ie) + mode = MP_QSTR_IN; + } + mp_printf(print, ", mode=%q.%q", MP_QSTR_Pin, mode); + qstr pull = MP_QSTRnull; + if (gpio_io_config.pu) { + pull = MP_QSTR_PULL_UP; + } else if (gpio_io_config.pd) { + pull = MP_QSTR_PULL_DOWN; + } + if (pull != MP_QSTRnull) { + mp_printf(print, ", pull=%q.%q", MP_QSTR_Pin, pull); + } + if (gpio_io_config.drv != GPIO_DRIVE_CAP_2) { + mp_printf(print, ", drive=Pin.DRIVE_%u", gpio_io_config.drv); + } + #endif + mp_printf(print, ")"); } // pin.init(mode=None, pull=-1, *, value, drive, hold) From f563d3c965b7da662e6817376baffdf832c21955 Mon Sep 17 00:00:00 2001 From: Meir Armon Date: Fri, 20 Jun 2025 17:45:41 +0300 Subject: [PATCH 064/635] esp32/modmachine: Add new machine.wake_pins() function. When waking from deep sleep, it could be helpful to know what pins triggered the wake up since the wake pins could be configured to multiple pins. Signed-off-by: Meir Armon --- docs/library/machine.rst | 7 +++++++ ports/esp32/modmachine.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/docs/library/machine.rst b/docs/library/machine.rst index 481820defc1..dad6128feec 100644 --- a/docs/library/machine.rst +++ b/docs/library/machine.rst @@ -163,6 +163,13 @@ Power related functions Availability: ESP32, WiPy. +.. function:: wake_pins() + + Returns the GPIO pin numbers of those pins which caused wakeup from deep sleep as a + tuple of integers. + + Availability: ESP32. + Miscellaneous functions ----------------------- diff --git a/ports/esp32/modmachine.c b/ports/esp32/modmachine.c index ec972bfc68e..c0c45f948b2 100644 --- a/ports/esp32/modmachine.c +++ b/ports/esp32/modmachine.c @@ -36,6 +36,7 @@ #include "esp_sleep.h" #include "esp_pm.h" +#include "py/objtuple.h" #include "modmachine.h" #include "machine_rtc.h" @@ -73,6 +74,7 @@ \ /* Wake reasons */ \ { MP_ROM_QSTR(MP_QSTR_wake_reason), MP_ROM_PTR(&machine_wake_reason_obj) }, \ + { MP_ROM_QSTR(MP_QSTR_wake_pins), MP_ROM_PTR(&machine_wake_pins_obj) }, \ { MP_ROM_QSTR(MP_QSTR_PIN_WAKE), MP_ROM_INT(ESP_SLEEP_WAKEUP_EXT0) }, \ { MP_ROM_QSTR(MP_QSTR_EXT0_WAKE), MP_ROM_INT(ESP_SLEEP_WAKEUP_EXT0) }, \ { MP_ROM_QSTR(MP_QSTR_EXT1_WAKE), MP_ROM_INT(ESP_SLEEP_WAKEUP_EXT1) }, \ @@ -310,6 +312,39 @@ static mp_obj_t machine_wake_reason(size_t n_args, const mp_obj_t *pos_args, mp_ } static MP_DEFINE_CONST_FUN_OBJ_KW(machine_wake_reason_obj, 0, machine_wake_reason); +static mp_obj_t machine_wake_pins(void) { + uint64_t status = 0; + int len, index; + + // There will be only one wake-up source, so it is OK to logically OR all the + // wake-up source statuses. + #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED + status |= esp_sleep_get_gpio_wakeup_status(); + #endif + + #if SOC_PM_SUPPORT_EXT1_WAKEUP && SOC_RTCIO_PIN_COUNT > 0 + status |= esp_sleep_get_ext1_wakeup_status(); + #endif + + // Only a few (~8) pins might cause wakeup. + // Therefore, we calculate the required space in a first pass. + for (index = 0, len = 0; index < 64; index++) { + len += (status & (1ULL << index)) ? 1 : 0; + } + if (len) { + mp_obj_tuple_t *tuple = MP_OBJ_TO_PTR(mp_obj_new_tuple(len, NULL)); + + for (index = 0, len = 0; index < 64; index++) { + if (status & (1ULL << index)) { + tuple->items[len++] = MP_OBJ_NEW_SMALL_INT(index); + } + } + return MP_OBJ_FROM_PTR(tuple); + } + return mp_obj_new_tuple(0, NULL); +} +static MP_DEFINE_CONST_FUN_OBJ_0(machine_wake_pins_obj, machine_wake_pins); + MP_NORETURN static void mp_machine_reset(void) { esp_restart(); } From a8ba8fab30a9ec0e00ce4c04927872c27730dac4 Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Mon, 23 Mar 2026 17:24:44 -0600 Subject: [PATCH 065/635] esp32/machine_sdcard: Add support for SDMMC power ctrl via internal LDO. A board can #define MICROPY_HW_SDMMC_LDO_CHAN_ID in mpconfigboard.h for an internal LDO to control power to the SDMMC GPIO pins. This is needed to use SDIO 3.0, because the IO level has to switch between 3.3V and 1.8V. Signed-off-by: Dryw Wade --- ports/esp32/machine_sdcard.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/ports/esp32/machine_sdcard.c b/ports/esp32/machine_sdcard.c index edecabaac76..8e09d09c9a3 100644 --- a/ports/esp32/machine_sdcard.c +++ b/ports/esp32/machine_sdcard.c @@ -35,6 +35,9 @@ #if SOC_SDMMC_HOST_SUPPORTED #include "driver/sdmmc_host.h" +#if SOC_SDMMC_IO_POWER_EXTERNAL && defined(MICROPY_HW_SDMMC_LDO_CHAN_ID) +#include "sd_pwr_ctrl_by_on_chip_ldo.h" +#endif #endif #include "driver/sdspi_host.h" #include "sdmmc_cmd.h" @@ -313,6 +316,14 @@ static mp_obj_t machine_sdcard_make_new(const mp_obj_type_t *type, size_t n_args self->host = _temp_host; } #endif + #if SOC_SDMMC_IO_POWER_EXTERNAL && defined(MICROPY_HW_SDMMC_LDO_CHAN_ID) + sd_pwr_ctrl_ldo_config_t ldo_config = { + .ldo_chan_id = MICROPY_HW_SDMMC_LDO_CHAN_ID, + }; + sd_pwr_ctrl_handle_t pwr_ctrl_handle = NULL; + check_esp_err(sd_pwr_ctrl_new_on_chip_ldo(&ldo_config, &pwr_ctrl_handle)); + self->host.pwr_ctrl_handle = pwr_ctrl_handle; + #endif DEBUG_printf(" Calling host.init()"); @@ -434,6 +445,11 @@ static mp_obj_t sd_deinit(mp_obj_t self_in) { // SD card used a (dedicated) SPI bus, so free that SPI bus. spi_bus_free(self->host.slot); } + #if SOC_SDMMC_IO_POWER_EXTERNAL && defined(MICROPY_HW_SDMMC_LDO_CHAN_ID) + if (self->host.pwr_ctrl_handle) { + check_esp_err(sd_pwr_ctrl_del_on_chip_ldo(self->host.pwr_ctrl_handle)); + } + #endif self->flags &= ~SDCARD_CARD_FLAGS_HOST_INIT_DONE; } From 169678c266f49f2cc6edeecd07e4682dd8dd6feb Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Mon, 23 Mar 2026 17:25:35 -0600 Subject: [PATCH 066/635] esp32/boards/ESP32_GENERIC_P4: Set SDMMC LDO channel. The ESP32-P4-Function-EV-Board uses LDO 4 for controlling SDMMC GPIO power. This is required to use SD cards with this board. Signed-off-by: Dryw Wade --- ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h | 1 + 1 file changed, 1 insertion(+) diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h index b7a88784802..6a7ff83cec0 100644 --- a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h @@ -12,6 +12,7 @@ #define MICROPY_PY_ESPNOW (0) #define MICROPY_HW_ENABLE_SDCARD (1) +#define MICROPY_HW_SDMMC_LDO_CHAN_ID (4) #ifndef USB_SERIAL_JTAG_PACKET_SZ_BYTES #define USB_SERIAL_JTAG_PACKET_SZ_BYTES (64) From dc44bdbac9607742d9b3f2364265bff2af788725 Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Thu, 2 Apr 2026 14:31:47 -0600 Subject: [PATCH 067/635] esp32/machine_sdcard: Make LDO channel configurable from Python. Can now call machine.SDCard(ldo=...) to specify LDO channel. Channel defaults to MICROPY_HW_SDMMC_LDO_CHAN_ID if defined, otherwise None (disabled). Signed-off-by: Dryw Wade --- ports/esp32/machine_sdcard.c | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/ports/esp32/machine_sdcard.c b/ports/esp32/machine_sdcard.c index 8e09d09c9a3..09c41e26ea9 100644 --- a/ports/esp32/machine_sdcard.c +++ b/ports/esp32/machine_sdcard.c @@ -35,7 +35,7 @@ #if SOC_SDMMC_HOST_SUPPORTED #include "driver/sdmmc_host.h" -#if SOC_SDMMC_IO_POWER_EXTERNAL && defined(MICROPY_HW_SDMMC_LDO_CHAN_ID) +#if SOC_SDMMC_IO_POWER_EXTERNAL #include "sd_pwr_ctrl_by_on_chip_ldo.h" #endif #endif @@ -214,6 +214,9 @@ static mp_obj_t machine_sdcard_make_new(const mp_obj_type_t *type, size_t n_args ARG_cmd, ARG_data, #endif + #if SOC_SDMMC_IO_POWER_EXTERNAL + ARG_ldo, + #endif ARG_freq, }; #if SOC_SDMMC_HOST_SUPPORTED @@ -236,6 +239,13 @@ static mp_obj_t machine_sdcard_make_new(const mp_obj_type_t *type, size_t n_args { MP_QSTR_cmd, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_data, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, #endif + #if SOC_SDMMC_IO_POWER_EXTERNAL + #ifdef MICROPY_HW_SDMMC_LDO_CHAN_ID + { MP_QSTR_ldo, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(MICROPY_HW_SDMMC_LDO_CHAN_ID)} }, + #else + { MP_QSTR_ldo, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + #endif + #endif // freq is valid for both SPI and SDMMC interfaces { MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 20000000} }, }; @@ -316,13 +326,15 @@ static mp_obj_t machine_sdcard_make_new(const mp_obj_type_t *type, size_t n_args self->host = _temp_host; } #endif - #if SOC_SDMMC_IO_POWER_EXTERNAL && defined(MICROPY_HW_SDMMC_LDO_CHAN_ID) - sd_pwr_ctrl_ldo_config_t ldo_config = { - .ldo_chan_id = MICROPY_HW_SDMMC_LDO_CHAN_ID, - }; - sd_pwr_ctrl_handle_t pwr_ctrl_handle = NULL; - check_esp_err(sd_pwr_ctrl_new_on_chip_ldo(&ldo_config, &pwr_ctrl_handle)); - self->host.pwr_ctrl_handle = pwr_ctrl_handle; + #if SOC_SDMMC_IO_POWER_EXTERNAL + if (arg_vals[ARG_ldo].u_obj != mp_const_none) { + sd_pwr_ctrl_ldo_config_t ldo_config = { + .ldo_chan_id = mp_obj_get_int(arg_vals[ARG_ldo].u_obj), + }; + sd_pwr_ctrl_handle_t pwr_ctrl_handle = NULL; + check_esp_err(sd_pwr_ctrl_new_on_chip_ldo(&ldo_config, &pwr_ctrl_handle)); + self->host.pwr_ctrl_handle = pwr_ctrl_handle; + } #endif DEBUG_printf(" Calling host.init()"); @@ -445,7 +457,7 @@ static mp_obj_t sd_deinit(mp_obj_t self_in) { // SD card used a (dedicated) SPI bus, so free that SPI bus. spi_bus_free(self->host.slot); } - #if SOC_SDMMC_IO_POWER_EXTERNAL && defined(MICROPY_HW_SDMMC_LDO_CHAN_ID) + #if SOC_SDMMC_IO_POWER_EXTERNAL if (self->host.pwr_ctrl_handle) { check_esp_err(sd_pwr_ctrl_del_on_chip_ldo(self->host.pwr_ctrl_handle)); } From f640267d73f8c57418ea162c2d47debf5f5da46b Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Wed, 6 May 2026 19:45:06 -0600 Subject: [PATCH 068/635] docs/library/machine.SDCard: Document new LDO argument for ESP32-P4. Signed-off-by: Dryw Wade --- docs/library/machine.SDCard.rst | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/docs/library/machine.SDCard.rst b/docs/library/machine.SDCard.rst index c4a0d5d172b..1677a6e3108 100644 --- a/docs/library/machine.SDCard.rst +++ b/docs/library/machine.SDCard.rst @@ -24,7 +24,7 @@ or a non-standard pin assignment. The exact subset of arguments supported will vary from platform to platform. .. class:: SDCard(slot=1, width=1, cd=None, wp=None, sck=None, miso=None, mosi=None, - cs=None, cmd=None, data=None, freq=20000000) + cs=None, cmd=None, data=None, ldo=None, freq=20000000) This class provides access to SD or MMC storage cards using either a dedicated SD/MMC interface hardware or through an SPI channel. @@ -60,6 +60,9 @@ vary from platform to platform. - *data* can be used to specify a list or tuple of SD data bus pins (ESP32-S3 only). + - *ldo* can be used to specify the internal LDO channel used for SD + card logic level for SDIO 3.0 (ESP32-P4 only). + - *freq* selects the SD/MMC interface frequency in Hz. Implementation-specific details @@ -188,6 +191,16 @@ parameters ``sck``, ``cs``, ``miso``, ``mosi`` as needed to assign pins. In either mode the ``cd`` and ``wp`` pins default to disabled, unless set in the constructor. +ESP32-P4 +~~~~~~~~ + +The ESP32-P4 has multiple internal adjustable LDO regulators, and some boards use +one of LDOs to control the SD card logic level required by SDIO 3.0. Most boards +will automatically select the correct LDO channel, but it may be necessary to +manually specify the ``ldo`` parameter as an integer (1 through 4). For example:: + + sd = SDCard(ldo=4) + Other ESP32 chips ~~~~~~~~~~~~~~~~~ From 4cf5c50c57ea264d2b6e8dd7ab015f5d1e9c8eb1 Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Thu, 9 Apr 2026 08:58:20 -0600 Subject: [PATCH 069/635] esp32/modnetwork: Always enable PHY_GENERIC. Also enable MICROPY_PY_NETWORK_LAN if SOC_EMAC_SUPPORTED is defined, which enables on ESP32-P4. Signed-off-by: Dryw Wade --- ports/esp32/modnetwork.h | 2 +- ports/esp32/mpconfigport.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/esp32/modnetwork.h b/ports/esp32/modnetwork.h index 68260dd19a3..47fd733c086 100644 --- a/ports/esp32/modnetwork.h +++ b/ports/esp32/modnetwork.h @@ -37,7 +37,7 @@ #endif // PHY_GENERIC support requires newer IDF version -#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) && CONFIG_IDF_TARGET_ESP32 +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) #define PHY_GENERIC_ENABLED (1) #else #define PHY_GENERIC_ENABLED (0) diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index 938f26e27c6..a77e13cf3f5 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -395,7 +395,7 @@ typedef long mp_off_t; void boardctrl_startup(void); #ifndef MICROPY_PY_NETWORK_LAN -#if CONFIG_IDF_TARGET_ESP32 || (CONFIG_ETH_USE_SPI_ETHERNET && (CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL || CONFIG_ETH_SPI_ETHERNET_DM9051 || CONFIG_ETH_SPI_ETHERNET_W5500)) +#if SOC_EMAC_SUPPORTED || (CONFIG_ETH_USE_SPI_ETHERNET && (CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL || CONFIG_ETH_SPI_ETHERNET_DM9051 || CONFIG_ETH_SPI_ETHERNET_W5500)) #define MICROPY_PY_NETWORK_LAN (1) #else #define MICROPY_PY_NETWORK_LAN (0) From 2e04624709651b797906db80672bb89e2cec964f Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Mon, 4 May 2026 10:17:07 -0600 Subject: [PATCH 070/635] esp32/network_lan: Make EMAC RMII pins configurable on ESP32-P4. Fixes #19035. Signed-off-by: Dryw Wade --- ports/esp32/network_lan.c | 71 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/ports/esp32/network_lan.c b/ports/esp32/network_lan.c index 37f72c26349..cf4566f7896 100644 --- a/ports/esp32/network_lan.c +++ b/ports/esp32/network_lan.c @@ -54,6 +54,16 @@ typedef struct _lan_if_obj_t { bool initialized; int8_t mdc_pin; int8_t mdio_pin; + #if CONFIG_IDF_TARGET_ESP32P4 + int8_t crs_dv_pin; + int8_t rxd0_pin; + int8_t rxd1_pin; + int8_t tx_en_pin; + int8_t txd0_pin; + int8_t txd1_pin; + int8_t clk_in_pin; + int8_t clk_out_pin; + #endif int8_t phy_reset_pin; int8_t phy_power_pin; int8_t phy_cs_pin; @@ -115,7 +125,12 @@ static mp_obj_t get_lan(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar } enum { ARG_id, ARG_mdc, ARG_mdio, ARG_reset, ARG_power, ARG_phy_addr, ARG_phy_type, - ARG_spi, ARG_cs, ARG_int, ARG_ref_clk_mode, ARG_ref_clk }; + ARG_spi, ARG_cs, ARG_int, ARG_ref_clk_mode, ARG_ref_clk, + #if CONFIG_IDF_TARGET_ESP32P4 + ARG_crs_dv, ARG_rxd0, ARG_rxd1, ARG_tx_en, + ARG_txd0, ARG_txd1, ARG_clk_in, ARG_clk_out, + #endif + }; static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_mdc, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, @@ -129,6 +144,16 @@ static mp_obj_t get_lan(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar { MP_QSTR_int, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_ref_clk_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, { MP_QSTR_ref_clk, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + #if CONFIG_IDF_TARGET_ESP32P4 + { MP_QSTR_crs_dv, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_rxd0, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_rxd1, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_tx_en, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_txd0, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_txd1, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_clk_in, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_clk_out, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, + #endif }; mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; @@ -148,6 +173,16 @@ static mp_obj_t get_lan(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar self->phy_power_pin = GET_PIN(ARG_power); self->phy_cs_pin = GET_PIN(ARG_cs); self->phy_int_pin = GET_PIN(ARG_int); + #if CONFIG_IDF_TARGET_ESP32P4 + self->crs_dv_pin = GET_PIN(ARG_crs_dv); + self->rxd0_pin = GET_PIN(ARG_rxd0); + self->rxd1_pin = GET_PIN(ARG_rxd1); + self->tx_en_pin = GET_PIN(ARG_tx_en); + self->txd0_pin = GET_PIN(ARG_txd0); + self->txd1_pin = GET_PIN(ARG_txd1); + self->clk_in_pin = GET_PIN(ARG_clk_in); + self->clk_out_pin = GET_PIN(ARG_clk_out); + #endif if (args[ARG_phy_addr].u_int < 0x00 || args[ARG_phy_addr].u_int > 0x1f) { mp_raise_ValueError(MP_ERROR_TEXT("invalid phy address")); @@ -293,6 +328,40 @@ static mp_obj_t get_lan(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar } esp32_config.smi_mdc_gpio_num = self->mdc_pin; esp32_config.smi_mdio_gpio_num = self->mdio_pin; + + #if CONFIG_IDF_TARGET_ESP32P4 + if (self->crs_dv_pin != -1) { + esp32_config.emac_dataif_gpio.rmii.crs_dv_num = self->crs_dv_pin; + } + if (self->rxd0_pin != -1) { + esp32_config.emac_dataif_gpio.rmii.rxd0_num = self->rxd0_pin; + } + if (self->rxd1_pin != -1) { + esp32_config.emac_dataif_gpio.rmii.rxd1_num = self->rxd1_pin; + } + if (self->tx_en_pin != -1) { + esp32_config.emac_dataif_gpio.rmii.tx_en_num = self->tx_en_pin; + } + if (self->txd0_pin != -1) { + esp32_config.emac_dataif_gpio.rmii.txd0_num = self->txd0_pin; + } + if (self->txd1_pin != -1) { + esp32_config.emac_dataif_gpio.rmii.txd1_num = self->txd1_pin; + } + if (self->clk_out_pin != -1) { + if (self->clk_in_pin == -1) { + mp_raise_ValueError(MP_ERROR_TEXT("clk_in must be specified if clk_out is specified")); + } + esp32_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT; + esp32_config.clock_config.rmii.clock_gpio = (emac_rmii_clock_gpio_t)self->clk_out_pin; + esp32_config.clock_config_out_in.rmii.clock_mode = EMAC_CLK_EXT_IN; + esp32_config.clock_config_out_in.rmii.clock_gpio = (emac_rmii_clock_gpio_t)self->clk_in_pin; + } else if (self->clk_in_pin != -1) { + esp32_config.clock_config.rmii.clock_mode = EMAC_CLK_EXT_IN; + esp32_config.clock_config.rmii.clock_gpio = (emac_rmii_clock_gpio_t)self->clk_in_pin; + } + #endif + mac = esp_eth_mac_new_esp32(&esp32_config, &mac_config); } #endif From 2b5f5f5347fcd26d58105a82c14f5021f0aafaf1 Mon Sep 17 00:00:00 2001 From: Mo Nazemi Date: Sun, 19 Apr 2026 17:30:00 +0100 Subject: [PATCH 071/635] esp32/network_lan: Fix LAN event handler base filtering. Prevent WiFi IP events from corrupting Ethernet status. Signed-off-by: Mo Nazemi --- ports/esp32/network_lan.c | 53 ++++++++++++++++++++++----------------- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/ports/esp32/network_lan.c b/ports/esp32/network_lan.c index cf4566f7896..e5fcdd8a121 100644 --- a/ports/esp32/network_lan.c +++ b/ports/esp32/network_lan.c @@ -80,29 +80,36 @@ static uint8_t eth_status = 0; static void eth_event_handler(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) { - switch (event_id) { - case ETHERNET_EVENT_CONNECTED: - eth_status = ETH_CONNECTED; - ESP_LOGI("ethernet", "Ethernet Link Up"); - break; - case ETHERNET_EVENT_DISCONNECTED: - eth_status = ETH_DISCONNECTED; - ESP_LOGI("ethernet", "Ethernet Link Down"); - break; - case ETHERNET_EVENT_START: - eth_status = ETH_STARTED; - ESP_LOGI("ethernet", "Ethernet Started"); - break; - case ETHERNET_EVENT_STOP: - eth_status = ETH_STOPPED; - ESP_LOGI("ethernet", "Ethernet Stopped"); - break; - case IP_EVENT_ETH_GOT_IP: - eth_status = ETH_GOT_IP; - ESP_LOGI("ethernet", "Ethernet Got IP"); - break; - default: - break; + if (event_base == ETH_EVENT) { + switch (event_id) { + case ETHERNET_EVENT_CONNECTED: + eth_status = ETH_CONNECTED; + ESP_LOGI("ethernet", "Ethernet Link Up"); + break; + case ETHERNET_EVENT_DISCONNECTED: + eth_status = ETH_DISCONNECTED; + ESP_LOGI("ethernet", "Ethernet Link Down"); + break; + case ETHERNET_EVENT_START: + eth_status = ETH_STARTED; + ESP_LOGI("ethernet", "Ethernet Started"); + break; + case ETHERNET_EVENT_STOP: + eth_status = ETH_STOPPED; + ESP_LOGI("ethernet", "Ethernet Stopped"); + break; + default: + break; + } + } else if (event_base == IP_EVENT) { + switch (event_id) { + case IP_EVENT_ETH_GOT_IP: + eth_status = ETH_GOT_IP; + ESP_LOGI("ethernet", "Ethernet Got IP"); + break; + default: + break; + } } } From e28c15f0faf608ad64921fb0fe7284f6356438e4 Mon Sep 17 00:00:00 2001 From: Ihor Nehrutsa Date: Thu, 7 May 2026 11:09:35 +0300 Subject: [PATCH 072/635] esp32/machine_i2c: Allow SoftI2C to be disabled. To disable `machine.SoftI2C` set zero #define MICROPY_PY_MACHINE_SOFTI2C (0) in `ports/esp32/mpconfigport.h`. Signed-off-by: Ihor Nehrutsa --- extmod/modmachine.h | 2 ++ ports/esp32/machine_i2c.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/extmod/modmachine.h b/extmod/modmachine.h index 18ee229dc79..80e1a384e7b 100644 --- a/extmod/modmachine.h +++ b/extmod/modmachine.h @@ -88,6 +88,7 @@ #define MICROPY_PY_MACHINE_UART_IRQ (0) #endif +#if MICROPY_PY_MACHINE_SOFTI2C // Temporary support for legacy construction of SoftI2C via I2C type. #define MP_MACHINE_I2C_CHECK_FOR_LEGACY_SOFTI2C_CONSTRUCTION(n_args, n_kw, all_args) \ do { \ @@ -100,6 +101,7 @@ return MP_OBJ_TYPE_GET_SLOT(&mp_machine_soft_i2c_type, make_new)(&mp_machine_soft_i2c_type, n_args, n_kw, all_args); \ } \ } while (0) +#endif // Temporary support for legacy construction of SoftSPI via SPI type. #define MP_MACHINE_SPI_CHECK_FOR_LEGACY_SOFTSPI_CONSTRUCTION(n_args, n_kw, all_args) \ diff --git a/ports/esp32/machine_i2c.c b/ports/esp32/machine_i2c.c index 9fb89660f74..2c59849d301 100644 --- a/ports/esp32/machine_i2c.c +++ b/ports/esp32/machine_i2c.c @@ -332,10 +332,12 @@ static void machine_hw_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp_p } mp_obj_t machine_hw_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + #if MICROPY_PY_MACHINE_SOFTI2C // Create a SoftI2C instance if no id is specified (or is -1) but other arguments are given if (n_args != 0) { MP_MACHINE_I2C_CHECK_FOR_LEGACY_SOFTI2C_CONSTRUCTION(n_args, n_kw, all_args); } + #endif // Parse args enum { ARG_id, ARG_scl, ARG_sda, ARG_freq, ARG_timeout }; From ea1e10f087686de019efbc4c7fdde778279049f6 Mon Sep 17 00:00:00 2001 From: Ihor Nehrutsa Date: Thu, 7 May 2026 12:25:12 +0300 Subject: [PATCH 073/635] esp32/machine_hw_spi: Allow SoftSPI to be disabled. To disable `machine.SoftSPI` set zero in line #define MICROPY_PY_MACHINE_SOFTSPI (0) in file `ports/esp32/mpconfigport.h`. Signed-off-by: Ihor Nehrutsa --- extmod/modmachine.h | 2 ++ ports/esp32/machine_hw_spi.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/extmod/modmachine.h b/extmod/modmachine.h index 80e1a384e7b..6d651d0bf6f 100644 --- a/extmod/modmachine.h +++ b/extmod/modmachine.h @@ -103,6 +103,7 @@ } while (0) #endif +#if MICROPY_PY_MACHINE_SOFTSPI // Temporary support for legacy construction of SoftSPI via SPI type. #define MP_MACHINE_SPI_CHECK_FOR_LEGACY_SOFTSPI_CONSTRUCTION(n_args, n_kw, all_args) \ do { \ @@ -115,6 +116,7 @@ return MP_OBJ_TYPE_GET_SLOT(&mp_machine_soft_spi_type, make_new)(&mp_machine_soft_spi_type, n_args, n_kw, all_args); \ } \ } while (0) +#endif #if MICROPY_PY_MACHINE_I2C || MICROPY_PY_MACHINE_SOFTI2C diff --git a/ports/esp32/machine_hw_spi.c b/ports/esp32/machine_hw_spi.c index aea6bd00fe8..7153084b1b6 100644 --- a/ports/esp32/machine_hw_spi.c +++ b/ports/esp32/machine_hw_spi.c @@ -436,7 +436,9 @@ static void machine_hw_spi_init(mp_obj_base_t *self_in, size_t n_args, const mp_ } mp_obj_t machine_hw_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + #if MICROPY_PY_MACHINE_SOFTSPI MP_MACHINE_SPI_CHECK_FOR_LEGACY_SOFTSPI_CONSTRUCTION(n_args, n_kw, all_args); + #endif mp_arg_val_t args[MP_ARRAY_SIZE(spi_allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(spi_allowed_args), spi_allowed_args, args); From 6fa7d5be270fa4133f10112c1ed3b501ecbf69d2 Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Tue, 30 Dec 2025 10:59:50 -0700 Subject: [PATCH 074/635] rp2/machine_spi: Detect RX overrun when using DMA transfers. Fixes bug where SPI can freeze if another DMA channel is tranferring to/from PSRAM. Fixes issue #18471. Signed-off-by: Dryw Wade --- ports/rp2/machine_spi.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/ports/rp2/machine_spi.c b/ports/rp2/machine_spi.c index 680a3df2878..9a3bf3a708b 100644 --- a/ports/rp2/machine_spi.c +++ b/ports/rp2/machine_spi.c @@ -273,6 +273,7 @@ static void machine_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8 bool use_dma = chan_rx >= 0 && chan_tx >= 0; // note src is guaranteed to be non-NULL bool write_only = dest == NULL; + bool success = true; if (use_dma) { uint8_t dev_null; @@ -297,8 +298,23 @@ static void machine_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8 false); dma_start_channel_mask((1u << chan_rx) | (1u << chan_tx)); - dma_channel_wait_for_finish_blocking(chan_rx); dma_channel_wait_for_finish_blocking(chan_tx); + + // Fix for #18471. Wait for SPI to finish then check for RX overrun + while (spi_is_busy(self->spi_inst) || spi_is_readable(self->spi_inst)) { + } + if (spi_get_const_hw(self->spi_inst)->ris & SPI_SSPRIS_RORRIS_BITS) { + // RX overrun occurred. Clear the flag for future transfers + spi_get_hw(self->spi_inst)->icr = SPI_SSPICR_RORIC_BITS; + + // RX DMA channel needs to be manually aborted + dma_channel_abort(chan_rx); + + // An RX overrun is only a problem if we were actually reading + if (!write_only) { + success = false; + } + } } // If we have claimed only one channel successfully, we should release immediately @@ -317,6 +333,11 @@ static void machine_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8 spi_write_read_blocking(self->spi_inst, src, dest, len); } } + + // Raise OSError if something went wrong + if (!success) { + mp_raise_OSError(MP_EIO); + } } // Buffer protocol implementation for SPI. From c4979d43dd9a711ed9094b23b9dfce4ea91b2541 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sat, 25 Apr 2026 01:10:55 +0200 Subject: [PATCH 075/635] rp2/mphalport: Optimise cycle counter retrieval in RV32 mode. This commit reduces the instruction count for the inline assembler sequence used in `mp_hal_ticks_cpu` when building the firmware in RISC-V mode. The code used a two instruction sequence to set the value of the `mcountinhibit` CSR to a fixed bit pattern, in order to have the cycle counter always enabled. Whilst this works, it also has the side-effect of always inhibiting the instructions counter, which may not be wanted in certain applications. Since all we need to do is to clear one bit, rather than setting the whole register we can just use the `CSRRCI` opcode to clear bit 0 of the CSR instead. This is done in a single instruction and leaves other register bits alone. Signed-off-by: Alessandro Gatti --- ports/rp2/mphalport.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/ports/rp2/mphalport.c b/ports/rp2/mphalport.c index d46360cb95e..32a1a645d2a 100644 --- a/ports/rp2/mphalport.c +++ b/ports/rp2/mphalport.c @@ -130,8 +130,7 @@ mp_uint_t mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) { #if PICO_RISCV __attribute__((naked)) mp_uint_t mp_hal_ticks_cpu(void) { __asm volatile ( - "li a0, 4\n" // mask value to uninhibit mcycle counter - "csrw mcountinhibit, a0\n" // uninhibit mcycle counter + "csrci mcountinhibit, 1\n" // uninhibit mcycle counter "csrr a0, mcycle\n" // get mcycle counter "ret\n" ); From aba71b3a2d7e78489bb5882b285e9397dcd52024 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sat, 25 Apr 2026 01:16:16 +0200 Subject: [PATCH 076/635] rp2/machine_bitstream: Shorten time-critical function init in RV32 mode. This commit reduces the instructions count for the bitstream module's time-critical function setup procedure, when the firmware is built for RISC-V. The original code used a separate function with three opcodes to make sure the hardware cycle counter is turned on. However, all of that could be condensed in a single opcode placed in lieu of the function call. An instance of the `CSRRCI` opcode is placed in the function opcode stream to clear bit 0 of the `mcountinhibit` CSR. `CSRRCI` is supposed to also store the original value of the CSR into a register, but luckily `zero`/`x0` is a valid target so the opcode can be placed safely without disrupting the existing registers' state. Signed-off-by: Alessandro Gatti --- ports/rp2/machine_bitstream.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/ports/rp2/machine_bitstream.c b/ports/rp2/machine_bitstream.c index 8411179f1ae..65ea1df00c0 100644 --- a/ports/rp2/machine_bitstream.c +++ b/ports/rp2/machine_bitstream.c @@ -40,14 +40,6 @@ #if PICO_RISCV -__attribute__((naked)) void mcycle_init(void) { - __asm volatile ( - "li a0, 4\n" - "csrw mcountinhibit, a0\n" - "ret\n" - ); -} - __attribute__((naked)) uint32_t mcycle_get(void) { __asm volatile ( "csrr a0, mcycle\n" @@ -99,7 +91,8 @@ void __time_critical_func(machine_bitstream_high_low)(mp_hal_pin_obj_t pin, uint #elif PICO_RISCV - mcycle_init(); + // Uninhibit the cycle counter. + __asm volatile ("csrci mcountinhibit, 1\n"); for (size_t i = 0; i < len; ++i) { uint8_t b = buf[i]; From 4e6dc0b5690c30b9ee5cfb48c432537abda285f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Wed, 25 Mar 2026 15:53:31 +0100 Subject: [PATCH 077/635] lib/littlefs: Update LittleFS to v2.11.3. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Daniël van de Giessen --- lib/littlefs/lfs2.c | 41 +++++++++++++++++++++++++---------------- lib/littlefs/lfs2.h | 11 ++++++----- 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/lib/littlefs/lfs2.c b/lib/littlefs/lfs2.c index 6c3c3ece76b..039bd0f0971 100644 --- a/lib/littlefs/lfs2.c +++ b/lib/littlefs/lfs2.c @@ -258,7 +258,7 @@ static int lfs2_bd_prog(lfs2_t *lfs2, continue; } - // pcache must have been flushed, either by programming and + // pcache must have been flushed, either by programming an // entire block or manually flushing the pcache LFS2_ASSERT(pcache->block == LFS2_BLOCK_NULL); @@ -286,7 +286,7 @@ static int lfs2_bd_erase(lfs2_t *lfs2, lfs2_block_t block) { // some operations on paths static inline lfs2_size_t lfs2_path_namelen(const char *path) { - return strcspn(path, "/"); + return (lfs2_size_t)strcspn(path, "/"); } static inline bool lfs2_path_islast(const char *path) { @@ -1291,6 +1291,7 @@ static lfs2_stag_t lfs2_dir_fetchmatch(lfs2_t *lfs2, // found a match for our fetcher? if ((fmask & tag) == (fmask & ftag)) { + LFS2_ASSERT(cb != NULL); int res = cb(data, tag, &(struct lfs2_diskoff){ dir->pair[0], off+sizeof(tag)}); if (res < 0) { @@ -1501,7 +1502,7 @@ static lfs2_stag_t lfs2_dir_find(lfs2_t *lfs2, lfs2_mdir_t *dir, if (lfs2_tag_type3(tag) == LFS2_TYPE_DIR) { name += strspn(name, "/"); } - lfs2_size_t namelen = strcspn(name, "/"); + lfs2_size_t namelen = (lfs2_size_t)strcspn(name, "/"); // skip '.' if (namelen == 1 && memcmp(name, ".", 1) == 0) { @@ -1520,7 +1521,7 @@ static lfs2_stag_t lfs2_dir_find(lfs2_t *lfs2, lfs2_mdir_t *dir, int depth = 1; while (true) { suffix += strspn(suffix, "/"); - sufflen = strcspn(suffix, "/"); + sufflen = (lfs2_size_t)strcspn(suffix, "/"); if (sufflen == 0) { break; } @@ -1761,7 +1762,7 @@ static int lfs2_dir_commitcrc(lfs2_t *lfs2, struct lfs2_commit *commit) { commit->off = noff; // perturb valid bit? - commit->ptag = ntag ^ ((0x80UL & ~eperturb) << 24); + commit->ptag = ntag ^ ((lfs2_tag_t)(0x80 & ~eperturb) << 24); // reset crc for next commit commit->crc = 0xffffffff; @@ -3244,10 +3245,12 @@ static int lfs2_file_open_(lfs2_t *lfs2, lfs2_file_t *file, #endif static int lfs2_file_close_(lfs2_t *lfs2, lfs2_file_t *file) { -#ifndef LFS2_READONLY - int err = lfs2_file_sync_(lfs2, file); -#else int err = 0; +#ifndef LFS2_READONLY + // it's not safe to do anything if our file errored + if (!(file->flags & LFS2_F_ERRED)) { + err = lfs2_file_sync_(lfs2, file); + } #endif // remove from list of mdirs @@ -3429,18 +3432,12 @@ static int lfs2_file_flush(lfs2_t *lfs2, lfs2_file_t *file) { #ifndef LFS2_READONLY static int lfs2_file_sync_(lfs2_t *lfs2, lfs2_file_t *file) { - if (file->flags & LFS2_F_ERRED) { - // it's not safe to do anything if our file errored - return 0; - } - int err = lfs2_file_flush(lfs2, file); if (err) { file->flags |= LFS2_F_ERRED; return err; } - if ((file->flags & LFS2_F_DIRTY) && !lfs2_pair_isnull(file->m.pair)) { // before we commit metadata, we need sync the disk to make sure @@ -3485,6 +3482,17 @@ static int lfs2_file_sync_(lfs2_t *lfs2, lfs2_file_t *file) { file->flags &= ~LFS2_F_DIRTY; } + // mark any other file handles as dirty + desync + for (lfs2_file_t *f = (lfs2_file_t*)lfs2->mlist; f; f = f->next) { + if (file != f + && f->type == LFS2_TYPE_REG + && lfs2_pair_cmp(f->m.pair, file->m.pair) == 0 + && f->id == file->id) { + f->flags |= LFS2_F_DUSTY; + } + } + + file->flags &= ~LFS2_F_ERRED & ~LFS2_F_DUSTY; return 0; } #endif @@ -3692,7 +3700,7 @@ static lfs2_ssize_t lfs2_file_write_(lfs2_t *lfs2, lfs2_file_t *file, return nsize; } - file->flags &= ~LFS2_F_ERRED; + file->flags &= ~LFS2_F_ERRED & ~LFS2_F_DUSTY; return nsize; } #endif @@ -4771,7 +4779,8 @@ int lfs2_fs_traverse_(lfs2_t *lfs2, continue; } - if ((f->flags & LFS2_F_DIRTY) && !(f->flags & LFS2_F_INLINE)) { + if (((f->flags & LFS2_F_DIRTY) || (f->flags & LFS2_F_DUSTY)) + && !(f->flags & LFS2_F_INLINE)) { int err = lfs2_ctz_traverse(lfs2, &f->cache, &lfs2->rcache, f->ctz.head, f->ctz.size, cb, data); if (err) { diff --git a/lib/littlefs/lfs2.h b/lib/littlefs/lfs2.h index 77477aaff83..99fb3ce1620 100644 --- a/lib/littlefs/lfs2.h +++ b/lib/littlefs/lfs2.h @@ -135,14 +135,15 @@ enum lfs2_open_flags { // internally used flags #ifndef LFS2_READONLY - LFS2_F_DIRTY = 0x010000, // File does not match storage - LFS2_F_WRITING = 0x020000, // File has been written since last flush + LFS2_F_DIRTY = 0x00010000, // File does not match storage due to write + LFS2_F_DUSTY = 0x00020000, // File does not match storage due to desync + LFS2_F_WRITING = 0x00040000, // File has been written since last flush #endif - LFS2_F_READING = 0x040000, // File has been read since last flush + LFS2_F_READING = 0x00080000, // File has been read since last flush #ifndef LFS2_READONLY - LFS2_F_ERRED = 0x080000, // An error occurred during write + LFS2_F_ERRED = 0x00100000, // An error occurred during write #endif - LFS2_F_INLINE = 0x100000, // Currently inlined in directory entry + LFS2_F_INLINE = 0x01000000, // Currently inlined in directory entry }; // File seek flags From 64f0394d80ca1cfbac47c0d0f9adeb6b483efa13 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Wed, 8 Apr 2026 14:00:44 -0500 Subject: [PATCH 078/635] extmod/vfs_blockdev: Use memoryview when available. This prevents Python code from accidentally performing an operation that resizes the buffer. However, in the case that the build excludes memoryview, the crash is still possible. Closes: #17848 Signed-off-by: Jeff Epler --- extmod/vfs_blockdev.c | 4 +++ tests/extmod/vfs_blockdev_invalid2.py | 37 +++++++++++++++++++++++ tests/extmod/vfs_blockdev_invalid2.py.exp | 1 + tests/run-tests.py | 1 + 4 files changed, 43 insertions(+) create mode 100644 tests/extmod/vfs_blockdev_invalid2.py create mode 100644 tests/extmod/vfs_blockdev_invalid2.py.exp diff --git a/extmod/vfs_blockdev.c b/extmod/vfs_blockdev.c index 5c7d248ac5a..7fad2c29a5c 100644 --- a/extmod/vfs_blockdev.c +++ b/extmod/vfs_blockdev.c @@ -49,7 +49,11 @@ void mp_vfs_blockdev_init(mp_vfs_blockdev_t *self, mp_obj_t bdev) { // Helper function to minimise code size of read/write functions // note the n_args argument is moved to the end for further code size reduction (args keep same position in caller and callee). static int mp_vfs_blockdev_call_rw(mp_obj_t *args, size_t block_num, size_t block_off, size_t len, void *buf, size_t n_args) { + #if MICROPY_PY_BUILTINS_MEMORYVIEW + mp_obj_array_t ar = {{&mp_type_memoryview}, 'B' | MP_OBJ_ARRAY_TYPECODE_FLAG_RW, 0, len, buf}; + #else mp_obj_array_t ar = {{&mp_type_bytearray}, BYTEARRAY_TYPECODE, 0, len, buf}; + #endif args[2] = MP_OBJ_NEW_SMALL_INT(block_num); args[3] = MP_OBJ_FROM_PTR(&ar); args[4] = MP_OBJ_NEW_SMALL_INT(block_off); // ignored for n_args == 2 diff --git a/tests/extmod/vfs_blockdev_invalid2.py b/tests/extmod/vfs_blockdev_invalid2.py new file mode 100644 index 00000000000..8905f833cf7 --- /dev/null +++ b/tests/extmod/vfs_blockdev_invalid2.py @@ -0,0 +1,37 @@ +# Tests where the block device returns invalid values + +try: + import vfs + + vfs.VfsFat + memoryview +except (NameError, ImportError, AttributeError): + print("SKIP") + raise SystemExit + + +class BadDev: + SEC_SIZE = 512 + + def __init__(self, blocks): + self.blocks = blocks + + def readblocks(self, n, buf): + assert len(buf) == self.SEC_SIZE + buf[:] = bytearray(self.SEC_SIZE + 1) # Attempts to enlarge passed-in buf + + def writeblocks(self, n, buf): + pass + + def ioctl(self, op, arg): + if op == 4: # MP_BLOCKDEV_IOCTL_BLOCK_COUNT + return self.blocks + if op == 5: # MP_BLOCKDEV_IOCTL_BLOCK_SIZE + return self.SEC_SIZE + + +bdev = BadDev(512) +try: + vfs.VfsFat.mkfs(bdev) +except ValueError as e: + print("ValueError") diff --git a/tests/extmod/vfs_blockdev_invalid2.py.exp b/tests/extmod/vfs_blockdev_invalid2.py.exp new file mode 100644 index 00000000000..94274de1bb3 --- /dev/null +++ b/tests/extmod/vfs_blockdev_invalid2.py.exp @@ -0,0 +1 @@ +ValueError diff --git a/tests/run-tests.py b/tests/run-tests.py index f6a4a33adee..344adc8faa6 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -283,6 +283,7 @@ "extmod/time_mktime.py", "extmod/time_res.py", "extmod/tls_sslcontext_ciphers.py", + "extmod/vfs_blockdev_invalid2.py", "extmod/vfs_fat_fileio1.py", "extmod/vfs_fat_finaliser.py", "extmod/vfs_fat_more.py", From 80a9abbf494e11af59a66cfa024339af84f008ba Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 14 Apr 2026 15:49:19 +0200 Subject: [PATCH 079/635] extmod/machine_i2c: Add a deinit method to machine.I2C. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds `.deinit()` to the `machine.I2C` class, bringing it in line with both the target I2C class variant and the rest of the peripheral classes. Ports that want to allocate I²C bus entries dynamically can implement the `self.deinit()` method to add deallocation/cleanup code, otherwise this method is entirely optional to have. If no method is found in the port-provided object structure then calling `deinit()` on the object will do nothing, following what the `machine.SPI` object does. This addresses #19096. Signed-off-by: Alessandro Gatti --- docs/library/machine.I2C.rst | 2 -- extmod/machine_i2c.c | 12 ++++++++++++ extmod/modmachine.h | 1 + 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/docs/library/machine.I2C.rst b/docs/library/machine.I2C.rst index 635d5873444..a10c6cf6d74 100644 --- a/docs/library/machine.I2C.rst +++ b/docs/library/machine.I2C.rst @@ -101,8 +101,6 @@ General Methods Turn off the I2C bus. - Availability: WiPy. - .. method:: I2C.scan() Scan all I2C addresses between 0x08 and 0x77 inclusive and return a list of diff --git a/extmod/machine_i2c.c b/extmod/machine_i2c.c index bddf7752999..c0b868421f5 100644 --- a/extmod/machine_i2c.c +++ b/extmod/machine_i2c.c @@ -319,6 +319,16 @@ static mp_obj_t machine_i2c_init(size_t n_args, const mp_obj_t *args, mp_map_t * } MP_DEFINE_CONST_FUN_OBJ_KW(machine_i2c_init_obj, 1, machine_i2c_init); +static mp_obj_t machine_i2c_deinit(mp_obj_t self_in) { + mp_obj_base_t *self = (mp_obj_base_t *)MP_OBJ_TO_PTR(self_in); + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->type, protocol); + if (i2c_p->deinit != NULL) { + i2c_p->deinit(self); + } + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_1(machine_i2c_deinit_obj, machine_i2c_deinit); + static mp_obj_t machine_i2c_scan(mp_obj_t self_in) { mp_obj_base_t *self = MP_OBJ_TO_PTR(self_in); mp_obj_t list = mp_obj_new_list(0, NULL); @@ -633,6 +643,7 @@ static MP_DEFINE_CONST_FUN_OBJ_KW(machine_i2c_writeto_mem_obj, 1, machine_i2c_wr static const mp_rom_map_elem_t machine_i2c_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_i2c_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_i2c_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_scan), MP_ROM_PTR(&machine_i2c_scan_obj) }, // primitive I2C operations @@ -724,6 +735,7 @@ int mp_machine_soft_i2c_write(mp_obj_base_t *self_in, const uint8_t *src, size_t static const mp_machine_i2c_p_t mp_machine_soft_i2c_p = { .init = mp_machine_soft_i2c_init, + .deinit = NULL, .start = (int (*)(mp_obj_base_t *))mp_hal_i2c_start, .stop = (int (*)(mp_obj_base_t *))mp_hal_i2c_stop, .read = mp_machine_soft_i2c_read, diff --git a/extmod/modmachine.h b/extmod/modmachine.h index 6d651d0bf6f..baa1d384565 100644 --- a/extmod/modmachine.h +++ b/extmod/modmachine.h @@ -161,6 +161,7 @@ typedef struct _mp_machine_i2c_p_t { bool transfer_supports_write1; #endif void (*init)(mp_obj_base_t *obj, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args); + void (*deinit)(mp_obj_base_t *obj); // can be NULL int (*start)(mp_obj_base_t *obj); int (*stop)(mp_obj_base_t *obj); int (*read)(mp_obj_base_t *obj, uint8_t *dest, size_t len, bool nack); From e47c528fe58fd49a20c000854576d433efde0e55 Mon Sep 17 00:00:00 2001 From: Julia Vassiliki Date: Mon, 4 May 2026 10:56:46 +1000 Subject: [PATCH 080/635] extmod/machine_i2c: Transfer WRITE1 address in single buffer adaptor. Without this, the register address is not copied into the single buffer, and so the requested register address is garbage when the driver reads it. Signed-off-by: Julia Vassiliki --- extmod/machine_i2c.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/extmod/machine_i2c.c b/extmod/machine_i2c.c index c0b868421f5..6df040b370a 100644 --- a/extmod/machine_i2c.c +++ b/extmod/machine_i2c.c @@ -271,6 +271,15 @@ int mp_machine_i2c_transfer_adaptor(mp_obj_base_t *self, uint16_t addr, size_t n len += bufs[i].len; } } + #if MICROPY_PY_MACHINE_I2C_TRANSFER_WRITE1 + if (flags & MP_MACHINE_I2C_FLAG_WRITE1) { + assert(flags & MP_MACHINE_I2C_FLAG_READ); + assert(n >= 1); + // If set, the "first mp_machine_i2c_buf_t in a transfer is a write", + // so we need to copy it. + memcpy(buf, bufs[0].buf, bufs[0].len); + } + #endif } mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->type, protocol); From 3288766533a2a726f209fa324675e200adbdee7a Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Thu, 23 Apr 2026 16:56:11 +0200 Subject: [PATCH 081/635] shared/tinyusb: Add USB device qualifier descriptor. USB 2.0 requires high-speed capable devices to provide a Device Qualifier descriptor. Signed-off-by: iabdalkader --- shared/tinyusb/mp_usbd.h | 3 +++ shared/tinyusb/mp_usbd_descriptor.c | 21 +++++++++++++++++++++ shared/tinyusb/mp_usbd_runtime.c | 6 ++++++ 3 files changed, 30 insertions(+) diff --git a/shared/tinyusb/mp_usbd.h b/shared/tinyusb/mp_usbd.h index d73cb5ade82..c455f0bc343 100644 --- a/shared/tinyusb/mp_usbd.h +++ b/shared/tinyusb/mp_usbd.h @@ -98,6 +98,9 @@ void mp_usbd_hex_str(char *out_str, const uint8_t *bytes, size_t bytes_len); // Built-in USB device and configuration descriptor values extern const tusb_desc_device_t mp_usbd_builtin_desc_dev; extern const uint8_t mp_usbd_builtin_desc_cfg[MP_USBD_BUILTIN_DESC_CFG_LEN]; +#if (CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED) +extern const tusb_desc_device_qualifier_t mp_usbd_builtin_desc_qual; +#endif void mp_usbd_task_callback(mp_sched_node_t *node); diff --git a/shared/tinyusb/mp_usbd_descriptor.c b/shared/tinyusb/mp_usbd_descriptor.c index d0c8845b680..0b3f5752469 100644 --- a/shared/tinyusb/mp_usbd_descriptor.c +++ b/shared/tinyusb/mp_usbd_descriptor.c @@ -53,6 +53,21 @@ const tusb_desc_device_t mp_usbd_builtin_desc_dev = { .bNumConfigurations = 1, }; +#if (CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED) +// Device qualifier descriptor for high-speed devices. +const tusb_desc_device_qualifier_t mp_usbd_builtin_desc_qual = { + .bLength = sizeof(tusb_desc_device_qualifier_t), + .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER, + .bcdUSB = 0x0200, + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .bNumConfigurations = 0x01, + .bReserved = 0x00, +}; +#endif + const uint8_t mp_usbd_builtin_desc_cfg[MP_USBD_BUILTIN_DESC_CFG_LEN] = { TUD_CONFIG_DESCRIPTOR(1, USBD_ITF_BUILTIN_MAX, USBD_STR_0, MP_USBD_BUILTIN_DESC_CFG_LEN, 0, USBD_MAX_POWER_MA), @@ -149,6 +164,12 @@ const uint8_t *tud_descriptor_configuration_cb(uint8_t index) { return mp_usbd_builtin_desc_cfg; } +#if (CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED) +uint8_t const *tud_descriptor_device_qualifier_cb(void) { + return (uint8_t const *)&mp_usbd_builtin_desc_qual; +} +#endif + #else // If runtime device support is enabled, descriptor callbacks are implemented in usbd.c diff --git a/shared/tinyusb/mp_usbd_runtime.c b/shared/tinyusb/mp_usbd_runtime.c index ef6bd87edda..4a1de40791b 100644 --- a/shared/tinyusb/mp_usbd_runtime.c +++ b/shared/tinyusb/mp_usbd_runtime.c @@ -126,6 +126,12 @@ const uint8_t *tud_descriptor_configuration_cb(uint8_t index) { return result ? result : &mp_usbd_builtin_desc_cfg; } +#if (CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED) +uint8_t const *tud_descriptor_device_qualifier_cb(void) { + return (const uint8_t *)&mp_usbd_builtin_desc_qual; +} +#endif + const char *mp_usbd_runtime_string_cb(uint8_t index) { mp_obj_usb_device_t *usbd = MP_OBJ_TO_PTR(MP_STATE_VM(usbd)); nlr_buf_t nlr; From 64431309680c0579c49a8ba0076dd9979dae3fbc Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Sun, 12 Apr 2026 19:32:05 +0200 Subject: [PATCH 082/635] tools/mpremote: Fix length calculation in RemoteCommand for arrays. Refactor the byte length calculation in the wr_bytes and read methods to use a new `buffer_nbytes` function. This change corrects the accuracy of byte length determination for various buffer types. Closes: #17665 Signed-off-by: Jos Verlinde --- tools/mpremote/mpremote/transport_serial.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/tools/mpremote/mpremote/transport_serial.py b/tools/mpremote/mpremote/transport_serial.py index b3584945bc5..dbd47cffd18 100644 --- a/tools/mpremote/mpremote/transport_serial.py +++ b/tools/mpremote/mpremote/transport_serial.py @@ -536,12 +536,20 @@ def wr_s32(self, i): self.fout.write(self.buf4) def wr_bytes(self, b): - self.wr_s32(len(b)) + self.wr_s32(self.buffer_nbytes(b)) self.fout.write(b) # str and bytes act the same in MicroPython wr_str = wr_bytes + def buffer_nbytes(self, obj): + if isinstance(obj, (str, bytes, bytearray)): + return len(obj) + mv = memoryview(obj) + if hasattr(mv, "itemsize"): + return len(mv) * mv.itemsize + # Fallback for uncommon buffer providers. + return len(bytes(obj)) class RemoteFile(io.IOBase): def __init__(self, cmd, fd, is_text): @@ -611,7 +619,7 @@ def readinto(self, buf): c = self.cmd c.begin(CMD_READ) c.wr_s8(self.fd) - c.wr_s32(len(buf)) + c.wr_s32(c.buffer_nbytes(buf)) n = c.rd_bytes(buf) c.end() return n From 670d7753653c5e5a87aee16e5c50bc95bd6ab83a Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Wed, 22 Apr 2026 18:05:51 +0200 Subject: [PATCH 083/635] tools/mpremote: Add tests for array readinto and write. Signed-off-by: Jos Verlinde --- tools/mpremote/tests/_test_mount_readinto_array.py | 11 +++++++++++ tools/mpremote/tests/_test_mount_write_array.py | 8 ++++++++ tools/mpremote/tests/test_mount.sh | 11 +++++++++++ tools/mpremote/tests/test_mount.sh.exp | 7 +++++++ 4 files changed, 37 insertions(+) create mode 100644 tools/mpremote/tests/_test_mount_readinto_array.py create mode 100644 tools/mpremote/tests/_test_mount_write_array.py diff --git a/tools/mpremote/tests/_test_mount_readinto_array.py b/tools/mpremote/tests/_test_mount_readinto_array.py new file mode 100644 index 00000000000..41b2576744a --- /dev/null +++ b/tools/mpremote/tests/_test_mount_readinto_array.py @@ -0,0 +1,11 @@ +from array import array +import os + +with open("/remote/test", "wb") as f: + f.write(b"abcd") +a = array("H", (0 for _ in range(2))) +with open("/remote/test", "rb") as f: + n = f.readinto(a) +os.remove("/remote/test") +print(n) +print(list(a)) diff --git a/tools/mpremote/tests/_test_mount_write_array.py b/tools/mpremote/tests/_test_mount_write_array.py new file mode 100644 index 00000000000..68748115811 --- /dev/null +++ b/tools/mpremote/tests/_test_mount_write_array.py @@ -0,0 +1,8 @@ +from array import array +import os + +h = array("h", (0x4041 for _ in range(50))) +with open("/remote/testfile", "wb") as f: + n = f.write(h) +os.remove("/remote/testfile") +print(n) diff --git a/tools/mpremote/tests/test_mount.sh b/tools/mpremote/tests/test_mount.sh index 724ae1417fc..21541c735b5 100755 --- a/tools/mpremote/tests/test_mount.sh +++ b/tools/mpremote/tests/test_mount.sh @@ -1,6 +1,8 @@ #!/bin/bash set -e +TEST_DIR=$(dirname $0) + # Create a local directory structure and mount the parent directory on the device. echo ----- mkdir -p "${TMP}/mount_package" @@ -30,3 +32,12 @@ cat "${TMP}/test.txt" # Test RemoteFile.readline and RemoteFile.readlines methods. echo ----- $MPREMOTE mount ${TMP} exec "print(open('test.txt').readlines())" + +echo ----- +# Test write() with array returns byte count, not item count. +# See https://github.com/micropython/micropython/issues/17665 +$MPREMOTE mount ${TMP} run "${TEST_DIR}/_test_mount_write_array.py" + +# Test readinto() with array returns byte count and fills correctly. +echo ----- +$MPREMOTE mount ${TMP} run "${TEST_DIR}/_test_mount_readinto_array.py" diff --git a/tools/mpremote/tests/test_mount.sh.exp b/tools/mpremote/tests/test_mount.sh.exp index 616cb75bcf5..7a5884b56f0 100644 --- a/tools/mpremote/tests/test_mount.sh.exp +++ b/tools/mpremote/tests/test_mount.sh.exp @@ -8,3 +8,10 @@ hello world ----- ['hello world\n'] Local directory ${TMP} is mounted at /remote +----- +100 +Local directory ${TMP} is mounted at /remote +----- +4 +[25185, 25699] +Local directory ${TMP} is mounted at /remote From a595bbba67271550735cf6d1be533b81fb676fee Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Mon, 23 Mar 2026 12:39:17 +0100 Subject: [PATCH 084/635] tools/mpremote: Add an alias for codeberg repos. This commit introduces an alias to access codeberg repos from within mpremote's package manager. Right now packages hosted on codeberg could only be referenced by their full URL, unlike other packages hosted on either GitHub or GitLab. To make access those packages easier, now they can be referenced as "codeberg:org/repo@branch". Signed-off-by: Alessandro Gatti --- docs/reference/packages.rst | 11 +++++-- tools/mpremote/README.md | 1 + tools/mpremote/mpremote/main.py | 2 +- tools/mpremote/mpremote/mip.py | 55 ++++++++++++++------------------- 4 files changed, 35 insertions(+), 34 deletions(-) diff --git a/docs/reference/packages.rst b/docs/reference/packages.rst index 5b5f626d452..adc9f95e01f 100644 --- a/docs/reference/packages.rst +++ b/docs/reference/packages.rst @@ -38,13 +38,15 @@ install third-party libraries. The simplest way is to download a file directly:: When installing a file directly, the ``target`` argument is still supported to set the destination path, but ``mpy`` and ``version`` are ignored. -The URL can also start with ``github:`` or ``gitlab:`` as a simple way of pointing to content -hosted on GitHub or GitLab:: +The URL can also start with ``github:``, ``gitlab:``, or ``codeberg:`` as a simple +way of pointing to content hosted on GitHub, GitLab, or Codeberg:: >>> mip.install("github:org/repo/path/foo.py") # Uses default branch >>> mip.install("github:org/repo/path/foo.py", version="branch-or-tag") # Optionally specify the branch or tag >>> mip.install("gitlab:org/repo/path/foo.py") # Uses default branch >>> mip.install("gitlab:org/repo/path/foo.py", version="branch-or-tag") # Optionally specify the branch or tag + >>> mip.install("codeberg:org/repo/path/foo.py") # Uses default branch + >>> mip.install("codeberg:org/repo/path/foo.py", version="branch-or-tag") # Optionally specify the branch or tag More sophisticated packages (i.e. with more than one file, or with dependencies) can be downloaded by specifying the path to their ``package.json``. @@ -52,6 +54,7 @@ can be downloaded by specifying the path to their ``package.json``. >>> mip.install("http://example.com/x/package.json") >>> mip.install("github:org/user/path/package.json") >>> mip.install("gitlab:org/user/path/package.json") + >>> mip.install("codeberg:org/user/path/package.json") If no json file is specified, then "package.json" is implicitly added:: @@ -60,6 +63,8 @@ If no json file is specified, then "package.json" is implicitly added:: >>> mip.install("github:org/repo", version="branch-or-tag") >>> mip.install("gitlab:org/repo") # Uses default branch of that repo >>> mip.install("gitlab:org/repo", version="branch-or-tag") + >>> mip.install("codeberg:org/repo") # Uses default branch of that repo + >>> mip.install("codeberg:org/repo", version="branch-or-tag") Using ``mip`` on the Unix port ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -89,6 +94,8 @@ can be used from a host PC to install packages to a locally connected device $ mpremote mip install github:org/repo@branch-or-tag $ mpremote mip install gitlab:org/repo $ mpremote mip install gitlab:org/repo@branch-or-tag + $ mpremote mip install codeberg:org/repo + $ mpremote mip install codeberg:org/repo@branch-or-tag The ``--target=path``, ``--no-mpy``, and ``--index`` arguments can be set:: diff --git a/tools/mpremote/README.md b/tools/mpremote/README.md index 2bf784be291..abd62f9dceb 100644 --- a/tools/mpremote/README.md +++ b/tools/mpremote/README.md @@ -82,3 +82,4 @@ Examples: mpremote mip install aioble mpremote mip install github:org/repo@branch mpremote mip install gitlab:org/repo@branch + mpremote mip install codeberg:org/repo@branch diff --git a/tools/mpremote/mpremote/main.py b/tools/mpremote/mpremote/main.py index b31186ba2e1..b57de0e25fc 100644 --- a/tools/mpremote/mpremote/main.py +++ b/tools/mpremote/mpremote/main.py @@ -246,7 +246,7 @@ def argparse_mip(): cmd_parser.add_argument( "packages", nargs="+", - help="list package specifications, e.g. name, name@version, github:org/repo, github:org/repo@branch, gitlab:org/repo, gitlab:org/repo@branch", + help="list package specifications, e.g. name, name@version, github:org/repo, github:org/repo@branch, gitlab:org/repo, gitlab:org/repo@branch, codeberg:org/repo, codeberg:org/repo@branch", ) return cmd_parser diff --git a/tools/mpremote/mpremote/mip.py b/tools/mpremote/mpremote/mip.py index 0d12ae651ec..3748fb980eb 100644 --- a/tools/mpremote/mpremote/mip.py +++ b/tools/mpremote/mpremote/mip.py @@ -5,7 +5,6 @@ import urllib.error import urllib.request import json -import tempfile import os import os.path @@ -14,7 +13,19 @@ _PACKAGE_INDEX = "https://micropython.org/pi/v2" -allowed_mip_url_prefixes = ("http://", "https://", "github:", "gitlab:") +# Since all URLs are accessed via HTTPS, the URL scheme is added by _rewrite_url. +# The first three format parameters are assumed to be the organisation, the +# repository names, and the branch/tag name, in this order. +_HOSTS = { + # https://codeberg.org/api/v1/repos/{org}/{repo}/raw/{path}?ref={branch} + "codeberg:": "codeberg.org/api/v1/repos/{}/{}/raw/{p}?ref={}", + # https://raw.githubusercontent.com/{org}/{repo}/{branch}/{path} + "github:": "raw.githubusercontent.com/{}/{}/{}/{p}", + # https://gitlab.com/{org}/{repo}/-/raw/{branch}/{path} + "gitlab:": "gitlab.com/{}/{}/-/raw/{}/{p}", +} + +_ALLOWED_MIP_URL_PREFIXES = ("http://", "https://", "codeberg:", "github:", "gitlab:") # This implements os.makedirs(os.dirname(path)) @@ -44,37 +55,19 @@ def _check_exists(transport, path, short_hash): def _rewrite_url(url, branch=None): - if not branch: - branch = "HEAD" - if url.startswith("github:"): - url = url[7:].split("/") - url = ( - "https://raw.githubusercontent.com/" - + url[0] - + "/" - + url[1] - + "/" - + branch - + "/" - + "/".join(url[2:]) - ) - elif url.startswith("gitlab:"): - url = url[7:].split("/") - url = ( - "https://gitlab.com/" - + url[0] - + "/" - + url[1] - + "/-/raw/" - + branch - + "/" - + "/".join(url[2:]) + for provider, url_format in _HOSTS.items(): + if not url.startswith(provider): + continue + components = url[len(provider) :].split("/") + # Add https:// prefix to the final URL. + return _ALLOWED_MIP_URL_PREFIXES[1] + url_format.format( + components[0], components[1], branch or "HEAD", p="/".join(components[2:]) ) return url def _download_file(transport, url, dest): - if url.startswith(allowed_mip_url_prefixes): + if url.startswith(_ALLOWED_MIP_URL_PREFIXES): try: with urllib.request.urlopen(url) as src: data = src.read() @@ -101,7 +94,7 @@ def _download_file(transport, url, dest): def _install_json(transport, package_json_url, index, target, version, mpy): base_url = "" - if package_json_url.startswith(allowed_mip_url_prefixes): + if package_json_url.startswith(_ALLOWED_MIP_URL_PREFIXES): try: with urllib.request.urlopen(_rewrite_url(package_json_url, version)) as response: package_json = json.load(response) @@ -131,7 +124,7 @@ def _install_json(transport, package_json_url, index, target, version, mpy): _download_file(transport, file_url, fs_target_path) for target_path, url in package_json.get("urls", ()): fs_target_path = target + "/" + target_path - if base_url and not url.startswith(allowed_mip_url_prefixes): + if base_url and not url.startswith(_ALLOWED_MIP_URL_PREFIXES): url = f"{base_url}/{url}" # Relative URLs _download_file(transport, _rewrite_url(url, version), fs_target_path) for dep, dep_version in package_json.get("deps", ()): @@ -139,7 +132,7 @@ def _install_json(transport, package_json_url, index, target, version, mpy): def _install_package(transport, package, index, target, version, mpy): - if package.startswith(allowed_mip_url_prefixes): + if package.startswith(_ALLOWED_MIP_URL_PREFIXES): if package.endswith(".py") or package.endswith(".mpy"): print(f"Downloading {package} to {target}") _download_file( From cc62017317da5af7deaf9cab28ec2e2d825b063d Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Thu, 30 Apr 2026 18:42:02 +0200 Subject: [PATCH 085/635] py/modbuiltins: Let "dir" be disabled if requested. This commit makes it possible to disable the `dir` built-in function from being included in the interpreter image. The function in question is rarely used outside of interactive contexts, and in production code the main use of this function is to implement interactive debug/management consoles over a serial port. However, outside of that scope, the space taken by such function could probably be better used elsewhere. This feature inherits the same configuration level as `enumerate`, since it performs the same operation but on class members rather than data elements. This should be enabled by default on all ports except for `nrf` (for which it is now explicitly enabled) and the `minimal` variants of the `unix` and `zephyr` ports. The latter two ports are meant to also run with the smallest available feature set, so `tests/basics/builtin_dir.py` had to be made optional to make CI run cleanly for those two ports' test runs in their minimal configuration. Signed-off-by: Alessandro Gatti --- ports/nrf/mpconfigport.h | 1 + py/modbuiltins.c | 4 ++++ py/mpconfig.h | 5 +++++ tests/basics/builtin_dir.py | 7 +++++++ 4 files changed, 17 insertions(+) diff --git a/ports/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h index 946c7f42d70..d5cbab73103 100644 --- a/ports/nrf/mpconfigport.h +++ b/ports/nrf/mpconfigport.h @@ -277,6 +277,7 @@ #define MICROPY_PY_ATTRTUPLE (1) #define MICROPY_PY_BUILTINS_BYTEARRAY (1) #define MICROPY_PY_BUILTINS_DICT_FROMKEYS (1) +#define MICROPY_PY_BUILTINS_DIR (1) #define MICROPY_PY_BUILTINS_ENUMERATE (1) #define MICROPY_PY_BUILTINS_EVAL_EXEC (1) #define MICROPY_PY_BUILTINS_FILTER (1) diff --git a/py/modbuiltins.c b/py/modbuiltins.c index 9617b8fcdae..eabc562f19d 100644 --- a/py/modbuiltins.c +++ b/py/modbuiltins.c @@ -155,6 +155,7 @@ static mp_obj_t mp_builtin_chr(mp_obj_t o_in) { } MP_DEFINE_CONST_FUN_OBJ_1(mp_builtin_chr_obj, mp_builtin_chr); +#if MICROPY_PY_BUILTINS_DIR static mp_obj_t mp_builtin_dir(size_t n_args, const mp_obj_t *args) { mp_obj_t dir = mp_obj_new_list(0, NULL); if (n_args == 0) { @@ -187,6 +188,7 @@ static mp_obj_t mp_builtin_dir(size_t n_args, const mp_obj_t *args) { return dir; } MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_builtin_dir_obj, 0, 1, mp_builtin_dir); +#endif static mp_obj_t mp_builtin_divmod(mp_obj_t o1_in, mp_obj_t o2_in) { return mp_binary_op(MP_BINARY_OP_DIVMOD, o1_in, o2_in); @@ -687,7 +689,9 @@ static const mp_rom_map_elem_t mp_module_builtins_globals_table[] = { #if MICROPY_CPYTHON_COMPAT { MP_ROM_QSTR(MP_QSTR_delattr), MP_ROM_PTR(&mp_builtin_delattr_obj) }, #endif + #if MICROPY_PY_BUILTINS_DIR { MP_ROM_QSTR(MP_QSTR_dir), MP_ROM_PTR(&mp_builtin_dir_obj) }, + #endif { MP_ROM_QSTR(MP_QSTR_divmod), MP_ROM_PTR(&mp_builtin_divmod_obj) }, #if MICROPY_PY_BUILTINS_EVAL_EXEC { MP_ROM_QSTR(MP_QSTR_eval), MP_ROM_PTR(&mp_builtin_eval_obj) }, diff --git a/py/mpconfig.h b/py/mpconfig.h index f46e79911ed..edc54bd26ef 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -1479,6 +1479,11 @@ typedef time_t mp_timestamp_t; #define MICROPY_PY_BUILTINS_ROUND_INT (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_EXTRA_FEATURES) #endif +// Whether to implement dir() to enumerate object fields. +#ifndef MICROPY_PY_BUILTINS_DIR +#define MICROPY_PY_BUILTINS_DIR (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_CORE_FEATURES) +#endif + // Whether to support complete set of special methods for user // classes, or only the most used ones. "Inplace" methods are // controlled by MICROPY_PY_ALL_INPLACE_SPECIAL_METHODS below. diff --git a/tests/basics/builtin_dir.py b/tests/basics/builtin_dir.py index 1eecbd044b7..2aa89dfe0a2 100644 --- a/tests/basics/builtin_dir.py +++ b/tests/basics/builtin_dir.py @@ -1,5 +1,12 @@ # test builtin dir +try: + dir +except NameError: + print("SKIP") + raise SystemExit + + # dir of locals print('__name__' in dir()) From 7eaa5221075d51faa58ed821bf4b9fd54b0e4150 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Fri, 29 Aug 2025 09:51:25 -0500 Subject: [PATCH 086/635] py/asmarm: Fix UBsan diagnostics for left-shift of int. Ths fixes the following type of diagnostic: "runtime error: left shift of 14 by 28 places cannot be represented in type 'int'" and ensures the resulting 32-bit value is correct. Signed-off-by: Jeff Epler --- py/asmarm.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/py/asmarm.h b/py/asmarm.h index 5ae952ee8a7..0cc43fd5acc 100644 --- a/py/asmarm.h +++ b/py/asmarm.h @@ -50,21 +50,21 @@ #define ASM_ARM_REG_LR (ASM_ARM_REG_R14) #define ASM_ARM_REG_PC (ASM_ARM_REG_R15) -#define ASM_ARM_CC_EQ (0x0 << 28) -#define ASM_ARM_CC_NE (0x1 << 28) -#define ASM_ARM_CC_CS (0x2 << 28) -#define ASM_ARM_CC_CC (0x3 << 28) -#define ASM_ARM_CC_MI (0x4 << 28) -#define ASM_ARM_CC_PL (0x5 << 28) -#define ASM_ARM_CC_VS (0x6 << 28) -#define ASM_ARM_CC_VC (0x7 << 28) -#define ASM_ARM_CC_HI (0x8 << 28) -#define ASM_ARM_CC_LS (0x9 << 28) -#define ASM_ARM_CC_GE (0xa << 28) -#define ASM_ARM_CC_LT (0xb << 28) -#define ASM_ARM_CC_GT (0xc << 28) -#define ASM_ARM_CC_LE (0xd << 28) -#define ASM_ARM_CC_AL (0xe << 28) +#define ASM_ARM_CC_EQ (0x0u << 28) +#define ASM_ARM_CC_NE (0x1u << 28) +#define ASM_ARM_CC_CS (0x2u << 28) +#define ASM_ARM_CC_CC (0x3u << 28) +#define ASM_ARM_CC_MI (0x4u << 28) +#define ASM_ARM_CC_PL (0x5u << 28) +#define ASM_ARM_CC_VS (0x6u << 28) +#define ASM_ARM_CC_VC (0x7u << 28) +#define ASM_ARM_CC_HI (0x8u << 28) +#define ASM_ARM_CC_LS (0x9u << 28) +#define ASM_ARM_CC_GE (0xau << 28) +#define ASM_ARM_CC_LT (0xbu << 28) +#define ASM_ARM_CC_GT (0xcu << 28) +#define ASM_ARM_CC_LE (0xdu << 28) +#define ASM_ARM_CC_AL (0xeu << 28) typedef struct _asm_arm_t { mp_asm_base_t base; From 91dadc57d724ace6184162e2f76299795af88fd2 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Fri, 29 Aug 2025 09:52:01 -0500 Subject: [PATCH 087/635] py/asmthumb: Fix UBsan diagnostics for left-shift of negative. This fixes the diagnostic "runtime error: left shift of negative value -1" and ensures the correct instruction is assembled. Signed-off-by: Jeff Epler --- py/asmthumb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py/asmthumb.c b/py/asmthumb.c index 58cc7aea880..4226ae28127 100644 --- a/py/asmthumb.c +++ b/py/asmthumb.c @@ -246,7 +246,7 @@ void asm_thumb_mov_reg_reg(asm_thumb_t *as, uint reg_dest, uint reg_src) { void asm_thumb_mov_reg_i16(asm_thumb_t *as, uint mov_op, uint reg_dest, int i16_src) { assert(reg_dest < ASM_THUMB_REG_R15); // mov[wt] reg_dest, #i16_src - asm_thumb_op32(as, mov_op | ((i16_src >> 1) & 0x0400) | ((i16_src >> 12) & 0xf), ((i16_src << 4) & 0x7000) | (reg_dest << 8) | (i16_src & 0xff)); + asm_thumb_op32(as, mov_op | ((i16_src >> 1) & 0x0400) | ((i16_src >> 12) & 0xf), (((uint16_t)i16_src << 4) & 0x7000) | (reg_dest << 8) | (i16_src & 0xff)); } static void asm_thumb_mov_rlo_i16(asm_thumb_t *as, uint rlo_dest, int i16_src) { From 8ecd995041c2c65fd1d69f9f4b0bb763272d8f83 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Fri, 26 Dec 2025 08:59:17 -0600 Subject: [PATCH 088/635] py/emitinlinerv32: Fix UBsan diagnostics for left-shift of mp_int_t. Signed-off-by: Jeff Epler --- py/emitinlinerv32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py/emitinlinerv32.c b/py/emitinlinerv32.c index e81b152087d..7ed9243ec9f 100644 --- a/py/emitinlinerv32.c +++ b/py/emitinlinerv32.c @@ -505,7 +505,7 @@ static bool serialise_argument(emit_inline_asm_t *emit, const opcode_t *opcode, return false; } - mp_uint_t immediate = mp_obj_get_int_truncated(object) << shift; + mp_uint_t immediate = ((mp_uint_t)mp_obj_get_int_truncated(object)) << shift; if (kind & U) { if (!is_in_unsigned_mask(mask, immediate)) { goto out_of_range; From 9da627f9a082b631f986cf8245162c300b34ebfe Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sat, 28 Feb 2026 20:58:01 +0100 Subject: [PATCH 089/635] py/emitinlinerv32: Add Zcmp opcodes to the inline assembler. This commit adds support for Zcmp opcodes to the RV32 inline assembler. Five new opcodes were added: CM.PUSH, CM.POP, CM.POPRET, CM.POPRETZ, CM.MVA01S, and CM.MVSA01, which introduce multi-register push and pop (similar to Thumb's PUSH and POP opcodes) and shortcuts to swap registers A0 and A1 with two chosen S-registers. Signed-off-by: Alessandro Gatti --- py/asmrv32.h | 34 ++- py/emitinlinerv32.c | 191 +++++++++++++ tests/feature_check/inlineasm_rv32_zcmp.py | 10 + .../feature_check/inlineasm_rv32_zcmp.py.exp | 1 + tests/inlineasm/rv32/asm_ext_zcmp.py | 264 ++++++++++++++++++ tests/inlineasm/rv32/asm_ext_zcmp.py.exp | 32 +++ 6 files changed, 531 insertions(+), 1 deletion(-) create mode 100644 tests/feature_check/inlineasm_rv32_zcmp.py create mode 100644 tests/feature_check/inlineasm_rv32_zcmp.py.exp create mode 100644 tests/inlineasm/rv32/asm_ext_zcmp.py create mode 100644 tests/inlineasm/rv32/asm_ext_zcmp.py.exp diff --git a/py/asmrv32.h b/py/asmrv32.h index c25b1aa4e26..b89163d50da 100644 --- a/py/asmrv32.h +++ b/py/asmrv32.h @@ -201,6 +201,14 @@ void asm_rv32_end_pass(asm_rv32_t *state); ((op & 0x03) | ((ft6 & 0x3F) << 10) | ((ft2 & 0x03) << 8) | \ ((rlist & 0x0F) << 4) | ((imm & 0x03) << 2)) +#define RV32_ENCODE_TYPE_CMMV(op, ft6, ft2, r1s, r2s) \ + ((op & 0x03) | ((ft6 & 0x3F) << 10) | ((ft2 & 0x03) << 5) | \ + ((((r1s >= ASM_RV32_REG_S0 && r1s <= ASM_RV32_REG_S1) ? \ + (r1s - ASM_RV32_REG_S0) : (r1s - ASM_RV32_REG_S2 + 2)) & 0x07) << 7) | \ + ((((r2s >= ASM_RV32_REG_S0 && r2s <= ASM_RV32_REG_S1) ? \ + (r2s - ASM_RV32_REG_S0) : (r2s - ASM_RV32_REG_S2 + 2)) & 0x07) << 2)) + + #define RV32_ENCODE_TYPE_CR(op, ft4, rs1, rs2) \ ((op & 0x03) | ((rs2 & 0x1F) << 2) | ((rs1 & 0x1F) << 7) | ((ft4 & 0x0F) << 12)) @@ -444,12 +452,36 @@ static inline void asm_rv32_opcode_cxor(asm_rv32_t *state, mp_uint_t rd, mp_uint asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CA(0x01, 0x23, 0x01, rd, rs)); } +// CM.MVA01S R1S', R2S' +static inline void asm_rv32_opcode_cmmva01s(asm_rv32_t *state, mp_uint_t r1s, mp_uint_t r2s) { + // CMMV: 101011 ... 11 ... 10 + asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CMMV(0x02, 0x2B, 0x03, r1s, r2s)); +} + +// CM.MVSA01 R1S', R2S' +static inline void asm_rv32_opcode_cmmvsa01(asm_rv32_t *state, mp_uint_t r1s, mp_uint_t r2s) { + // CMMV: 101011 ... 01 ... 10 + asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CMMV(0x02, 0x2B, 0x01, r1s, r2s)); +} + +// CM.POP {REG_LIST}, IMMEDIATE +static inline void asm_rv32_opcode_cmpop(asm_rv32_t *state, mp_uint_t reg_list, mp_uint_t immediate) { + // CMPP: 10111010 .... .. 10 + asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CMPP(0x02, 0x2E, 0x02, reg_list, immediate)); +} + // CM.POPRET {REG_LIST}, IMMEDIATE static inline void asm_rv32_opcode_cmpopret(asm_rv32_t *state, mp_uint_t reg_list, mp_uint_t immediate) { - // CMPP: 10111110 ... .. 10 + // CMPP: 10111110 .... .. 10 asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CMPP(0x02, 0x2F, 0x02, reg_list, immediate)); } +// CM.POPRETZ {REG_LIST}, IMMEDIATE +static inline void asm_rv32_opcode_cmpopretz(asm_rv32_t *state, mp_uint_t reg_list, mp_uint_t immediate) { + // CMPP: 10111100 .... .. 10 + asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CMPP(0x02, 0x2F, 0x00, reg_list, immediate)); +} + // CM.PUSH {REG_LIST}, -IMMEDIATE static inline void asm_rv32_opcode_cmpush(asm_rv32_t *state, mp_uint_t reg_list, mp_uint_t immediate) { // CMPP: 10111000 .... .. 10 diff --git a/py/emitinlinerv32.c b/py/emitinlinerv32.c index 7ed9243ec9f..b175ae0ddc8 100644 --- a/py/emitinlinerv32.c +++ b/py/emitinlinerv32.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -693,6 +694,192 @@ static void handle_opcode(emit_inline_asm_t *emit, const opcode_t *opcode_data, } } +static bool extract_register_list(emit_inline_asm_t *emit, qstr opcode, mp_parse_node_t node, mp_uint_t *reglist) { + assert(reglist != NULL && "Register list pointer is NULL."); + + // As per §28.9, valid register list values are as follows: + // + // {ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2}, ..., {ra, s0-s8}, + // {ra, s0-s9}, {ra, s0-s11} + // + // {ra, s0-s10} is *not* valid + + // case 1: {ra} + // PN_atom_brace { ID("ra") } + // + // case 2: {ra,s0} -> + // PN_atom_brace { PN_dictorsetmaker { ID("ra") + // PN_dictorsetmaker_list { ID("s0") } } } + // + // case 3: {ra,s0-s1} -> + // PN_atom_brace { PN_dictorsetmaker { ID("ra") + // PN_dictorsetmaker_list { PN_arith_expr { + // ID("s0") TOKEN(MP_TOKEN_OP_MINUS) ID("s1") } } } } + + if (!MP_PARSE_NODE_IS_STRUCT_KIND(node, PN_atom_brace) || + MP_PARSE_NODE_STRUCT_NUM_NODES((mp_parse_node_struct_t *)node) != 1) { + return false; + } + + mp_parse_node_struct_t *nodes = (mp_parse_node_struct_t *)node; + mp_uint_t register_id = 0; + + if (MP_PARSE_NODE_IS_ID(nodes->nodes[0])) { + if (!parse_register_node(nodes->nodes[0], ®ister_id, false)) { + return false; + } + *reglist = 4; + return register_id == ASM_RV32_REG_RA; + } + + if (!MP_PARSE_NODE_IS_STRUCT_KIND(nodes->nodes[0], PN_dictorsetmaker) || + MP_PARSE_NODE_STRUCT_NUM_NODES((mp_parse_node_struct_t *)nodes->nodes[0]) != 2) { + return false; + } + nodes = (mp_parse_node_struct_t *)nodes->nodes[0]; + if (!MP_PARSE_NODE_IS_ID(nodes->nodes[0]) || + !MP_PARSE_NODE_IS_STRUCT_KIND(nodes->nodes[1], PN_dictorsetmaker_list) || + !parse_register_node(nodes->nodes[0], ®ister_id, false) || + register_id != ASM_RV32_REG_RA) { + return false; + } + mp_parse_node_t *list_nodes; + size_t list_nodes_count = mp_parse_node_extract_list(&nodes->nodes[1], PN_dictorsetmaker_list2, &list_nodes); + if (list_nodes_count != 1 || !MP_PARSE_NODE_IS_STRUCT_KIND(list_nodes[0], PN_dictorsetmaker_list)) { + return false; + } + nodes = (mp_parse_node_struct_t *)list_nodes[0]; + if (MP_PARSE_NODE_STRUCT_NUM_NODES(nodes) != 1) { + return false; + } + if (MP_PARSE_NODE_IS_ID(nodes->nodes[0])) { + if (!parse_register_node(nodes->nodes[0], ®ister_id, false) || + register_id != ASM_RV32_REG_S0) { + return false; + } + *reglist = 5; + return true; + } + + if (MP_PARSE_NODE_IS_STRUCT_KIND(nodes->nodes[0], PN_arith_expr)) { + nodes = (mp_parse_node_struct_t *)nodes->nodes[0]; + if (MP_PARSE_NODE_STRUCT_NUM_NODES(nodes) != 3 || + !MP_PARSE_NODE_IS_ID(nodes->nodes[0]) || + !MP_PARSE_NODE_IS_TOKEN_KIND(nodes->nodes[1], MP_TOKEN_OP_MINUS) || + !MP_PARSE_NODE_IS_ID(nodes->nodes[2])) { + return false; + } + if (!parse_register_node(nodes->nodes[0], ®ister_id, false) || + register_id != ASM_RV32_REG_S0) { + return false; + } + if (!parse_register_node(nodes->nodes[2], ®ister_id, false) || + register_id == ASM_RV32_REG_S10) { + return false; + } + if (register_id == ASM_RV32_REG_S1) { + *reglist = 6; + return true; + } + if (register_id >= ASM_RV32_REG_S2 && register_id <= ASM_RV32_REG_S11) { + *reglist = 7 + MIN(register_id, ASM_RV32_REG_S10) - ASM_RV32_REG_S2; + return true; + } + } + + return false; +} + +static const qstr_short_t ZCMP_OPCODE_NAMES[] = { + MP_QSTR_cm_push, MP_QSTR_cm_pop, MP_QSTR_cm_popret, + MP_QSTR_cm_popretz, MP_QSTR_cm_mva01s, MP_QSTR_cm_mvsa01, +}; + +static const void *ZCMP_OPCODE_HANDLERS[] = { + asm_rv32_opcode_cmpush, asm_rv32_opcode_cmpop, + asm_rv32_opcode_cmpopret, asm_rv32_opcode_cmpopretz, + asm_rv32_opcode_cmmva01s, asm_rv32_opcode_cmmvsa01, +}; + +typedef void (*call_xi_t)(asm_rv32_t *state, mp_uint_t register_list, mp_int_t adjustment); +typedef void (*call_ss_t)(asm_rv32_t *state, mp_uint_t r1, mp_uint_t r2); + +static bool handle_zcmp_opcode(emit_inline_asm_t *emit, qstr opcode, mp_parse_node_t *argument_nodes) { + mp_uint_t argument_index = 0; + + for (size_t index = 0; index < MP_ARRAY_SIZE(ZCMP_OPCODE_NAMES); index++) { + if (ZCMP_OPCODE_NAMES[index] != opcode) { + continue; + } + const void *handler = ZCMP_OPCODE_HANDLERS[index]; + if (opcode == MP_QSTR_cm_mva01s || opcode == MP_QSTR_cm_mvsa01) { + mp_uint_t register_lhs = 0; + mp_uint_t register_rhs = 0; + + if (!parse_register_node(argument_nodes[0], ®ister_lhs, false) || + ((1U << register_lhs) & 0x00FC0300) == 0) { + goto invalid_s_register; + } + + if (!parse_register_node(argument_nodes[1], ®ister_rhs, false) || + ((1U << register_rhs) & 0x00FC0300) == 0) { + argument_index = 1; + goto invalid_s_register; + } + + if (register_lhs == register_rhs) { + emit_inline_rv32_error_exc(emit, + mp_obj_new_exception_msg_varg(&mp_type_SyntaxError, + MP_ERROR_TEXT("opcode '%q': registers must be different"), + opcode)); + return false; + } + + ((call_ss_t)handler)(&emit->as, register_lhs, register_rhs); + return true; + } + + mp_uint_t register_list; + if (!extract_register_list(emit, opcode, argument_nodes[0], ®ister_list)) { + emit_inline_rv32_error_exc(emit, + mp_obj_new_exception_msg_varg(&mp_type_SyntaxError, + MP_ERROR_TEXT("opcode '%q': malformed register list"), + opcode)); + return false; + } + + mp_obj_t stack_adjustment_object; + if (!mp_parse_node_get_int_maybe(argument_nodes[1], &stack_adjustment_object)) { + emit_inline_rv32_error_exc(emit, + mp_obj_new_exception_msg_varg(&mp_type_SyntaxError, + ET_WRONG_ARGUMENT_KIND, opcode, 2, MP_QSTR_integer)); + return false; + } + mp_int_t stack_adjustment = mp_obj_get_int(stack_adjustment_object); + // Either 0, 16, 32, or 48. + if ((abs((int32_t)stack_adjustment) & ~0x30U) != 0 || + ((opcode == MP_QSTR_cm_push) && stack_adjustment > 0) || + ((opcode != MP_QSTR_cm_push) && stack_adjustment < 0)) { + emit_inline_rv32_error_exc(emit, + mp_obj_new_exception_msg_varg(&mp_type_SyntaxError, + MP_ERROR_TEXT("opcode '%q': invalid stack adjustment"), + opcode)); + return false; + } + ((call_xi_t)handler)(&emit->as, register_list, abs((int32_t)stack_adjustment)); + return true; + } + + return false; + +invalid_s_register: + emit_inline_rv32_error_exc(emit, + mp_obj_new_exception_msg_varg(&mp_type_SyntaxError, + MP_ERROR_TEXT("opcode '%q' argument %d: wrong register(s)"), + opcode, argument_index + 1)); + return false; +} + static void emit_inline_rv32_opcode(emit_inline_asm_t *emit, qstr opcode, mp_uint_t arguments_count, mp_parse_node_t *argument_nodes) { const opcode_t *opcode_data = NULL; for (mp_uint_t index = 0; index < MP_ARRAY_SIZE(OPCODES); index++) { @@ -702,6 +889,10 @@ static void emit_inline_rv32_opcode(emit_inline_asm_t *emit, qstr opcode, mp_uin } } + if ((asm_rv32_allowed_extensions() & RV32_EXT_ZCMP) && !opcode_data && (arguments_count == 2) && handle_zcmp_opcode(emit, opcode, argument_nodes)) { + return; + } + if (!opcode_data || (asm_rv32_allowed_extensions() & opcode_data->required_extensions) != opcode_data->required_extensions) { emit_inline_rv32_error_exc(emit, mp_obj_new_exception_msg_varg(&mp_type_SyntaxError, MP_ERROR_TEXT("invalid RV32 instruction '%q'"), opcode)); diff --git a/tests/feature_check/inlineasm_rv32_zcmp.py b/tests/feature_check/inlineasm_rv32_zcmp.py new file mode 100644 index 00000000000..5ead2a3f693 --- /dev/null +++ b/tests/feature_check/inlineasm_rv32_zcmp.py @@ -0,0 +1,10 @@ +# check if RISC-V 32 inline asm supported Zcmp opcodes + + +@micropython.asm_rv32 +def f(): + cm_mva01s(s0, s1) + + +f() +print("rv32_zcmp") diff --git a/tests/feature_check/inlineasm_rv32_zcmp.py.exp b/tests/feature_check/inlineasm_rv32_zcmp.py.exp new file mode 100644 index 00000000000..1fe96068194 --- /dev/null +++ b/tests/feature_check/inlineasm_rv32_zcmp.py.exp @@ -0,0 +1 @@ +rv32_zcmp diff --git a/tests/inlineasm/rv32/asm_ext_zcmp.py b/tests/inlineasm/rv32/asm_ext_zcmp.py new file mode 100644 index 00000000000..619478def7f --- /dev/null +++ b/tests/inlineasm/rv32/asm_ext_zcmp.py @@ -0,0 +1,264 @@ +CMMV_TEMPLATE = """ +@micropython.asm_rv32 +def t(): + cm_mv{}({}, {}) +""" + +CMMV_TESTS = ( + ("s0", "s9", False), + ("s0", "s0", False), + ("s1", "s1", False), + ("s9", "s10", False), + ("s0", "s1", True), + ("s1", "s2", True), + ("s2", "s3", True), + ("s3", "s4", True), +) + + +def cmmv_test(op, tests): + passed = True + for lhs, rhs, success in tests: + try: + exec(CMMV_TEMPLATE.format(op, lhs, rhs)) + if success is False: + print("cm.mv{} {} {} syntax fail".format(op, lhs, rhs)) + passed = False + except SyntaxError: + if success is True: + print("cm.mv{} {} {} syntax fail".format(op, lhs, rhs)) + passed = False + if passed: + print("cm.mv{} syntax pass".format(op)) + + +cmmv_test("a01s", CMMV_TESTS) +cmmv_test("sa01", CMMV_TESTS) + + +CMPP_TEMPLATE = """ +@micropython.asm_rv32 +def t(): + cm_push({}, {}) + cm_pop{}({}, {}) +""" + + +CMPP_TESTS = ( + ("", 0, 0, False), + ("ra", 0, 0, False), + ("ra, s0", 0, 0, False), + ("ra, s0-s1", 0, 0, False), + ("ra, s0-s10", 0, 0, False), + ("{}", 0, 0, False), + ("{t0}", 0, 0, False), + ("{s0}", 0, 0, False), + ("{s0-s1}", 0, 0, False), + ("{ra, s1-s0}", 0, 0, False), + ("{ra, s0-s10}", 0, 0, False), + ("{ra}", 16, -16, False), + ("{ra, s0}", -20, 20, False), + ("{ra}", 0, 0, True), + ("{ra, s0}", 0, 0, True), + ("{ra, s0-s1}", 0, 0, True), + ("{ra, s0-s5}", 0, 0, True), + ("{ra, s0-s11}", 0, 0, True), + ("{ra}", -16, 16, True), + ("{ra, s0}", -16, 16, True), + ("{ra, s0-s1}", -16, 16, True), + ("{ra}", -32, 32, True), + ("{ra, s0}", -32, 32, True), + ("{ra, s0-s1}", -32, 32, True), + ("{ra}", -48, 48, True), + ("{ra, s0}", -48, 48, True), + ("{ra, s0-s1}", -48, 48, True), +) + + +def cmpp_test(op, tests): + passed = True + for lhs, rhs_in, rhs_out, success in tests: + try: + exec(CMPP_TEMPLATE.format(lhs, rhs_in, op, lhs, rhs_out)) + if success is False: + print("cm.push/cm.pop{} {} {} {} syntax fail".format(op, lhs, rhs_in, rhs_out)) + passed = False + except SyntaxError: + if success is True: + print("cm.push/cm.pop{} {} {} {} syntax fail".format(op, lhs, rhs_in, rhs_out)) + passed = False + if passed: + print("cm.push/cm.pop{} syntax pass".format(op)) + + +cmpp_test("", CMPP_TESTS) +cmpp_test("ret", CMPP_TESTS) +cmpp_test("retz", CMPP_TESTS) + + +CM_POP_TEMPLATE = """ +@micropython.asm_rv32 +def t(a0): + mv(t0, s0) + mv(a1, a0) + mv(s0, a0) + cm_push({{ra, s0}}, {}) + add(s0, a1, a1) + cm_pop({{ra, s0}}, {}) + bne(s0, a0, fail) + li(a0, 1) + c_j(end) + label(fail) + li(a0, 0) + label(end) + mv(s0, t0) +print("cm.push/cm.pop {}", t(0x1234) == 1) +""" + +for stack_adj in 0, 16, 32, 48: + exec(CM_POP_TEMPLATE.format(-stack_adj, stack_adj, stack_adj)) + + +CM_POPRET_TEMPLATE = """ +@micropython.asm_rv32 +def t(a0): + mv(t0, ra) + mv(a1, s0) + jal(ra, clobber) + mv(ra, t0) + bne(s0, a1, fail) + li(a0, 1) + c_j(end) + label(fail) + li(a0, 0) + label(end) + c_jr(ra) + label(clobber) + cm_push({{ra, s0}}, {}) + mv(s0, a0) + cm_popret({{ra, s0}}, {}) +print("cm.push/cm.popret {}", t(0x1234) == 1) +""" + +for stack_adj in 0, 16, 32, 48: + exec(CM_POPRET_TEMPLATE.format(-stack_adj, stack_adj, stack_adj)) + + +CM_POPRETZ_TEMPLATE = """ +@micropython.asm_rv32 +def t(a0): + mv(t0, ra) + mv(a1, s0) + jal(ra, clobber) + mv(ra, t0) + bne(a0, zero, fail) + bne(s0, a1, fail) + li(a0, 1) + c_j(end) + label(fail) + li(a0, 0) + label(end) + c_jr(ra) + label(clobber) + cm_push({{ra, s0}}, {}) + mv(s0, a0) + cm_popretz({{ra, s0}}, {}) +print("cm.push/cm.popretz {}", t(0x1234) == 1) +""" + + +for stack_adj in 0, 16, 32, 48: + exec(CM_POPRETZ_TEMPLATE.format(-stack_adj, stack_adj, stack_adj)) + + +REGLIST_TEMPLATE = """ +@micropython.asm_rv32 +def t(): + li(t6, 0) +{save} + cm_push({reglist}, 0) +{trash} + cm_pop({reglist}, 0) +{compare} + c_j(restore) + label(fail) + li(t6, 1) + label(restore) +{restore} + mv(a0, t6) +print("reglist {reglist}", t() == 0) +""" + +REG_MAP = [ + ("ra", "a0", "{ra}"), + ("s0", "a1", "{ra,s0}"), + ("s1", "a2", "{ra,s0-s1}"), + ("s2", "a3", "{ra,s0-s2}"), + ("s3", "a4", "{ra,s0-s3}"), + ("s4", "a5", "{ra,s0-s4}"), + ("s5", "a6", "{ra,s0-s5}"), + ("s6", "a7", "{ra,s0-s6}"), + ("s7", "t0", "{ra,s0-s7}"), + ("s8", "t1", "{ra,s0-s8}"), + ("s9", "t2", "{ra,s0-s9}"), + ("s10", "t3", "{ra,s0-s11}"), + ("s11", "t4", "{ra,s0-s11}"), +] + +for i in range(len(REG_MAP)): + save = "" + trash = "" + compare = "" + restore = "" + _, _, reglist = REG_MAP[i] + for j in range(i + 1): + r1, r2, _ = REG_MAP[j] + save += " mv({}, {})\n".format(r2, r1) + trash += " li({}, {})\n".format(r1, (0x1111_1111 * (j + 1)) & 0xFFFF_FFFF) + compare += " bne({}, {}, fail)\n".format(r2, r1) + restore += " mv({}, {})\n".format(r1, r2) + exec( + REGLIST_TEMPLATE.format( + save=save, trash=trash, compare=compare, restore=restore, reglist=reglist + ) + ) + + +@micropython.asm_rv32 +def test_cm_mva01s(a0, a1): + cm_push({ra, s0 - s11}, 0) + mv(s4, a0) + mv(s5, a1) + li(a0, 0) + li(a1, 0) + cm_mva01s(s4, s5) + bne(a0, s4, fail) + bne(a1, s5, fail) + li(a0, 1) + c_j(end) + label(fail) + li(a0, 0) + label(end) + cm_pop({ra, s0 - s11}, 0) + + +print("cm.mva01s", test_cm_mva01s(100, 200) == 1) + + +@micropython.asm_rv32 +def test_cm_mvsa01(a0, a1): + cm_push({ra, s0 - s11}, 0) + li(s6, 0x12345678) + li(s7, 0x87654321) + cm_mvsa01(s6, s7) + bne(a0, s6, fail) + bne(a1, s7, fail) + li(a0, 1) + c_j(end) + label(fail) + li(a0, 0) + label(end) + cm_pop({ra, s0 - s11}, 0) + + +print("cm.mvsa01", test_cm_mvsa01(100, 200) == 1) diff --git a/tests/inlineasm/rv32/asm_ext_zcmp.py.exp b/tests/inlineasm/rv32/asm_ext_zcmp.py.exp new file mode 100644 index 00000000000..62850dfff4a --- /dev/null +++ b/tests/inlineasm/rv32/asm_ext_zcmp.py.exp @@ -0,0 +1,32 @@ +cm.mva01s syntax pass +cm.mvsa01 syntax pass +cm.push/cm.pop syntax pass +cm.push/cm.popret syntax pass +cm.push/cm.popretz syntax pass +cm.push/cm.pop 0 True +cm.push/cm.pop 16 True +cm.push/cm.pop 32 True +cm.push/cm.pop 48 True +cm.push/cm.popret 0 True +cm.push/cm.popret 16 True +cm.push/cm.popret 32 True +cm.push/cm.popret 48 True +cm.push/cm.popretz 0 True +cm.push/cm.popretz 16 True +cm.push/cm.popretz 32 True +cm.push/cm.popretz 48 True +reglist {ra} True +reglist {ra,s0} True +reglist {ra,s0-s1} True +reglist {ra,s0-s2} True +reglist {ra,s0-s3} True +reglist {ra,s0-s4} True +reglist {ra,s0-s5} True +reglist {ra,s0-s6} True +reglist {ra,s0-s7} True +reglist {ra,s0-s8} True +reglist {ra,s0-s9} True +reglist {ra,s0-s11} True +reglist {ra,s0-s11} True +cm.mva01s True +cm.mvsa01 True From 9b5f206647a3a907a831fd059b72b26fe79e3200 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 12 May 2026 00:54:16 +0200 Subject: [PATCH 090/635] qemu: Enable Zcmp extension for VIRT_RV32. This commit provides custom settings to the qemu binary that enable support for Zcmp opcodes in the emulated machine. Zcmp opcodes share some encodings with the Zcd extension (compressed double-precision floating point opcodes), and QEMU enables the Zcd extension by default. This effectively prevents Zcmp opcodes from working in the default configuration. With these changes now the Zcd extension is switched off, so the Zcmp extension can be switched on instead. Since now we have a way to exercise emitted Zcmp code for both the native emitter and the inline assembler, support for both is enabled in the default QEMU port configuration for the VIRT_RV32 board too. Signed-off-by: Alessandro Gatti --- ports/qemu/Makefile | 2 +- ports/qemu/boards/VIRT_RV32/mpconfigboard.mk | 2 +- ports/qemu/mpconfigport.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/ports/qemu/Makefile b/ports/qemu/Makefile index 49b242603cb..ce3e3bd6f3f 100644 --- a/ports/qemu/Makefile +++ b/ports/qemu/Makefile @@ -105,7 +105,7 @@ GCC_VERSION = $(word 1, $(subst ., , $(shell $(CC) -dumpversion))) RV32_ABI = ilp32 -QEMU_ARGS += -bios none +QEMU_ARGS += -bios none -cpu rv32,zcd=off,zcmp=on # GCC 10 and lower do not recognise the Zicsr extension in the architecture name. ifeq ($(shell test $(GCC_VERSION) -le 10; echo $$?),0) diff --git a/ports/qemu/boards/VIRT_RV32/mpconfigboard.mk b/ports/qemu/boards/VIRT_RV32/mpconfigboard.mk index e38991aa341..8e5325275c9 100644 --- a/ports/qemu/boards/VIRT_RV32/mpconfigboard.mk +++ b/ports/qemu/boards/VIRT_RV32/mpconfigboard.mk @@ -14,4 +14,4 @@ MICROPY_HW_ROMFS_PART0_SIZE = 0x00400000 SRC_BOARD_O += shared/runtime/gchelper_native.o shared/runtime/gchelper_rv32i.o -MPY_CROSS_FLAGS += -march=rv32imc -march-flags=zba +MPY_CROSS_FLAGS += -march=rv32imc -march-flags=zba,zcmp diff --git a/ports/qemu/mpconfigport.h b/ports/qemu/mpconfigport.h index c9867a1fb70..17be9903b94 100644 --- a/ports/qemu/mpconfigport.h +++ b/ports/qemu/mpconfigport.h @@ -43,6 +43,7 @@ #if (__riscv_xlen == 32) #define MICROPY_EMIT_RV32 (1) #define MICROPY_EMIT_RV32_ZBA (1) +#define MICROPY_EMIT_RV32_ZCMP (1) #define MICROPY_EMIT_INLINE_RV32 (1) #elif (__riscv_xlen == 64) #define MICROPY_PERSISTENT_CODE_LOAD_NATIVE (1) From 7c1f1c4dbbd0ac03610947aaa73be59f3546c6df Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 7 Apr 2026 18:43:05 +1000 Subject: [PATCH 091/635] py/mpconfig: Enable lwIP socket.SOCK_RAW by default. This commit adds default settings for `MICROPY_PY_LWIP` and `MICROPY_PY_LWIP_SOCK_RAW` to `py/mpconfig.h`, to make these settings more visible and consistent with other settings. `MICROPY_PY_LWIP_SOCK_RAW` is now enabled by default, and ports updated to take this into account. This will enable it on the alif port where it was previously not enabled. Signed-off-by: Damien George --- ports/esp8266/mpconfigport.h | 1 - ports/mimxrt/mpconfigport.h | 1 - ports/renesas-ra/mpconfigport.h | 1 - ports/rp2/mpconfigport.h | 1 - ports/stm32/mpconfigport.h | 1 - py/mpconfig.h | 10 ++++++++++ 6 files changed, 10 insertions(+), 5 deletions(-) diff --git a/ports/esp8266/mpconfigport.h b/ports/esp8266/mpconfigport.h index f8838ea3688..df5185e36f4 100644 --- a/ports/esp8266/mpconfigport.h +++ b/ports/esp8266/mpconfigport.h @@ -64,7 +64,6 @@ #define MICROPY_PY_TIME_TIME_TIME_NS (1) #define MICROPY_PY_TIME_INCLUDEFILE "ports/esp8266/modtime.c" #define MICROPY_PY_LWIP (1) -#define MICROPY_PY_LWIP_SOCK_RAW (1) #define MICROPY_PY_MACHINE (1) #define MICROPY_PY_MACHINE_INCLUDEFILE "ports/esp8266/modmachine.c" #define MICROPY_PY_MACHINE_RESET (1) diff --git a/ports/mimxrt/mpconfigport.h b/ports/mimxrt/mpconfigport.h index 01461b9a5c9..6309c467b62 100644 --- a/ports/mimxrt/mpconfigport.h +++ b/ports/mimxrt/mpconfigport.h @@ -157,7 +157,6 @@ uint32_t trng_random_u32(void); #endif #define MICROPY_PY_WEBSOCKET (MICROPY_PY_LWIP) #define MICROPY_PY_WEBREPL (MICROPY_PY_LWIP) -#define MICROPY_PY_LWIP_SOCK_RAW (MICROPY_PY_LWIP) #ifndef MICROPY_PY_NETWORK_PPP_LWIP #define MICROPY_PY_NETWORK_PPP_LWIP (MICROPY_PY_LWIP) #endif diff --git a/ports/renesas-ra/mpconfigport.h b/ports/renesas-ra/mpconfigport.h index d6194494f6e..0387374335a 100644 --- a/ports/renesas-ra/mpconfigport.h +++ b/ports/renesas-ra/mpconfigport.h @@ -128,7 +128,6 @@ #define MICROPY_PY_TIME_GMTIME_LOCALTIME_MKTIME (1) #define MICROPY_PY_TIME_TIME_TIME_NS (1) #define MICROPY_PY_TIME_INCLUDEFILE "ports/renesas-ra/modtime.c" -#define MICROPY_PY_LWIP_SOCK_RAW (MICROPY_PY_LWIP) #ifndef MICROPY_PY_MACHINE #define MICROPY_PY_MACHINE (1) #define MICROPY_PY_MACHINE_INCLUDEFILE "ports/renesas-ra/modmachine.c" diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index 29d084582bb..0bfaf6098ad 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -199,7 +199,6 @@ #define MICROPY_VFS_ROM (MICROPY_HW_ROMFS_BYTES > 0) #define MICROPY_SSL_MBEDTLS (1) #define MICROPY_PY_LWIP_PPP (MICROPY_PY_NETWORK_PPP_LWIP) -#define MICROPY_PY_LWIP_SOCK_RAW (MICROPY_PY_LWIP) // Hardware timer alarm index. Available range 0-3. // Number 3 is currently used by pico-sdk alarm pool (PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM) diff --git a/ports/stm32/mpconfigport.h b/ports/stm32/mpconfigport.h index 19d4ef8ae0f..2389f8fb92f 100644 --- a/ports/stm32/mpconfigport.h +++ b/ports/stm32/mpconfigport.h @@ -109,7 +109,6 @@ #define MICROPY_PY_TIME_TIME_TIME_NS (1) #define MICROPY_PY_TIME_INCLUDEFILE "ports/stm32/modtime.c" #define MICROPY_PY_LWIP_PPP (MICROPY_PY_NETWORK_PPP_LWIP) -#define MICROPY_PY_LWIP_SOCK_RAW (MICROPY_PY_LWIP) #ifndef MICROPY_PY_MACHINE #define MICROPY_PY_MACHINE (1) #define MICROPY_PY_MACHINE_INCLUDEFILE "ports/stm32/modmachine.c" diff --git a/py/mpconfig.h b/py/mpconfig.h index edc54bd26ef..1553c28ae4d 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -2133,6 +2133,16 @@ typedef time_t mp_timestamp_t; #define MICROPY_PY_SOCKET_LISTEN_BACKLOG_DEFAULT (2) #endif +// Whether to enable lwIP bindings to be used as the implementation of the `socket` module +#ifndef MICROPY_PY_LWIP +#define MICROPY_PY_LWIP (0) +#endif + +// Whether to support raw sockets via the `socket.SOCK_RAW` constant +#ifndef MICROPY_PY_LWIP_SOCK_RAW +#define MICROPY_PY_LWIP_SOCK_RAW (MICROPY_PY_LWIP) +#endif + #ifndef MICROPY_PY_SSL #define MICROPY_PY_SSL (0) #endif From 14450cba117b9e1974dc6460238a0f447d43f2dc Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 14 Apr 2026 13:37:07 +1000 Subject: [PATCH 092/635] py/builtinimport: Prevent warning when building with compiler disabled. If the compiler and persistent code loading are both disabled then this bit of code is never used, so disable it as well. Signed-off-by: Damien George --- py/builtinimport.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/py/builtinimport.c b/py/builtinimport.c index 2c7d796680f..dfdb6e297d7 100644 --- a/py/builtinimport.c +++ b/py/builtinimport.c @@ -238,7 +238,9 @@ static void do_load(mp_module_context_t *module_obj, vstr_t *file) { #endif // MICROPY_MODULE_FROZEN + #if MICROPY_ENABLE_COMPILER || (MICROPY_PERSISTENT_CODE_LOAD && MICROPY_HAS_FILE_READER) qstr file_qstr = qstr_from_str(file_str); + #endif // If we support loading .mpy files then check if the file extension is of // the correct format and, if so, load and execute the file. From ea9e9ac6884e7c850920e566023ae699a459e8fe Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Mon, 13 Apr 2026 16:30:03 +0200 Subject: [PATCH 093/635] py/gc: Add a fast version of gc_info. The existing gc_info is very slow on large heaps. This patch adds a fast version that only computes total/used/free which can be used for frequent polling. Signed-off-by: iabdalkader --- py/gc.c | 19 +++++++++++++++++++ py/gc.h | 1 + 2 files changed, 20 insertions(+) diff --git a/py/gc.c b/py/gc.c index 5fe26ef8905..c1a19da3efa 100644 --- a/py/gc.c +++ b/py/gc.c @@ -825,6 +825,25 @@ void gc_info(gc_info_t *info) { GC_EXIT(); } +// Fast version of gc_info that only computes total/used/free. +void gc_info_fast(gc_info_t *info) { + GC_ENTER(); + memset(info, 0, sizeof(*info)); + const uint8_t lut[16] = {2, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0}; + for (mp_state_mem_area_t *area = &MP_STATE_MEM(area); area != NULL; area = NEXT_AREA(area)) { + size_t free_blocks = 0; + info->total += area->gc_pool_end - area->gc_pool_start; + for (size_t i = 0; i < area->gc_alloc_table_byte_len; i++) { + uint8_t atb = area->gc_alloc_table_start[i]; + free_blocks += lut[atb & 0xF] + lut[atb >> 4]; + } + info->free += free_blocks; + } + info->free *= BYTES_PER_BLOCK; + info->used = info->total - info->free; + GC_EXIT(); +} + #if MICROPY_PY_WEAKREF // Mark the GC heap pointer as having a weakref. void gc_weakref_mark(void *ptr) { diff --git a/py/gc.h b/py/gc.h index 4679d6dc863..ca73685d947 100644 --- a/py/gc.h +++ b/py/gc.h @@ -86,6 +86,7 @@ typedef struct _gc_info_t { } gc_info_t; void gc_info(gc_info_t *info); +void gc_info_fast(gc_info_t *info); void gc_dump_info(const mp_print_t *print); void gc_dump_alloc_table(const mp_print_t *print); From 936596c28a3b6a98c8ff7d2d84693ccbe0de0213 Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Tue, 14 Apr 2026 09:24:13 +0200 Subject: [PATCH 094/635] tests/ports/unix: Add gc_info_fast test. Add gc_info_fast to coverage tests. Signed-off-by: iabdalkader --- ports/unix/coverage.c | 22 ++++++++++++++++++++++ tests/ports/unix/extra_coverage.py.exp | 2 ++ 2 files changed, 24 insertions(+) diff --git a/ports/unix/coverage.c b/ports/unix/coverage.c index ff944b2488c..b21de2a5eb6 100644 --- a/ports/unix/coverage.c +++ b/ports/unix/coverage.c @@ -276,6 +276,28 @@ static mp_obj_t extra_coverage(void) { // calling gc_nbytes with a non-heap pointer mp_printf(&mp_plat_print, "%d\n", (int)gc_nbytes(NULL)); + + // test gc_info_fast + void *p0 = gc_alloc(4, 0); + void *p1 = gc_alloc(4, 0); + void *p2 = gc_alloc(4, 0); + + // Create a hole + gc_free(p1); + + gc_info_t info_slow; + gc_info_t info_fast; + + gc_info(&info_slow); + gc_info_fast(&info_fast); + + // Free allocs + gc_free(p0); + gc_free(p2); + + // Should be equal + mp_printf(&mp_plat_print, "%d\n", info_slow.used == info_fast.used); + mp_printf(&mp_plat_print, "%d\n", info_slow.free == info_fast.free); } // GC initialisation and allocation stress test, to check the logic behind ALLOC_TABLE_GAP_BYTE diff --git a/tests/ports/unix/extra_coverage.py.exp b/tests/ports/unix/extra_coverage.py.exp index 75d885290c0..f856a9dcd2a 100644 --- a/tests/ports/unix/extra_coverage.py.exp +++ b/tests/ports/unix/extra_coverage.py.exp @@ -33,6 +33,8 @@ abc # GC 0 0 +1 +1 # GC part 2 pass # tracked allocation From af78a82979b85d6062775444e73dbc41301a364e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Tue, 3 Feb 2026 18:23:28 +0100 Subject: [PATCH 095/635] zephyr/zephyr_filesystem: Fail chdir if path is not a dir. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fail chdir if path is not a dir. Signed-off-by: Fin Maaß --- ports/zephyr/zephyr_filesystem.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ports/zephyr/zephyr_filesystem.c b/ports/zephyr/zephyr_filesystem.c index 2ca72625355..9b0134e7e1e 100644 --- a/ports/zephyr/zephyr_filesystem.c +++ b/ports/zephyr/zephyr_filesystem.c @@ -453,6 +453,10 @@ static mp_obj_t zephyr_fs_chdir(mp_obj_t vfs_in, mp_obj_t path_in) { return mp_const_none; } + if (stats.type != FS_DIR_ENTRY_DIR) { + mp_raise_OSError(MP_ENOTDIR); + } + vstr_reset(&self->cur_dir); vstr_add_strn(&self->cur_dir, chdir.buf, lc); From 8752c81af7a5bb475e8146b06ba0244b7f735509 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Tue, 3 Feb 2026 18:26:34 +0100 Subject: [PATCH 096/635] zephyr/zephyr_filesystem: Handle trailing dot in path. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the trailing dot if it exists, as zephyr doesn't handle it. Signed-off-by: Fin Maaß --- ports/zephyr/zephyr_filesystem.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/ports/zephyr/zephyr_filesystem.c b/ports/zephyr/zephyr_filesystem.c index 9b0134e7e1e..3e68db12c62 100644 --- a/ports/zephyr/zephyr_filesystem.c +++ b/ports/zephyr/zephyr_filesystem.c @@ -71,21 +71,25 @@ typedef struct _zephyr_fs_obj_t { const char *zephyr_fs_make_path(zephyr_fs_obj_t *self, mp_obj_t path_in) { const char *path = mp_obj_str_get_str(path_in); + size_t path_len = strlen(path); + size_t l = vstr_len(&self->root_dir); if (path[0] != '/') { - size_t l = vstr_len(&self->root_dir); size_t lc = vstr_len(&self->cur_dir); vstr_add_str(&self->root_dir, "/"); vstr_add_strn(&self->root_dir, self->cur_dir.buf, lc); - vstr_add_str(&self->root_dir, path); - path = vstr_null_terminated_str(&self->root_dir); - self->root_dir.len = l; - } else { - size_t l = vstr_len(&self->root_dir); - vstr_add_str(&self->root_dir, path); - path = vstr_null_terminated_str(&self->root_dir); - self->root_dir.len = l; } + + if (path_len > 0 && + (path[path_len - 1] == '.' && (path_len == 1 || path[path_len - 2] == '/'))) { + // if path ends with '/.', remove the trailing dot + path_len--; + } + + vstr_add_strn(&self->root_dir, path, path_len); + path = vstr_null_terminated_str(&self->root_dir); + self->root_dir.len = l; + return path; } From 8c8fdd8e4faf593ebbdc40fa0c0073d5edd57f84 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Tue, 3 Feb 2026 18:28:40 +0100 Subject: [PATCH 097/635] zephyr/zephyr_filesystem: Don't mount automounted node again. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't unmount automounted node before mounting it again. Instead do nothing. Signed-off-by: Fin Maaß --- ports/zephyr/zephyr_filesystem.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/ports/zephyr/zephyr_filesystem.c b/ports/zephyr/zephyr_filesystem.c index 3e68db12c62..da8a48d3168 100644 --- a/ports/zephyr/zephyr_filesystem.c +++ b/ports/zephyr/zephyr_filesystem.c @@ -657,19 +657,25 @@ static MP_DEFINE_CONST_FUN_OBJ_1(zephyr_fs_umount_obj, zephyr_fs_umount); static mp_obj_t zephyr_fs_mount(mp_obj_t self_in, mp_obj_t readonly, mp_obj_t mkfs) { zephyr_fs_obj_t *self = MP_OBJ_TO_PTR(self_in); + struct fs_mount_t *mount = self->mount; int err; (void)readonly; (void)mkfs; - err = fs_mount(self->mount); + if (sys_dnode_is_linked(&mount->node) && (mount->flags & FS_MOUNT_FLAG_AUTOMOUNT) != 0) { + // Already mounted with automount, nothing to do + return mp_const_none; + } + + err = fs_mount(mount); if (err == -EBUSY) { - err = fs_unmount(self->mount); + err = fs_unmount(mount); if (err < 0) { mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("error un-mounting Zephyr File System: %q"), mp_errno_to_str(MP_OBJ_NEW_SMALL_INT(-err))); return mp_const_none; } - err = fs_mount(self->mount); + err = fs_mount(mount); } if (err == -EROFS) { From 92b1fcffbac9ee37aa8be6c76d77419971c8f7fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 4 Feb 2026 18:00:49 +0100 Subject: [PATCH 098/635] zephyr/modules: Refactor flash functions in `_boot.py`. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refactor flash functions in `_boot.py`. Also handle case in `create_flash_partition` when VfsLfs2 is not enabled and therefore not being a attribute of vfs. Signed-off-by: Fin Maaß --- ports/zephyr/modules/_boot.py | 49 +++++++++++++++++------------------ 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/ports/zephyr/modules/_boot.py b/ports/zephyr/modules/_boot.py index ab3ed9c6340..f7d7a5b126d 100644 --- a/ports/zephyr/modules/_boot.py +++ b/ports/zephyr/modules/_boot.py @@ -25,23 +25,21 @@ def mount_filesystem_flash(): and mount it on /flash. Return True if successful, False otherwise. """ - if _FLASH in FileSystem.fstab(): - fs = FileSystem(_FLASH) - retval = True + if _FLASH not in FileSystem.fstab(): + return False + fs = FileSystem(_FLASH) + try: + vfs.mount(fs, _FLASH) + except OSError: + if not hasattr(fs, "mkfs"): + return False try: + fs.mkfs() vfs.mount(fs, _FLASH) except OSError: - if getattr(fs, "mkfs", None): - try: - fs.mkfs() - vfs.mount(fs, _FLASH) - except OSError: - print("Error formatting flash partition") - retval = False - else: - retval = False - return retval - return False + print("Error formatting flash partition") + return False + return True def create_flash_partition(): @@ -49,20 +47,21 @@ def create_flash_partition(): and mount it on /flash. Return True if successful, False otherwise. """ - if _STORAGE_KEY in FlashArea.areas: - bdev = FlashArea(*FlashArea.areas[_STORAGE_KEY]) - retval = True + if _STORAGE_KEY not in FlashArea.areas: + return False + bdev = FlashArea(*FlashArea.areas[_STORAGE_KEY]) + try: + vfs.mount(bdev, _FLASH) + except OSError: + if not hasattr(vfs, "VfsLfs2"): + return False try: + vfs.VfsLfs2.mkfs(bdev) vfs.mount(bdev, _FLASH) except OSError: - try: - vfs.VfsLfs2.mkfs(bdev) - vfs.mount(bdev, _FLASH) - except OSError: - print("Error formatting flash partition") - retval = False - return retval - return False + print("Error formatting flash partition") + return False + return True def mount_all_disks(): From 0e22f5547e7a2b7433ab66f8d44954351c0d600a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 4 Feb 2026 18:04:47 +0100 Subject: [PATCH 099/635] zephyr/modules: Mount all zephyr filesystems in `_boot.py`. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mount all zephyr filesystems in `_boot.py` and not just `/flash`. Prefer them to `DiskAccess`, as they could be in both. Signed-off-by: Fin Maaß --- ports/zephyr/modules/_boot.py | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/ports/zephyr/modules/_boot.py b/ports/zephyr/modules/_boot.py index f7d7a5b126d..6671c103775 100644 --- a/ports/zephyr/modules/_boot.py +++ b/ports/zephyr/modules/_boot.py @@ -18,6 +18,7 @@ _FLASH_LIB = const("/flash/lib") _STORAGE_KEY = const("storage") _FLASH_EXISTS = False +_FS_EXISTS = False def mount_filesystem_flash(): @@ -64,6 +65,25 @@ def create_flash_partition(): return True +def mount_all_filesystems(): + """Mount all filesystems excluding "/flash" + Return True if successful, False otherwise. + """ + retval = False + for fs_str in FileSystem.fstab(): + if fs_str == _FLASH: + continue + fs = FileSystem(fs_str) + try: + vfs.mount(fs, fs_str) + sys.path.append(f"{fs_str}/lib") + os.chdir(fs_str) + retval = True + except OSError as e: + print(f"Error mounting {fs_str}: {e}") + return retval + + def mount_all_disks(): """Now mount all the DiskAreas (if any).""" retval = False @@ -81,13 +101,16 @@ def mount_all_disks(): # Prefer FileSystem over FlashArea Access +if FileSystem and mount_all_filesystems(): + _FS_EXISTS = True if FileSystem and mount_filesystem_flash(): _FLASH_EXISTS = True elif FlashArea and create_flash_partition(): _FLASH_EXISTS = True +# Prefer filesystems (excluding /flash) to disks # Prefer disks to /flash -if not (DiskAccess and mount_all_disks()): +if not (_FS_EXISTS or (DiskAccess and mount_all_disks())): if _FLASH_EXISTS: os.chdir(_FLASH) @@ -98,4 +121,5 @@ def mount_all_disks(): # Cleanup globals for boot.py/main.py del FlashArea, DiskAccess, FileSystem, zephyr del sys, vfs, os, const -del mount_filesystem_flash, create_flash_partition, mount_all_disks, _FLASH_EXISTS +del mount_filesystem_flash, create_flash_partition, mount_all_disks, mount_all_filesystems +del _FLASH_EXISTS, _FS_EXISTS From 83f7d7881b658527269f653549937616d6a126c1 Mon Sep 17 00:00:00 2001 From: Antonio Galea Date: Mon, 13 Apr 2026 11:56:30 +0200 Subject: [PATCH 100/635] zephyr/mphalport: Add mp_hal_get_random. This is a very simple `mp_hal_get_random()` leveraging cryptographically secure RNG, if available. Signed-off-by: Antonio Galea --- ports/zephyr/mphalport.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/ports/zephyr/mphalport.h b/ports/zephyr/mphalport.h index dc3ee33558f..ddbdba44e3e 100644 --- a/ports/zephyr/mphalport.h +++ b/ports/zephyr/mphalport.h @@ -1,5 +1,6 @@ #include #include +#include #include "shared/runtime/interrupt_char.h" #define MICROPY_BEGIN_ATOMIC_SECTION irq_lock @@ -93,3 +94,9 @@ static inline void mp_hal_pin_od_low(mp_hal_pin_obj_t pin) { static inline void mp_hal_pin_od_high(mp_hal_pin_obj_t pin) { (void)gpio_pin_set_raw(pin->port, pin->pin, 1); } + +#if CONFIG_HARDWARE_DEVICE_CS_GENERATOR || CONFIG_PSA_CSPRNG_GENERATOR +static inline void mp_hal_get_random(size_t n, uint8_t *buf) { + sys_csrand_get(buf, n); +} +#endif From 394976c5a94d12678ef2676b5b9cb3205ad17eda Mon Sep 17 00:00:00 2001 From: Antonio Galea Date: Mon, 4 May 2026 11:41:36 +0200 Subject: [PATCH 101/635] zephyr/mpconfigport: Auto enable MICROPY_PY_OS_URANDOM when possible. Signed-off-by: Antonio Galea --- ports/zephyr/mpconfigport.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ports/zephyr/mpconfigport.h b/ports/zephyr/mpconfigport.h index 7fc5196ec30..d40668481af 100644 --- a/ports/zephyr/mpconfigport.h +++ b/ports/zephyr/mpconfigport.h @@ -112,6 +112,9 @@ #define MICROPY_PY_BINASCII (1) #define MICROPY_PY_HASHLIB (1) #define MICROPY_PY_OS (1) +#if CONFIG_HARDWARE_DEVICE_CS_GENERATOR || CONFIG_PSA_CSPRNG_GENERATOR +#define MICROPY_PY_OS_URANDOM (1) +#endif #define MICROPY_PY_TIME_TIME_TIME_NS (1) #define MICROPY_PY_TIME_INCLUDEFILE "ports/zephyr/modtime.c" #define MICROPY_PY_ZEPHYR (1) From d7de8ee64c44b627b92da2d42ebe2f282564eb85 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Apr 2026 12:20:54 +1000 Subject: [PATCH 102/635] zephyr/modbluetooth_zephyr: Use BT_LE_ADV_OPT_CONN for connection flag. Changed in zephyr commit e24d3b92a3a2b016d932d075fad0b2d9e1922f22, the only option for connectable advertising is now BT_LE_ADV_OPT_CONN, whose value is _BT_LE_ADV_OPT_CONNECTABLE|_BT_LE_ADV_OPT_ONE_TIME. Signed-off-by: Damien George --- ports/zephyr/modbluetooth_zephyr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/ports/zephyr/modbluetooth_zephyr.c b/ports/zephyr/modbluetooth_zephyr.c index c1b8ddfd8b4..debc3b638be 100644 --- a/ports/zephyr/modbluetooth_zephyr.c +++ b/ports/zephyr/modbluetooth_zephyr.c @@ -409,8 +409,7 @@ int mp_bluetooth_gap_advertise_start(bool connectable, int32_t interval_us, cons .id = 0, .sid = 0, .secondary_max_skip = 0, - .options = (connectable ? BT_LE_ADV_OPT_CONNECTABLE : 0) - | BT_LE_ADV_OPT_ONE_TIME + .options = (connectable ? BT_LE_ADV_OPT_CONN : 0) | BT_LE_ADV_OPT_USE_IDENTITY | BT_LE_ADV_OPT_SCANNABLE, .interval_min = interval_us / 625, From a22b55b8d2cdfcbae29a45bebbd6ae2521b889de Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Apr 2026 12:23:08 +1000 Subject: [PATCH 103/635] zephyr/boards/nucleo_wb55rg: Remove scratch_partition deletion. It was removed in zephyr commit b348fd4d7a6ba92aa45ae8d96ad018c0e0cf11db. Signed-off-by: Damien George --- ports/zephyr/boards/nucleo_wb55rg.overlay | 1 - 1 file changed, 1 deletion(-) diff --git a/ports/zephyr/boards/nucleo_wb55rg.overlay b/ports/zephyr/boards/nucleo_wb55rg.overlay index d9a4d3f24c5..7f14439882e 100644 --- a/ports/zephyr/boards/nucleo_wb55rg.overlay +++ b/ports/zephyr/boards/nucleo_wb55rg.overlay @@ -6,7 +6,6 @@ /* Delete the defined partitions and create bigger one for storage. */ /delete-node/ &slot1_partition; -/delete-node/ &scratch_partition; /delete-node/ &storage_partition; &flash0 { partitions { From ca29431e9a357db27b83052de9e122f43a8ba8aa Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Apr 2026 12:24:17 +1000 Subject: [PATCH 104/635] zephyr/boards/qemu_x86: Enable CONFIG_X86_SSE2 for _Float16 use. Otherwise there is a compiler error. Likely due to the update to use zephyr SDK 1.0.1. Signed-off-by: Damien George --- ports/zephyr/boards/qemu_x86.conf | 3 +++ tools/ci.sh | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/ports/zephyr/boards/qemu_x86.conf b/ports/zephyr/boards/qemu_x86.conf index 1d04675df41..2012cb45930 100644 --- a/ports/zephyr/boards/qemu_x86.conf +++ b/ports/zephyr/boards/qemu_x86.conf @@ -5,3 +5,6 @@ CONFIG_NET_SLIP_TAP=y # QEMU doesn't have a watchdog, so disable it CONFIG_WATCHDOG=n CONFIG_WDT_DISABLE_AT_BOOT=n + +# x86 Features, needed for _Float16 +CONFIG_X86_SSE2=y diff --git a/tools/ci.sh b/tools/ci.sh index b1c71d195b7..623af339caf 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -1043,7 +1043,7 @@ function ci_zephyr_install { function ci_zephyr_build { git submodule update --init lib/micropython-lib - docker exec zephyr-ci west build -p auto -b qemu_x86 -- -DCONF_FILE=prj_minimal.conf + docker exec zephyr-ci west build -p auto -b qemu_x86 -- -DCONF_FILE='prj_minimal.conf;boards/qemu_x86.conf' docker exec zephyr-ci west build -p auto -b frdm_k64f docker exec zephyr-ci west build -p auto -b mimxrt1050_evk docker exec zephyr-ci west build -p auto -b nucleo_wb55rg # for bluetooth From 87da5062eb0dc43f70e0bcb98848675cba7e1f43 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Apr 2026 12:25:46 +1000 Subject: [PATCH 105/635] zephyr/prj_minimal.conf: Enable CONFIG_UART_CONSOLE_DEBUG_SERVER_HOOKS. To be consistent with the setting in `prj.conf`, so that the function `uart_console_in_debug_hook_install()` is enabled. Signed-off-by: Damien George --- ports/zephyr/prj_minimal.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/ports/zephyr/prj_minimal.conf b/ports/zephyr/prj_minimal.conf index 6fb5eadd5b6..9155c45d86a 100644 --- a/ports/zephyr/prj_minimal.conf +++ b/ports/zephyr/prj_minimal.conf @@ -3,6 +3,7 @@ CONFIG_MAIN_STACK_SIZE=4096 CONFIG_POLL=y CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE_DEBUG_SERVER_HOOKS=y CONFIG_CONSOLE_SUBSYS=y CONFIG_CONSOLE_GETCHAR=y CONFIG_CONSOLE_GETCHAR_BUFSIZE=258 From 0715bec0639ccc58815814545055f033b1693a9d Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Apr 2026 12:27:55 +1000 Subject: [PATCH 106/635] zephyr: Upgrade to Zephyr v4.4.0. Updates the Zephyr port build instructions and CI to use the latest Zephyr release tag. Tested on frdm_k64f and nucleo_wb55rg. Signed-off-by: Damien George --- docs/zephyr/tutorial/repl.rst | 4 ++-- ports/zephyr/README.md | 16 ++++++++-------- tools/ci.sh | 8 ++++---- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/docs/zephyr/tutorial/repl.rst b/docs/zephyr/tutorial/repl.rst index 1b16c5ad21d..cb90ca86ec6 100644 --- a/docs/zephyr/tutorial/repl.rst +++ b/docs/zephyr/tutorial/repl.rst @@ -31,8 +31,8 @@ With your serial program open (PuTTY, screen, picocom, etc) you may see a blank screen with a flashing cursor. Press Enter (or reset the board) and you should be presented with the following text:: - *** Booting Zephyr OS build v4.2.0 *** - MicroPython v1.26.0-preview.451.gebc9525c9 on 2025-07-25; zephyr-frdm_k64f with mk64f12 + *** Booting Zephyr OS build v4.4.0 *** + MicroPython v1.29.0-preview.69.g8a56be6660 on 2026-04-27; zephyr-frdm_k64f with mk64f12 Type "help()" for more information. >>> diff --git a/ports/zephyr/README.md b/ports/zephyr/README.md index be5e322ca55..238c5882191 100644 --- a/ports/zephyr/README.md +++ b/ports/zephyr/README.md @@ -5,8 +5,8 @@ This is a work-in-progress port of MicroPython to Zephyr RTOS (http://zephyrproject.org). This port tries to support all Zephyr versions supported upstream, -i.e. currently v3.7 (LTS), v4.2 and the development branch. The CI is -setup to use the latest version, i.e. v4.2. +i.e. currently v3.7 (LTS), v4.4 and the development branch. The CI is +setup to use the latest version, i.e. v4.4. All boards supported by Zephyr (with standard level of features support, like UART console) should work with MicroPython (but not all @@ -35,23 +35,23 @@ Over time, bindings for various Zephyr subsystems may be added. Building -------- -Follow to Zephyr web site for Getting Started instruction of installing -Zephyr SDK, getting Zephyr source code, and setting up development -environment. (Direct link: -https://docs.zephyrproject.org/latest/getting_started/index.html). +Follow the Zephyr website's +[Getting Started Guide](https://docs.zephyrproject.org/latest/develop/getting_started/index.html) +for installing the Zephyr SDK, getting Zephyr source code, and setting +up a development environment. You may want to build Zephyr's own sample applications to make sure your setup is correct. If you already have Zephyr installed but are having issues building the MicroPython port then try installing the correct version of Zephyr via: - $ west init zephyrproject -m https://github.com/zephyrproject-rtos/zephyr --mr v4.2.0 + $ west init zephyrproject -m https://github.com/zephyrproject-rtos/zephyr --mr v4.4.0 Alternatively, you don't have to redo the Zephyr installation to just switch from master to a tagged release, you can instead do: $ cd zephyrproject/zephyr - $ git checkout v4.2.0 + $ git checkout v4.4.0 $ west update With Zephyr installed you may then need to configure your environment, diff --git a/tools/ci.sh b/tools/ci.sh index 623af339caf..fbdec9c3a88 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -1001,9 +1001,9 @@ function ci_windows_build { ######################################################################################## # ports/zephyr -ZEPHYR_DOCKER_VERSION=v0.28.1 -ZEPHYR_SDK_VERSION=0.17.2 -ZEPHYR_VERSION=v4.2.0 +ZEPHYR_DOCKER_VERSION=v0.29.2 +ZEPHYR_SDK_VERSION=1.0.1 +ZEPHYR_VERSION=v4.4.0 function ci_zephyr_setup { IMAGE=ghcr.io/zephyrproject-rtos/ci:${ZEPHYR_DOCKER_VERSION} @@ -1045,7 +1045,7 @@ function ci_zephyr_build { git submodule update --init lib/micropython-lib docker exec zephyr-ci west build -p auto -b qemu_x86 -- -DCONF_FILE='prj_minimal.conf;boards/qemu_x86.conf' docker exec zephyr-ci west build -p auto -b frdm_k64f - docker exec zephyr-ci west build -p auto -b mimxrt1050_evk + docker exec zephyr-ci west build -p auto -b mimxrt1050_evk/mimxrt1052/qspi docker exec zephyr-ci west build -p auto -b nucleo_wb55rg # for bluetooth } From d3a7b5a51a1284161782994ad5e5948ee441d2de Mon Sep 17 00:00:00 2001 From: Vdragon Date: Sun, 3 May 2026 19:31:26 +0200 Subject: [PATCH 107/635] zephyr/mphalport: Provide MP_HAL_CLEAN_DCACHE. Provide function to clean dcache in emitglue. Signed-off-by: Vdragon --- ports/zephyr/mphalport.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/ports/zephyr/mphalport.h b/ports/zephyr/mphalport.h index ddbdba44e3e..e835598aa25 100644 --- a/ports/zephyr/mphalport.h +++ b/ports/zephyr/mphalport.h @@ -1,6 +1,7 @@ #include #include #include +#include #include "shared/runtime/interrupt_char.h" #define MICROPY_BEGIN_ATOMIC_SECTION irq_lock @@ -95,6 +96,14 @@ static inline void mp_hal_pin_od_high(mp_hal_pin_obj_t pin) { (void)gpio_pin_set_raw(pin->port, pin->pin, 1); } +// Provide cache clean when possible. +#ifdef CONFIG_CACHE_MANAGEMENT +#define MP_HAL_CLEAN_DCACHE(fun_data, fun_len) \ + if (sys_cache_data_flush_and_invd_range((void *)fun_data, fun_len) != 0) { \ + sys_cache_data_flush_and_invd_all(); \ + } +#endif + #if CONFIG_HARDWARE_DEVICE_CS_GENERATOR || CONFIG_PSA_CSPRNG_GENERATOR static inline void mp_hal_get_random(size_t n, uint8_t *buf) { sys_csrand_get(buf, n); From 20fc2efb718c7e9221f2befab2370d5ecf65e209 Mon Sep 17 00:00:00 2001 From: Vdragon Date: Sun, 3 May 2026 19:59:30 +0200 Subject: [PATCH 108/635] zephyr/boards: Update and fix Bouffalolab boards. Fix UART missing character at output, enable newly supported features. Signed-off-by: Vdragon --- ports/zephyr/boards/ai_m61_32s_kit.conf | 33 ++++++++++++++++++++-- ports/zephyr/boards/ai_m61_32s_kit.overlay | 6 +++- ports/zephyr/boards/ai_m62_12f_kit.conf | 33 ++++++++++++++++++++-- ports/zephyr/boards/ai_m62_12f_kit.overlay | 6 +++- ports/zephyr/boards/ai_wb2_12f_kit.conf | 33 ++++++++++++++++++++-- ports/zephyr/boards/ai_wb2_12f_kit.overlay | 4 +++ ports/zephyr/boards/bflb/manifest.py | 8 ++++++ 7 files changed, 112 insertions(+), 11 deletions(-) create mode 100644 ports/zephyr/boards/bflb/manifest.py diff --git a/ports/zephyr/boards/ai_m61_32s_kit.conf b/ports/zephyr/boards/ai_m61_32s_kit.conf index e99a379fde7..5d0a1893384 100644 --- a/ports/zephyr/boards/ai_m61_32s_kit.conf +++ b/ports/zephyr/boards/ai_m61_32s_kit.conf @@ -1,23 +1,28 @@ # Hardware features. CONFIG_PINCTRL=y CONFIG_GPIO=y -CONFIG_WATCHDOG=n +CONFIG_WATCHDOG=y CONFIG_CONSOLE_SUBSYS=y CONFIG_CONSOLE_GETCHAR=y -CONFIG_CONSOLE_GETCHAR_BUFSIZE=256 +CONFIG_CONSOLE_GETCHAR_BUFSIZE=1024 +CONFIG_CONSOLE_PUTCHAR_BUFSIZE=1024 CONFIG_I2C=y CONFIG_I2C_TARGET=y CONFIG_SPI=y CONFIG_MEMC=y +CONFIG_ENTROPY_GENERATOR=y # Disable networking. CONFIG_NETWORKING=n # MicroPython config. -CONFIG_MICROPY_HEAP_SIZE=262144 +CONFIG_MICROPY_HEAP_SIZE=196608 CONFIG_MAIN_STACK_SIZE=16384 CONFIG_MICROPY_CONFIG_ROM_LEVEL_FULL_FEATURES=y +CONFIG_MICROPY_FROZEN_MANIFEST="boards/bflb/manifest.py" +# Threads +CONFIG_THREAD_CUSTOM_DATA=y # File System Configuration CONFIG_FLASH=y @@ -30,3 +35,25 @@ CONFIG_MICROPY_VFS_LFS1=n CONFIG_MICROPY_VFS_LFS2=n # Default heap for littlefs is too small CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=8192 + +# Bluetooth +CONFIG_BT=y +CONFIG_BT_DEVICE_NAME_DYNAMIC=y +CONFIG_BT_DEVICE_APPEARANCE_DYNAMIC=y +CONFIG_BT_GATT_DYNAMIC_DB=y +CONFIG_BT_PERIPHERAL=y +CONFIG_BT_CENTRAL=y +CONFIG_BT_GATT_CLIENT=y +CONFIG_BT_GATT_ENFORCE_SUBSCRIPTION=n +CONFIG_BT_DIS=y +CONFIG_BT_DIS_PNP=n +CONFIG_BT_SMP=y +CONFIG_BT_BUF_ACL_RX_SIZE=672 +CONFIG_BT_BUF_ACL_TX_SIZE=672 +CONFIG_BT_L2CAP_TX_MTU=672 +CONFIG_BT_BUF_CMD_TX_SIZE=255 +CONFIG_BT_PERIPHERAL_PREF_MIN_INT=6 +CONFIG_BT_HCI_TX_STACK_SIZE=2048 +CONFIG_BT_RX_STACK_SIZE=4096 +CONFIG_BT_BUF_ACL_TX_COUNT=8 +CONFIG_BT_BUF_EVT_RX_COUNT=16 diff --git a/ports/zephyr/boards/ai_m61_32s_kit.overlay b/ports/zephyr/boards/ai_m61_32s_kit.overlay index 59e9f3ad696..edce5d20e28 100644 --- a/ports/zephyr/boards/ai_m61_32s_kit.overlay +++ b/ports/zephyr/boards/ai_m61_32s_kit.overlay @@ -21,7 +21,7 @@ heap_sram1 { compatible = "micropython,heap"; - size = ; + size = ; memory-region = <&sram1>; }; @@ -31,3 +31,7 @@ memory-region = <&psram>; }; }; + +&wdt0 { + status = "okay"; +}; diff --git a/ports/zephyr/boards/ai_m62_12f_kit.conf b/ports/zephyr/boards/ai_m62_12f_kit.conf index aa4c7c6b35b..aed79be69fe 100644 --- a/ports/zephyr/boards/ai_m62_12f_kit.conf +++ b/ports/zephyr/boards/ai_m62_12f_kit.conf @@ -1,22 +1,27 @@ # Hardware features. CONFIG_PINCTRL=y CONFIG_GPIO=y -CONFIG_WATCHDOG=n +CONFIG_WATCHDOG=y CONFIG_CONSOLE_SUBSYS=y CONFIG_CONSOLE_GETCHAR=y -CONFIG_CONSOLE_GETCHAR_BUFSIZE=256 +CONFIG_CONSOLE_GETCHAR_BUFSIZE=1024 +CONFIG_CONSOLE_PUTCHAR_BUFSIZE=1024 CONFIG_I2C=y CONFIG_I2C_TARGET=y CONFIG_SPI=y +CONFIG_ENTROPY_GENERATOR=y # Disable networking. CONFIG_NETWORKING=n # MicroPython config. -CONFIG_MICROPY_HEAP_SIZE=262144 +CONFIG_MICROPY_HEAP_SIZE=196608 CONFIG_MAIN_STACK_SIZE=16384 CONFIG_MICROPY_CONFIG_ROM_LEVEL_FULL_FEATURES=y +CONFIG_MICROPY_FROZEN_MANIFEST="boards/bflb/manifest.py" +# Threads +CONFIG_THREAD_CUSTOM_DATA=y # File System Configuration CONFIG_FLASH=y @@ -29,3 +34,25 @@ CONFIG_MICROPY_VFS_LFS1=n CONFIG_MICROPY_VFS_LFS2=n # Default heap for littlefs is too small CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=8192 + +# Bluetooth +CONFIG_BT=y +CONFIG_BT_DEVICE_NAME_DYNAMIC=y +CONFIG_BT_DEVICE_APPEARANCE_DYNAMIC=y +CONFIG_BT_GATT_DYNAMIC_DB=y +CONFIG_BT_PERIPHERAL=y +CONFIG_BT_CENTRAL=y +CONFIG_BT_GATT_CLIENT=y +CONFIG_BT_GATT_ENFORCE_SUBSCRIPTION=n +CONFIG_BT_DIS=y +CONFIG_BT_DIS_PNP=n +CONFIG_BT_SMP=y +CONFIG_BT_BUF_ACL_RX_SIZE=672 +CONFIG_BT_BUF_ACL_TX_SIZE=672 +CONFIG_BT_L2CAP_TX_MTU=672 +CONFIG_BT_BUF_CMD_TX_SIZE=255 +CONFIG_BT_PERIPHERAL_PREF_MIN_INT=6 +CONFIG_BT_HCI_TX_STACK_SIZE=2048 +CONFIG_BT_RX_STACK_SIZE=4096 +CONFIG_BT_BUF_ACL_TX_COUNT=8 +CONFIG_BT_BUF_EVT_RX_COUNT=16 diff --git a/ports/zephyr/boards/ai_m62_12f_kit.overlay b/ports/zephyr/boards/ai_m62_12f_kit.overlay index 17cb2ffdc9d..a23aaa70aa0 100644 --- a/ports/zephyr/boards/ai_m62_12f_kit.overlay +++ b/ports/zephyr/boards/ai_m62_12f_kit.overlay @@ -21,7 +21,11 @@ heap_sram1 { compatible = "micropython,heap"; - size = ; + size = ; memory-region = <&sram1>; }; }; + +&wdt0 { + status = "okay"; +}; diff --git a/ports/zephyr/boards/ai_wb2_12f_kit.conf b/ports/zephyr/boards/ai_wb2_12f_kit.conf index 73ceb27bb71..b9301ec54d2 100644 --- a/ports/zephyr/boards/ai_wb2_12f_kit.conf +++ b/ports/zephyr/boards/ai_wb2_12f_kit.conf @@ -1,22 +1,27 @@ # Hardware features. CONFIG_PINCTRL=y CONFIG_GPIO=y -CONFIG_WATCHDOG=n +CONFIG_WATCHDOG=y CONFIG_CONSOLE_SUBSYS=y CONFIG_CONSOLE_GETCHAR=y -CONFIG_CONSOLE_GETCHAR_BUFSIZE=256 +CONFIG_CONSOLE_GETCHAR_BUFSIZE=1024 +CONFIG_CONSOLE_PUTCHAR_BUFSIZE=1024 CONFIG_I2C=y CONFIG_I2C_TARGET=y CONFIG_SPI=y +CONFIG_ENTROPY_GENERATOR=y # Disable networking. CONFIG_NETWORKING=n # MicroPython config. -CONFIG_MICROPY_HEAP_SIZE=131072 +CONFIG_MICROPY_HEAP_SIZE=32768 CONFIG_MAIN_STACK_SIZE=16384 CONFIG_MICROPY_CONFIG_ROM_LEVEL_FULL_FEATURES=y +CONFIG_MICROPY_FROZEN_MANIFEST="boards/bflb/manifest.py" +# Threads +CONFIG_THREAD_CUSTOM_DATA=y # File System Configuration CONFIG_FLASH=y @@ -29,3 +34,25 @@ CONFIG_MICROPY_VFS_LFS1=n CONFIG_MICROPY_VFS_LFS2=n # Default heap for littlefs is too small CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=8192 + +# Bluetooth +CONFIG_BT=y +CONFIG_BT_DEVICE_NAME_DYNAMIC=y +CONFIG_BT_DEVICE_APPEARANCE_DYNAMIC=y +CONFIG_BT_GATT_DYNAMIC_DB=y +CONFIG_BT_PERIPHERAL=y +CONFIG_BT_CENTRAL=y +CONFIG_BT_GATT_CLIENT=y +CONFIG_BT_GATT_ENFORCE_SUBSCRIPTION=n +CONFIG_BT_DIS=y +CONFIG_BT_DIS_PNP=n +CONFIG_BT_SMP=y +CONFIG_BT_BUF_ACL_RX_SIZE=672 +CONFIG_BT_BUF_ACL_TX_SIZE=672 +CONFIG_BT_L2CAP_TX_MTU=672 +CONFIG_BT_BUF_CMD_TX_SIZE=255 +CONFIG_BT_PERIPHERAL_PREF_MIN_INT=6 +CONFIG_BT_HCI_TX_STACK_SIZE=2048 +CONFIG_BT_RX_STACK_SIZE=4096 +CONFIG_BT_BUF_ACL_TX_COUNT=5 +CONFIG_BT_BUF_EVT_RX_COUNT=10 diff --git a/ports/zephyr/boards/ai_wb2_12f_kit.overlay b/ports/zephyr/boards/ai_wb2_12f_kit.overlay index e6e7fdd5141..f277b6cf6cb 100644 --- a/ports/zephyr/boards/ai_wb2_12f_kit.overlay +++ b/ports/zephyr/boards/ai_wb2_12f_kit.overlay @@ -25,3 +25,7 @@ memory-region = <&dtcm>; }; }; + +&wdt0 { + status = "okay"; +}; diff --git a/ports/zephyr/boards/bflb/manifest.py b/ports/zephyr/boards/bflb/manifest.py new file mode 100644 index 00000000000..a8f2c7ce39a --- /dev/null +++ b/ports/zephyr/boards/bflb/manifest.py @@ -0,0 +1,8 @@ +include("$(MPY_DIR)/extmod/asyncio") + +freeze("$(PORT_DIR)/modules") + +require("upysh") +require("aioble") +require("aiorepl") +require("utop") From f90e5d719de78ee428f7324cc3d04bd7b0ffb9bc Mon Sep 17 00:00:00 2001 From: Vdragon Date: Sun, 10 May 2026 04:35:10 +0200 Subject: [PATCH 109/635] zephyr/uart_core: Give a little bit of time to putchar. Allow putchar to wait a little as sometimes the CPU is very significantly faster than the UART. Signed-off-by: Vdragon --- ports/zephyr/uart_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/zephyr/uart_core.c b/ports/zephyr/uart_core.c index 0c1c5c1e00d..db87821c735 100644 --- a/ports/zephyr/uart_core.c +++ b/ports/zephyr/uart_core.c @@ -140,7 +140,7 @@ int mp_console_init(void) { tty_set_rx_buf(&mp_console_serial, mp_console_rxbuf, sizeof(mp_console_rxbuf)); tty_set_rx_timeout(&mp_console_serial, 0); - tty_set_tx_timeout(&mp_console_serial, 1); + tty_set_tx_timeout(&mp_console_serial, 2); return 0; } From 0abb3b3311d41b3d3b24be44470f70cb6ed94535 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 21 Jun 2025 22:44:26 +1000 Subject: [PATCH 110/635] shared/libc/string0: Add implementation of atoi needed by netif_find(). Signed-off-by: Andrew Leech --- shared/libc/string0.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/shared/libc/string0.c b/shared/libc/string0.c index 3909f70ed80..ea774205c4e 100644 --- a/shared/libc/string0.c +++ b/shared/libc/string0.c @@ -259,3 +259,13 @@ size_t strcspn(const char *s, const char *reject) { } return s - ss; } + +// Decimal-only, non-negative integers; no leading whitespace handling. +// Marked weak so a libc-provided atoi() takes precedence if available. +__attribute__((weak)) int atoi(const char *num) { + int value = 0; + while (*num >= '0' && *num <= '9') { + value = value * 10 + (*num++ - '0'); + } + return value; +} From bf1369bf8c068506221798e5ff1d650bfe151523 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 24 Mar 2026 09:19:09 +1100 Subject: [PATCH 111/635] shared/netutils/dhcpserver: Add send_router flag. When false, the DHCP server omits the Router option from DHCP responses. This prevents point-to-point links (like USB NCM) from advertising a default gateway that hijacks the host's internet route. Defaults to true for backward compatibility with CYW43 AP mode. Signed-off-by: Andrew Leech --- shared/netutils/dhcpserver.c | 5 ++++- shared/netutils/dhcpserver.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/shared/netutils/dhcpserver.c b/shared/netutils/dhcpserver.c index 1c788ac1156..c54dad357a7 100644 --- a/shared/netutils/dhcpserver.c +++ b/shared/netutils/dhcpserver.c @@ -280,7 +280,9 @@ static void dhcp_server_process(void *arg, struct udp_pcb *upcb, struct pbuf *p, opt_write_n(&opt, DHCP_OPT_SERVER_ID, 4, &ip_2_ip4(&d->ip)->addr); opt_write_n(&opt, DHCP_OPT_SUBNET_MASK, 4, &ip_2_ip4(&d->nm)->addr); - opt_write_n(&opt, DHCP_OPT_ROUTER, 4, &ip_2_ip4(&d->ip)->addr); // aka gateway; can have multiple addresses + if (d->send_router) { + opt_write_n(&opt, DHCP_OPT_ROUTER, 4, &ip_2_ip4(&d->ip)->addr); // aka gateway; can have multiple addresses + } opt_write_n(&opt, DHCP_OPT_DNS, 4, &ip_2_ip4(&d->ip)->addr); opt_write_u32(&opt, DHCP_OPT_IP_LEASE_TIME, DEFAULT_LEASE_TIME_S); *opt++ = DHCP_OPT_END; @@ -295,6 +297,7 @@ void dhcp_server_init(dhcp_server_t *d, ip_addr_t *ip, ip_addr_t *nm) { ip_addr_copy(d->ip, *ip); ip_addr_copy(d->nm, *nm); memset(d->lease, 0, sizeof(d->lease)); + d->send_router = true; if (dhcp_socket_new_dgram(&d->udp, d, dhcp_server_process) != 0) { return; } diff --git a/shared/netutils/dhcpserver.h b/shared/netutils/dhcpserver.h index 2349d2ea427..24224d6aadd 100644 --- a/shared/netutils/dhcpserver.h +++ b/shared/netutils/dhcpserver.h @@ -41,6 +41,7 @@ typedef struct _dhcp_server_t { ip_addr_t nm; dhcp_server_lease_t lease[DHCPS_MAX_IP]; struct udp_pcb *udp; + bool send_router; // advertise server IP as default gateway } dhcp_server_t; void dhcp_server_init(dhcp_server_t *d, ip_addr_t *ip, ip_addr_t *nm); From 87a64037a6b83ee2807ddd8d3d6c3de90c62ae32 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 21 Jun 2025 22:45:25 +1000 Subject: [PATCH 112/635] stm32/lwip_inc: Remove redundant LWIP_IPV6=0 define. lwIP's own opt.h defaults LWIP_IPV6 to 0, so the explicit hardcoded define here was redundant and prevented overriding the value from elsewhere. Signed-off-by: Andrew Leech --- ports/stm32/lwip_inc/lwipopts.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/ports/stm32/lwip_inc/lwipopts.h b/ports/stm32/lwip_inc/lwipopts.h index 5711ba8944e..62b0dab4844 100644 --- a/ports/stm32/lwip_inc/lwipopts.h +++ b/ports/stm32/lwip_inc/lwipopts.h @@ -8,8 +8,6 @@ #define LWIP_LOOPIF_MULTICAST 1 #define LWIP_LOOPBACK_MAX_PBUFS 8 -#define LWIP_IPV6 0 - #define LWIP_RAND() rng_get() // Increase memory for lwIP to get better performance. @@ -22,7 +20,7 @@ #define MEMP_NUM_TCP_SEG (64) #endif -// Include common lwIP configuration. +// Include common lwIP configuration (also mpconfig.h). #include "extmod/lwip-include/lwipopts_common.h" extern uint32_t rng_get(void); From 7d77d3e0dd1b883ddf80ac163a5990d16f938cb6 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 21 Jun 2025 22:45:25 +1000 Subject: [PATCH 113/635] stm32/main: Init network stack before boot.py. So `boot.py` can call network.USB_NET() (for example) without hitting an uninitialised stack. Signed-off-by: Andrew Leech --- ports/stm32/main.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ports/stm32/main.c b/ports/stm32/main.c index 17111c6df98..6612d354701 100644 --- a/ports/stm32/main.c +++ b/ports/stm32/main.c @@ -608,6 +608,10 @@ void stm32_main(uint32_t reset_mode) { extint_init0(); timer_init0(); + #if MICROPY_PY_NETWORK + mod_network_init(); + #endif + #if MICROPY_HW_ENABLE_CAN pyb_can_init0(); #endif @@ -699,10 +703,6 @@ void stm32_main(uint32_t reset_mode) { servo_init(); #endif - #if MICROPY_PY_NETWORK - mod_network_init(); - #endif - // At this point everything is fully configured and initialised. // Run main.py (or whatever else a board configures at this stage). From dfdc71ffceb2ec2464c5d0421f169f42c198ebd2 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 25 Mar 2026 10:36:56 +1100 Subject: [PATCH 114/635] stm32: Fix case where initialising Classic CAN1 corrupts CAN2,3. - CAN1 init would clear all filters including CAN2 filter range. - CAN3 init would call can_clearfilter() with empty self->can values, the HAL layer interpreted this as clearing all CAN1 filters. To fix this clearing filter banks is moved to deinit, so they're already clean before the next init (they should be clear on initial init, due to peripheral reset). The only corner case is that if you initialise CAN1 and set too many filters, initialise CAN2, then some of the CAN1 filters may now apply to CAN2. However this would not have worked correctly in the current version either (the extra CAN1 filters would have been silently cleared). Includes expanded unit tests to cover arbitrary pairs of CAN instances. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/stm32/pyb_can.c | 35 ++++++-- tests/extmod_hardware/machine_can2.py | 44 --------- tests/extmod_hardware/machine_can2.py.exp | 5 -- .../extmod_hardware/machine_can_instances.py | 74 +++++++++++++++ tests/ports/stm32/pyb_can2.py | 50 ----------- tests/ports/stm32/pyb_can2.py.exp | 5 -- tests/ports/stm32/pyb_can_instances.py | 90 +++++++++++++++++++ 7 files changed, 193 insertions(+), 110 deletions(-) delete mode 100644 tests/extmod_hardware/machine_can2.py delete mode 100644 tests/extmod_hardware/machine_can2.py.exp create mode 100644 tests/extmod_hardware/machine_can_instances.py delete mode 100644 tests/ports/stm32/pyb_can2.py delete mode 100644 tests/ports/stm32/pyb_can2.py.exp create mode 100644 tests/ports/stm32/pyb_can_instances.py diff --git a/ports/stm32/pyb_can.c b/ports/stm32/pyb_can.c index 2d676b23d20..d60c3c42d4d 100644 --- a/ports/stm32/pyb_can.c +++ b/ports/stm32/pyb_can.c @@ -80,7 +80,7 @@ #endif #else -#define CAN_MAX_FILTER (28) +#define CAN_MAX_FILTER_CAN1_2 (28) // This limit is the max across CAN1+CAN2 shared indexing #define CAN_MAX_DATA_FRAME (8) #define CAN_DEFAULT_PRESCALER (100) @@ -232,12 +232,8 @@ static mp_obj_t pyb_can_init_helper(pyb_can_obj_t *self, size_t n_args, const mp self->can.Init.DataTimeSeg1 = args[ARG_brs_bs1].u_int; // DataTimeSeg1 = Propagation_segment + Phase_segment_1 self->can.Init.DataTimeSeg2 = args[ARG_brs_bs2].u_int; #else - // Init filter banks for classic CAN. + // set the can2_start_bank value can2_start_bank = args[ARG_num_filter_banks].u_int; - int bank_offs = (self->can_id == 2) ? can2_start_bank : 0; - for (int f = 0; f < CAN_MAX_FILTER; f++) { - can_clearfilter(&self->can, f + bank_offs, can2_start_bank); - } #endif mp_uint_t mode = args[ARG_mode].u_int; @@ -307,6 +303,33 @@ static MP_DEFINE_CONST_FUN_OBJ_KW(pyb_can_init_obj, 1, pyb_can_init); // deinit() static mp_obj_t pyb_can_deinit(mp_obj_t self_in) { pyb_can_obj_t *self = MP_OBJ_TO_PTR(self_in); + + #if !MICROPY_HW_ENABLE_FDCAN + // Clear filter banks for classic CAN, in case of re-init + int filter_min, filter_max; + switch (self->can_id) { + #ifdef MICROPY_HW_CAN3_NAME + case 3: // CAN3 filter numbering is independent of 1+2 + filter_min = 0; + filter_max = CAN_HW_MAX_FILTER; + break; + #endif + #ifdef MICROPY_HW_CAN2_NAME + case 2: // CAN2 filters run from can2_start_bank to the max + filter_min = can2_start_bank; + filter_max = CAN_MAX_FILTER_CAN1_2; + break; + #endif + default: // CAN1 filters run from 0 to can2_start_bank + filter_min = 0; + filter_max = can2_start_bank; + break; + } + for (int f = filter_min; f < filter_max; f++) { + can_clearfilter(&self->can, f, can2_start_bank); + } + #endif + can_deinit(&self->can); self->is_enabled = false; return mp_const_none; diff --git a/tests/extmod_hardware/machine_can2.py b/tests/extmod_hardware/machine_can2.py deleted file mode 100644 index 0ecced82865..00000000000 --- a/tests/extmod_hardware/machine_can2.py +++ /dev/null @@ -1,44 +0,0 @@ -# Test machine.CAN(1) and machine.CAN(2) using loopback -# -# Single device test, assumes support for loopback and no connections to the CAN pins -# -# This test is ported from tests/ports/stm32/pyb_can2.py - -try: - from machine import CAN - - CAN(2, 125_000) -except (ImportError, ValueError): - print("SKIP") - raise SystemExit - -import time - -# Setting up each CAN peripheral independently is deliberate here, to catch -# catch cases where initialising CAN2 breaks CAN1 - -can1 = CAN(1, 125_000, mode=CAN.MODE_LOOPBACK) -can1.set_filters([(0x100, 0x700, 0)]) - -can2 = CAN(2, 125_000, mode=CAN.MODE_LOOPBACK) -can2.set_filters([(0x000, 0x7F0, 0)]) - -# Drain any old messages in RX FIFOs -for can in (can1, can2): - while can.recv(): - pass - -for id, can in ((1, can1), (2, can2)): - print("testing", id) - # message1 should only receive on can1, message2 on can2 - can.send(0x123, b"message1", 0) - can.send(0x003, "message2", 0) - time.sleep_ms(10) - did_recv = False - while res := can.recv(): - did_recv = True - print(hex(res[0]), bytes(res[1]), res[2], res[3]) - if not did_recv: - print("no rx!") - -print("done") diff --git a/tests/extmod_hardware/machine_can2.py.exp b/tests/extmod_hardware/machine_can2.py.exp deleted file mode 100644 index bfb6a5088ba..00000000000 --- a/tests/extmod_hardware/machine_can2.py.exp +++ /dev/null @@ -1,5 +0,0 @@ -testing 1 -0x123 b'message1' 0 0 -testing 2 -0x3 b'message2' 0 0 -done diff --git a/tests/extmod_hardware/machine_can_instances.py b/tests/extmod_hardware/machine_can_instances.py new file mode 100644 index 00000000000..e280466e547 --- /dev/null +++ b/tests/extmod_hardware/machine_can_instances.py @@ -0,0 +1,74 @@ +# Test multiple concurrent CAN instances using loopback. +# Initialising in any order shouldn't break TX, RX or filtering. +# +# This test is ported from tests/ports/stm32/pyb_can_instances.py + +try: + from machine import CAN + + CAN(2, 125_000) # skip any board which doesn't have at least 2 CAN peripherals +except (ImportError, ValueError): + print("SKIP") + raise SystemExit + +import time +import unittest + +# Some boards have 3x CAN peripherals, test all three +HAS_CAN3 = True +try: + CAN(3, 125_000) +except ValueError: + HAS_CAN3 = False + + +class Test(unittest.TestCase): + def test_can12(self): + self._test_pairs([(1, 2), (2, 1)]) + + @unittest.skipUnless(HAS_CAN3, "no CAN3") + def test_can3(self): + self._test_pairs([(1, 3), (3, 1), (2, 3), (3, 2)]) + + def _test_pairs(self, seq): + for id_a, id_b in seq: + with self.subTest("Testing CAN pair", id_a=id_a, id_b=id_b): + self._test_controller_pair(id_a, id_b) + + def _test_controller_pair(self, id_a, id_b): + # Setting up each CAN peripheral independently is deliberate here, to catch + # catch cases where initialising CAN2 breaks CAN1 or vice versa + can_a = CAN(id_a, 125_000, mode=CAN.MODE_LOOPBACK) + can_a.set_filters([(0x100, 0x700, 0)]) + + can_b = CAN(id_b, 125_000, mode=CAN.MODE_LOOPBACK) + can_b.set_filters([(0x000, 0x7F0, 0)]) + + try: + # Drain any old messages in RX FIFOs + for can in (can_a, can_b): + while can.recv(): + pass + + for which, id, can in (("A", id_a, can_a), ("B", id_b, can_b)): + # print("testing config", which, "with controller", can) + # message1 should only receive on can_a, message2 on can_b + can.send(0x123, "message1", 0) + can.send(0x003, "message2", 0) + time.sleep_ms(10) + n_recv = 0 + while res := can.recv(): + n_recv += 1 + # print(res) + if can == can_a: + self.assertEqual(res[1], b"message1", "can_a should receive message1 only") + if can == can_b: + self.assertEqual(res[1], b"message2", "can_b should receive message2 only") + self.assertEqual(n_recv, 1, "Each instance should receive exactly 1 message") + finally: + can_a.deinit() + can_b.deinit() + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/ports/stm32/pyb_can2.py b/tests/ports/stm32/pyb_can2.py deleted file mode 100644 index 62ae935357c..00000000000 --- a/tests/ports/stm32/pyb_can2.py +++ /dev/null @@ -1,50 +0,0 @@ -try: - from pyb import CAN - - CAN(2) -except (ImportError, ValueError): - print("SKIP") - raise SystemExit - -# Classic CAN (aka bxCAN) hardware has a different filter API -# and some different behaviours to newer FDCAN hardware -IS_CLASSIC = hasattr(CAN, "MASK16") - -# Setting up each CAN peripheral independently is deliberate here, to catch -# catch cases where initialising CAN2 breaks CAN1 - -can1 = CAN(1, CAN.LOOPBACK) -if IS_CLASSIC: - can1.setfilter(0, CAN.LIST16, 0, (123, 124, 125, 126)) -else: - can1.setfilter(0, CAN.RANGE, 0, (123, 126)) - -can2 = CAN(2, CAN.LOOPBACK) -if IS_CLASSIC: - can2.setfilter(0, CAN.LIST16, 0, (3, 4, 5, 6)) -else: - can2.setfilter(0, CAN.RANGE, 0, (3, 6)) - -# Drain any old messages in RX FIFOs -for can in (can1, can2): - while can.any(0): - can.recv(0) - -for id, can in ((1, can1), (2, can2)): - print("testing", id) - # message1 should only receive on can1, message2 on can2 - can.send("message1", 123) - can.send("message2", 3) - did_recv = False - try: - while True: - res = can.recv(0, timeout=50) - # not printing all of 'res' as the filter index result is different - # on Classic vs FD-CAN - print("rx", res[0], res[4]) - did_recv = True - except OSError: - if not did_recv: - print("no rx!") - -print("done") diff --git a/tests/ports/stm32/pyb_can2.py.exp b/tests/ports/stm32/pyb_can2.py.exp deleted file mode 100644 index 9696f2fa010..00000000000 --- a/tests/ports/stm32/pyb_can2.py.exp +++ /dev/null @@ -1,5 +0,0 @@ -testing 1 -rx 123 b'message1' -testing 2 -rx 3 b'message2' -done diff --git a/tests/ports/stm32/pyb_can_instances.py b/tests/ports/stm32/pyb_can_instances.py new file mode 100644 index 00000000000..a5f6d3d8d5c --- /dev/null +++ b/tests/ports/stm32/pyb_can_instances.py @@ -0,0 +1,90 @@ +# Test that initialising CAN instances in any order doesn't break +# TX, RX or filtering +try: + from pyb import CAN + + CAN(2) # skip any board which doesn't have at least 2 CAN peripherals +except (ImportError, ValueError): + print("SKIP") + raise SystemExit + +import unittest +import errno + +# Classic CAN (aka bxCAN) hardware has a different filter API +# and some different behaviours to newer FDCAN hardware +IS_CLASSIC = hasattr(CAN, "MASK16") + +# Some boards have 3x CAN peripherals, test all three +HAS_CAN3 = True +try: + CAN(3) +except ValueError: + HAS_CAN3 = False + + +class Test(unittest.TestCase): + def test_can12(self): + self._test_pairs([(1, 2), (2, 1)]) + + @unittest.skipUnless(HAS_CAN3, "no CAN3") + def test_can3(self): + self._test_pairs([(1, 3), (3, 1), (2, 3), (3, 2)]) + + def _test_pairs(self, seq): + for id_a, id_b in seq: + with self.subTest("Testing CAN pair", id_a=id_a, id_b=id_b): + self._test_controller_pair(id_a, id_b) + + def _test_controller_pair(self, id_a, id_b): + # Setting up each CAN peripheral independently is deliberate here, to catch + # catch cases where initialising CAN2 breaks CAN1 or vice versa + try: + can_a = CAN(id_a, CAN.LOOPBACK) + if IS_CLASSIC: + can_a.setfilter(0, CAN.LIST16, 0, (123, 124, 125, 126)) + else: + can_a.setfilter(0, CAN.RANGE, 0, (123, 126)) + + can_b = CAN(id_b, CAN.LOOPBACK) + if IS_CLASSIC: + can_b.setfilter(0, CAN.LIST16, 0, (3, 4, 5, 6)) + else: + can_b.setfilter(0, CAN.RANGE, 0, (3, 6)) + + # Drain any old messages in RX FIFOs + for can in (can_a, can_b): + while can.any(0): + can.recv(0) + + for which, id, can in (("A", id_a, can_a), ("B", id_b, can_b)): + print("testing config", which, "with controller", can) + # message1 should only receive on can_a, message2 on can_b + can.send("message1", 123) + can.send("message2", 3) + n_recv = 0 + try: + while True: + res = can.recv(0, timeout=50) + n_recv += 1 + print("received", res) + if can == can_a: + self.assertEqual( + res[4], b"message1", "can_a should receive message1 only" + ) + if can == can_b: + self.assertEqual( + res[4], b"message2", "can_b should receive message2 only" + ) + except OSError as e: + if e.errno != errno.ETIMEDOUT: + raise + print("recv timed out") + self.assertEqual(n_recv, 1, "Each instance should receive exactly 1 message") + finally: + can_a.deinit() + can_b.deinit() + + +if __name__ == "__main__": + unittest.main() From 0394ce95909ed88c5a7928b676312c9c19490bbc Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 25 Mar 2026 10:44:03 +1100 Subject: [PATCH 115/635] stm32: Don't disable CAN1 clock if CAN2 is still active (Classic CAN). This turned out not to be needed for the bugfix in previous commit, but seems like a good practice anyway. Signed-off-by: Angus Gratton --- ports/stm32/can.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/ports/stm32/can.c b/ports/stm32/can.c index fd03e895f46..1ffe677c1c6 100644 --- a/ports/stm32/can.c +++ b/ports/stm32/can.c @@ -145,7 +145,7 @@ bool can_init(CAN_HandleTypeDef *can, int can_id, can_tx_mode_t tx_mode, uint32_ sce_irq = CAN2_SCE_IRQn; pins[0] = MICROPY_HW_CAN2_TX; pins[1] = MICROPY_HW_CAN2_RX; - __HAL_RCC_CAN1_CLK_ENABLE(); // CAN2 is a "slave" and needs CAN1 enabled as well + __HAL_RCC_CAN1_CLK_ENABLE(); // CAN2 depends on CAN1 being enabled __HAL_RCC_CAN2_CLK_ENABLE(); break; #endif @@ -156,7 +156,7 @@ bool can_init(CAN_HandleTypeDef *can, int can_id, can_tx_mode_t tx_mode, uint32_ sce_irq = CAN3_SCE_IRQn; pins[0] = MICROPY_HW_CAN3_TX; pins[1] = MICROPY_HW_CAN3_RX; - __HAL_RCC_CAN3_CLK_ENABLE(); // CAN3 is a "master" and doesn't need CAN1 enabled as well + __HAL_RCC_CAN3_CLK_ENABLE(); // CAN3 is independent from CAN1/2 break; #endif @@ -190,15 +190,25 @@ bool can_init(CAN_HandleTypeDef *can, int can_id, can_tx_mode_t tx_mode, uint32_ return true; } +static void can1_reset_disable(void) { + __HAL_RCC_CAN1_FORCE_RESET(); + __HAL_RCC_CAN1_RELEASE_RESET(); + __HAL_RCC_CAN1_CLK_DISABLE(); +} + void can_deinit(CAN_HandleTypeDef *can) { HAL_CAN_DeInit(can); if (can->Instance == CAN1) { HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn); HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn); HAL_NVIC_DisableIRQ(CAN1_SCE_IRQn); - __HAL_RCC_CAN1_FORCE_RESET(); - __HAL_RCC_CAN1_RELEASE_RESET(); - __HAL_RCC_CAN1_CLK_DISABLE(); + #if defined(CAN2) + if (!__HAL_RCC_CAN2_IS_CLK_ENABLED()) { // CAN2 depends on CAN1 being enabled + can1_reset_disable(); + } + #else + can1_reset_disable(); + #endif #if defined(CAN2) } else if (can->Instance == CAN2) { HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn); @@ -207,6 +217,9 @@ void can_deinit(CAN_HandleTypeDef *can) { __HAL_RCC_CAN2_FORCE_RESET(); __HAL_RCC_CAN2_RELEASE_RESET(); __HAL_RCC_CAN2_CLK_DISABLE(); + if (!NVIC_GetEnableIRQ(CAN1_SCE_IRQn)) { + can1_reset_disable(); // CAN1 isn't enabled, so safe to disable as well + } #endif #if defined(CAN3) } else if (can->Instance == CAN3) { From 6574d98370193ee94c663668868d41bfad95f8b3 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 23 Apr 2026 10:16:02 +1000 Subject: [PATCH 116/635] tests/stm32/pyb_can: Update test for boards with CAN(3). This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- tests/ports/stm32/pyb_can.py | 3 ++- tests/ports/stm32/pyb_can.py.exp | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/ports/stm32/pyb_can.py b/tests/ports/stm32/pyb_can.py index 8178d91fe74..a1a3ac2cbd1 100644 --- a/tests/ports/stm32/pyb_can.py +++ b/tests/ports/stm32/pyb_can.py @@ -18,7 +18,7 @@ IS_H7 = (not IS_CLASSIC) and "STM32H7" in str(sys.implementation) # test we can correctly create by id (2 handled in can2.py test) -for bus in (-1, 0, 1, 3): +for bus in (-1, 0, 1, 4): try: CAN(bus, CAN.LOOPBACK) print("CAN", bus) @@ -176,6 +176,7 @@ print("failed, wrong data received", r) # Test filters +print("==== TEST filters ====") for n in [0, 8, 16, 24]: filter_id = 0b00001000 << n filter_mask = 0b00011100 << n diff --git a/tests/ports/stm32/pyb_can.py.exp b/tests/ports/stm32/pyb_can.py.exp index 80f44981231..3c37074f0fa 100644 --- a/tests/ports/stm32/pyb_can.py.exp +++ b/tests/ports/stm32/pyb_can.py.exp @@ -1,7 +1,7 @@ ValueError -1 ValueError 0 CAN 1 -ValueError 3 +ValueError 4 CAN(1) True CAN(1, CAN.LOOPBACK, auto_restart=False) @@ -27,6 +27,7 @@ ValueError ==== TEST extframe=True ==== CAN(1, CAN.LOOPBACK, auto_restart=False) extframe passed +==== TEST filters ==== ('0x8', '0x1c', '0xa', True, b'ok') ('0x800', '0x1c00', '0xa00', True, b'ok') ('0x80000', '0x1c0000', '0xa0000', True, b'ok') From 3ef656adfb2625a31d39ce559fcca5693e1bd5f3 Mon Sep 17 00:00:00 2001 From: Jeongseop Lim Date: Fri, 20 Mar 2026 14:48:24 +0900 Subject: [PATCH 117/635] tests/cpydiff: Add two tests for user __str__ return type difference. Document two str()-related CPython compatibility differences in tests/cpydiff/: - core_class_strrettype.py: __str__/__repr__ returning a non-string type does not raise TypeError. MicroPython silently converts and prints the value. Relates to #18941. - core_class_subclassret.py: str() does not preserve str subclass type from __str__/__repr__ return value. MicroPython always returns a plain str instance. Relates to #18942. Signed-off-by: Jeongseop Lim --- tests/cpydiff/core_class_strrettype.py | 14 ++++++++++++++ tests/cpydiff/core_class_subclassret.py | 19 +++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 tests/cpydiff/core_class_strrettype.py create mode 100644 tests/cpydiff/core_class_subclassret.py diff --git a/tests/cpydiff/core_class_strrettype.py b/tests/cpydiff/core_class_strrettype.py new file mode 100644 index 00000000000..398b5bb1a3b --- /dev/null +++ b/tests/cpydiff/core_class_strrettype.py @@ -0,0 +1,14 @@ +""" +categories: Core,Classes +description: ``__str__`` returning non-string type does not raise TypeError +cause: MicroPython's instance_print does not validate that ``__str__`` or ``__repr__`` return a str or its subclass +workaround: Ensure ``__str__`` and ``__repr__`` always return a str instance or its subclass +""" + + +class Foo: + def __str__(self): + return True + + +print(str(Foo())) diff --git a/tests/cpydiff/core_class_subclassret.py b/tests/cpydiff/core_class_subclassret.py new file mode 100644 index 00000000000..681a16e879b --- /dev/null +++ b/tests/cpydiff/core_class_subclassret.py @@ -0,0 +1,19 @@ +""" +categories: Core,Classes +description: str() does not preserve str subclass type from ``__str__`` or ``__repr__`` return value +cause: Implementation discards str subclass type returned by ``__str__`` or ``__repr__`` and always returns a plain str instance from str(). +workaround: Do not rely on str() preserving str subclass types +""" + + +class MyStr(str): + pass + + +class Foo: + def __str__(self): + return MyStr("abc") + + +result = str(Foo()) +print(type(result)) From 200db69894040caf8d32c383f9fc3c9cff0ac7db Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 30 Apr 2026 13:51:49 +1000 Subject: [PATCH 118/635] tests/run-tests.py: Skip string_escape.py as an mpy if no unicode. `mpy-cross` has unicode strings enabled, so when a .py is compiled to .mpy it will store strings encoded as utf-8. If a target does not have unicode enabled then tests with utf-8 characters will fail. Skip such tests (currently only one) in such situations. Signed-off-by: Damien George --- tests/run-tests.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/run-tests.py b/tests/run-tests.py index 344adc8faa6..38f78620e44 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -893,6 +893,8 @@ def run_tests(pyb, tests, args, result_dir, num_threads=1): skip_tests.add("float/float_parse_doubleprec.py") if not args.unicode: + if args.via_mpy: + skip_tests.add("basics/string_escape.py") # stores a utf-8 character in the mpy file skip_tests.add("extmod/json_loads.py") # tests loading a utf-8 character if skip_slice: From 7d19adbf287c50768b7f47d3f94c12df0b287d5f Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 8 May 2026 12:17:45 +1000 Subject: [PATCH 119/635] stm32/tinyusb_port: Add missing USB_HS_PHYC_PLL1_PLLSEL constants. These are needed by TinyUSB's synopsys/dwc2 driver, and are not available in the current version of stm32lib used in this repository. Signed-off-by: Damien George --- ports/stm32/tinyusb_port/tusb_config.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/ports/stm32/tinyusb_port/tusb_config.h b/ports/stm32/tinyusb_port/tusb_config.h index 4d74eec9b37..c6d4dd6b6f6 100644 --- a/ports/stm32/tinyusb_port/tusb_config.h +++ b/ports/stm32/tinyusb_port/tusb_config.h @@ -46,6 +46,22 @@ #endif #endif +#if defined(USB_HS_PHYC) && !defined(USB_HS_PHYC_PLL1_PLLSEL_Pos) +// Providing missing definitions of USB_HS_PHYC_PLL1_PLLSEL constants, required by TinyUSB. +// (These are added in a newer version of the STM32F7xx CMSIS files.) +#define USB_HS_PHYC_PLL1_PLLSEL_Pos (1U) +#define USB_HS_PHYC_PLL1_PLLSEL_Msk (0x7UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) +#define USB_HS_PHYC_PLL1_PLLSEL (USB_HS_PHYC_PLL1_PLLSEL_Msk) +#define USB_HS_PHYC_PLL1_PLLSEL_1 (0x1UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) +#define USB_HS_PHYC_PLL1_PLLSEL_2 (0x2UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) +#define USB_HS_PHYC_PLL1_PLLSEL_3 (0x4UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) +#define USB_HS_PHYC_PLL1_PLLSEL_12MHZ (0x00000000U) +#define USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ (USB_HS_PHYC_PLL1_PLLSEL_1) +#define USB_HS_PHYC_PLL1_PLLSEL_16MHZ (USB_HS_PHYC_PLL1_PLLSEL_1 | USB_HS_PHYC_PLL1_PLLSEL_2) +#define USB_HS_PHYC_PLL1_PLLSEL_24MHZ (USB_HS_PHYC_PLL1_PLLSEL_3) +#define USB_HS_PHYC_PLL1_PLLSEL_25MHZ (USB_HS_PHYC_PLL1_PLLSEL_2 | USB_HS_PHYC_PLL1_PLLSEL_3) +#endif + #include "shared/tinyusb/tusb_config.h" #endif // MICROPY_INCLUDED_STM32_TINYUSB_PORT_TUSB_CONFIG_H From cfdace9745fdd5063465d45c611b27efa09576ec Mon Sep 17 00:00:00 2001 From: Amirreza Hamzavi Date: Wed, 12 Feb 2025 04:02:04 +0330 Subject: [PATCH 120/635] esp32/espnow: Add support for espnow v2.0. Co-authored-by: Angus Gratton Signed-off-by: Amirreza Hamzavi --- docs/library/espnow.rst | 72 ++++++++++++++++++-------- ports/esp32/modespnow.c | 39 ++++++++++---- py/ringbuf.h | 5 ++ tests/multi_espnow/20_send_echo.py | 9 +++- tests/multi_espnow/20_send_echo.py.exp | 4 +- 5 files changed, 91 insertions(+), 38 deletions(-) diff --git a/docs/library/espnow.rst b/docs/library/espnow.rst index 14a92c11400..498fa9937d5 100644 --- a/docs/library/espnow.rst +++ b/docs/library/espnow.rst @@ -32,23 +32,42 @@ ESP-NOW is a connection-less wireless communication protocol supporting: - Direct communication between up to 20 registered peers: - - Without the need for a wireless access point (AP), +- Without the need for a wireless access point (AP), - Encrypted and unencrypted communication (up to 6 encrypted peers), -- Message sizes up to 250 bytes, +- Message sizes up to 1470 bytes (For ESP-NOW v2), -- Can operate alongside Wifi operation (:doc:`network.WLAN`) on +- Can operate alongside Wi-Fi operation (:doc:`network.WLAN`) on ESP32 and ESP8266 devices. +- Track the Wi-Fi signal strength (RSSI) of ESP-NOW peer devices. + It is especially useful for small IoT networks, latency sensitive or power sensitive applications (such as battery operated devices) and for long-range communication between devices (hundreds of metres). -This module also supports tracking the Wifi signal strength (RSSI) of peer -devices. +ESP-NOW Versions +~~~~~~~~~~~~~~~~ + +Since ESP-IDF V5.4, two ESP-NOW versions are supported when running on ESP32: +V1 and V2. + +- The maximum packet length supported by V2 devices is 1470 bytes +- The maximum packet length supported by V1 devices is 250 bytes. + +To check at runtime whether ESP-NOW V2 is available, check the value of +`espnow.MAX_DATA_LEN`. -A simple example would be: +ESP-NOW V2 devices are capable of receiving packets from both V2 and V1 devices. + +ESP-NOW V1 devices (including ESP8266) can receive packets from other V1 +devices, or from V2 devices if the packet length doesn't exceed 250 bytes. For +packets exceeding this length, a V1 device will either truncate the data to the +first 250 bytes or discard the packet entirely. + +Example +~~~~~~~ **Sender:** :: @@ -148,23 +167,26 @@ Configuration .. data:: Options: - *rxbuf*: (default=526) Get/set the size in bytes of the internal - buffer used to store incoming ESPNow packet data. The default size is - selected to fit two max-sized ESPNow packets (250 bytes) with associated - mac_address (6 bytes), a message byte count (1 byte) and RSSI data plus + *rxbuf*: (default=528 or 2972) Get/set the size in bytes of the internal + buffer used to store incoming ESP-NOW packet data. The default size is + selected to fit two max-sized ESP-NOW packets (250 or 1470 bytes) with associated + mac_address (6 bytes), a message byte count (2 byte) and RSSI data plus buffer overhead. Increase this if you expect to receive a lot of large packets or expect bursty incoming traffic. - **Note:** The recv buffer is allocated by `ESPNow.active()`. Changing - this value will have no effect until the next call of - `ESPNow.active(True)`. + .. note:: If only using ESP-NOW V1 packets and low throughput, recommend + setting ``rxbuf=528`` here to reduce memory overhead. - *timeout_ms*: (default=300,000) Default timeout (in milliseconds) - for receiving ESPNow messages. If *timeout_ms* is less than zero, then + .. note:: The recv buffer is allocated by `ESPNow.active()`. Changing + this value will have no effect until the next call of + `ESPNow.active(True)`. + + *timeout_ms*: (default=300_000) Default timeout (in milliseconds) + for receiving ESP-NOW messages. If *timeout_ms* is less than zero, then wait forever. The timeout can also be provided as arg to `recv()`/`irecv()`/`recvinto()`. - *rate*: (ESP32 only) Set the transmission data rate for ESPNow packets. + *rate*: (ESP32 only) Set the transmission data rate for ESP-NOW packets. The default setting is `espnow.RATE_1M`. It's recommended to use one of the other ``espnow.RATE_nnn`` constants to set this, but it's also possible to pass an integer corresponding to the `enum wifi_phy_rate_t @@ -214,12 +236,12 @@ after reboot/reset). This reduces the reliability of receiving ESP-NOW messages .. data:: Arguments: - - *mac*: byte string exactly ``espnow.ADDR_LEN`` (6 bytes) long or + - *mac*: byte string exactly `espnow.ADDR_LEN` (6 bytes) long or ``None``. If *mac* is ``None`` (ESP32 only) the message will be sent to all registered peers, except any broadcast or multicast MAC addresses. - - *msg*: string or byte-string up to ``espnow.MAX_DATA_LEN`` (250) + - *msg*: string or byte-string up to `espnow.MAX_DATA_LEN` (250 or 1470) bytes long. - *sync*: @@ -327,10 +349,10 @@ after reboot/reset). This reduces the reliability of receiving ESP-NOW messages .. data:: Arguments: *data*: A list of at least two elements, ``[peer, msg]``. ``msg`` must - be a bytearray large enough to hold the message (250 bytes). On the - ESP8266, ``peer`` should be a bytearray of 6 bytes. The MAC address of - the sender and the message will be stored in these bytearrays (see Note - on ESP32 below). + be a bytearray large enough to hold the received message (recommended at + least `espnow.MAX_DATA_LEN`). On the ESP8266, ``peer`` should be a + bytearray of 6 bytes. The MAC address of the sender and the message will + be stored in these bytearrays (see Note on ESP32 below). *timeout_ms*: (Optional) Timeout in milliseconds (see `ESPNow.recv()`). @@ -343,6 +365,10 @@ after reboot/reset). This reduces the reliability of receiving ESP-NOW messages - See `ESPNow.recv()`. + - This function will also raise a ``ValueError`` if the received message + is too large for the provided buffer. If this error is raised, received + message(s) will be lost. + **Note:** On the ESP32: - It is unnecessary to provide a bytearray in the first element of the @@ -570,7 +596,7 @@ Callback Methods Constants --------- -.. data:: espnow.MAX_DATA_LEN(=250) +.. data:: espnow.MAX_DATA_LEN(=250 or 1470 for ESPNow V1 or V2) espnow.KEY_LEN(=16) espnow.ADDR_LEN(=6) espnow.MAX_TOTAL_PEER_NUM(=20) diff --git a/ports/esp32/modespnow.c b/ports/esp32/modespnow.c index c7a9c6eb1b9..e0c5680836d 100644 --- a/ports/esp32/modespnow.c +++ b/ports/esp32/modespnow.c @@ -62,6 +62,16 @@ #define MICROPY_PY_ESPNOW_EXTRA_PEER_METHODS 1 #endif +// Set maximum possible data length based on IDF version +// TODO Delete this after dropping support for IDF < 5.4 +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) +#define ESP_NOW_MAX_POSSIBLE_DATA_LEN ESP_NOW_MAX_DATA_LEN_V2 +#else +#define ESP_NOW_MAX_POSSIBLE_DATA_LEN ESP_NOW_MAX_DATA_LEN +#endif + +#define MAX_DATA_LEN_V1 ESP_NOW_MAX_DATA_LEN + // Relies on gcc Variadic Macros and Statement Expressions #define NEW_TUPLE(...) \ ({mp_obj_t _z[] = {__VA_ARGS__}; mp_obj_new_tuple(MP_ARRAY_SIZE(_z), _z); }) @@ -72,7 +82,7 @@ static const uint8_t ESPNOW_MAGIC = 0x99; // Use this for peeking at the header of the next packet in the buffer. typedef struct { uint8_t magic; // = ESPNOW_MAGIC - uint8_t msg_len; // Length of the message + uint16_t msg_len; // Length of the message #if MICROPY_PY_ESPNOW_RSSI uint32_t time_ms; // Timestamp (ms) when packet is received int8_t rssi; // RSSI value (dBm) (-127 to 0) @@ -82,15 +92,16 @@ typedef struct { typedef struct { espnow_hdr_t hdr; // The header uint8_t peer[6]; // Peer address - uint8_t msg[0]; // Message is up to 250 bytes + uint8_t msg[0]; // Message is up to 250 or 1470 bytes } __attribute__((packed)) espnow_pkt_t; // The maximum length of an espnow packet (bytes) static const size_t MAX_PACKET_LEN = ( - (sizeof(espnow_pkt_t) + ESP_NOW_MAX_DATA_LEN)); + (sizeof(espnow_pkt_t) + ESP_NOW_MAX_POSSIBLE_DATA_LEN)); -// Enough for 2 full-size packets: 2 * (6 + 7 + 250) = 526 bytes -// Will allocate an additional 7 bytes for buffer overhead +// Enough for 2 full-size packets: +// V1.0: 2 * (6 + 8 + 250) = 528 bytes (keeping this default for compatibility) +// V2.0: 2 * (6 + 8 + 1470) = 2972 bytes static const size_t DEFAULT_RECV_BUFFER_SIZE = (2 * MAX_PACKET_LEN); // Default timeout (millisec) to wait for incoming ESPNow messages (5 minutes). @@ -381,9 +392,11 @@ static uint8_t *_get_bytes_len(mp_obj_t obj, size_t len) { return _get_bytes_len_rw(obj, len, MP_BUFFER_READ); } +#if !MICROPY_PY_ESPNOW_RSSI static uint8_t *_get_bytes_len_w(mp_obj_t obj, size_t len) { return _get_bytes_len_rw(obj, len, MP_BUFFER_WRITE); } +#endif // Return C pointer to the MAC address. // Raise ValueError if mac_addr is wrong type or is not 6 bytes long. @@ -412,7 +425,7 @@ static int ringbuf_get_bytes_wait(ringbuf_t *r, uint8_t *data, size_t len, mp_in // Arguments: // buffers: (Optional) list of bytearrays to store return values. // timeout_ms: (Optional) timeout in milliseconds (or None). -// Buffers should be a list: [bytearray(6), bytearray(250)] +// Buffers should be a list: [bytearray(6), bytearray(250 or 1470)] // If buffers is 4 elements long, the rssi and timestamp values will be // loaded into the 3rd and 4th elements. // Default timeout is set with ESPNow.config(timeout=milliseconds). @@ -425,6 +438,7 @@ static mp_obj_t espnow_recvinto(size_t n_args, const mp_obj_t *args) { mp_obj_list_t *list = mp_obj_list_ensure(args[1], 2); mp_obj_array_t *msg = MP_OBJ_TO_PTR(list->items[1]); + mp_buffer_info_t msg_buf; if (mp_obj_is_type(msg, &mp_type_bytearray)) { msg->len += msg->free; // Make all the space in msg array available msg->free = 0; @@ -434,7 +448,8 @@ static mp_obj_t espnow_recvinto(size_t n_args, const mp_obj_t *args) { #else uint8_t *peer_buf = _get_bytes_len_w(list->items[0], ESP_NOW_ETH_ALEN); #endif // MICROPY_PY_ESPNOW_RSSI - uint8_t *msg_buf = _get_bytes_len_w(msg, ESP_NOW_MAX_DATA_LEN); + + mp_get_buffer_raise(msg, &msg_buf, MP_BUFFER_WRITE); // Read the packet header from the incoming buffer espnow_hdr_t hdr; @@ -443,11 +458,13 @@ static mp_obj_t espnow_recvinto(size_t n_args, const mp_obj_t *args) { } int msg_len = hdr.msg_len; - // Check the message packet header format and read the message data + // Check the message packet header format, check the message will fit in the buffer, + // and then read the message data if (hdr.magic != ESPNOW_MAGIC - || msg_len > ESP_NOW_MAX_DATA_LEN + || msg_len > msg_buf.len || ringbuf_get_bytes(self->recv_buffer, peer_buf, ESP_NOW_ETH_ALEN) < 0 - || ringbuf_get_bytes(self->recv_buffer, msg_buf, msg_len) < 0) { + || ringbuf_get_bytes(self->recv_buffer, msg_buf.buf, msg_len) < 0) { + ringbuf_reset(self->recv_buffer); // Prevent ringbuffer getting out of sync mp_raise_ValueError(MP_ERROR_TEXT("ESPNow.recv(): buffer error")); } if (mp_obj_is_type(msg, &mp_type_bytearray)) { @@ -809,7 +826,7 @@ static MP_DEFINE_CONST_DICT(esp_espnow_locals_dict, esp_espnow_locals_dict_table static const mp_rom_map_elem_t espnow_globals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR__espnow) }, { MP_ROM_QSTR(MP_QSTR_ESPNowBase), MP_ROM_PTR(&esp_espnow_type) }, - { MP_ROM_QSTR(MP_QSTR_MAX_DATA_LEN), MP_ROM_INT(ESP_NOW_MAX_DATA_LEN)}, + { MP_ROM_QSTR(MP_QSTR_MAX_DATA_LEN), MP_ROM_INT(ESP_NOW_MAX_POSSIBLE_DATA_LEN)}, { MP_ROM_QSTR(MP_QSTR_ADDR_LEN), MP_ROM_INT(ESP_NOW_ETH_ALEN)}, { MP_ROM_QSTR(MP_QSTR_KEY_LEN), MP_ROM_INT(ESP_NOW_KEY_LEN)}, { MP_ROM_QSTR(MP_QSTR_MAX_TOTAL_PEER_NUM), MP_ROM_INT(ESP_NOW_MAX_TOTAL_PEER_NUM)}, diff --git a/py/ringbuf.h b/py/ringbuf.h index d5aed429c56..d3c0f460138 100644 --- a/py/ringbuf.h +++ b/py/ringbuf.h @@ -51,6 +51,11 @@ typedef struct _ringbuf_t { (r)->iget = (r)->iput = 0; \ } +static inline void ringbuf_reset(ringbuf_t *r) { + // Reset the ringbuffer to empty + r->iget = r->iput = 0; +} + static inline int ringbuf_get(ringbuf_t *r) { if (r->iget == r->iput) { return -1; diff --git a/tests/multi_espnow/20_send_echo.py b/tests/multi_espnow/20_send_echo.py index 4c325bf68c5..e71db937219 100644 --- a/tests/multi_espnow/20_send_echo.py +++ b/tests/multi_espnow/20_send_echo.py @@ -35,7 +35,12 @@ def echo_server(e): def echo_test(e, peer, msg, sync): - print("TEST: send/recv(msglen=", len(msg), ",sync=", sync, "): ", end="", sep="") + # to get the same log output regardless of ESP-NOW V1 or V2, + # log the exact length unless it's overlong + msg_len = len(msg) + if msg_len > espnow.MAX_DATA_LEN: + msg_len = "max+{}".format(msg_len - espnow.MAX_DATA_LEN) + print("TEST: send/recv(msglen=", msg_len, ",sync=", sync, "): ", end="", sep="") try: if not e.send(peer, msg, sync): print("ERROR: Send failed.") @@ -88,6 +93,6 @@ def instance1(): multitest.next() peer = PEERS[0] e.add_peer(peer) - echo_client(e, peer, [1, 2, 8, 100, 249, 250, 251, 0]) + echo_client(e, peer, [1, 2, 8, 100, 249, 250, espnow.MAX_DATA_LEN + 1, 0]) echo_test(e, peer, b"!done", True) e.active(False) diff --git a/tests/multi_espnow/20_send_echo.py.exp b/tests/multi_espnow/20_send_echo.py.exp index e43900bcf64..3703593523d 100644 --- a/tests/multi_espnow/20_send_echo.py.exp +++ b/tests/multi_espnow/20_send_echo.py.exp @@ -8,7 +8,7 @@ TEST: send/recv(msglen=8,sync=True): OK TEST: send/recv(msglen=100,sync=True): OK TEST: send/recv(msglen=249,sync=True): OK TEST: send/recv(msglen=250,sync=True): OK -TEST: send/recv(msglen=251,sync=True): ERROR: OSError: +TEST: send/recv(msglen=max+1,sync=True): ERROR: OSError: TEST: send/recv(msglen=0,sync=True): ERROR: OSError: TEST: send/recv(msglen=1,sync=False): OK TEST: send/recv(msglen=2,sync=False): OK @@ -16,6 +16,6 @@ TEST: send/recv(msglen=8,sync=False): OK TEST: send/recv(msglen=100,sync=False): OK TEST: send/recv(msglen=249,sync=False): OK TEST: send/recv(msglen=250,sync=False): OK -TEST: send/recv(msglen=251,sync=False): ERROR: OSError: +TEST: send/recv(msglen=max+1,sync=False): ERROR: OSError: TEST: send/recv(msglen=0,sync=False): ERROR: OSError: TEST: send/recv(msglen=5,sync=True): OK From ff81c35b075ef1ede2f5fddd260f48686c8cf15c Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 7 May 2026 15:51:53 +1000 Subject: [PATCH 121/635] tests/multi_espnow: Add a specific test for ESP-NOW V2 packet lengths. Signed-off-by: Angus Gratton --- tests/multi_espnow/45_recv_espnow_v2.py | 136 ++++++++++++++++++++ tests/multi_espnow/45_recv_espnow_v2.py.exp | 14 ++ 2 files changed, 150 insertions(+) create mode 100644 tests/multi_espnow/45_recv_espnow_v2.py create mode 100644 tests/multi_espnow/45_recv_espnow_v2.py.exp diff --git a/tests/multi_espnow/45_recv_espnow_v2.py b/tests/multi_espnow/45_recv_espnow_v2.py new file mode 100644 index 00000000000..07a23ad1363 --- /dev/null +++ b/tests/multi_espnow/45_recv_espnow_v2.py @@ -0,0 +1,136 @@ +# Test of a ESP-NOW V2 echo server and client transferring data, as a variant of +# 40_recv_test.py. +# +# This test requires both instances to be ESP32s built with ESP-IDF V5.5 or +# newer for ESP-NOW V2 support. +# +# Explicitly tests the irecv(), rev() and recvinto() methods. + +try: + import network, os + import random + import espnow +except ImportError: + print("SKIP") + raise SystemExit + +if espnow.MAX_DATA_LEN < 1470: # Check for V2 support + print("SKIP") + raise SystemExit + +# Set read timeout to 8 seconds +timeout_ms = 8000 +default_pmk = b"VerySecretValue!" +sync = True + + +def echo_server(e): + peers = [] + while True: + peer, msg = e.irecv(timeout_ms) + if peer is None: + return + if peer not in peers: + peers.append(peer) + e.add_peer(peer) + + # Echo the MAC and message back to the sender + if not e.send(peer, msg, sync): + print("ERROR: send() failed to", peer.hex()) + return + + if msg == b"!done": + return + + +def client_send(e, peer, msg, sync): + import time + + time.sleep_ms(100) + print("TEST: send/recv(msglen=", len(msg), ",sync=", sync, "): ", end="", sep="") + try: + if not e.send(peer, msg, sync): + print("ERROR: Send failed.") + return + except OSError as exc: + # Don't print exc as it is differs for esp32 and esp8266 + print("ERROR: OSError:", exc) # FIXME + return + + +def init(sta_active=True, ap_active=False): + wlans = [network.WLAN(i) for i in [network.WLAN.IF_STA, network.WLAN.IF_AP]] + e = espnow.ESPNow() + e.active(True) + e.set_pmk(default_pmk) + wlans[0].active(sta_active) + wlans[1].active(ap_active) + wlans[0].disconnect() # Force esp8266 STA interface to disconnect from AP + return e + + +# Server +def instance0(): + e = init(True, False) + multitest.globals(PEERS=[network.WLAN(i).config("mac") for i in (0, 1)]) + multitest.next() + print("Server Start") + echo_server(e) + print("Server Done") + e.active(False) + + +def check_recv(s, r): + if s == r: + print("OK") + else: + print("ERROR: Received != Sent") + print("Sent", len(s), "bytes") + if r is None: + print("Receive timed out") + else: + print("Received", len(r), "bytes") + + +# Client +def instance1(): + # Instance 1 (the client) + e = init(True, False) + e.config(timeout_ms=timeout_ms) + multitest.next() + peer = PEERS[0] + e.add_peer(peer) + + print("RECVINTO() test...") + msg = os.urandom(768) + client_send(e, peer, msg, True) + data = [bytearray(espnow.ADDR_LEN), bytearray(espnow.MAX_DATA_LEN)] + n = e.recvinto(data) + check_recv(msg, data[1]) + + print("IRECV() test...") + msg = os.urandom(768) + client_send(e, peer, msg, True) + p2, msg2 = e.irecv() + check_recv(msg, msg2) + + print("RECV() test...") + msg = os.urandom(1024) + client_send(e, peer, msg, True) + p2, msg2 = e.recv() + check_recv(msg, msg2) + + print("ITERATOR() test...") + msg = os.urandom(espnow.MAX_DATA_LEN) + client_send(e, peer, msg, True) + p2, msg2 = next(e) + check_recv(msg, msg2) + + # Tell the server to stop + print("DONE") + msg = b"!done" + client_send(e, peer, msg, True) + p2, msg2 = e.irecv() + check_recv(msg, msg2) + + e.active(False) diff --git a/tests/multi_espnow/45_recv_espnow_v2.py.exp b/tests/multi_espnow/45_recv_espnow_v2.py.exp new file mode 100644 index 00000000000..3638cc40640 --- /dev/null +++ b/tests/multi_espnow/45_recv_espnow_v2.py.exp @@ -0,0 +1,14 @@ +--- instance0 --- +Server Start +Server Done +--- instance1 --- +RECVINTO() test... +TEST: send/recv(msglen=768,sync=True): OK +IRECV() test... +TEST: send/recv(msglen=768,sync=True): OK +RECV() test... +TEST: send/recv(msglen=1024,sync=True): OK +ITERATOR() test... +TEST: send/recv(msglen=1470,sync=True): OK +DONE +TEST: send/recv(msglen=5,sync=True): OK From 55558477fa84ec820f3027452ea21815d5fac8d5 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 7 May 2026 17:22:46 +1000 Subject: [PATCH 122/635] esp32/espnow: Clear the recv_cb & arg on deinit. These won't be accessed again until a new callback is set, but it stops the objects being kept alive unnecessarily. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/esp32/modespnow.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ports/esp32/modespnow.c b/ports/esp32/modespnow.c index e0c5680836d..294a0be3702 100644 --- a/ports/esp32/modespnow.c +++ b/ports/esp32/modespnow.c @@ -235,6 +235,8 @@ mp_obj_t espnow_deinit(mp_obj_t _) { check_esp_err(esp_now_unregister_recv_cb()); check_esp_err(esp_now_unregister_send_cb()); check_esp_err(esp_now_deinit()); + self->recv_cb = mp_const_none; + self->recv_cb_arg = mp_const_none; self->recv_buffer->buf = NULL; self->recv_buffer = NULL; self->peer_count = 0; // esp_now_deinit() removes all peers. From 3d78efa8c22f072c378efb93eb5d1f43d87fdf6f Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 22 Apr 2026 16:08:53 +1000 Subject: [PATCH 123/635] esp32/boards: Change MICROPY_HW_MCU_NAME to add a hyphen after "ESP32". This makes all esp32 boards have a consistent naming scheme used by the MICROPY_HW_MCU_NAME macro, to have a hyphen after "ESP32" (if there's anything following it). This makes it easier to detect the SoC variant, eg "ESP32-S2", which now only requires a single check, rather than supporting strings with and without a hyphen. Signed-off-by: Damien George --- ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h | 2 +- ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h | 2 +- ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h | 2 +- ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.h | 2 +- ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.h | 2 +- ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h | 2 +- ports/esp32/boards/ESP32_GENERIC_S2/mpconfigboard.h | 2 +- ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.h | 2 +- .../esp32/boards/GARATRONIC_PYBSTICK26_ESP32C3/mpconfigboard.h | 2 +- ports/esp32/boards/M5STACK_ATOMS3_LITE/mpconfigboard.h | 2 +- ports/esp32/boards/M5STACK_NANOC6/mpconfigboard.h | 2 +- ports/esp32/boards/SEEED_XIAO_ESP32C6/mpconfigboard.h | 2 +- ports/esp32/boards/SOLDERED_NULA_MINI/mpconfigboard.h | 2 +- ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h | 2 +- ports/esp32/boards/UM_TINYC6/mpconfigboard.h | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h b/ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h index 3ca587ae407..855040b3cd9 100644 --- a/ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h +++ b/ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h @@ -1,5 +1,5 @@ #define MICROPY_HW_BOARD_NAME "Arduino Nano ESP32" -#define MICROPY_HW_MCU_NAME "ESP32S3" +#define MICROPY_HW_MCU_NAME "ESP32-S3" // Network config #define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-nano-esp32" diff --git a/ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h index 300ddb0e235..60f27420f73 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h @@ -5,7 +5,7 @@ #endif #ifndef MICROPY_HW_MCU_NAME -#define MICROPY_HW_MCU_NAME "ESP32C2" +#define MICROPY_HW_MCU_NAME "ESP32-C2" #endif #define MICROPY_HW_ENABLE_SDCARD (0) diff --git a/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h index 988c7db8a14..c3d798b6e5e 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h @@ -1,7 +1,7 @@ // This configuration is for a generic ESP32C3 board with 4MiB (or more) of flash. #define MICROPY_HW_BOARD_NAME "ESP32C3 module" -#define MICROPY_HW_MCU_NAME "ESP32C3" +#define MICROPY_HW_MCU_NAME "ESP32-C3" // Enable UART REPL for modules that have an external USB-UART and don't use native USB. #define MICROPY_HW_ENABLE_UART_REPL (1) diff --git a/ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.h index 55246849775..62f9c6f3c9a 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.h @@ -1,7 +1,7 @@ // This configuration is for a generic ESP32C5 board with 4MiB (or more) of flash. #define MICROPY_HW_BOARD_NAME "ESP32C5 module" -#define MICROPY_HW_MCU_NAME "ESP32C5" +#define MICROPY_HW_MCU_NAME "ESP32-C5" #define MICROPY_PY_MACHINE_I2S (0) #define MICROPY_HW_ENABLE_UART_REPL (1) diff --git a/ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.h index 712e1fca157..e7e7e49f902 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.h @@ -1,7 +1,7 @@ // This configuration is for a generic ESP32C6 board with 4MiB (or more) of flash. #define MICROPY_HW_BOARD_NAME "ESP32C6 module" -#define MICROPY_HW_MCU_NAME "ESP32C6" +#define MICROPY_HW_MCU_NAME "ESP32-C6" // Enable UART REPL for modules that have an external USB-UART and don't use native USB. #define MICROPY_HW_ENABLE_UART_REPL (1) diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h index 6a7ff83cec0..9cfb8b92403 100644 --- a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h @@ -6,7 +6,7 @@ #endif #ifndef MICROPY_HW_MCU_NAME -#define MICROPY_HW_MCU_NAME "ESP32P4" +#define MICROPY_HW_MCU_NAME "ESP32-P4" #endif #define MICROPY_PY_ESPNOW (0) diff --git a/ports/esp32/boards/ESP32_GENERIC_S2/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_S2/mpconfigboard.h index 9e03e8269b1..3c5e3685a41 100644 --- a/ports/esp32/boards/ESP32_GENERIC_S2/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_S2/mpconfigboard.h @@ -1,5 +1,5 @@ #define MICROPY_HW_BOARD_NAME "Generic ESP32S2 module" -#define MICROPY_HW_MCU_NAME "ESP32S2" +#define MICROPY_HW_MCU_NAME "ESP32-S2" #define MICROPY_PY_BLUETOOTH (0) diff --git a/ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.h index c714fe2c227..0eada86a37b 100644 --- a/ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.h @@ -2,7 +2,7 @@ // Can be set by mpconfigboard.cmake. #define MICROPY_HW_BOARD_NAME "Generic ESP32S3 module" #endif -#define MICROPY_HW_MCU_NAME "ESP32S3" +#define MICROPY_HW_MCU_NAME "ESP32-S3" // Enable UART REPL for modules that have an external USB-UART and don't use native USB. #define MICROPY_HW_ENABLE_UART_REPL (1) diff --git a/ports/esp32/boards/GARATRONIC_PYBSTICK26_ESP32C3/mpconfigboard.h b/ports/esp32/boards/GARATRONIC_PYBSTICK26_ESP32C3/mpconfigboard.h index c9796d1f659..28910a3c222 100644 --- a/ports/esp32/boards/GARATRONIC_PYBSTICK26_ESP32C3/mpconfigboard.h +++ b/ports/esp32/boards/GARATRONIC_PYBSTICK26_ESP32C3/mpconfigboard.h @@ -1,5 +1,5 @@ #define MICROPY_HW_BOARD_NAME "PYBSTICK26_ESP32C3" -#define MICROPY_HW_MCU_NAME "ESP32C3" +#define MICROPY_HW_MCU_NAME "ESP32-C3" #define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "pybstick26_esp32c3" #define MICROPY_HW_I2C0_SCL (1) diff --git a/ports/esp32/boards/M5STACK_ATOMS3_LITE/mpconfigboard.h b/ports/esp32/boards/M5STACK_ATOMS3_LITE/mpconfigboard.h index 14bde8438bb..aaea0e30525 100644 --- a/ports/esp32/boards/M5STACK_ATOMS3_LITE/mpconfigboard.h +++ b/ports/esp32/boards/M5STACK_ATOMS3_LITE/mpconfigboard.h @@ -1,5 +1,5 @@ #define MICROPY_HW_BOARD_NAME "M5Stack AtomS3 Lite" -#define MICROPY_HW_MCU_NAME "ESP32S3" +#define MICROPY_HW_MCU_NAME "ESP32-S3" #define MICROPY_PY_MACHINE_DAC (0) diff --git a/ports/esp32/boards/M5STACK_NANOC6/mpconfigboard.h b/ports/esp32/boards/M5STACK_NANOC6/mpconfigboard.h index 16ddc1e51d3..c9528025914 100644 --- a/ports/esp32/boards/M5STACK_NANOC6/mpconfigboard.h +++ b/ports/esp32/boards/M5STACK_NANOC6/mpconfigboard.h @@ -1,5 +1,5 @@ #define MICROPY_HW_BOARD_NAME "M5Stack NanoC6" -#define MICROPY_HW_MCU_NAME "ESP32C6" +#define MICROPY_HW_MCU_NAME "ESP32-C6" #define MICROPY_HW_I2C0_SCL (1) #define MICROPY_HW_I2C0_SDA (2) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C6/mpconfigboard.h b/ports/esp32/boards/SEEED_XIAO_ESP32C6/mpconfigboard.h index a85f1389986..c3df2f8f970 100644 --- a/ports/esp32/boards/SEEED_XIAO_ESP32C6/mpconfigboard.h +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C6/mpconfigboard.h @@ -1,5 +1,5 @@ #define MICROPY_HW_BOARD_NAME "Seeed XIAO ESP32C6" -#define MICROPY_HW_MCU_NAME "ESP32C6" +#define MICROPY_HW_MCU_NAME "ESP32-C6" #define MICROPY_HW_I2C0_SCL (23) #define MICROPY_HW_I2C0_SDA (22) diff --git a/ports/esp32/boards/SOLDERED_NULA_MINI/mpconfigboard.h b/ports/esp32/boards/SOLDERED_NULA_MINI/mpconfigboard.h index 658919eaf4f..87fdba97da5 100644 --- a/ports/esp32/boards/SOLDERED_NULA_MINI/mpconfigboard.h +++ b/ports/esp32/boards/SOLDERED_NULA_MINI/mpconfigboard.h @@ -1,7 +1,7 @@ // This configuration is for a generic ESP32C6 board with 4MiB (or more) of flash. #define MICROPY_HW_BOARD_NAME "Soldered NULA Mini" -#define MICROPY_HW_MCU_NAME "ESP32C6" +#define MICROPY_HW_MCU_NAME "ESP32-C6" // Enable UART REPL for modules that have an external USB-UART and don't use native USB. #define MICROPY_HW_ENABLE_UART_REPL (1) diff --git a/ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h b/ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h index 7c892399da9..0da84f9920b 100644 --- a/ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h +++ b/ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h @@ -1,7 +1,7 @@ // Board specific definitions for the SparkFun Thing Plus ESP32-C5. #define MICROPY_HW_BOARD_NAME "SparkFun Thing Plus ESP32-C5" -#define MICROPY_HW_MCU_NAME "ESP32C5" +#define MICROPY_HW_MCU_NAME "ESP32-C5" #define MICROPY_HW_I2C0_SCL (24) #define MICROPY_HW_I2C0_SDA (23) diff --git a/ports/esp32/boards/UM_TINYC6/mpconfigboard.h b/ports/esp32/boards/UM_TINYC6/mpconfigboard.h index 131116e9ffb..15a7edc1c56 100644 --- a/ports/esp32/boards/UM_TINYC6/mpconfigboard.h +++ b/ports/esp32/boards/UM_TINYC6/mpconfigboard.h @@ -1,5 +1,5 @@ #define MICROPY_HW_BOARD_NAME "Unexpected Maker TinyC6" -#define MICROPY_HW_MCU_NAME "ESP32C6" +#define MICROPY_HW_MCU_NAME "ESP32-C6" #define MICROPY_HW_I2C0_SCL (7) #define MICROPY_HW_I2C0_SDA (6) From 334c0311d3c6c65a37c502a4acea9c93e3404274 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 22 Apr 2026 16:11:04 +1000 Subject: [PATCH 124/635] tests: Update ESP32-Cx detection to match standard name. Signed-off-by: Damien George --- tests/multi_espnow/75_rate.py | 4 ++-- tests/ports/esp32/esp32_idf_heap_info.py | 2 +- tests/target_wiring/esp32.py | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/multi_espnow/75_rate.py b/tests/multi_espnow/75_rate.py index 9c05a24bd00..805ac4f0701 100644 --- a/tests/multi_espnow/75_rate.py +++ b/tests/multi_espnow/75_rate.py @@ -17,13 +17,13 @@ # Currently the config(rate=...) implementation is not compatible with ESP32-C6 # (this test passes when C6 is receiver, but not if C6 is sender.) -if "ESP32C6" in sys.implementation._machine: +if "ESP32-C6" in sys.implementation._machine: print("SKIP") raise SystemExit # ESP32-C2 doesn't support Long Range mode. This test is currently written assuming # LR mode can be enabled. -if "ESP32C2" in sys.implementation._machine: +if "ESP32-C2" in sys.implementation._machine: print("SKIP") raise SystemExit diff --git a/tests/ports/esp32/esp32_idf_heap_info.py b/tests/ports/esp32/esp32_idf_heap_info.py index 2f45295938d..91ac6cd7bc0 100644 --- a/tests/ports/esp32/esp32_idf_heap_info.py +++ b/tests/ports/esp32/esp32_idf_heap_info.py @@ -13,7 +13,7 @@ MIN_EXEC = 3 impl = str(sys.implementation) -if "ESP32C2" in impl: +if "ESP32-C2" in impl: # ESP32-C2 is less fragmented (yay!) and only has two memory regions MIN_DATA = 2 MIN_EXEC = 2 diff --git a/tests/target_wiring/esp32.py b/tests/target_wiring/esp32.py index d94a6f60759..068f14ae77e 100644 --- a/tests/target_wiring/esp32.py +++ b/tests/target_wiring/esp32.py @@ -9,7 +9,7 @@ uart_loopback_args = (1,) uart_loopback_kwargs = {"tx": 4, "rx": 5} -if "ESP32C" in sys.implementation._machine: +if "ESP32-C" in sys.implementation._machine: spi_standalone_args_list = [(1,)] else: spi_standalone_args_list = [(1,), (2,)] From 5b7a7d8f81c88c3bee8fb9c2162c05800757fb7b Mon Sep 17 00:00:00 2001 From: Nicko van Someren Date: Tue, 30 Dec 2025 09:41:28 -0700 Subject: [PATCH 125/635] rp2/rp2_dma: Add support for DMA pacing timers. Signed-off-by: Nicko van Someren --- docs/library/rp2.DMA.rst | 77 ++++++++++- ports/rp2/modrp2.c | 1 + ports/rp2/modrp2.h | 1 + ports/rp2/rp2_dma.c | 213 ++++++++++++++++++++++++++++++- tests/ports/rp2/rp2_dma_timer.py | 84 ++++++++++++ 5 files changed, 372 insertions(+), 4 deletions(-) create mode 100644 tests/ports/rp2/rp2_dma_timer.py diff --git a/docs/library/rp2.DMA.rst b/docs/library/rp2.DMA.rst index c5e3f31aa2e..0f1ae46c214 100644 --- a/docs/library/rp2.DMA.rst +++ b/docs/library/rp2.DMA.rst @@ -5,7 +5,7 @@ class DMA -- access to the RP2040's DMA controller ================================================== The :class:`DMA` class offers access to the RP2040's Direct Memory Access (DMA) -controller, providing the ability move data between memory blocks and/or IO registers. The DMA +controller, providing the ability to move data between memory blocks and/or IO registers. The DMA controller has its own, separate read and write bus master connections onto the bus fabric and each DMA channel can independently read data from one address and write it back to another address, optionally incrementing one or both pointers, allowing it to perform transfers on behalf @@ -14,6 +14,10 @@ RP2040's DMA controller has 12 independent DMA channels that can run concurrentl details of the RP2040's DMA system see section 2.5 of the `RP2040 Datasheet `_. +The companion class :class:`DMATimer` provides access to the DMA controller's pacing timers. +These timers can be used to control the speed of transfers into memory or peripherals that do +not have their own transfer request signalling. + Examples -------- @@ -138,7 +142,8 @@ Methods disables chaining (this is the default). - *treq_sel*: ``int`` Select a Transfer Request signal. See section 2.5.3 in the RP2040 - datasheet for details. + datasheet for details. You may also pass a :class:`DMATimer` instance to use that timer + for pacing the transfer. - *irq_quiet*: ``bool`` Do not generate interrupt at the end of each transfer. Interrupts will instead be generated when a zero value is written to the trigger @@ -148,7 +153,7 @@ Methods - *bswap*: ``bool`` If set to true, bytes in words or half-words will be reversed before writing (default: ``True``). - - *sniff_en*: ``bool`` Set to ``True`` to allow data to be accessed by the chips sniff + - *sniff_en*: ``bool`` Set to ``True`` to allow data to be accessed by the chip's sniff hardware (default: ``False``). - *write_err*: ``bool`` Setting this to ``True`` will clear a previously reported write @@ -291,3 +296,69 @@ below is a Pythonic version of the example in sub-section 2.5.6.2. This example idles while waiting for the transfer to complete; alternatively it could set an interrupt handler and return immediately. + +class DMATimer -- pacing timers for DMA transfers +================================================= + +The RP2040 and RP2350 DMA controllers provide four "pacing" timers that can be used to +control the rate at which DMA transfers take place. In the absence of specifying a transfer +request signal using the ``treq_sel`` parameter in the control configuration the DMA controller +will try to transfer data as fast as the bus will allow, which can be as fast as the system +clock speed. Often I/O operations should happen +at some lower rate, and it is also sometimes valuable to moderate the rate of transfers from +memory to memory in order to avoid overloading the bus (particularly when using external +PSRAM, which is much slower than the on-chip SRAM). By using a :class:`DMATimer` the user +can select a rate that is a rational fraction of the system clock speed. Each timer can +independently trigger transfer requests at rate that is ``X/Y`` times the system clock, +where ``X < Y``. + +:class:`DMATimer` objects can be used directly as the value for treq_sel passed into the +:meth:`DMA.pack_ctrl()` function, since the value if ``int(dma_timer)`` is the index +of the transfer request selector for the timer. Thus if you want to pace a transfer to +run at 10,000 operations per second you can use:: + + dma = rp2.DMA() + timer = rp2.DMATimer(freq=10000) + ctrl = d.pack_ctrl(treq_sel=timer) # Default control value with paced by the timer + dma.config(read=src, write=dst, count=length, ctrl=ctrl, trigger=True) + +Note: The underlying DMA pacing timer will get released when a :class:`DMATimer` gets +garbage collected. If you are setting in motion a DMA transfer that is not expected to +complete before the timer object goes out of scope then it is a good idea to keep a +reference to it so that the timer does not get reassigned to some other caller (which +might change the frequency on you). + +Constructor +----------- + +.. class:: DMATimer(timer_id=None, *, freq=None, ratio=None) + + Claim one of the DMA pacing timers for exclusive use and optionally set the frequency or ratio. + + - *timer_id*: Which timer to use. Leave empty to select any unclaimed timer. + - *freq*: The optional value to assign to the :attr:`freq` attribute. + - *ratio*: The optional value to assign to the :attr:`ratio` attribute. + + If both ``freq`` and ``ratio`` are provided then ``ratio`` is used. + +Methods +------- + +.. method:: DMATimer.close() + + Release the exclusive claim on the underlying timer. + +Attributes +---------- + +.. attribute:: DMATimer.ratio + + Set or read the ``(X, Y)`` tuple for the system clock division ratio. When setting the ratio + both X and Y need to in the range 0 < X, Y < 65536. + +.. attribute:: DMATimer.freq + + Set or read the DMATimer frequency in Hz. When setting, the frequency will be set to the closest + frequency that can be achieved by the divider. Reading the frequency back will show the actual + selected frequency, to the nearest 1Hz. The requested value needs be less than or equal to the + system clock speed and greater than or equal to 1/65535 of the system clock. diff --git a/ports/rp2/modrp2.c b/ports/rp2/modrp2.c index 5a43c11e719..59c2eb54c05 100644 --- a/ports/rp2/modrp2.c +++ b/ports/rp2/modrp2.c @@ -95,6 +95,7 @@ static const mp_rom_map_elem_t rp2_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PIO), MP_ROM_PTR(&rp2_pio_type) }, { MP_ROM_QSTR(MP_QSTR_StateMachine), MP_ROM_PTR(&rp2_state_machine_type) }, { MP_ROM_QSTR(MP_QSTR_DMA), MP_ROM_PTR(&rp2_dma_type) }, + { MP_ROM_QSTR(MP_QSTR_DMATimer), MP_ROM_PTR(&rp2_dma_timer_type) }, { MP_ROM_QSTR(MP_QSTR_bootsel_button), MP_ROM_PTR(&rp2_bootsel_button_obj) }, #if MICROPY_PY_NETWORK_CYW43 diff --git a/ports/rp2/modrp2.h b/ports/rp2/modrp2.h index 9360acb4fb4..fc2c5fa9c9e 100644 --- a/ports/rp2/modrp2.h +++ b/ports/rp2/modrp2.h @@ -32,6 +32,7 @@ extern const mp_obj_type_t rp2_flash_type; extern const mp_obj_type_t rp2_pio_type; extern const mp_obj_type_t rp2_state_machine_type; extern const mp_obj_type_t rp2_dma_type; +extern const mp_obj_type_t rp2_dma_timer_type; void rp2_pio_init(void); void rp2_pio_deinit(void); diff --git a/ports/rp2/rp2_dma.c b/ports/rp2/rp2_dma.c index 7e4d3cd92bf..35dbd6a3f24 100644 --- a/ports/rp2/rp2_dma.c +++ b/ports/rp2/rp2_dma.c @@ -34,6 +34,7 @@ #include "hardware/irq.h" #include "hardware/dma.h" +#include "hardware/clocks.h" #define CHANNEL_CLOSED 0xff @@ -57,6 +58,216 @@ typedef struct _rp2_dma_ctrl_field_t { // 7 bits available here. } rp2_dma_ctrl_field_t; +typedef struct _rp2_dma_timer_obj_t { + mp_obj_base_t base; + uint8_t timer_id; + bool closed; +} rp2_dma_timer_obj_t; + + +#define DMA_TIMER_MAX_TERMS 65536 +static inline void rp2_timer_find_best_ratio(uint32_t p, uint32_t q, uint32_t *x, uint32_t *y) { + // Find the values x and y such that x/y is the closest fraction to p/q for which + // both terms are less than DMA_TIMER_MAX_TERMS. + + // This implementation computes the continued fraction and then checks if the + // best semi-convergent is obviously better (i.e. > a/2) + + uint32_t h_curr = 1, k_curr = 0; + uint32_t h_prev = 0, k_prev = 1; + + while (q != 0) { + uint32_t a = p / q; + uint32_t h_next = a * h_curr + h_prev; + uint32_t k_next = a * k_curr + k_prev; + + if (h_next >= DMA_TIMER_MAX_TERMS || k_next >= DMA_TIMER_MAX_TERMS) { + // The next convergent would overflow. Check if there is obviously a better semi-convergent. + // If there is a value of n that is >= a/2 then it will always be better than the current ratio. + uint32_t n = DMA_TIMER_MAX_TERMS; + if (h_curr) { + n = (DMA_TIMER_MAX_TERMS - 1 - h_prev) / h_curr; + } + if (k_curr) { + uint32_t nk = (DMA_TIMER_MAX_TERMS - 1 - k_prev) / k_curr; + if (nk < n) { + n = nk; + } + } + + if (n != DMA_TIMER_MAX_TERMS && n > 0 && n >= (a + 1) / 2) { + *x = n * h_curr + h_prev; + *y = n * k_curr + k_prev; + return; + } + // We didn't find a better n, so break out of the loop + break; + } + uint32_t r = p % q; + p = q; + q = r; + h_prev = h_curr; + k_prev = k_curr; + h_curr = h_next; + k_curr = k_next; + } + + *x = h_curr; + *y = k_curr; +} + +static void rp2_dma_timer_set_freq(rp2_dma_timer_obj_t *self, mp_obj_t f_obj) { + const mp_int_t freq = mp_obj_get_int(f_obj); + uint32_t sys_clk_hz = clock_get_hz(clk_sys); + + // Value needs to be between 1 and 1/65535 times the sysclk frequency + if (freq > sys_clk_hz || (sys_clk_hz / 65535) > freq) { + mp_raise_ValueError(MP_ERROR_TEXT("value out of range")); + } + uint32_t x, y; + rp2_timer_find_best_ratio(freq, sys_clk_hz, &x, &y); + dma_timer_set_fraction(self->timer_id, (uint16_t)x, (uint16_t)y); +} + +static void rp2_dma_timer_set_ratio(rp2_dma_timer_obj_t *self, mp_obj_t o) { + // Value needs to be a 2-tuple + mp_obj_t *num_dom; + mp_obj_get_array_fixed_n(o, 2, &num_dom); + + const mp_int_t numerator = mp_obj_get_int(num_dom[0]); + const mp_int_t denominator = mp_obj_get_int(num_dom[1]); + if (numerator < 1 || numerator > 65535 || denominator < 1 || denominator > 65535 || numerator > denominator) { + mp_raise_ValueError(MP_ERROR_TEXT("value out of range")); + } + dma_timer_set_fraction(self->timer_id, (uint16_t)numerator, (uint16_t)denominator); +} + +static mp_obj_t rp2_dma_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + enum { ARG_id, ARG_freq, ARG_ratio }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_ratio, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + mp_arg_val_t parsed[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, args, MP_ARRAY_SIZE(allowed_args), allowed_args, parsed); + + int dma_timer_id; + + if (parsed[ARG_id].u_obj != MP_OBJ_NULL) { + dma_timer_id = mp_obj_get_int(parsed[ARG_id].u_obj); + if (dma_timer_id < 0 || dma_timer_id >= 4) { + mp_raise_ValueError(MP_ERROR_TEXT("value out of range")); + } + if (dma_timer_is_claimed(dma_timer_id)) { + mp_raise_OSError(MP_EBUSY); + } + dma_timer_claim(dma_timer_id); + } else { + dma_timer_id = dma_claim_unused_timer(false); + if (dma_timer_id < 0) { + mp_raise_OSError(MP_EBUSY); + } + } + + rp2_dma_timer_obj_t *self = mp_obj_malloc_with_finaliser(rp2_dma_timer_obj_t, &rp2_dma_timer_type); + self->timer_id = dma_timer_id; + self->closed = false; + + // If you try to set both, "ratio" wins over "freq" + if (parsed[ARG_ratio].u_obj != MP_OBJ_NULL) { + rp2_dma_timer_set_ratio(self, parsed[ARG_ratio].u_obj); + } else if (parsed[ARG_freq].u_obj != MP_OBJ_NULL) { + rp2_dma_timer_set_freq(self, parsed[ARG_freq].u_obj); + } + + // Return the DMA object. + return MP_OBJ_FROM_PTR(self); +} + +static void rp2_dma_timer_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + rp2_dma_timer_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "%q(%u)", MP_QSTR_DMATimer, self->timer_id); +} + +static void rp2_dma_timer_attr(mp_obj_t self_in, qstr attr_in, mp_obj_t *dest) { + rp2_dma_timer_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (dest[0] == MP_OBJ_NULL) { + // Load attribute + if (attr_in == MP_QSTR_freq) { + uint32_t sys_clk_hz = clock_get_hz(clk_sys); + uint32_t reg_value = dma_hw->timer[self->timer_id]; + uint32_t num = (reg_value >> DMA_TIMER0_X_LSB) & 0xffff; + uint32_t dom = (reg_value >> DMA_TIMER0_Y_LSB) & 0xffff; + uint64_t fx = ((uint64_t)sys_clk_hz) * ((uint64_t)num); + fx /= dom; + dest[0] = mp_obj_new_int_from_uint((uint)fx); + } else if (attr_in == MP_QSTR_ratio) { + uint32_t reg_value = dma_hw->timer[self->timer_id]; + mp_obj_t num_dom[2]; + num_dom[0] = mp_obj_new_int_from_uint((reg_value >> DMA_TIMER0_X_LSB) & 0xffff); + num_dom[1] = mp_obj_new_int_from_uint((reg_value >> DMA_TIMER0_Y_LSB) & 0xffff); + + dest[0] = mp_obj_new_tuple(2, num_dom); + } else { + // Continue attribute search in locals dict. + dest[1] = MP_OBJ_SENTINEL; + } + } else { + // Set or delete attribute + if (dest[1] == MP_OBJ_NULL) { + // We don't support deleting attributes. + return; + } + + if (attr_in == MP_QSTR_freq) { + rp2_dma_timer_set_freq(self, dest[1]); + dest[0] = MP_OBJ_NULL; // indicate success + } else if (attr_in == MP_QSTR_ratio) { + rp2_dma_timer_set_ratio(self, dest[1]); + dest[0] = MP_OBJ_NULL; // indicate success + } + } +} + +static mp_obj_t rp2_dma_timer_unary_op(mp_unary_op_t op, mp_obj_t o_in) { + rp2_dma_timer_obj_t *self = MP_OBJ_TO_PTR(o_in); + if (op == MP_UNARY_OP_INT_MAYBE) { + // The value of int(timer) is the DMA pacing request index (treq_sel) + return mp_obj_new_int_from_uint((mp_uint_t)dma_get_timer_dreq(self->timer_id)); + } + return MP_OBJ_NULL; +} + +static mp_obj_t rp2_dma_timer_close(mp_obj_t self_in) { + rp2_dma_timer_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (!self->closed) { + dma_timer_unclaim(self->timer_id); + self->closed = true; + } + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_1(rp2_dma_timer_close_obj, rp2_dma_timer_close); + +static const mp_rom_map_elem_t rp2_dma_timer_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_close), MP_ROM_PTR(&rp2_dma_timer_close_obj) }, + { MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&rp2_dma_timer_close_obj) }, +}; +static MP_DEFINE_CONST_DICT(rp2_dma_timer_locals_dict, rp2_dma_timer_locals_dict_table); + + +MP_DEFINE_CONST_OBJ_TYPE( + rp2_dma_timer_type, + MP_QSTR_DMATimer, + MP_TYPE_FLAG_NONE, + make_new, rp2_dma_timer_make_new, + print, rp2_dma_timer_print, + attr, rp2_dma_timer_attr, + locals_dict, &rp2_dma_timer_locals_dict, + unary_op, rp2_dma_timer_unary_op + ); + static const rp2_dma_ctrl_field_t rp2_dma_ctrl_fields_table[] = { { MP_QSTR_enable, DMA_CH0_CTRL_TRIG_EN_LSB, 1, 0 }, { MP_QSTR_high_pri, DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB, 1, 0 }, @@ -158,7 +369,7 @@ static mp_obj_t rp2_dma_make_new(const mp_obj_type_t *type, size_t n_args, size_ return MP_OBJ_FROM_PTR(self); } -static void rp2_dma_error_if_closed(rp2_dma_obj_t *self) { +static void rp2_dma_error_if_closed(rp2_dma_obj_t const *self) { if (self->channel == CHANNEL_CLOSED) { mp_raise_ValueError(MP_ERROR_TEXT("channel closed")); } diff --git a/tests/ports/rp2/rp2_dma_timer.py b/tests/ports/rp2/rp2_dma_timer.py new file mode 100644 index 00000000000..f80981795c1 --- /dev/null +++ b/tests/ports/rp2/rp2_dma_timer.py @@ -0,0 +1,84 @@ +# Test rp2.DMATimer functionality. + +import time +import machine +import rp2 +import unittest + +K = 16 + +SRC = bytes(i & 0xFF for i in range(K << 10)) + + +class Test(unittest.TestCase): + def setUp(self): + self.timer = rp2.DMATimer(0) + self.dma = rp2.DMA() + + def tearDown(self): + self.dma.close() + self.timer.close() + + def test_printing(self): + timer = self.timer + self.assertEqual(str(timer), "DMATimer(0)") + + def test_set_ratio_unity(self): + timer = self.timer + timer.ratio = (1, 1) + self.assertEqual(timer.ratio, (1, 1)) + + def test_set_ratio(self): + timer = self.timer + timer.ratio = (1, 1) + base_clock = timer.freq + num, den = (47, 97) + target = base_clock * num // den + timer.ratio = (num, den) + self.assertEqual(timer.freq, target) + + def test_set_freq(self): + timer = self.timer + timer.ratio = (1, 1) + base_clock = timer.freq + num, den = (53, 101) + target = base_clock * num // den + timer.freq = target + self.assertEqual(timer.ratio, (num, den)) + + def test_speed_throttle(self): + def time_dma(d): + start = time.ticks_us() + d.active(1) + while d.active(): + pass + end = time.ticks_us() + return time.ticks_diff(end, start) + + speeds = [5000 * (10**i) for i in range(4)] + dma = self.dma + timer = self.timer + ctrl = dma.pack_ctrl(treq_sel=timer) + dest = bytearray(2048) + + times = [] + deltas = [] + + for i, speed in enumerate(speeds): + timer.freq = speed + dma.config(read=SRC, write=dest, count=len(dest) // 4, ctrl=ctrl) + t = time_dma(dma) + times.append(t) + if i > 0: + deltas.append(times[i - 1] - t) + + # The ratio between the first two times should be very close to 10 + self.assertIn(times[0] * 10 // times[1], range(95, 105)) + + # The ratios between successive deltas (which removes the overhead) should also be about 10 + for i in range(len(deltas) - 1): + self.assertIn(deltas[i] * 10 // deltas[i + 1], range(95, 105)) + + +if __name__ == "__main__": + unittest.main() From 7db3204ae9a2dd5e901179c35a9ff241adf80523 Mon Sep 17 00:00:00 2001 From: Ned Konz Date: Wed, 31 Dec 2025 13:14:11 -0800 Subject: [PATCH 126/635] rp2/rp2_pio: Correct bit access for rp2_state_machine_init. If you call `rp2.StateMachine.init()` with `pull_thresh=32` it will overwrite the FJOIN_TX bit in the SMx_SHIFTCTRL register. This commit fixes that issue. Signed-off-by: Ned Konz --- ports/rp2/rp2_pio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/rp2/rp2_pio.c b/ports/rp2/rp2_pio.c index 81351431cb9..945482d5e52 100644 --- a/ports/rp2/rp2_pio.c +++ b/ports/rp2/rp2_pio.c @@ -230,7 +230,7 @@ typedef struct _asm_pio_config_t { static void asm_pio_override_shiftctrl(mp_obj_t arg, uint32_t bits, uint32_t lsb, pio_sm_config *config) { if (arg != mp_const_none) { - config->shiftctrl = (config->shiftctrl & ~bits) | (mp_obj_get_int(arg) << lsb); + config->shiftctrl = (config->shiftctrl & ~bits) | ((mp_obj_get_int(arg) << lsb) & bits); } } From b9d709c590b344eb03fddb3924875a48f0c8e4e5 Mon Sep 17 00:00:00 2001 From: "David (Pololu)" Date: Tue, 27 Jan 2026 10:56:36 -0800 Subject: [PATCH 127/635] rp2/clocks_extra: Set VREG like the SDK does: needed for 200 MHz. The RP2040 now supports running at 200 MHz, but the datasheet says that speed requires an elevated core supply of 1.15 V. The SDK implements that in runtime_clocks_init, but we do not call that function because we override it in clocks_extra.c. Signed-off-by: David (Pololu) --- ports/rp2/clocks_extra.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/ports/rp2/clocks_extra.c b/ports/rp2/clocks_extra.c index ab3e6261f4b..db364397582 100644 --- a/ports/rp2/clocks_extra.c +++ b/ports/rp2/clocks_extra.c @@ -14,6 +14,7 @@ #include "hardware/irq.h" #include "hardware/gpio.h" #include "hardware/ticks.h" +#include "hardware/vreg.h" #if PICO_RP2040 // The RTC clock frequency is 48MHz divided by power of 2 (to ensure an integer @@ -86,6 +87,13 @@ void runtime_init_clocks_optional_usb(bool init_usb) { XOSC_HZ, XOSC_HZ); + #if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN) + if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) { + vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN); + busy_wait_at_least_cycles((uint32_t)((SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US * (uint64_t)XOSC_HZ) / 1000000)); + } + #endif + /// \tag::configure_clk_sys[] // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz clock_configure(clk_sys, From 45c67ab47000136b953bd2162abc6375d075b19e Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Thu, 7 May 2026 12:30:34 -0500 Subject: [PATCH 128/635] unix/coverage: Use SIZE_FMT for size_t printf args. Signed-off-by: Jeff Epler --- ports/unix/coverage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/unix/coverage.c b/ports/unix/coverage.c index b21de2a5eb6..e85539f39a6 100644 --- a/ports/unix/coverage.c +++ b/ports/unix/coverage.c @@ -669,10 +669,10 @@ static mp_obj_t extra_coverage(void) { mp_printf(&mp_plat_print, "mp_obj_list_optional_arg same list? %d\n", MP_OBJ_TO_PTR(list) == as_ptr); as_ptr = mp_obj_list_optional_arg(mp_const_none, list_len); - mp_printf(&mp_plat_print, "mp_obj_list_optional_arg new list len %d\n", as_ptr->len); + mp_printf(&mp_plat_print, "mp_obj_list_optional_arg new list len " SIZE_FMT "\n", as_ptr->len); as_ptr = mp_obj_list_optional_arg(MP_OBJ_NULL, list_len); - mp_printf(&mp_plat_print, "mp_obj_list_optional_arg new list from NULL len %d\n", as_ptr->len); + mp_printf(&mp_plat_print, "mp_obj_list_optional_arg new list from NULL len " SIZE_FMT "\n", as_ptr->len); } // runtime utils From 48a00ea637ff9e950aff0f2c405cfd8e4e595ae1 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Thu, 7 May 2026 14:11:34 -0500 Subject: [PATCH 129/635] extmod/machine_can: Use UINT_FMT for mp_uint_t printf arg. Signed-off-by: Jeff Epler --- extmod/machine_can.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/extmod/machine_can.c b/extmod/machine_can.c index 11577d9da94..57bf5b8ab6a 100644 --- a/extmod/machine_can.c +++ b/extmod/machine_can.c @@ -664,8 +664,8 @@ static void machine_can_print(const mp_print_t *print, mp_obj_t self_in, mp_prin break; } - mp_printf(print, "CAN(%d, bitrate=%u, mode=CAN.%q, sjw=%u, tseg1=%u, tseg2=%u, f_clock=%u)", - self->can_idx + 1, + mp_printf(print, "CAN(" UINT_FMT ", bitrate=%u, mode=CAN.%q, sjw=%u, tseg1=%u, tseg2=%u, f_clock=%u)", + self->can_idx + 1U, actual_bitrate, mode, self->sjw, From 1c63211817d9c5164542b94771634cf80b300fdf Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 1 May 2026 12:38:23 +0000 Subject: [PATCH 130/635] github/workflows: Bump actions/github-script from 8 to 9. Bumps [actions/github-script](https://github.com/actions/github-script) from 8 to 9. - [Release notes](https://github.com/actions/github-script/releases) - [Commits](https://github.com/actions/github-script/compare/v8...v9) --- updated-dependencies: - dependency-name: actions/github-script dependency-version: '9' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/code_size_comment.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/code_size_comment.yml b/.github/workflows/code_size_comment.yml index 2eed0b06b8e..ea9d45ddb87 100644 --- a/.github/workflows/code_size_comment.yml +++ b/.github/workflows/code_size_comment.yml @@ -15,7 +15,7 @@ jobs: steps: - name: 'Download artifact' id: download-artifact - uses: actions/github-script@v8 + uses: actions/github-script@v9 with: result-encoding: string script: | @@ -56,7 +56,7 @@ jobs: run: unzip code-size-report.zip - name: Post comment to pull request if: steps.download-artifact.outputs.result == 'ok' - uses: actions/github-script@v8 + uses: actions/github-script@v9 with: github-token: ${{secrets.GITHUB_TOKEN}} script: | From 89b924ffbd3e283c3d84e90d79f4df41955a951e Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 18 May 2026 14:07:10 +1000 Subject: [PATCH 131/635] lib/CMSIS_5: Add new submodule for CMSIS 5. At version 5.9.0, to replace the existing copy at `lib/cmsis`. Signed-off-by: Damien George --- .gitmodules | 3 +++ lib/CMSIS_5 | 1 + 2 files changed, 4 insertions(+) create mode 160000 lib/CMSIS_5 diff --git a/.gitmodules b/.gitmodules index d2c229dd6d7..29690552d4b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -74,3 +74,6 @@ [submodule "lib/alif-security-toolkit"] path = lib/alif-security-toolkit url = https://github.com/micropython/alif-security-toolkit.git +[submodule "lib/CMSIS_5"] + path = lib/CMSIS_5 + url = https://github.com/ARM-software/CMSIS_5.git diff --git a/lib/CMSIS_5 b/lib/CMSIS_5 new file mode 160000 index 00000000000..2b7495b8535 --- /dev/null +++ b/lib/CMSIS_5 @@ -0,0 +1 @@ +Subproject commit 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c From 6a5fb7d64406da366d5cd6a216e5220ec1f63fb7 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 18 May 2026 14:08:00 +1000 Subject: [PATCH 132/635] lib/CMSIS_6: Add new submodule for CMSIS 6. At version v6.3.0. Signed-off-by: Damien George --- .gitmodules | 3 +++ lib/CMSIS_6 | 1 + 2 files changed, 4 insertions(+) create mode 160000 lib/CMSIS_6 diff --git a/.gitmodules b/.gitmodules index 29690552d4b..9220232ac36 100644 --- a/.gitmodules +++ b/.gitmodules @@ -77,3 +77,6 @@ [submodule "lib/CMSIS_5"] path = lib/CMSIS_5 url = https://github.com/ARM-software/CMSIS_5.git +[submodule "lib/CMSIS_6"] + path = lib/CMSIS_6 + url = https://github.com/ARM-software/CMSIS_6.git diff --git a/lib/CMSIS_6 b/lib/CMSIS_6 new file mode 160000 index 00000000000..45dab712ad8 --- /dev/null +++ b/lib/CMSIS_6 @@ -0,0 +1 @@ +Subproject commit 45dab712ad84f8cbbf2b7bfc089c19088507df6f From 36d29c29e66f72479cdfed450db767d6b1bf088a Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 18 May 2026 14:12:14 +1000 Subject: [PATCH 133/635] ports: Switch ports to use lib/CMSIS_5 instead of lib/cmsis. This is a no-op change to the firmware because these CMSIS sources are equivalent (verified building the default board for all 6 affected ports). Signed-off-by: Damien George --- ports/alif/Makefile | 2 +- ports/alif/alif.mk | 2 +- ports/mimxrt/Makefile | 4 ++-- ports/nrf/Makefile | 4 ++-- ports/nrf/drivers/secureboot/secureboot.mk | 2 +- ports/renesas-ra/Makefile | 4 ++-- ports/samd/Makefile | 4 ++-- ports/stm32/Makefile | 4 ++-- ports/stm32/mboot/Makefile | 2 +- tools/ci.sh | 2 +- 10 files changed, 15 insertions(+), 15 deletions(-) diff --git a/ports/alif/Makefile b/ports/alif/Makefile index 0c02e170d95..1cde61cdb5b 100644 --- a/ports/alif/Makefile +++ b/ports/alif/Makefile @@ -2,7 +2,7 @@ BOARD ?= ALIF_ENSEMBLE BOARD_DIR ?= boards/$(BOARD) BUILD ?= build-$(BOARD) MCU_CORE ?= M55_HP -GIT_SUBMODULES += lib/tinyusb lib/alif_ensemble-cmsis-dfp lib/alif-security-toolkit +GIT_SUBMODULES += lib/CMSIS_5 lib/tinyusb lib/alif_ensemble-cmsis-dfp lib/alif-security-toolkit PORT ?= /dev/ttyACM0 ALIF_TOOLS ?= $(TOP)/lib/alif-security-toolkit/toolkit diff --git a/ports/alif/alif.mk b/ports/alif/alif.mk index 469e13f3ee1..22b2c33ec5a 100644 --- a/ports/alif/alif.mk +++ b/ports/alif/alif.mk @@ -27,7 +27,7 @@ MPY_CROSS_FLAGS += -march=armv7emdp CROSS_COMPILE ?= arm-none-eabi- ALIF_DFP_REL_TOP ?= lib/alif_ensemble-cmsis-dfp ALIF_DFP_REL_HERE ?= $(TOP)/lib/alif_ensemble-cmsis-dfp -CMSIS_DIR ?= $(TOP)/lib/cmsis/inc +CMSIS_DIR ?= $(TOP)/lib/CMSIS_5/CMSIS/Core/Include MCU_CORE ?= M55_HP LD_FILE ?= mcu/ensemble.ld.S diff --git a/ports/mimxrt/Makefile b/ports/mimxrt/Makefile index 5bf2690c236..f4ddc761087 100644 --- a/ports/mimxrt/Makefile +++ b/ports/mimxrt/Makefile @@ -20,7 +20,7 @@ endif BUILD ?= build-$(BOARD) PORT ?= /dev/ttyACM0 CROSS_COMPILE ?= arm-none-eabi- -GIT_SUBMODULES += lib/tinyusb lib/nxp_driver +GIT_SUBMODULES += lib/CMSIS_5 lib/tinyusb lib/nxp_driver UF2CONV ?= $(TOP)/tools/uf2conv.py # MicroPython feature configurations @@ -73,7 +73,7 @@ GEN_PINS_SRC = $(BUILD)/pins_gen.c INC += -I$(BOARD_DIR) INC += -I$(BUILD) INC += -I$(TOP) -INC += -I$(TOP)/lib/cmsis/inc +INC += -I$(TOP)/lib/CMSIS_5/CMSIS/Core/Include INC += -I$(TOP)/lib/oofatfs INC += -I$(TOP)/lib/tinyusb/hw INC += -I$(TOP)/lib/tinyusb/hw/bsp/teensy_40 diff --git a/ports/nrf/Makefile b/ports/nrf/Makefile index e39bf9639b8..7d276a1d852 100644 --- a/ports/nrf/Makefile +++ b/ports/nrf/Makefile @@ -64,7 +64,7 @@ FROZEN_MANIFEST ?= modules/manifest.py include ../../py/py.mk include ../../extmod/extmod.mk -GIT_SUBMODULES += lib/nrfx lib/tinyusb +GIT_SUBMODULES += lib/CMSIS_5 lib/nrfx lib/tinyusb MICROPY_VFS_FAT ?= 0 @@ -73,7 +73,7 @@ CROSS_COMPILE ?= arm-none-eabi- INC += -I. INC += -I../.. INC += -I$(BUILD) -INC += -I./../../lib/cmsis/inc +INC += -I./../../lib/CMSIS_5/CMSIS/Core/Include INC += -I./modules/machine INC += -I./modules/ubluepy INC += -I./modules/music diff --git a/ports/nrf/drivers/secureboot/secureboot.mk b/ports/nrf/drivers/secureboot/secureboot.mk index 89833cb6def..88c5154c7b7 100644 --- a/ports/nrf/drivers/secureboot/secureboot.mk +++ b/ports/nrf/drivers/secureboot/secureboot.mk @@ -15,7 +15,7 @@ SRC_SECUREBOOT += $(addprefix $(TOP)/lib/nrfx/mdk/,\ .PHONY: secureboot clean INC_SECUREBOOT += -I./../../lib/nrfx/mdk -INC_SECUREBOOT += -I./../../lib/cmsis/inc +INC_SECUREBOOT += -I./../../lib/CMSIS_5/CMSIS/Core/Include MCU_SERIES = m33 diff --git a/ports/renesas-ra/Makefile b/ports/renesas-ra/Makefile index 4a76d9dacc4..b9e68d99da1 100644 --- a/ports/renesas-ra/Makefile +++ b/ports/renesas-ra/Makefile @@ -43,13 +43,13 @@ FROZEN_MANIFEST ?= boards/manifest.py include $(TOP)/py/py.mk include $(TOP)/extmod/extmod.mk -GIT_SUBMODULES += lib/fsp lib/tinyusb +GIT_SUBMODULES += lib/CMSIS_5 lib/fsp lib/tinyusb MCU_SERIES_UPPER = $(shell echo $(MCU_SERIES) | tr '[:lower:]' '[:upper:]') CMSIS_MCU_LOWER = $(shell echo $(CMSIS_MCU) | tr '[:upper:]' '[:lower:]') LD_DIR=boards -CMSIS_DIR=lib/cmsis/inc +CMSIS_DIR=lib/CMSIS_5/CMSIS/Core/Include HAL_DIR=lib/fsp STARTUP_FILE ?= lib/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o SYSTEM_FILE ?= lib/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o diff --git a/ports/samd/Makefile b/ports/samd/Makefile index 150fc19958d..7eb7e06861c 100644 --- a/ports/samd/Makefile +++ b/ports/samd/Makefile @@ -52,14 +52,14 @@ FROZEN_MANIFEST ?= boards/manifest.py include $(TOP)/py/py.mk include $(TOP)/extmod/extmod.mk -GIT_SUBMODULES += lib/asf4 lib/tinyusb +GIT_SUBMODULES += lib/CMSIS_5 lib/asf4 lib/tinyusb INC += -I. INC += -I$(TOP) INC += -I$(BUILD) INC += -I$(BOARD_DIR) INC += -Imcu/$(MCU_SERIES_LOWER) -INC += -I$(TOP)/lib/cmsis/inc +INC += -I$(TOP)/lib/CMSIS_5/CMSIS/Core/Include INC += -I$(TOP)/lib/asf4/$(MCU_SERIES_LOWER)/hal/include INC += -I$(TOP)/lib/asf4/$(MCU_SERIES_LOWER)/hal/utils/include INC += -I$(TOP)/lib/asf4/$(MCU_SERIES_LOWER)/config diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index b212abae621..6e5df0d8188 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -58,7 +58,7 @@ MBOOT_TEXT0_ADDR ?= 0x08000000 include $(TOP)/py/py.mk include $(TOP)/extmod/extmod.mk -GIT_SUBMODULES += lib/libhydrogen lib/stm32lib lib/tinyusb +GIT_SUBMODULES += lib/CMSIS_5 lib/libhydrogen lib/stm32lib lib/tinyusb CROSS_COMPILE ?= arm-none-eabi- LD_DIR=boards @@ -105,7 +105,7 @@ CMSIS_MCU_HDR = $(STM32LIB_CMSIS_ABS)/Include/$(CMSIS_MCU_LOWER).h INC += -I. INC += -I$(TOP) INC += -I$(BUILD) -INC += -I$(TOP)/lib/cmsis/inc +INC += -I$(TOP)/lib/CMSIS_5/CMSIS/Core/Include INC += -I$(STM32LIB_CMSIS_ABS)/Include INC += -I$(STM32LIB_HAL_ABS)/Inc INC += -I$(USBDEV_DIR)/core/inc -I$(USBDEV_DIR)/class/inc diff --git a/ports/stm32/mboot/Makefile b/ports/stm32/mboot/Makefile index fe343f90ae7..da159e39880 100755 --- a/ports/stm32/mboot/Makefile +++ b/ports/stm32/mboot/Makefile @@ -64,7 +64,7 @@ INC += -I. INC += -I.. INC += -I$(TOP) INC += -I$(BUILD) -INC += -I$(TOP)/lib/cmsis/inc +INC += -I$(TOP)/lib/CMSIS_5/CMSIS/Core/Include INC += -I$(STM32LIB_CMSIS_ABS)/Include INC += -I$(STM32LIB_HAL_ABS)/Inc INC += -I../$(USBDEV_DIR)/core/inc -I../$(USBDEV_DIR)/class/inc diff --git a/tools/ci.sh b/tools/ci.sh index fbdec9c3a88..89ba973ebd6 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -91,7 +91,7 @@ function ci_code_size_build { # Override the list by setting PORTS_TO_CHECK in the environment before invoking ci. : ${PORTS_TO_CHECK:=bmus3xpdv} - SUBMODULES="lib/asf4 lib/berkeley-db-1.xx lib/btstack lib/cyw43-driver lib/lwip lib/mbedtls lib/micropython-lib lib/nxp_driver lib/pico-sdk lib/stm32lib lib/tinyusb" + SUBMODULES="lib/CMSIS_5 lib/CMSIS_6 lib/asf4 lib/berkeley-db-1.xx lib/btstack lib/cyw43-driver lib/lwip lib/mbedtls lib/micropython-lib lib/nxp_driver lib/pico-sdk lib/stm32lib lib/tinyusb" # Default GitHub pull request sets HEAD to a generated merge commit # between PR branch (HEAD^2) and base branch (i.e. master) (HEAD^1). From a22c79b2c460a86ecee0ebd3523537beb4b89edb Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 18 May 2026 14:16:23 +1000 Subject: [PATCH 134/635] lib/cmsis: Remove copy of CMSIS 5. This is now replaced by the `lib/CMSIS_5` submodule, which has exactly the same content at the 5.9.0 tag in the directory `CMSIS/Core/Include`. Signed-off-by: Damien George --- lib/cmsis/inc/cachel1_armv7.h | 411 --- lib/cmsis/inc/cmsis_armcc.h | 888 ----- lib/cmsis/inc/cmsis_armclang.h | 1503 --------- lib/cmsis/inc/cmsis_armclang_ltm.h | 1928 ----------- lib/cmsis/inc/cmsis_compiler.h | 283 -- lib/cmsis/inc/cmsis_gcc.h | 2211 ------------- lib/cmsis/inc/cmsis_iccarm.h | 1002 ------ lib/cmsis/inc/cmsis_version.h | 39 - lib/cmsis/inc/core_armv81mml.h | 4228 ------------------------ lib/cmsis/inc/core_armv8mbl.h | 2222 ------------- lib/cmsis/inc/core_armv8mml.h | 3209 ------------------ lib/cmsis/inc/core_cm0.h | 952 ------ lib/cmsis/inc/core_cm0plus.h | 1087 ------- lib/cmsis/inc/core_cm1.h | 979 ------ lib/cmsis/inc/core_cm23.h | 2297 ------------- lib/cmsis/inc/core_cm3.h | 1943 ----------- lib/cmsis/inc/core_cm33.h | 3277 ------------------- lib/cmsis/inc/core_cm35p.h | 3277 ------------------- lib/cmsis/inc/core_cm4.h | 2129 ------------ lib/cmsis/inc/core_cm55.h | 4817 ---------------------------- lib/cmsis/inc/core_cm7.h | 2366 -------------- lib/cmsis/inc/core_cm85.h | 4672 --------------------------- lib/cmsis/inc/core_sc000.h | 1030 ------ lib/cmsis/inc/core_sc300.h | 1917 ----------- lib/cmsis/inc/core_starmc1.h | 3592 --------------------- lib/cmsis/inc/mpu_armv7.h | 275 -- lib/cmsis/inc/mpu_armv8.h | 352 -- lib/cmsis/inc/pac_armv81.h | 206 -- lib/cmsis/inc/pmu_armv8.h | 337 -- lib/cmsis/inc/tz_context.h | 70 - 30 files changed, 53499 deletions(-) delete mode 100644 lib/cmsis/inc/cachel1_armv7.h delete mode 100644 lib/cmsis/inc/cmsis_armcc.h delete mode 100644 lib/cmsis/inc/cmsis_armclang.h delete mode 100644 lib/cmsis/inc/cmsis_armclang_ltm.h delete mode 100644 lib/cmsis/inc/cmsis_compiler.h delete mode 100644 lib/cmsis/inc/cmsis_gcc.h delete mode 100644 lib/cmsis/inc/cmsis_iccarm.h delete mode 100644 lib/cmsis/inc/cmsis_version.h delete mode 100644 lib/cmsis/inc/core_armv81mml.h delete mode 100644 lib/cmsis/inc/core_armv8mbl.h delete mode 100644 lib/cmsis/inc/core_armv8mml.h delete mode 100644 lib/cmsis/inc/core_cm0.h delete mode 100644 lib/cmsis/inc/core_cm0plus.h delete mode 100644 lib/cmsis/inc/core_cm1.h delete mode 100644 lib/cmsis/inc/core_cm23.h delete mode 100644 lib/cmsis/inc/core_cm3.h delete mode 100644 lib/cmsis/inc/core_cm33.h delete mode 100644 lib/cmsis/inc/core_cm35p.h delete mode 100644 lib/cmsis/inc/core_cm4.h delete mode 100644 lib/cmsis/inc/core_cm55.h delete mode 100644 lib/cmsis/inc/core_cm7.h delete mode 100644 lib/cmsis/inc/core_cm85.h delete mode 100644 lib/cmsis/inc/core_sc000.h delete mode 100644 lib/cmsis/inc/core_sc300.h delete mode 100644 lib/cmsis/inc/core_starmc1.h delete mode 100644 lib/cmsis/inc/mpu_armv7.h delete mode 100644 lib/cmsis/inc/mpu_armv8.h delete mode 100644 lib/cmsis/inc/pac_armv81.h delete mode 100644 lib/cmsis/inc/pmu_armv8.h delete mode 100644 lib/cmsis/inc/tz_context.h diff --git a/lib/cmsis/inc/cachel1_armv7.h b/lib/cmsis/inc/cachel1_armv7.h deleted file mode 100644 index abebc95f946..00000000000 --- a/lib/cmsis/inc/cachel1_armv7.h +++ /dev/null @@ -1,411 +0,0 @@ -/****************************************************************************** - * @file cachel1_armv7.h - * @brief CMSIS Level 1 Cache API for Armv7-M and later - * @version V1.0.1 - * @date 19. April 2021 - ******************************************************************************/ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_CACHEL1_ARMV7_H -#define ARM_CACHEL1_ARMV7_H - -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#ifndef __SCB_DCACHE_LINE_SIZE -#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -#ifndef __SCB_ICACHE_LINE_SIZE -#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ - -#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/lib/cmsis/inc/cmsis_armcc.h b/lib/cmsis/inc/cmsis_armcc.h deleted file mode 100644 index a955d471391..00000000000 --- a/lib/cmsis/inc/cmsis_armcc.h +++ /dev/null @@ -1,888 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.3.2 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - /* __ARM_ARCH_8_1M_MAIN__ not applicable */ - -/* CMSIS compiler control DSP macros */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __ARM_FEATURE_DSP 1 -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __memory_changed() -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; - __ISB(); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/lib/cmsis/inc/cmsis_armclang.h b/lib/cmsis/inc/cmsis_armclang.h deleted file mode 100644 index 69114177477..00000000000 --- a/lib/cmsis/inc/cmsis_armclang.h +++ /dev/null @@ -1,1503 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.4.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -#define __SADD8 __builtin_arm_sadd8 -#define __QADD8 __builtin_arm_qadd8 -#define __SHADD8 __builtin_arm_shadd8 -#define __UADD8 __builtin_arm_uadd8 -#define __UQADD8 __builtin_arm_uqadd8 -#define __UHADD8 __builtin_arm_uhadd8 -#define __SSUB8 __builtin_arm_ssub8 -#define __QSUB8 __builtin_arm_qsub8 -#define __SHSUB8 __builtin_arm_shsub8 -#define __USUB8 __builtin_arm_usub8 -#define __UQSUB8 __builtin_arm_uqsub8 -#define __UHSUB8 __builtin_arm_uhsub8 -#define __SADD16 __builtin_arm_sadd16 -#define __QADD16 __builtin_arm_qadd16 -#define __SHADD16 __builtin_arm_shadd16 -#define __UADD16 __builtin_arm_uadd16 -#define __UQADD16 __builtin_arm_uqadd16 -#define __UHADD16 __builtin_arm_uhadd16 -#define __SSUB16 __builtin_arm_ssub16 -#define __QSUB16 __builtin_arm_qsub16 -#define __SHSUB16 __builtin_arm_shsub16 -#define __USUB16 __builtin_arm_usub16 -#define __UQSUB16 __builtin_arm_uqsub16 -#define __UHSUB16 __builtin_arm_uhsub16 -#define __SASX __builtin_arm_sasx -#define __QASX __builtin_arm_qasx -#define __SHASX __builtin_arm_shasx -#define __UASX __builtin_arm_uasx -#define __UQASX __builtin_arm_uqasx -#define __UHASX __builtin_arm_uhasx -#define __SSAX __builtin_arm_ssax -#define __QSAX __builtin_arm_qsax -#define __SHSAX __builtin_arm_shsax -#define __USAX __builtin_arm_usax -#define __UQSAX __builtin_arm_uqsax -#define __UHSAX __builtin_arm_uhsax -#define __USAD8 __builtin_arm_usad8 -#define __USADA8 __builtin_arm_usada8 -#define __SSAT16 __builtin_arm_ssat16 -#define __USAT16 __builtin_arm_usat16 -#define __UXTB16 __builtin_arm_uxtb16 -#define __UXTAB16 __builtin_arm_uxtab16 -#define __SXTB16 __builtin_arm_sxtb16 -#define __SXTAB16 __builtin_arm_sxtab16 -#define __SMUAD __builtin_arm_smuad -#define __SMUADX __builtin_arm_smuadx -#define __SMLAD __builtin_arm_smlad -#define __SMLADX __builtin_arm_smladx -#define __SMLALD __builtin_arm_smlald -#define __SMLALDX __builtin_arm_smlaldx -#define __SMUSD __builtin_arm_smusd -#define __SMUSDX __builtin_arm_smusdx -#define __SMLSD __builtin_arm_smlsd -#define __SMLSDX __builtin_arm_smlsdx -#define __SMLSLD __builtin_arm_smlsld -#define __SMLSLDX __builtin_arm_smlsldx -#define __SEL __builtin_arm_sel -#define __QADD __builtin_arm_qadd -#define __QSUB __builtin_arm_qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/lib/cmsis/inc/cmsis_armclang_ltm.h b/lib/cmsis/inc/cmsis_armclang_ltm.h deleted file mode 100644 index 1e255d5907f..00000000000 --- a/lib/cmsis/inc/cmsis_armclang_ltm.h +++ /dev/null @@ -1,1928 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang_ltm.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.5.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/lib/cmsis/inc/cmsis_compiler.h b/lib/cmsis/inc/cmsis_compiler.h deleted file mode 100644 index adbf296f15a..00000000000 --- a/lib/cmsis/inc/cmsis_compiler.h +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/lib/cmsis/inc/cmsis_gcc.h b/lib/cmsis/inc/cmsis_gcc.h deleted file mode 100644 index 67bda4ef3c3..00000000000 --- a/lib/cmsis/inc/cmsis_gcc.h +++ /dev/null @@ -1,2211 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.4.1 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -#define __USAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); - } else { - result = __SXTB16(__ROR(op1, rotate)) ; - } - return result; -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); - } else { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; -} - - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/lib/cmsis/inc/cmsis_iccarm.h b/lib/cmsis/inc/cmsis_iccarm.h deleted file mode 100644 index 65b824b009c..00000000000 --- a/lib/cmsis/inc/cmsis_iccarm.h +++ /dev/null @@ -1,1002 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.3.0 - * @date 14. April 2021 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2021 IAR Systems -// Copyright (c) 2017-2021 Arm Limited. All rights reserved. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#undef __WEAK /* undo the definition from DLib_Defaults.h */ -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - -#ifndef __PROGRAM_START -#define __PROGRAM_START __iar_program_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP CSTACK$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT CSTACK$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __vector_table -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE @".intvec" -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL STACKSEAL$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __arm_wsr("CONTROL", control); - __iar_builtin_ISB(); -} - - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __arm_wsr("CONTROL_NS", control); - __iar_builtin_ISB(); -} - - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - __iar_builtin_ISB(); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/lib/cmsis/inc/cmsis_version.h b/lib/cmsis/inc/cmsis_version.h deleted file mode 100644 index 8b4765f186e..00000000000 --- a/lib/cmsis/inc/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.5 - * @date 02. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/lib/cmsis/inc/core_armv81mml.h b/lib/cmsis/inc/core_armv81mml.h deleted file mode 100644 index 94128a1a709..00000000000 --- a/lib/cmsis/inc/core_armv81mml.h +++ /dev/null @@ -1,4228 +0,0 @@ -/**************************************************************************//** - * @file core_armv81mml.h - * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File - * @version V1.4.2 - * @date 13. October 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_ARMV81MML_H_GENERIC -#define __CORE_ARMV81MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMV81MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS ARMV81MML definitions */ -#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -#if defined ( __CC_ARM ) - #error Legacy Arm Compiler does not support Armv8.1-M target architecture. -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV81MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV81MML_H_DEPENDANT -#define __CORE_ARMV81MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv81MML_REV - #define __ARMv81MML_REV 0x0000U - #warning "__ARMv81MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #if __FPU_PRESENT != 0U - #ifndef __FPU_DP - #define __FPU_DP 0U - #warning "__FPU_DP not defined in device header file; using default!" - #endif - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __PMU_PRESENT - #define __PMU_PRESENT 0U - #warning "__PMU_PRESENT not defined in device header file; using default!" - #endif - - #if __PMU_PRESENT != 0U - #ifndef __PMU_NUM_EVENTCNT - #define __PMU_NUM_EVENTCNT 2U - #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" - #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) - #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ - #endif - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv81MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ - uint32_t RESERVED4[14U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ -#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ - -#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ -#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ -#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ - -#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ -#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ - -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ -#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ - -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ -#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ - -#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ -#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ - -#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ -#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ - -#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ -#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ - -#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ -#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ - -#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ -#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ - -#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ -#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ - -#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ -#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ - -/* SCB Debug Feature Register 0 Definitions */ -#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ -#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ - -#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ -#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB RAS Fault Status Register Definitions */ -#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ -#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ - -#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ -#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ - -#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ -#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[3U]; - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ -#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) - \brief Type definitions for the Performance Monitoring Unit (PMU) - @{ - */ - -/** - \brief Structure type to access the Performance Monitoring Unit (PMU). - */ -typedef struct -{ - __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ - uint32_t RESERVED1[224]; - __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ - uint32_t RESERVED3[480]; - __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ - uint32_t RESERVED4[7]; - __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ - uint32_t RESERVED5[7]; - __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ - uint32_t RESERVED6[7]; - __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ - uint32_t RESERVED7[7]; - __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ - uint32_t RESERVED8[7]; - __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ - uint32_t RESERVED9[7]; - __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ - uint32_t RESERVED10[79]; - __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ - uint32_t RESERVED11[108]; - __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ - __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ - uint32_t RESERVED12[3]; - __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ - __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ - uint32_t RESERVED13[3]; - __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ - __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ - __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ - __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ - __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ - __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ - __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ - __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ -} PMU_Type; - -/** \brief PMU Event Counter Registers (0-30) Definitions */ - -#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ -#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ - -/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ - -#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ -#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ - -/** \brief PMU Count Enable Set Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ -#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ - -#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ -#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ - -#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ -#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ - -#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ -#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ - -#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ -#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ - -#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ -#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ - -#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ -#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ - -#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ -#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ - -#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ -#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ - -#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ -#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ - -#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ -#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ - -#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ -#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ - -#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ -#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ - -#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ -#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ - -#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ -#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ - -#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ -#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ - -#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ -#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ - -#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ -#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ - -#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ -#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ - -#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ -#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ - -#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ -#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ - -#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ -#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ - -#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ -#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ - -#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ -#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ - -#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ -#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ - -#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ -#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ - -#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ -#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ - -#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ -#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ - -#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ -#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ - -#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ -#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ - -#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ -#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ - -#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ -#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ - -/** \brief PMU Count Enable Clear Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ -#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ -#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ - -#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ -#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ -#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ -#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ -#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ -#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ -#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ -#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ -#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ -#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ -#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ -#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ -#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ -#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ -#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ -#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ -#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ -#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ -#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ -#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ -#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ -#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ -#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ -#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ -#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ -#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ -#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ -#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ -#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ -#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ - -#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ -#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ - -/** \brief PMU Interrupt Enable Set Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ -#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ - -/** \brief PMU Interrupt Enable Clear Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ - -#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ - -/** \brief PMU Overflow Flag Status Set Register Definitions */ - -#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ -#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ - -#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ -#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ - -#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ -#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ - -#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ -#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ - -#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ -#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ - -#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ -#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ - -#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ -#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ - -#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ -#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ - -#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ -#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ - -#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ -#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ - -#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ -#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ - -#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ -#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ - -#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ -#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ - -#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ -#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ - -#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ -#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ - -#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ -#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ - -#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ -#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ - -#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ -#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ - -#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ -#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ - -#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ -#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ - -#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ -#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ - -#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ -#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ - -#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ -#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ - -#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ -#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ - -#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ -#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ - -#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ -#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ - -#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ -#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ - -#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ -#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ - -#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ -#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ - -#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ -#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ - -#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ -#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ - -#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ -#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ - -/** \brief PMU Overflow Flag Status Clear Register Definitions */ - -#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ -#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ -#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ - -#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ -#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ -#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ -#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ -#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ -#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ -#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ -#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ -#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ -#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ -#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ -#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ -#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ -#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ -#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ -#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ -#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ -#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ -#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ -#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ -#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ -#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ -#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ -#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ -#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ -#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ -#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ -#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ -#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ -#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ - -#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ -#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ - -/** \brief PMU Software Increment Counter */ - -#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ -#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ - -#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ -#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ - -#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ -#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ - -#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ -#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ - -#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ -#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ - -#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ -#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ - -#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ -#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ - -#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ -#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ - -#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ -#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ - -#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ -#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ - -#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ -#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ - -#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ -#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ - -#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ -#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ - -#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ -#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ - -#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ -#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ - -#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ -#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ - -#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ -#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ - -#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ -#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ - -#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ -#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ - -#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ -#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ - -#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ -#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ - -#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ -#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ - -#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ -#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ - -#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ -#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ - -#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ -#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ - -#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ -#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ - -#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ -#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ - -#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ -#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ - -#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ -#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ - -#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ -#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ - -#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ -#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ - -/** \brief PMU Control Register Definitions */ - -#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ -#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ - -#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ -#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ -#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ -#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ - -#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ -#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ - -#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ -#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ - -/** \brief PMU Type Register Definitions */ - -#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ -#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ - -#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ -#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ - -#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ -#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ - -#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ -#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ - -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ - -/** \brief PMU Authentication Status Register Definitions */ - -#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ - -/*@} end of group CMSIS_PMU */ -#endif - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ -#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ - -#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ -#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ -#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ - -#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ -#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ - -#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ -#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ -#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ - -#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ -#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ - -#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ -#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ -#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ - -#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ -#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ - -#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ -#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ - -#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ -#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ - -#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ -#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ - -#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ -#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ -#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ - -#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ -#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ - -#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ -#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ - -#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ -#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ -#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Set Clear Exception and Monitor Control Register Definitions */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ - -#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ -#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ -#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ - -#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ -#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ -#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ -#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ - -#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ -#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ - -#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ -#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ - -#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ -#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ -#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ - -#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ -#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ - -#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ -#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ - -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ -#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ - -#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ - #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## PMU functions and events #################################### */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - -#include "pmu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - -/* ########################## MVE functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_MveFunctions MVE Functions - \brief Function that provides MVE type. - @{ - */ - -/** - \brief get MVE type - \details returns the MVE type - \returns - - \b 0: No Vector Extension (MVE) - - \b 1: Integer Vector Extension (MVE-I) - - \b 2: Floating-point Vector Extension (MVE-F) - */ -__STATIC_INLINE uint32_t SCB_GetMVEType(void) -{ - const uint32_t mvfr1 = FPU->MVFR1; - if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) - { - return 2U; - } - else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) - { - return 1U; - } - else - { - return 0U; - } -} - - -/*@} end of CMSIS_Core_MveFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV81MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_armv8mbl.h b/lib/cmsis/inc/core_armv8mbl.h deleted file mode 100644 index 932d3d188bf..00000000000 --- a/lib/cmsis/inc/core_armv8mbl.h +++ /dev/null @@ -1,2222 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 27. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_armv8mml.h b/lib/cmsis/inc/core_armv8mml.h deleted file mode 100644 index c119fbf2424..00000000000 --- a/lib/cmsis/inc/core_armv8mml.h +++ /dev/null @@ -1,3209 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.2.3 - * @date 13. October 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS Armv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (80U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm0.h b/lib/cmsis/inc/core_cm0.h deleted file mode 100644 index 6441ff34190..00000000000 --- a/lib/cmsis/inc/core_cm0.h +++ /dev/null @@ -1,952 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 21. August 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ - /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm0plus.h b/lib/cmsis/inc/core_cm0plus.h deleted file mode 100644 index 4e7179a6146..00000000000 --- a/lib/cmsis/inc/core_cm0plus.h +++ /dev/null @@ -1,1087 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.9 - * @date 21. August 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -#else - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ -#endif - /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -#else - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ -#endif -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm1.h b/lib/cmsis/inc/core_cm1.h deleted file mode 100644 index 76b4569743a..00000000000 --- a/lib/cmsis/inc/core_cm1.h +++ /dev/null @@ -1,979 +0,0 @@ -/**************************************************************************//** - * @file core_cm1.h - * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File - * @version V1.0.1 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM1_H_GENERIC -#define __CORE_CM1_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M1 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM1 definitions */ -#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ - __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (1U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM1_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM1_H_DEPENDANT -#define __CORE_CM1_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM1_REV - #define __CM1_REV 0x0100U - #warning "__CM1_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M1 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ -#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ - -#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ -#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M1 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM1_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm23.h b/lib/cmsis/inc/core_cm23.h deleted file mode 100644 index 55fff995096..00000000000 --- a/lib/cmsis/inc/core_cm23.h +++ /dev/null @@ -1,2297 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 11. February 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm3.h b/lib/cmsis/inc/core_cm3.h deleted file mode 100644 index 74fb87e5c56..00000000000 --- a/lib/cmsis/inc/core_cm3.h +++ /dev/null @@ -1,1943 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.1.2 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ -#endif - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm33.h b/lib/cmsis/inc/core_cm33.h deleted file mode 100644 index 18a2e6fb034..00000000000 --- a/lib/cmsis/inc/core_cm33.h +++ /dev/null @@ -1,3277 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.2.3 - * @date 13. October 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm35p.h b/lib/cmsis/inc/core_cm35p.h deleted file mode 100644 index 3843d9542c5..00000000000 --- a/lib/cmsis/inc/core_cm35p.h +++ /dev/null @@ -1,3277 +0,0 @@ -/**************************************************************************//** - * @file core_cm35p.h - * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File - * @version V1.1.3 - * @date 13. October 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM35P_H_GENERIC -#define __CORE_CM35P_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M35P - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM35P definitions */ -#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ - __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (35U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM35P_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM35P_H_DEPENDANT -#define __CORE_CM35P_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM35P_REV - #define __CM35P_REV 0x0000U - #warning "__CM35P_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M35P */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM35P_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm4.h b/lib/cmsis/inc/core_cm4.h deleted file mode 100644 index e21cd149256..00000000000 --- a/lib/cmsis/inc/core_cm4.h +++ /dev/null @@ -1,2129 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.1.2 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ -#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ -#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm55.h b/lib/cmsis/inc/core_cm55.h deleted file mode 100644 index faa30ce36a9..00000000000 --- a/lib/cmsis/inc/core_cm55.h +++ /dev/null @@ -1,4817 +0,0 @@ -/**************************************************************************//** - * @file core_cm55.h - * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File - * @version V1.2.4 - * @date 21. April 2022 - ******************************************************************************/ -/* - * Copyright (c) 2018-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM55_H_GENERIC -#define __CORE_CM55_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M55 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM55 definitions */ -#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ - __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (55U) /*!< Cortex-M Core */ - -#if defined ( __CC_ARM ) - #error Legacy Arm Compiler does not support Armv8.1-M target architecture. -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM55_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM55_H_DEPENDANT -#define __CORE_CM55_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM55_REV - #define __CM55_REV 0x0000U - #warning "__CM55_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #if __FPU_PRESENT != 0U - #ifndef __FPU_DP - #define __FPU_DP 0U - #warning "__FPU_DP not defined in device header file; using default!" - #endif - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __PMU_PRESENT - #define __PMU_PRESENT 0U - #warning "__PMU_PRESENT not defined in device header file; using default!" - #endif - - #if __PMU_PRESENT != 0U - #ifndef __PMU_NUM_EVENTCNT - #define __PMU_NUM_EVENTCNT 8U - #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" - #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) - #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ - #endif - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M55 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core EWIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core PMU Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ - uint32_t RESERVED4[14U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ -#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ - -#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ -#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ -#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ - -#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ -#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ - -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ -#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ - -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ -#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ - -#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ -#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ - -#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ -#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ - -#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ -#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ - -#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ -#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ - -#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ -#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ - -#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ -#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ - -#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ -#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ - -/* SCB Debug Feature Register 0 Definitions */ -#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ -#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ - -#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ -#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB RAS Fault Status Register Definitions */ -#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ -#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ - -#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ -#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ - -#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ -#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ICB Implementation Control Block register (ICB) - \brief Type definitions for the Implementation Control Block Register - @{ - */ - -/** - \brief Structure type to access the Implementation Control Block (ICB). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} ICB_Type; - -/* Auxiliary Control Register Definitions */ -#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ -#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ - -#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ -#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ - -#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ -#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ - -#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ -#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ - -#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ -#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ - -#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ -#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ - -#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ -#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ - -#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ -#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ - -#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ -#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ - -#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ -#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ - -#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ -#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ - -#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -/* Interrupt Controller Type Register Definitions */ -#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_ICB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[3U]; - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) - @{ - */ - -/** - \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). - */ -typedef struct -{ - __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ - __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ - uint32_t RESERVED1[2U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ - __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ - uint32_t RESERVED2[313U]; - __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ - __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ - uint32_t RESERVED3[2U]; - __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ - uint32_t RESERVED4[44U]; - __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ - __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ - uint32_t RESERVED5[2U]; - __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ -} MemSysCtl_Type; - -/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ -#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ -#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ - -#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ -#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ - -#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ -#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ - -#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ -#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ - -#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ -#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ - -#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ -#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ - -#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ -#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ - -#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ -#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ - -/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ -#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ -#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ - -#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ -#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ - -#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ -#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ - -#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ -#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ - -/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ -#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ -#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ - -#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ -#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ - -/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ -#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ -#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ - -#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ -#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ - -/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ -#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ -#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ - -#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ -#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ - -/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ -#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ -#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ - -#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ -#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ - -/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ -#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ -#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ - -#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ -#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ - -#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ -#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ - -/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ -#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ -#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ - -#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ -#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ - -/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ -#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ -#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ - -#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ -#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ - -#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ -#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ - - -/*@}*/ /* end of group MemSysCtl_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup PwrModCtl_Type Power Mode Control Registers - \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) - @{ - */ - -/** - \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). - */ -typedef struct -{ - __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ - __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ -} PwrModCtl_Type; - -/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ -#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ - -#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ - -#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ - -/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ -#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ -#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ - -/*@}*/ /* end of group PwrModCtl_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup EWIC_Type External Wakeup Interrupt Controller Registers - \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) - @{ - */ - -/** - \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). - */ -typedef struct -{ - __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ - uint32_t RESERVED0[31U]; - __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ - __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ -} EWIC_Type; - -/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ -#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ -#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ - -#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ -#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ - -#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ -#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ - -/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ -#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ -#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ - -#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ -#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ - -#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ -#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ - -/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ -#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ -#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ - -/*@}*/ /* end of group EWIC_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Error Banking Registers (ERRBNK) - @{ - */ - -/** - \brief Structure type to access the Error Banking Registers (ERRBNK). - */ -typedef struct -{ - __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ - __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ - uint32_t RESERVED0[2U]; - __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ - __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ - uint32_t RESERVED1[2U]; - __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ -} ErrBnk_Type; - -/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ -#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ -#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ - -#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ -#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ - -#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ -#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ - -#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ -#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ - -#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ -#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ - -/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ -#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ -#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ - -#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ -#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ - -#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ -#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ - -#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ -#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ - -#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ -#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ - -/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ -#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ -#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ - -#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ -#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ - -#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ -#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ - -#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ -#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ - -#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ -#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ - -#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ -#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ - -/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ -#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ -#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ - -#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ -#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ - -#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ -#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ - -#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ -#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ - -#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ -#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ - -#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ -#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ - -/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ -#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ -#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ - -#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ -#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ - -#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ -#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ - -#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ -#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ - -#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ -#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ - -#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ -#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ - -#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ -#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ - -/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ -#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ -#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ - -#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ -#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ - -#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ -#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ - -#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ -#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ - -#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ -#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ - -#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ -#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ - -#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ -#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ - -/*@}*/ /* end of group ErrBnk_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) - @{ - */ - -/** - \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). - */ -typedef struct -{ - __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ - __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ -} PrcCfgInf_Type; - -/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ - -/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ - -/*@}*/ /* end of group PrcCfgInf_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup STL_Type Software Test Library Observation Registers - \brief Type definitions for the Software Test Library Observation Registerss (STL) - @{ - */ - -/** - \brief Structure type to access the Software Test Library Observation Registerss (STL). - */ -typedef struct -{ - __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ - __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ - uint32_t RESERVED0[2U]; - __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ - __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ - __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ - __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ - -} STL_Type; - -/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ -#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ -#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ - -#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ -#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ - -#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ -#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ - -#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ -#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ - -/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ -#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ -#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ - -#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ -#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ - -#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ -#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ - -#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ -#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ - -/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ -#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ -#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ - -#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ -#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ - -#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ -#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ - -/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ -#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ -#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ - -#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ -#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ - -/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ -#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ -#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ - -#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ -#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ - -/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ -#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ -#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ - -#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ -#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ - -/*@}*/ /* end of group STL_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ -#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) - \brief Type definitions for the Performance Monitoring Unit (PMU) - @{ - */ - -/** - \brief Structure type to access the Performance Monitoring Unit (PMU). - */ -typedef struct -{ - __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ - uint32_t RESERVED1[224]; - __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ - uint32_t RESERVED3[480]; - __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ - uint32_t RESERVED4[7]; - __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ - uint32_t RESERVED5[7]; - __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ - uint32_t RESERVED6[7]; - __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ - uint32_t RESERVED7[7]; - __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ - uint32_t RESERVED8[7]; - __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ - uint32_t RESERVED9[7]; - __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ - uint32_t RESERVED10[79]; - __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ - uint32_t RESERVED11[108]; - __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ - __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ - uint32_t RESERVED12[3]; - __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ - __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ - uint32_t RESERVED13[3]; - __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ - __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ - __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ - __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ - __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ - __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ - __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ - __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ -} PMU_Type; - -/** \brief PMU Event Counter Registers (0-30) Definitions */ - -#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ -#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ - -/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ - -#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ -#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ - -/** \brief PMU Count Enable Set Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ -#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ - -#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ -#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ - -#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ -#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ - -#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ -#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ - -#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ -#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ - -#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ -#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ - -#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ -#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ - -#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ -#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ - -#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ -#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ - -#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ -#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ - -#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ -#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ - -#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ -#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ - -#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ -#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ - -#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ -#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ - -#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ -#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ - -#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ -#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ - -#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ -#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ - -#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ -#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ - -#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ -#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ - -#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ -#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ - -#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ -#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ - -#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ -#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ - -#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ -#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ - -#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ -#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ - -#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ -#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ - -#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ -#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ - -#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ -#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ - -#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ -#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ - -#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ -#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ - -#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ -#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ - -#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ -#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ - -#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ -#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ - -/** \brief PMU Count Enable Clear Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ -#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ -#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ - -#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ -#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ -#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ -#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ -#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ -#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ -#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ -#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ -#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ -#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ -#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ -#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ -#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ -#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ -#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ -#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ -#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ -#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ -#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ -#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ -#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ -#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ -#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ -#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ -#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ -#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ -#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ -#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ -#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ -#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ - -#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ -#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ - -/** \brief PMU Interrupt Enable Set Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ -#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ - -/** \brief PMU Interrupt Enable Clear Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ - -#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ - -/** \brief PMU Overflow Flag Status Set Register Definitions */ - -#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ -#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ - -#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ -#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ - -#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ -#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ - -#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ -#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ - -#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ -#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ - -#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ -#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ - -#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ -#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ - -#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ -#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ - -#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ -#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ - -#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ -#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ - -#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ -#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ - -#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ -#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ - -#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ -#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ - -#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ -#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ - -#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ -#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ - -#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ -#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ - -#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ -#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ - -#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ -#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ - -#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ -#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ - -#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ -#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ - -#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ -#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ - -#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ -#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ - -#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ -#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ - -#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ -#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ - -#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ -#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ - -#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ -#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ - -#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ -#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ - -#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ -#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ - -#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ -#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ - -#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ -#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ - -#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ -#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ - -#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ -#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ - -/** \brief PMU Overflow Flag Status Clear Register Definitions */ - -#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ -#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ -#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ - -#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ -#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ -#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ -#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ -#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ -#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ -#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ -#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ -#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ -#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ -#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ -#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ -#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ -#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ -#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ -#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ -#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ -#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ -#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ -#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ -#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ -#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ -#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ -#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ -#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ -#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ -#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ -#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ -#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ -#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ - -#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ -#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ - -/** \brief PMU Software Increment Counter */ - -#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ -#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ - -#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ -#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ - -#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ -#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ - -#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ -#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ - -#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ -#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ - -#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ -#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ - -#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ -#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ - -#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ -#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ - -#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ -#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ - -#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ -#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ - -#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ -#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ - -#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ -#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ - -#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ -#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ - -#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ -#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ - -#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ -#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ - -#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ -#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ - -#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ -#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ - -#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ -#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ - -#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ -#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ - -#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ -#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ - -#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ -#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ - -#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ -#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ - -#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ -#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ - -#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ -#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ - -#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ -#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ - -#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ -#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ - -#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ -#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ - -#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ -#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ - -#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ -#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ - -#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ -#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ - -#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ -#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ - -/** \brief PMU Control Register Definitions */ - -#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ -#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ - -#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ -#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ -#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ -#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ - -#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ -#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ - -#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ -#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ - -/** \brief PMU Type Register Definitions */ - -#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ -#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ - -#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ -#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ - -#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ -#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ - -#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ -#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ - -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ - -/** \brief PMU Authentication Status Register Definitions */ - -#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ - - -/*@} end of group CMSIS_PMU */ -#endif - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ -#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ - -#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ -#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ -#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ - -#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ -#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ - -#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ -#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ -#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ - -#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ -#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ - -#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ -#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ -#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ - -#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ -#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ - -#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ -#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ - -#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ -#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ - -#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ -#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ - -#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ -#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ -#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ - -#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ -#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ - -#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ -#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ - -#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ -#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ -#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Set Clear Exception and Monitor Control Register Definitions */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ - -#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ -#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ -#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ - -#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ -#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ -#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ -#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ - -#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ -#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ - -#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ -#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ - -#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ -#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ -#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ - -#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ -#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ - -#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ -#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ - -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ -#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ - -#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ - #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ - #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ - #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ - #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ - #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ - #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ - #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ - #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ - #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ - #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ - #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ - -/* 'SCnSCB' is deprecated and replaced by 'ICB' */ -typedef ICB_Type SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) -#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) - -#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) -#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) - -#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) -#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) - -#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) -#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) - -#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) -#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) - -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) - -#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) -#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) - -#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) -#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) - -#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) -#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) - -#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) -#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) - -#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) -#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) - -#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) -#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) - -#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) -#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) - -#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) -#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) -#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) - -#define SCnSCB (ICB) -#define SCnSCB_NS (ICB_NS) - -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## PMU functions and events #################################### */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - -#include "pmu_armv8.h" - -/** - \brief Cortex-M55 PMU events - \note Architectural PMU events can be found in pmu_armv8.h -*/ - -#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ -#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ -#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ -#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ -#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ -#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ -#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ -#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ -#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ -#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ -#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ -#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ -#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ -#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ -#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ -#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ -#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ -#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ -#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ -#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ -#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - -/* ########################## MVE functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_MveFunctions MVE Functions - \brief Function that provides MVE type. - @{ - */ - -/** - \brief get MVE type - \details returns the MVE type - \returns - - \b 0: No Vector Extension (MVE) - - \b 1: Integer Vector Extension (MVE-I) - - \b 2: Floating-point Vector Extension (MVE-F) - */ -__STATIC_INLINE uint32_t SCB_GetMVEType(void) -{ - const uint32_t mvfr1 = FPU->MVFR1; - if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) - { - return 2U; - } - else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) - { - return 1U; - } - else - { - return 0U; - } -} - - -/*@} end of CMSIS_Core_MveFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM55_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm7.h b/lib/cmsis/inc/core_cm7.h deleted file mode 100644 index 010506e9fa4..00000000000 --- a/lib/cmsis/inc/core_cm7.h +++ /dev/null @@ -1,2366 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.1.6 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ - uint32_t RESERVED7[5U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ - -#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ -#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ -#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ - -#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ -#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ - -#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ -#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ - -#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ -#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ - -#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ -#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ - -#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ -#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ - -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ -#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ -#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - -/*@} end of CMSIS_Core_FpuFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_cm85.h b/lib/cmsis/inc/core_cm85.h deleted file mode 100644 index 60463111897..00000000000 --- a/lib/cmsis/inc/core_cm85.h +++ /dev/null @@ -1,4672 +0,0 @@ -/**************************************************************************//** - * @file core_cm85.h - * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File - * @version V1.0.4 - * @date 21. April 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM85_H_GENERIC -#define __CORE_CM85_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M85 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM85 definitions */ - -#define __CORTEX_M (85U) /*!< Cortex-M Core */ - -#if defined ( __CC_ARM ) - #error Legacy Arm Compiler does not support Armv8.1-M target architecture. -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM85_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM85_H_DEPENDANT -#define __CORE_CM85_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM85_REV - #define __CM85_REV 0x0001U - #warning "__CM85_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #if __FPU_PRESENT != 0U - #ifndef __FPU_DP - #define __FPU_DP 0U - #warning "__FPU_DP not defined in device header file; using default!" - #endif - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __PMU_PRESENT - #define __PMU_PRESENT 0U - #warning "__PMU_PRESENT not defined in device header file; using default!" - #endif - - #if __PMU_PRESENT != 0U - #ifndef __PMU_NUM_EVENTCNT - #define __PMU_NUM_EVENTCNT 8U - #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" - #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) - #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ - #endif - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M85 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core EWIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core PMU Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:1; /*!< bit: 20 Reserved */ - uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ - uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_B_Pos 21U /*!< xPSR: B Position */ -#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ - uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ - uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ - uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ - uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ -#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ - -#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ -#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ - -#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ -#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ - -#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ -#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ - -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ - uint32_t RESERVED4[14U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ -#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ - -#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ -#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ -#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ - -#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ -#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ - -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ -#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ - -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ -#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ - -#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ -#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ - -#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ -#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ - -#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ -#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ - -#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ -#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ - -#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ -#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ - -#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ -#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ - -#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ -#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ - -/* SCB Debug Feature Register 0 Definitions */ -#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ -#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ - -#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ -#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB RAS Fault Status Register Definitions */ -#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ -#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ - -#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ -#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ - -#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ -#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ICB Implementation Control Block register (ICB) - \brief Type definitions for the Implementation Control Block Register - @{ - */ - -/** - \brief Structure type to access the Implementation Control Block (ICB). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} ICB_Type; - -/* Auxiliary Control Register Definitions */ -#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ -#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ - -#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ -#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ - -#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ -#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ - -#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ -#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ - -#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ -#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ - -#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -/* Interrupt Controller Type Register Definitions */ -#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_ICB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[3U]; - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) - @{ - */ - -/** - \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). - */ -typedef struct -{ - __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ - __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ - uint32_t RESERVED1[2U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ - __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ - uint32_t RESERVED2[313U]; - __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ - __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ - uint32_t RESERVED3[2U]; - __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ - uint32_t RESERVED4[44U]; - __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ - __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ - uint32_t RESERVED5[2U]; - __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ -} MemSysCtl_Type; - -/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ -#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ -#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ - -#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ -#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ - -#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ -#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ - -#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ -#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ - -#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ -#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ - -#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ -#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ - -#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ -#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ - -/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ -#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ -#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ - -#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ -#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ - -/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ -#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ -#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ - -#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ -#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ - -/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ -#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ -#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ - -#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ -#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ - -/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ -#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ -#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ - -#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ -#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ - -/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ -#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ -#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ - -#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ -#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ - -/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ -#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ -#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ - -#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ -#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ - -#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ -#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ - -/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ -#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ -#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ - -#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ -#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ - -/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ -#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ -#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ - -#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ -#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ - -#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ -#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ - - -/*@}*/ /* end of group MemSysCtl_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup PwrModCtl_Type Power Mode Control Registers - \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) - @{ - */ - -/** - \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). - */ -typedef struct -{ - __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ - __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ -} PwrModCtl_Type; - -/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ -#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ - -#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ - -#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ - -/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ -#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ -#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ - -/*@}*/ /* end of group PwrModCtl_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup EWIC_Type External Wakeup Interrupt Controller Registers - \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) - @{ - */ - -/** - \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). - */ -typedef struct -{ - __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ - uint32_t RESERVED0[31U]; - __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ - __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ -} EWIC_Type; - -/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ -#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ -#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ - -#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ -#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ - -#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ -#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ - -/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ -#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ -#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ - -#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ -#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ - -#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ -#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ - -/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ -#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ -#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ - -/*@}*/ /* end of group EWIC_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Error Banking Registers (ERRBNK) - @{ - */ - -/** - \brief Structure type to access the Error Banking Registers (ERRBNK). - */ -typedef struct -{ - __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ - __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ - uint32_t RESERVED0[2U]; - __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ - __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ - uint32_t RESERVED1[2U]; - __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ -} ErrBnk_Type; - -/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ -#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ -#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ - -#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ -#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ - -#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ -#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ - -#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ -#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ - -#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ -#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ - -/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ -#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ -#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ - -#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ -#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ - -#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ -#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ - -#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ -#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ - -#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ -#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ - -/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ -#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ -#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ - -#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ -#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ - -#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ -#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ - -#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ -#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ - -#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ -#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ - -#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ -#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ - -/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ -#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ -#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ - -#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ -#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ - -#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ -#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ - -#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ -#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ - -#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ -#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ - -#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ -#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ - -/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ -#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ -#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ - -#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ -#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ - -#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ -#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ - -#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ -#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ - -#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ -#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ - -#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ -#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ - -#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ -#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ - -/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ -#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ -#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ - -#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ -#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ - -#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ -#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ - -#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ -#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ - -#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ -#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ - -#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ -#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ - -#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ -#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ - -/*@}*/ /* end of group ErrBnk_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) - @{ - */ - -/** - \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). - */ -typedef struct -{ - __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ - __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ -} PrcCfgInf_Type; - -/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ - -/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ - -/*@}*/ /* end of group PrcCfgInf_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ -#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) - \brief Type definitions for the Performance Monitoring Unit (PMU) - @{ - */ - -/** - \brief Structure type to access the Performance Monitoring Unit (PMU). - */ -typedef struct -{ - __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ - uint32_t RESERVED1[224]; - __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ - uint32_t RESERVED3[480]; - __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ - uint32_t RESERVED4[7]; - __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ - uint32_t RESERVED5[7]; - __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ - uint32_t RESERVED6[7]; - __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ - uint32_t RESERVED7[7]; - __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ - uint32_t RESERVED8[7]; - __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ - uint32_t RESERVED9[7]; - __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ - uint32_t RESERVED10[79]; - __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ - uint32_t RESERVED11[108]; - __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ - __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ - uint32_t RESERVED12[3]; - __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ - __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ - uint32_t RESERVED13[3]; - __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ - __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ - __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ - __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ - __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ - __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ - __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ - __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ -} PMU_Type; - -/** \brief PMU Event Counter Registers (0-30) Definitions */ - -#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ -#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ - -/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ - -#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ -#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ - -/** \brief PMU Count Enable Set Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ -#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ - -#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ -#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ - -#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ -#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ - -#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ -#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ - -#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ -#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ - -#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ -#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ - -#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ -#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ - -#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ -#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ - -#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ -#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ - -#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ -#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ - -#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ -#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ - -#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ -#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ - -#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ -#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ - -#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ -#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ - -#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ -#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ - -#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ -#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ - -#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ -#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ - -#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ -#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ - -#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ -#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ - -#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ -#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ - -#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ -#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ - -#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ -#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ - -#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ -#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ - -#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ -#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ - -#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ -#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ - -#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ -#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ - -#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ -#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ - -#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ -#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ - -#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ -#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ - -#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ -#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ - -#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ -#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ - -#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ -#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ - -/** \brief PMU Count Enable Clear Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ -#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ -#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ - -#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ -#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ -#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ -#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ -#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ -#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ -#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ -#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ -#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ -#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ -#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ -#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ -#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ -#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ -#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ -#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ -#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ -#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ -#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ -#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ -#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ -#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ -#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ -#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ -#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ -#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ -#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ -#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ -#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ -#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ - -#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ -#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ - -/** \brief PMU Interrupt Enable Set Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ -#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ - -/** \brief PMU Interrupt Enable Clear Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ - -#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ - -/** \brief PMU Overflow Flag Status Set Register Definitions */ - -#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ -#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ - -#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ -#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ - -#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ -#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ - -#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ -#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ - -#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ -#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ - -#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ -#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ - -#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ -#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ - -#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ -#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ - -#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ -#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ - -#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ -#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ - -#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ -#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ - -#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ -#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ - -#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ -#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ - -#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ -#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ - -#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ -#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ - -#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ -#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ - -#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ -#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ - -#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ -#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ - -#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ -#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ - -#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ -#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ - -#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ -#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ - -#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ -#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ - -#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ -#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ - -#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ -#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ - -#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ -#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ - -#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ -#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ - -#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ -#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ - -#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ -#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ - -#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ -#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ - -#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ -#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ - -#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ -#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ - -#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ -#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ - -/** \brief PMU Overflow Flag Status Clear Register Definitions */ - -#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ -#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ -#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ - -#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ -#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ -#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ -#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ -#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ -#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ -#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ -#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ -#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ -#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ -#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ -#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ -#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ -#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ -#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ -#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ -#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ -#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ -#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ -#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ -#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ -#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ -#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ -#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ -#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ -#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ -#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ -#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ -#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ -#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ - -#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ -#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ - -/** \brief PMU Software Increment Counter */ - -#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ -#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ - -#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ -#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ - -#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ -#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ - -#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ -#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ - -#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ -#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ - -#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ -#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ - -#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ -#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ - -#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ -#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ - -#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ -#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ - -#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ -#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ - -#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ -#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ - -#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ -#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ - -#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ -#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ - -#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ -#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ - -#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ -#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ - -#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ -#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ - -#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ -#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ - -#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ -#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ - -#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ -#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ - -#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ -#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ - -#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ -#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ - -#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ -#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ - -#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ -#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ - -#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ -#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ - -#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ -#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ - -#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ -#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ - -#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ -#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ - -#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ -#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ - -#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ -#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ - -#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ -#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ - -#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ -#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ - -/** \brief PMU Control Register Definitions */ - -#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ -#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ - -#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ -#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ -#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ -#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ - -#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ -#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ - -#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ -#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ - -/** \brief PMU Type Register Definitions */ - -#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ -#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ - -#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ -#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ - -#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ -#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ - -#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ -#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ - -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ - -/** \brief PMU Authentication Status Register Definitions */ - -#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ - - -/*@} end of group CMSIS_PMU */ -#endif - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ -#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ - -#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ -#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ -#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ - -#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ -#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ - -#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ -#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ -#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ - -#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ -#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ - -#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ -#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ -#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ - -#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ -#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ - -#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ -#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ - -#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ -#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ - -#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ -#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ - -#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ -#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ -#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ - -#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ -#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ - -#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ -#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ - -#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ -#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ -#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Set Clear Exception and Monitor Control Register Definitions */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ - -#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ -#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ -#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ - -#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ -#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ -#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ -#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ - -#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ -#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ - -#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ -#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ - -#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ -#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ -#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ - -#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ -#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ - -#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ -#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ - -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ -#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ - -#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ - #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ - #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ - #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ - #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ - #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ - #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ - #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ - #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ - #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ - -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## PMU functions and events #################################### */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - -#include "pmu_armv8.h" - -/** - \brief Cortex-M85 PMU events - \note Architectural PMU events can be found in pmu_armv8.h -*/ - -#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ -#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ -#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ -#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ -#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ -#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ -#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ -#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ -#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ -#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ -#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ -#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ -#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ -#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ -#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ -#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ -#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ -#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ -#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ -#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ -#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - -/* ########################## MVE functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_MveFunctions MVE Functions - \brief Function that provides MVE type. - @{ - */ - -/** - \brief get MVE type - \details returns the MVE type - \returns - - \b 0: No Vector Extension (MVE) - - \b 1: Integer Vector Extension (MVE-I) - - \b 2: Floating-point Vector Extension (MVE-F) - */ -__STATIC_INLINE uint32_t SCB_GetMVEType(void) -{ - const uint32_t mvfr1 = FPU->MVFR1; - if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) - { - return 2U; - } - else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) - { - return 1U; - } - else - { - return 0U; - } -} - - -/*@} end of CMSIS_Core_MveFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - -/* ################### PAC Key functions ########################### */ - -#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) -#include "pac_armv81.h" -#endif - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM85_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_sc000.h b/lib/cmsis/inc/core_sc000.h deleted file mode 100644 index dbc755fff39..00000000000 --- a/lib/cmsis/inc/core_sc000.h +++ /dev/null @@ -1,1030 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 27. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_sc300.h b/lib/cmsis/inc/core_sc300.h deleted file mode 100644 index d66621031e0..00000000000 --- a/lib/cmsis/inc/core_sc300.h +++ /dev/null @@ -1,1917 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.10 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/core_starmc1.h b/lib/cmsis/inc/core_starmc1.h deleted file mode 100644 index d86c8d3857f..00000000000 --- a/lib/cmsis/inc/core_starmc1.h +++ /dev/null @@ -1,3592 +0,0 @@ -/**************************************************************************//** - * @file core_starmc1.h - * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File - * @version V1.0.2 - * @date 07. April 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. - * Copyright (c) 2018-2022 Arm China. - * All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_STAR_H_GENERIC -#define __CORE_STAR_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup STAR-MC1 - @{ - */ - -#include "cmsis_version.h" - -/* Macro Define for STAR-MC1 */ -#define __STAR_MC (1U) /*!< STAR-MC Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_STAR_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_STAR_H_DEPENDANT -#define __CORE_STAR_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __STAR_REV - #define __STAR_REV 0x0000U - #warning "__STAR_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group STAR-MC1 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for STAR-MC1 processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED_ADD1[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ -} SCB_Type; - -typedef struct -{ - __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ - __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ -}EMSS_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ -#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ - -#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ -#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ - - - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache line Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ -#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ - -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean line by Set-way Register Definitions */ -#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ -#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ - -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ -#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ - -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* ArmChina: Implementation Defined */ -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ -#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ - -#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ -#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ - -#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ -#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ - -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses including - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/** - \brief Software Reset - \details Initiates a system reset request to reset the CPU. - */ -__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses including - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ - SCB_AIRCR_SYSRESETREQ_Msk ); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ -#endif - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_STAR_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/inc/mpu_armv7.h b/lib/cmsis/inc/mpu_armv7.h deleted file mode 100644 index d9eedf81a64..00000000000 --- a/lib/cmsis/inc/mpu_armv7.h +++ /dev/null @@ -1,275 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.1.2 - * @date 25. May 2020 - ******************************************************************************/ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes - -#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access -#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only -#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only -#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access -#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only -#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Memory Access Attributes -* -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ -#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (((MPU_RASR_ENABLE_Msk)))) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) - -/** -* MPU Memory Access Attribute for strongly ordered memory. -* - TEX: 000b -* - Shareable -* - Non-cacheable -* - Non-bufferable -*/ -#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) - -/** -* MPU Memory Access Attribute for device memory. -* - TEX: 000b (if shareable) or 010b (if non-shareable) -* - Shareable or non-shareable -* - Non-cacheable -* - Bufferable (if shareable) or non-bufferable (if non-shareable) -* -* \param IsShareable Configures the device memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) - -/** -* MPU Memory Access Attribute for normal memory. -* - TEX: 1BBb (reflecting outer cacheability rules) -* - Shareable or non-shareable -* - Cacheable or non-cacheable (reflecting inner cacheability rules) -* - Bufferable or non-bufferable (reflecting inner cacheability rules) -* -* \param OuterCp Configures the outer cache policy. -* \param InnerCp Configures the inner cache policy. -* \param IsShareable Configures the memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) - -/** -* MPU Memory Access Attribute non-cacheable policy. -*/ -#define ARM_MPU_CACHEP_NOCACHE 0U - -/** -* MPU Memory Access Attribute write-back, write and read allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_WRA 1U - -/** -* MPU Memory Access Attribute write-through, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WT_NWA 2U - -/** -* MPU Memory Access Attribute write-back, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_NWA 3U - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif diff --git a/lib/cmsis/inc/mpu_armv8.h b/lib/cmsis/inc/mpu_armv8.h deleted file mode 100644 index 3de16efc86a..00000000000 --- a/lib/cmsis/inc/mpu_armv8.h +++ /dev/null @@ -1,352 +0,0 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.1.3 - * @date 03. February 2021 - ******************************************************************************/ -/* - * Copyright (c) 2017-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - (((BASE) & MPU_RBAR_BASE_Msk) | \ - (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - diff --git a/lib/cmsis/inc/pac_armv81.h b/lib/cmsis/inc/pac_armv81.h deleted file mode 100644 index 854b60a204c..00000000000 --- a/lib/cmsis/inc/pac_armv81.h +++ /dev/null @@ -1,206 +0,0 @@ -/****************************************************************************** - * @file pac_armv81.h - * @brief CMSIS PAC key functions for Armv8.1-M PAC extension - * @version V1.0.0 - * @date 23. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef PAC_ARMV81_H -#define PAC_ARMV81_H - - -/* ################### PAC Key functions ########################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions - \brief Functions that access the PAC keys. - @{ - */ - -#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) - -/** - \brief read the PAC key used for privileged mode - \details Reads the PAC key stored in the PAC_KEY_P registers. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_p_0\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_p_1\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_p_2\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_p_3\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for privileged mode - \details writes the given PAC key to the PAC_KEY_P registers. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_p_0, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_p_1, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_p_2, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_p_3, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief read the PAC key used for unprivileged mode - \details Reads the PAC key stored in the PAC_KEY_U registers. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_u_0\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_u_1\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_u_2\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_u_3\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for unprivileged mode - \details writes the given PAC key to the PAC_KEY_U registers. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_u_0, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_u_1, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_u_2, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_u_3, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) - -/** - \brief read the PAC key used for privileged mode (non-secure) - \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_p_0_ns\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_p_1_ns\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_p_2_ns\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_p_3_ns\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for privileged mode (non-secure) - \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_p_0_ns, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_p_1_ns, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_p_2_ns, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_p_3_ns, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief read the PAC key used for unprivileged mode (non-secure) - \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_u_0_ns\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_u_1_ns\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_u_2_ns\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_u_3_ns\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for unprivileged mode (non-secure) - \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_u_0_ns, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_u_1_ns, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_u_2_ns, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_u_3_ns, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ - -#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ - -/*@} end of CMSIS_Core_PacKeyFunctions */ - - -#endif /* PAC_ARMV81_H */ diff --git a/lib/cmsis/inc/pmu_armv8.h b/lib/cmsis/inc/pmu_armv8.h deleted file mode 100644 index f8f3d8935b8..00000000000 --- a/lib/cmsis/inc/pmu_armv8.h +++ /dev/null @@ -1,337 +0,0 @@ -/****************************************************************************** - * @file pmu_armv8.h - * @brief CMSIS PMU API for Armv8.1-M PMU - * @version V1.0.1 - * @date 15. April 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_PMU_ARMV8_H -#define ARM_PMU_ARMV8_H - -/** - * \brief PMU Events - * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. - * */ - -#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ -#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ -#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ -#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ -#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ -#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ -#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ -#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ -#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ -#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ -#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ -#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ -#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ -#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ -#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ -#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ -#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ -#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ -#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ -#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ -#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ -#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ -#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ -#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ -#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ -#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ -#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ -#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ -#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ -#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ -#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ -#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ -#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ -#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ -#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ -#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ -#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ -#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ -#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ -#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ -#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ -#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ -#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ -#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ -#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ -#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ -#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ -#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ -#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ -#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ -#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ -#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ -#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ -#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ -#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ -#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ -#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ -#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ -#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ -#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ -#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ -#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ -#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ -#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ -#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ -#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ -#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ -#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ -#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ -#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ -#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ -#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ -#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ -#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ -#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ -#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ -#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ -#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ -#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ -#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ -#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ -#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ -#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ - -/** \brief PMU Functions */ - -__STATIC_INLINE void ARM_PMU_Enable(void); -__STATIC_INLINE void ARM_PMU_Disable(void); - -__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); - -__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); -__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); - -__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); -__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); - -__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); -__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); - -__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); -__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); - -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); - -__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); - -/** - \brief Enable the PMU -*/ -__STATIC_INLINE void ARM_PMU_Enable(void) -{ - PMU->CTRL |= PMU_CTRL_ENABLE_Msk; -} - -/** - \brief Disable the PMU -*/ -__STATIC_INLINE void ARM_PMU_Disable(void) -{ - PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; -} - -/** - \brief Set event to count for PMU eventer counter - \param [in] num Event counter (0-30) to configure - \param [in] type Event to count -*/ -__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) -{ - PMU->EVTYPER[num] = type; -} - -/** - \brief Reset cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) -{ - PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; -} - -/** - \brief Reset all event counters -*/ -__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) -{ - PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; -} - -/** - \brief Enable counters - \param [in] mask Counters to enable - \note Enables one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) -{ - PMU->CNTENSET = mask; -} - -/** - \brief Disable counters - \param [in] mask Counters to enable - \note Disables one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) -{ - PMU->CNTENCLR = mask; -} - -/** - \brief Read cycle counter - \return Cycle count -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) -{ - return PMU->CCNTR; -} - -/** - \brief Read event counter - \param [in] num Event counter (0-30) to read - \return Event count -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) -{ - return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; -} - -/** - \brief Read counter overflow status - \return Counter overflow status bits for the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) -{ - return PMU->OVSSET; -} - -/** - \brief Clear counter overflow status - \param [in] mask Counter overflow status bits to clear - \note Clears overflow status bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) -{ - PMU->OVSCLR = mask; -} - -/** - \brief Enable counter overflow interrupt request - \param [in] mask Counter overflow interrupt request bits to set - \note Sets overflow interrupt request bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) -{ - PMU->INTENSET = mask; -} - -/** - \brief Disable counter overflow interrupt request - \param [in] mask Counter overflow interrupt request bits to clear - \note Clears overflow interrupt request bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) -{ - PMU->INTENCLR = mask; -} - -/** - \brief Software increment event counter - \param [in] mask Counters to increment - \note Software increment bits for one or more event counters (0-30) -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) -{ - PMU->SWINC = mask; -} - -#endif diff --git a/lib/cmsis/inc/tz_context.h b/lib/cmsis/inc/tz_context.h deleted file mode 100644 index 0d09749f3a5..00000000000 --- a/lib/cmsis/inc/tz_context.h +++ /dev/null @@ -1,70 +0,0 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H From 855439672d0664b4d7d4f24bf4674ba20c2a8a06 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 15 Apr 2026 00:19:09 +1000 Subject: [PATCH 135/635] LICENSE: Update license info for CMSIS submodules. Signed-off-by: Damien George --- LICENSE | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/LICENSE b/LICENSE index 28b5239e5fe..b9078c7c71c 100644 --- a/LICENSE +++ b/LICENSE @@ -37,6 +37,8 @@ used during the build process and is not part of the compiled source code. /drivers /cc3100 (BSD-3-clause) /lib + /CMSIS_5 (Apache-2.0) + /CMSIS_6 (Apache-2.0) /asf4 (Apache-2.0) /axtls (BSD-3-clause) /config @@ -45,7 +47,6 @@ used during the build process and is not part of the compiled source code. /Rules.mak (GPL-2.0) /berkeley-db-1xx (BSD-4-clause) /btstack (See btstack/LICENSE) - /cmsis (BSD-3-clause) /crypto-algorithms (NONE) /libhydrogen (ISC) /libmetal (BSD-3-clause) From 72798f96f91f0ed0360b703e87328d19fc89dfc3 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 18 May 2026 14:29:23 +1000 Subject: [PATCH 136/635] mimxrt: Switch to CMSIS 6. Built all 14 boards, all have binary equivalent firmware. Signed-off-by: Damien George --- ports/mimxrt/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/mimxrt/Makefile b/ports/mimxrt/Makefile index f4ddc761087..d6f3361f5dd 100644 --- a/ports/mimxrt/Makefile +++ b/ports/mimxrt/Makefile @@ -20,7 +20,7 @@ endif BUILD ?= build-$(BOARD) PORT ?= /dev/ttyACM0 CROSS_COMPILE ?= arm-none-eabi- -GIT_SUBMODULES += lib/CMSIS_5 lib/tinyusb lib/nxp_driver +GIT_SUBMODULES += lib/CMSIS_6 lib/tinyusb lib/nxp_driver UF2CONV ?= $(TOP)/tools/uf2conv.py # MicroPython feature configurations @@ -73,7 +73,7 @@ GEN_PINS_SRC = $(BUILD)/pins_gen.c INC += -I$(BOARD_DIR) INC += -I$(BUILD) INC += -I$(TOP) -INC += -I$(TOP)/lib/CMSIS_5/CMSIS/Core/Include +INC += -I$(TOP)/lib/CMSIS_6/CMSIS/Core/Include INC += -I$(TOP)/lib/oofatfs INC += -I$(TOP)/lib/tinyusb/hw INC += -I$(TOP)/lib/tinyusb/hw/bsp/teensy_40 From 2eb5fadb221276bc86fd8e73ad0e851af5e6dcdb Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 18 May 2026 14:29:53 +1000 Subject: [PATCH 137/635] nrf: Switch to CMSIS 6. Built all 8 PCA100xx boards, and they have binary equivalent firmware with this change. Signed-off-by: Damien George --- ports/nrf/Makefile | 4 ++-- ports/nrf/drivers/secureboot/secureboot.mk | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ports/nrf/Makefile b/ports/nrf/Makefile index 7d276a1d852..c96d802ff50 100644 --- a/ports/nrf/Makefile +++ b/ports/nrf/Makefile @@ -64,7 +64,7 @@ FROZEN_MANIFEST ?= modules/manifest.py include ../../py/py.mk include ../../extmod/extmod.mk -GIT_SUBMODULES += lib/CMSIS_5 lib/nrfx lib/tinyusb +GIT_SUBMODULES += lib/CMSIS_6 lib/nrfx lib/tinyusb MICROPY_VFS_FAT ?= 0 @@ -73,7 +73,7 @@ CROSS_COMPILE ?= arm-none-eabi- INC += -I. INC += -I../.. INC += -I$(BUILD) -INC += -I./../../lib/CMSIS_5/CMSIS/Core/Include +INC += -I./../../lib/CMSIS_6/CMSIS/Core/Include INC += -I./modules/machine INC += -I./modules/ubluepy INC += -I./modules/music diff --git a/ports/nrf/drivers/secureboot/secureboot.mk b/ports/nrf/drivers/secureboot/secureboot.mk index 88c5154c7b7..9447d434714 100644 --- a/ports/nrf/drivers/secureboot/secureboot.mk +++ b/ports/nrf/drivers/secureboot/secureboot.mk @@ -15,7 +15,7 @@ SRC_SECUREBOOT += $(addprefix $(TOP)/lib/nrfx/mdk/,\ .PHONY: secureboot clean INC_SECUREBOOT += -I./../../lib/nrfx/mdk -INC_SECUREBOOT += -I./../../lib/CMSIS_5/CMSIS/Core/Include +INC_SECUREBOOT += -I./../../lib/CMSIS_6/CMSIS/Core/Include MCU_SERIES = m33 From 869f1b12acb3bef09c4e445659c688a353f2ba64 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 18 May 2026 14:30:06 +1000 Subject: [PATCH 138/635] samd: Switch to CMSIS 6. Built all 18 boards, all have binary equivalent firmware. Signed-off-by: Damien George --- ports/samd/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/samd/Makefile b/ports/samd/Makefile index 7eb7e06861c..5e46c2d0b35 100644 --- a/ports/samd/Makefile +++ b/ports/samd/Makefile @@ -52,14 +52,14 @@ FROZEN_MANIFEST ?= boards/manifest.py include $(TOP)/py/py.mk include $(TOP)/extmod/extmod.mk -GIT_SUBMODULES += lib/CMSIS_5 lib/asf4 lib/tinyusb +GIT_SUBMODULES += lib/CMSIS_6 lib/asf4 lib/tinyusb INC += -I. INC += -I$(TOP) INC += -I$(BUILD) INC += -I$(BOARD_DIR) INC += -Imcu/$(MCU_SERIES_LOWER) -INC += -I$(TOP)/lib/CMSIS_5/CMSIS/Core/Include +INC += -I$(TOP)/lib/CMSIS_6/CMSIS/Core/Include INC += -I$(TOP)/lib/asf4/$(MCU_SERIES_LOWER)/hal/include INC += -I$(TOP)/lib/asf4/$(MCU_SERIES_LOWER)/hal/utils/include INC += -I$(TOP)/lib/asf4/$(MCU_SERIES_LOWER)/config From 8d81160ad300d3244590e50ab76a882724fcb329 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 18 May 2026 14:30:23 +1000 Subject: [PATCH 139/635] stm32: Switch to CMSIS 6. Built the 30 NUCLEO_xxx boards, all have binary equivalent firmware except for NUCLEO_N657X0 (although it's firmware is the same size before and after this commit). Ran full test suite on OPENMV_N6 with CMSIS 6 to verify the N6 and it passed. Built mboot for NUCLEO_WB55, PYBV10, PYBD_SF2 and PYBD_SF6. All have binary equivalent firmware. Signed-off-by: Damien George --- ports/stm32/Makefile | 4 ++-- ports/stm32/mboot/Makefile | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 6e5df0d8188..00892c3ece6 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -58,7 +58,7 @@ MBOOT_TEXT0_ADDR ?= 0x08000000 include $(TOP)/py/py.mk include $(TOP)/extmod/extmod.mk -GIT_SUBMODULES += lib/CMSIS_5 lib/libhydrogen lib/stm32lib lib/tinyusb +GIT_SUBMODULES += lib/CMSIS_6 lib/libhydrogen lib/stm32lib lib/tinyusb CROSS_COMPILE ?= arm-none-eabi- LD_DIR=boards @@ -105,7 +105,7 @@ CMSIS_MCU_HDR = $(STM32LIB_CMSIS_ABS)/Include/$(CMSIS_MCU_LOWER).h INC += -I. INC += -I$(TOP) INC += -I$(BUILD) -INC += -I$(TOP)/lib/CMSIS_5/CMSIS/Core/Include +INC += -I$(TOP)/lib/CMSIS_6/CMSIS/Core/Include INC += -I$(STM32LIB_CMSIS_ABS)/Include INC += -I$(STM32LIB_HAL_ABS)/Inc INC += -I$(USBDEV_DIR)/core/inc -I$(USBDEV_DIR)/class/inc diff --git a/ports/stm32/mboot/Makefile b/ports/stm32/mboot/Makefile index da159e39880..859daafcc6e 100755 --- a/ports/stm32/mboot/Makefile +++ b/ports/stm32/mboot/Makefile @@ -64,7 +64,7 @@ INC += -I. INC += -I.. INC += -I$(TOP) INC += -I$(BUILD) -INC += -I$(TOP)/lib/CMSIS_5/CMSIS/Core/Include +INC += -I$(TOP)/lib/CMSIS_6/CMSIS/Core/Include INC += -I$(STM32LIB_CMSIS_ABS)/Include INC += -I$(STM32LIB_HAL_ABS)/Inc INC += -I../$(USBDEV_DIR)/core/inc -I../$(USBDEV_DIR)/class/inc From c6923ac976122077dda987474ffb6bfe1eac4c0f Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 7 May 2026 17:24:07 +1000 Subject: [PATCH 140/635] tests/multi_espnow: Log peer addresses as hex in errors. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- tests/multi_espnow/20_send_echo.py | 2 +- tests/multi_espnow/30_lmk_echo.py | 2 +- tests/multi_espnow/40_recv_test.py | 2 +- tests/multi_espnow/50_esp32_rssi_test.py | 2 +- tests/multi_espnow/60_irq_test.py | 2 +- tests/multi_espnow/80_asyncio_client.py | 2 +- tests/multi_espnow/90_memory_test.py | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/multi_espnow/20_send_echo.py b/tests/multi_espnow/20_send_echo.py index e71db937219..49cfcc19c17 100644 --- a/tests/multi_espnow/20_send_echo.py +++ b/tests/multi_espnow/20_send_echo.py @@ -27,7 +27,7 @@ def echo_server(e): # Echo the MAC and message back to the sender if not e.send(peer, msg, sync): - print("ERROR: send() failed to", peer) + print("ERROR: send() failed to", peer.hex()) return if msg == b"!done": diff --git a/tests/multi_espnow/30_lmk_echo.py b/tests/multi_espnow/30_lmk_echo.py index 2a6c77c6331..eca558c7793 100644 --- a/tests/multi_espnow/30_lmk_echo.py +++ b/tests/multi_espnow/30_lmk_echo.py @@ -45,7 +45,7 @@ def echo_server(e): # Echo the message back to the sender if not e.send(peer, msg, sync): - print("ERROR: send() failed to", peer) + print("ERROR: send() failed to", peer.hex()) return if peer not in peers: diff --git a/tests/multi_espnow/40_recv_test.py b/tests/multi_espnow/40_recv_test.py index 554db16ac17..2c6854851d5 100644 --- a/tests/multi_espnow/40_recv_test.py +++ b/tests/multi_espnow/40_recv_test.py @@ -28,7 +28,7 @@ def echo_server(e): # Echo the MAC and message back to the sender if not e.send(peer, msg, sync): - print("ERROR: send() failed to", peer) + print("ERROR: send() failed to", peer.hex()) return if msg == b"!done": diff --git a/tests/multi_espnow/50_esp32_rssi_test.py b/tests/multi_espnow/50_esp32_rssi_test.py index 8aded1c0994..7209ad341ef 100644 --- a/tests/multi_espnow/50_esp32_rssi_test.py +++ b/tests/multi_espnow/50_esp32_rssi_test.py @@ -29,7 +29,7 @@ def echo_server(e): # Echo the MAC and message back to the sender if not e.send(peer, msg, sync): - print("ERROR: send() failed to", peer) + print("ERROR: send() failed to", peer.hex()) return if msg == b"!done": diff --git a/tests/multi_espnow/60_irq_test.py b/tests/multi_espnow/60_irq_test.py index db8b8168690..d39f8bccc4c 100644 --- a/tests/multi_espnow/60_irq_test.py +++ b/tests/multi_espnow/60_irq_test.py @@ -29,7 +29,7 @@ def echo_server(e): # Echo the MAC and message back to the sender if not e.send(peer, msg, sync): - print("ERROR: send() failed to", peer) + print("ERROR: send() failed to", peer.hex()) return if msg == b"!done": diff --git a/tests/multi_espnow/80_asyncio_client.py b/tests/multi_espnow/80_asyncio_client.py index 8c34b98a3c4..61cf6108563 100644 --- a/tests/multi_espnow/80_asyncio_client.py +++ b/tests/multi_espnow/80_asyncio_client.py @@ -29,7 +29,7 @@ def echo_server(e): # Echo the MAC and message back to the sender if not e.send(peer, msg, sync): - print("ERROR: send() failed to", peer) + print("ERROR: send() failed to", peer.hex()) return if msg == b"!done": diff --git a/tests/multi_espnow/90_memory_test.py b/tests/multi_espnow/90_memory_test.py index b59ff61b594..fe30740e3ea 100644 --- a/tests/multi_espnow/90_memory_test.py +++ b/tests/multi_espnow/90_memory_test.py @@ -31,7 +31,7 @@ def echo_server(e): # Echo the MAC and message back to the sender if not e.send(peer, msg, sync): - print("ERROR: send() failed to", peer) + print("ERROR: send() failed to", peer.hex()) return if msg == b"!done": From 6d19fefc0cf6b5f427ea9d052fe1f53a018c7c34 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 7 May 2026 17:24:23 +1000 Subject: [PATCH 141/635] tests/multi_espnow/80_asyncio_client: Fix a possible race condition. Issue turned out to be something else, but I think there's still a potential race here without this fix. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- tests/multi_espnow/80_asyncio_client.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/multi_espnow/80_asyncio_client.py b/tests/multi_espnow/80_asyncio_client.py index 61cf6108563..b77ab54a202 100644 --- a/tests/multi_espnow/80_asyncio_client.py +++ b/tests/multi_espnow/80_asyncio_client.py @@ -66,6 +66,8 @@ async def client(e): e.add_peer(peer) multitest.next() + multitest.wait("server ready") + print("airecv() test...") msgs = [] for i in range(5): @@ -93,6 +95,7 @@ def instance0(): init(e, True, False) multitest.globals(PEERS=[network.WLAN(i).config("mac") for i in (0, 1)]) multitest.next() + multitest.broadcast("server ready") print("Server Start") echo_server(e) print("Server Done") From ec5a843fb62542a9dd2897f9504c0f64dade6d75 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 7 May 2026 17:25:47 +1000 Subject: [PATCH 142/635] tests/multi_espnow/75_rate: Fix cleanup of STA instance at end of test. Was causing the next test to fail (maybe only when the other instance skipped, not sure.) This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- tests/multi_espnow/75_rate.py | 73 +++++++++++++++++++---------------- 1 file changed, 39 insertions(+), 34 deletions(-) diff --git a/tests/multi_espnow/75_rate.py b/tests/multi_espnow/75_rate.py index 805ac4f0701..f676ab1d616 100644 --- a/tests/multi_espnow/75_rate.py +++ b/tests/multi_espnow/75_rate.py @@ -49,17 +49,21 @@ def init_sta(): # Receiver def instance0(): sta, e = init_sta() - multitest.globals(PEER=sta.config("mac")) - multitest.next() - while True: - peer, msg = e.recv(timeout_ms) - if peer is None: - print("Timeout") - break - # Note that we don't have any way in Python to tell what data rate this message - # was received with, so we're assuming the rate was correct. - print(msg) - e.active(False) + try: + multitest.globals(PEER=sta.config("mac")) + multitest.next() + while True: + peer, msg = e.recv(timeout_ms) + if peer is None: + print("Timeout") + break + # Note that we don't have any way in Python to tell what data rate this message + # was received with, so we're assuming the rate was correct. + print(msg) + finally: + # Important to stop both even if the test is skipped due to the other instance + sta.active(False) + e.active(False) # Sender @@ -67,26 +71,27 @@ def instance1(): sta, e = init_sta() multitest.next() peer = PEER - - e.add_peer(peer) - # Test normal, non-LR rates - for msg, rate in ( - (b"default rate", None), - (b"5Mbit", espnow.RATE_5M), - (b"11Mbit", espnow.RATE_11M), - (b"24Mbit", espnow.RATE_24M), - (b"54Mbit", espnow.RATE_54M), - (b"250K LR", espnow.RATE_LORA_250K), - (b"500K LR", espnow.RATE_LORA_500K), - # switch back to non-LR rates to check it's all OK - (b"1Mbit again", espnow.RATE_1M), - (b"11Mbit again", espnow.RATE_11M), - ): - if rate is not None: - e.config(rate=rate) - for _ in range(3): - e.send(peer, msg) - time.sleep_ms(50) # give messages some time to be received before continuing - e.del_peer(peer) - - e.active(False) + try: + e.add_peer(peer) + # Test normal, non-LR rates + for msg, rate in ( + (b"default rate", None), + (b"5Mbit", espnow.RATE_5M), + (b"11Mbit", espnow.RATE_11M), + (b"24Mbit", espnow.RATE_24M), + (b"54Mbit", espnow.RATE_54M), + (b"250K LR", espnow.RATE_LORA_250K), + (b"500K LR", espnow.RATE_LORA_500K), + # switch back to non-LR rates to check it's all OK + (b"1Mbit again", espnow.RATE_1M), + (b"11Mbit again", espnow.RATE_11M), + ): + if rate is not None: + e.config(rate=rate) + for _ in range(3): + e.send(peer, msg) + time.sleep_ms(50) # give messages some time to be received before continuing + e.del_peer(peer) + finally: + sta.active(False) + e.active(False) From b8f01259cf7e7d79083f5c8a34e3308ba11c89e9 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 7 May 2026 17:26:55 +1000 Subject: [PATCH 143/635] tests/multi_espnow/70_channel: Skip on ESP32-C6 (workaround). Test always fails on this chip, looks like possibly an ESP-IDF v5.5.1 bug. Signed-off-by: Angus Gratton --- tests/multi_espnow/70_channel.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/multi_espnow/70_channel.py b/tests/multi_espnow/70_channel.py index f3e8b947b12..90b963a7a4c 100644 --- a/tests/multi_espnow/70_channel.py +++ b/tests/multi_espnow/70_channel.py @@ -21,6 +21,11 @@ print("SKIP") raise SystemExit +# Workaround for a bug in ESP32-C6 where it doesn't select channels cleanly +# (probably an ESP-IDF v5.5.x bug, needs further investigation.) +if "ESP32-C6" in sys.implementation._machine: + print("SKIP") + raise SystemExit timeout_ms = 1000 default_pmk = b"MicroPyth0nRules" From 7ba33a27472427afdd62c10a51017555575cf066 Mon Sep 17 00:00:00 2001 From: Damien George Date: Sun, 17 May 2026 22:47:03 +1000 Subject: [PATCH 144/635] tests/feature_check: Remove .py.exp file for feature-check tests. Feature check .py.exp files are not needed at all (and most of them are empty). Instead, the output of the feaure test is checked against a known value within `run-tests.py` to see if that feature is enabled or not (and in some cases like `byteorder.py` there are multiple valid output values). Signed-off-by: Damien George --- tests/feature_check/async_check.py.exp | 0 tests/feature_check/bytearray.py.exp | 0 tests/feature_check/byteorder.py.exp | 0 tests/feature_check/complex.py.exp | 0 tests/feature_check/const.py.exp | 0 tests/feature_check/coverage.py.exp | 0 tests/feature_check/fstring.py.exp | 1 - tests/feature_check/inlineasm_rv32.py.exp | 1 - tests/feature_check/inlineasm_rv32_zba.py.exp | 1 - tests/feature_check/inlineasm_rv32_zcmp.py.exp | 1 - tests/feature_check/inlineasm_thumb.py.exp | 1 - tests/feature_check/inlineasm_thumb2.py.exp | 1 - tests/feature_check/inlineasm_xtensa.py.exp | 1 - tests/feature_check/int_64.py.exp | 1 - tests/feature_check/int_big.py.exp | 1 - tests/feature_check/native_check.py.exp | 0 tests/feature_check/repl_emacs_check.py.exp | 7 ------- tests/feature_check/repl_words_move_check.py.exp | 7 ------- tests/feature_check/reverse_ops.py.exp | 0 tests/feature_check/set_check.py.exp | 0 tests/feature_check/slice.py.exp | 0 tests/feature_check/target_info.py.exp | 0 tests/feature_check/tstring.py.exp | 1 - tests/run-tests.py | 12 ++++++++++-- 24 files changed, 10 insertions(+), 26 deletions(-) delete mode 100644 tests/feature_check/async_check.py.exp delete mode 100644 tests/feature_check/bytearray.py.exp delete mode 100644 tests/feature_check/byteorder.py.exp delete mode 100644 tests/feature_check/complex.py.exp delete mode 100644 tests/feature_check/const.py.exp delete mode 100644 tests/feature_check/coverage.py.exp delete mode 100644 tests/feature_check/fstring.py.exp delete mode 100644 tests/feature_check/inlineasm_rv32.py.exp delete mode 100644 tests/feature_check/inlineasm_rv32_zba.py.exp delete mode 100644 tests/feature_check/inlineasm_rv32_zcmp.py.exp delete mode 100644 tests/feature_check/inlineasm_thumb.py.exp delete mode 100644 tests/feature_check/inlineasm_thumb2.py.exp delete mode 100644 tests/feature_check/inlineasm_xtensa.py.exp delete mode 100644 tests/feature_check/int_64.py.exp delete mode 100644 tests/feature_check/int_big.py.exp delete mode 100644 tests/feature_check/native_check.py.exp delete mode 100644 tests/feature_check/repl_emacs_check.py.exp delete mode 100644 tests/feature_check/repl_words_move_check.py.exp delete mode 100644 tests/feature_check/reverse_ops.py.exp delete mode 100644 tests/feature_check/set_check.py.exp delete mode 100644 tests/feature_check/slice.py.exp delete mode 100644 tests/feature_check/target_info.py.exp delete mode 100644 tests/feature_check/tstring.py.exp diff --git a/tests/feature_check/async_check.py.exp b/tests/feature_check/async_check.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/bytearray.py.exp b/tests/feature_check/bytearray.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/byteorder.py.exp b/tests/feature_check/byteorder.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/complex.py.exp b/tests/feature_check/complex.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/const.py.exp b/tests/feature_check/const.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/coverage.py.exp b/tests/feature_check/coverage.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/fstring.py.exp b/tests/feature_check/fstring.py.exp deleted file mode 100644 index 73cdb8bcc87..00000000000 --- a/tests/feature_check/fstring.py.exp +++ /dev/null @@ -1 +0,0 @@ -a=1 diff --git a/tests/feature_check/inlineasm_rv32.py.exp b/tests/feature_check/inlineasm_rv32.py.exp deleted file mode 100644 index 5eecf09c224..00000000000 --- a/tests/feature_check/inlineasm_rv32.py.exp +++ /dev/null @@ -1 +0,0 @@ -rv32 diff --git a/tests/feature_check/inlineasm_rv32_zba.py.exp b/tests/feature_check/inlineasm_rv32_zba.py.exp deleted file mode 100644 index fde22f5f400..00000000000 --- a/tests/feature_check/inlineasm_rv32_zba.py.exp +++ /dev/null @@ -1 +0,0 @@ -rv32_zba diff --git a/tests/feature_check/inlineasm_rv32_zcmp.py.exp b/tests/feature_check/inlineasm_rv32_zcmp.py.exp deleted file mode 100644 index 1fe96068194..00000000000 --- a/tests/feature_check/inlineasm_rv32_zcmp.py.exp +++ /dev/null @@ -1 +0,0 @@ -rv32_zcmp diff --git a/tests/feature_check/inlineasm_thumb.py.exp b/tests/feature_check/inlineasm_thumb.py.exp deleted file mode 100644 index bb48e1a2f03..00000000000 --- a/tests/feature_check/inlineasm_thumb.py.exp +++ /dev/null @@ -1 +0,0 @@ -thumb diff --git a/tests/feature_check/inlineasm_thumb2.py.exp b/tests/feature_check/inlineasm_thumb2.py.exp deleted file mode 100644 index 05d125af9f6..00000000000 --- a/tests/feature_check/inlineasm_thumb2.py.exp +++ /dev/null @@ -1 +0,0 @@ -thumb2 diff --git a/tests/feature_check/inlineasm_xtensa.py.exp b/tests/feature_check/inlineasm_xtensa.py.exp deleted file mode 100644 index 036142c5097..00000000000 --- a/tests/feature_check/inlineasm_xtensa.py.exp +++ /dev/null @@ -1 +0,0 @@ -xtensa diff --git a/tests/feature_check/int_64.py.exp b/tests/feature_check/int_64.py.exp deleted file mode 100644 index aef5454e662..00000000000 --- a/tests/feature_check/int_64.py.exp +++ /dev/null @@ -1 +0,0 @@ -4611686018427387904 diff --git a/tests/feature_check/int_big.py.exp b/tests/feature_check/int_big.py.exp deleted file mode 100644 index 9dfe3354d59..00000000000 --- a/tests/feature_check/int_big.py.exp +++ /dev/null @@ -1 +0,0 @@ -1000000000000000000000000000000000000000000000 diff --git a/tests/feature_check/native_check.py.exp b/tests/feature_check/native_check.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/repl_emacs_check.py.exp b/tests/feature_check/repl_emacs_check.py.exp deleted file mode 100644 index 2dfb2da58b8..00000000000 --- a/tests/feature_check/repl_emacs_check.py.exp +++ /dev/null @@ -1,7 +0,0 @@ -MicroPython \.\+ version -Type "help()" for more information. ->>> # Check for emacs keys in REPL ->>> t = \.\+ ->>> t == 2 -True ->>> \$ diff --git a/tests/feature_check/repl_words_move_check.py.exp b/tests/feature_check/repl_words_move_check.py.exp deleted file mode 100644 index 2dfb2da58b8..00000000000 --- a/tests/feature_check/repl_words_move_check.py.exp +++ /dev/null @@ -1,7 +0,0 @@ -MicroPython \.\+ version -Type "help()" for more information. ->>> # Check for emacs keys in REPL ->>> t = \.\+ ->>> t == 2 -True ->>> \$ diff --git a/tests/feature_check/reverse_ops.py.exp b/tests/feature_check/reverse_ops.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/set_check.py.exp b/tests/feature_check/set_check.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/slice.py.exp b/tests/feature_check/slice.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/target_info.py.exp b/tests/feature_check/target_info.py.exp deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/tests/feature_check/tstring.py.exp b/tests/feature_check/tstring.py.exp deleted file mode 100644 index ba42b0ec666..00000000000 --- a/tests/feature_check/tstring.py.exp +++ /dev/null @@ -1 +0,0 @@ -tstring diff --git a/tests/run-tests.py b/tests/run-tests.py index 38f78620e44..aeb06661fc7 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -465,7 +465,9 @@ def detect_target_wiring_script(pyb, args): ] -def run_micropython(pyb, args, test_file, test_file_abspath, is_special=False): +def run_micropython( + pyb, args, test_file, test_file_abspath, is_special=False, is_feature_check=False +): had_crash = False if pyb is None: # run on PC @@ -648,6 +650,10 @@ def preexec_fn(): # canonical form for all ports/platforms is to use \n for end-of-line output_mupy = normalize_newlines(output_mupy) + # for feature-check tests, return the output as-is + if is_feature_check: + return output_mupy + # don't try to convert the output if we should skip this test if had_crash or output_mupy in (b"SKIP\n", b"SKIP-TOO-LARGE\n", b"CRASH"): return output_mupy @@ -710,7 +716,9 @@ def run_feature_check(pyb, args, test_file): # REPL feature tests will not run via pyboard because they require prompt interactivity return b"" test_file_path = base_path("feature_check", test_file) - return run_micropython(pyb, args, test_file_path, test_file_path, is_special=True) + return run_micropython( + pyb, args, test_file_path, test_file_path, is_special=True, is_feature_check=True + ) class TestError(Exception): From e0bac71beff6b5174bedcbbc4c9428cd287bba81 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 24 Apr 2026 16:55:58 +1000 Subject: [PATCH 145/635] extmod/nimble/modbluetooth_nimble: Remove unneeded variable decls. They are provided in a private header that is already included. Signed-off-by: Damien George --- extmod/nimble/modbluetooth_nimble.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/extmod/nimble/modbluetooth_nimble.c b/extmod/nimble/modbluetooth_nimble.c index 6b000f77f8a..4b8b6529e05 100644 --- a/extmod/nimble/modbluetooth_nimble.c +++ b/extmod/nimble/modbluetooth_nimble.c @@ -584,9 +584,6 @@ void nimble_reset_gatts_bss(void) { // These variables are defined in ble_hs.c and are only ever incremented // (during service registration) and never reset. // See https://github.com/apache/mynewt-nimble/issues/896 - extern uint16_t ble_hs_max_attrs; - extern uint16_t ble_hs_max_services; - extern uint16_t ble_hs_max_client_configs; ble_hs_max_attrs = 0; ble_hs_max_services = 0; ble_hs_max_client_configs = 0; From a4d32629d4bdea99da19cfa9df3a55361f2f222a Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 24 Apr 2026 17:00:48 +1000 Subject: [PATCH 146/635] esp32: Update to IDF v5.5.2 as recommended version. Also support v5.5.4, but don't use it yet due to possible issues discussed in #19149. Signed-off-by: Damien George --- .github/workflows/ports_esp32.yml | 2 +- ports/esp32/README.md | 4 ++-- ports/esp32/boards/sdkconfig.ble | 4 ++++ ports/esp32/esp32_common.cmake | 4 ++++ ports/esp32/lockfiles/dependencies.lock.esp32 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32c2 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32c3 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32c5 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32c6 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32p4 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32s2 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32s3 | 2 +- 12 files changed, 19 insertions(+), 11 deletions(-) diff --git a/.github/workflows/ports_esp32.yml b/.github/workflows/ports_esp32.yml index 56dce3b69d9..e2d3f3ad64d 100644 --- a/.github/workflows/ports_esp32.yml +++ b/.github/workflows/ports_esp32.yml @@ -20,7 +20,7 @@ concurrency: env: # Oldest and newest supported ESP-IDF versions, should match ports/esp32/README.md IDF_OLDEST_VER: &oldest "v5.3" - IDF_NEWEST_VER: &newest "v5.5.1" + IDF_NEWEST_VER: &newest "v5.5.2" jobs: build_idf: diff --git a/ports/esp32/README.md b/ports/esp32/README.md index 85e13904054..c097ca7e76d 100644 --- a/ports/esp32/README.md +++ b/ports/esp32/README.md @@ -52,8 +52,8 @@ manage the ESP32 microcontroller, as well as a way to manage the required build environment and toolchains needed to build the firmware. The ESP-IDF changes quickly and MicroPython only supports certain versions. The -current recommended version of ESP-IDF for MicroPython is v5.5.1. MicroPython -also supports v5.3, v5.4, v5.4.1 and v5.4.2. +current recommended version of ESP-IDF for MicroPython is v5.5.2. MicroPython +also supports v5.3, v5.4, v5.4.1, v5.4.2, v5.5.1 and v5.5.4. %p\n", ptr); return ptr; } diff --git a/extmod/nimble/syscfg/syscfg.h b/extmod/nimble/syscfg/syscfg.h index f26f8db9ec3..60f638fdb3a 100644 --- a/extmod/nimble/syscfg/syscfg.h +++ b/extmod/nimble/syscfg/syscfg.h @@ -17,7 +17,7 @@ void *nimble_realloc(void *ptr, size_t size); int nimble_sprintf(char *str, const char *fmt, ...); #define sprintf(str, fmt, ...) nimble_sprintf(str, fmt, __VA_ARGS__) -#define MYNEWT_VAL(x) MYNEWT_VAL_ ## x +#define MYNEWT_VAL(x) MYNEWT_VAL_##x #define MYNEWT_VAL_LOG_LEVEL (255) diff --git a/shared/libc/string0.c b/shared/libc/string0.c index ea774205c4e..de39768ca2b 100644 --- a/shared/libc/string0.c +++ b/shared/libc/string0.c @@ -42,14 +42,14 @@ void *memcpy(void *dst, const void *src, size_t n) { if (n & 2) { // copy half-word - *(uint16_t*)d = *(const uint16_t*)s; - d = (uint32_t*)((uint16_t*)d + 1); - s = (const uint32_t*)((const uint16_t*)s + 1); + *(uint16_t *)d = *(const uint16_t *)s; + d = (uint32_t *)((uint16_t *)d + 1); + s = (const uint32_t *)((const uint16_t *)s + 1); } if (n & 1) { // copy byte - *((uint8_t*)d) = *((const uint8_t*)s); + *((uint8_t *)d) = *((const uint8_t *)s); } } else { // unaligned access, copy bytes @@ -72,10 +72,10 @@ void *__memcpy_chk(void *dest, const void *src, size_t len, size_t slen) { } void *memmove(void *dest, const void *src, size_t n) { - if (src < dest && (uint8_t*)dest < (const uint8_t*)src + n) { + if (src < dest && (uint8_t *)dest < (const uint8_t *)src + n) { // need to copy backwards - uint8_t *d = (uint8_t*)dest + n - 1; - const uint8_t *s = (const uint8_t*)src + n - 1; + uint8_t *d = (uint8_t *)dest + n - 1; + const uint8_t *s = (const uint8_t *)src + n - 1; for (; n > 0; n--) { *d-- = *s--; } @@ -94,11 +94,11 @@ void *memset(void *s, int c, size_t n) { *s32++ = 0; } if (n & 2) { - *((uint16_t*)s32) = 0; - s32 = (uint32_t*)((uint16_t*)s32 + 1); + *((uint16_t *)s32) = 0; + s32 = (uint32_t *)((uint16_t *)s32 + 1); } if (n & 1) { - *((uint8_t*)s32) = 0; + *((uint8_t *)s32) = 0; } } else { uint8_t *s2 = s; @@ -115,8 +115,11 @@ int memcmp(const void *s1, const void *s2, size_t n) { while (n--) { char c1 = *s1_8++; char c2 = *s2_8++; - if (c1 < c2) return -1; - else if (c1 > c2) return 1; + if (c1 < c2) { + return -1; + } else if (c1 > c2) { + return 1; + } } return 0; } @@ -126,8 +129,9 @@ void *memchr(const void *s, int c, size_t n) { const unsigned char *p = s; do { - if (*p++ == c) - return ((void *)(p - 1)); + if (*p++ == c) { + return (void *)(p - 1); + } } while (--n != 0); } return 0; @@ -145,12 +149,19 @@ int strcmp(const char *s1, const char *s2) { while (*s1 && *s2) { char c1 = *s1++; // XXX UTF8 get char, next char char c2 = *s2++; // XXX UTF8 get char, next char - if (c1 < c2) return -1; - else if (c1 > c2) return 1; + if (c1 < c2) { + return -1; + } else if (c1 > c2) { + return 1; + } + } + if (*s2) { + return -1; + } else if (*s1) { + return 1; + } else { + return 0; } - if (*s2) return -1; - else if (*s1) return 1; - else return 0; } int strncmp(const char *s1, const char *s2, size_t n) { @@ -158,13 +169,21 @@ int strncmp(const char *s1, const char *s2, size_t n) { char c1 = *s1++; // XXX UTF8 get char, next char char c2 = *s2++; // XXX UTF8 get char, next char n--; - if (c1 < c2) return -1; - else if (c1 > c2) return 1; + if (c1 < c2) { + return -1; + } else if (c1 > c2) { + return 1; + } + } + if (n == 0) { + return 0; + } else if (*s2) { + return -1; + } else if (*s1) { + return 1; + } else { + return 0; } - if (n == 0) return 0; - else if (*s2) return -1; - else if (*s1) return 1; - else return 0; } char *strcpy(char *dest, const char *src) { @@ -179,21 +198,21 @@ char *strcpy(char *dest, const char *src) { // Public Domain implementation of strncpy from: // http://en.wikibooks.org/wiki/C_Programming/Strings#The_strncpy_function char *strncpy(char *s1, const char *s2, size_t n) { - char *dst = s1; - const char *src = s2; - /* Copy bytes, one at a time. */ - while (n > 0) { - n--; - if ((*dst++ = *src++) == '\0') { - /* If we get here, we found a null character at the end - of s2, so use memset to put null bytes at the end of - s1. */ - memset(dst, '\0', n); - break; - } - } - return s1; - } + char *dst = s1; + const char *src = s2; + /* Copy bytes, one at a time. */ + while (n > 0) { + n--; + if ((*dst++ = *src++) == '\0') { + /* If we get here, we found a null character at the end + of s2, so use memset to put null bytes at the end of + s1. */ + memset(dst, '\0', n); + break; + } + } + return s1; +} // needed because gcc optimises strcpy + strcat to this char *stpcpy(char *dest, const char *src) { @@ -218,29 +237,31 @@ char *strcat(char *dest, const char *src) { // Public Domain implementation of strchr from: // http://en.wikibooks.org/wiki/C_Programming/Strings#The_strchr_function -char *strchr(const char *s, int c) -{ +char *strchr(const char *s, int c) { /* Scan s for the character. When this loop is finished, s will either point to the end of the string or the character we were looking for. */ - while (*s != '\0' && *s != (char)c) + while (*s != '\0' && *s != (char)c) { s++; - return ((*s == c) ? (char *) s : 0); + } + return (*s == c) ? (char *)s : 0; } // Public Domain implementation of strstr from: // http://en.wikibooks.org/wiki/C_Programming/Strings#The_strstr_function -char *strstr(const char *haystack, const char *needle) -{ +char *strstr(const char *haystack, const char *needle) { size_t needlelen; /* Check for the null needle case. */ - if (*needle == '\0') - return (char *) haystack; + if (*needle == '\0') { + return (char *)haystack; + } needlelen = strlen(needle); - for (; (haystack = strchr(haystack, *needle)) != 0; haystack++) - if (strncmp(haystack, needle, needlelen) == 0) - return (char *) haystack; + for (; (haystack = strchr(haystack, *needle)) != 0; haystack++) { + if (strncmp(haystack, needle, needlelen) == 0) { + return (char *)haystack; + } + } return 0; } From 21f5eb0fcddd1ddfd4d31efe1cf62b1a5a3a21f9 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 22 Jun 2026 13:26:31 +1000 Subject: [PATCH 292/635] top: Update .git-blame-ignore-revs for latest formatting commit. Signed-off-by: Damien George --- .git-blame-ignore-revs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs index 195e1e06eea..97b5e558f40 100644 --- a/.git-blame-ignore-revs +++ b/.git-blame-ignore-revs @@ -1,3 +1,6 @@ +# all: Apply code formatting to new paths. +48c7daaa3d7068c127c5bc395ffa72029ab9bba1 + # all: Prune trailing whitespace. dda9b9c6da5d3c31fa8769e581a753e95a270803 From 93d543c03739d6637a9e77735d45bbf3ec0f0745 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Mon, 15 Jun 2026 06:32:48 +0200 Subject: [PATCH 293/635] shared/memzip/make-memzip.py: Update script to Python3. This commit updates the `make-memzip.py` utility to finish the migration to Python 3.x. The code still wasn't fully aware of how Python unified bytes and strings when it comes to I/O API. These changes help with that. Signed-off-by: Alessandro Gatti --- shared/memzip/make-memzip.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/shared/memzip/make-memzip.py b/shared/memzip/make-memzip.py index e406c55a43c..76fa368748b 100755 --- a/shared/memzip/make-memzip.py +++ b/shared/memzip/make-memzip.py @@ -11,7 +11,6 @@ import os import subprocess import sys -import types def create_zip(zip_filename, zip_dir): @@ -26,7 +25,7 @@ def create_zip(zip_filename, zip_dir): def create_c_from_file(c_filename, zip_filename): with open(zip_filename, "rb") as zip_file: - with open(c_filename, "wb") as c_file: + with open(c_filename, "wt") as c_file: print("#include ", file=c_file) print("", file=c_file) print("const uint8_t memzip_data[] = {", file=c_file) @@ -36,10 +35,7 @@ def create_c_from_file(c_filename, zip_filename): break print(" ", end="", file=c_file) for byte in buf: - if isinstance(byte, types.StringType): - print(" 0x{:02x},".format(ord(byte)), end="", file=c_file) - else: - print(" 0x{:02x},".format(byte), end="", file=c_file) + print(" 0x{:02x},".format(byte), end="", file=c_file) print("", file=c_file) print("};", file=c_file) From 095227cccdb5bd279174b11c4ffaa4490423738a Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Mon, 15 Jun 2026 06:35:40 +0200 Subject: [PATCH 294/635] shared/memzip/make-memzip.py: Improve script resilience. This commit makes the `make-memzip.py` utility more resilient in certain usage cases, which weren't accounted for in the original source. In some Linux distributions the `zip` command may not be available, although `unzip` could be. Unless the `zip` package is installed this script will fail with a generic "file not found" error, which has been addressed in these changes set. Also, the `zip` command by default adds a `.zip` suffix to archives, which wasn't accounted for. So, running `./make-memzip -z z1 -c z2 .` would fail, as the script would build `z1.zip` whilst the header generator attempted to open `z1` instead. This has now been fixed. Signed-off-by: Alessandro Gatti --- shared/memzip/make-memzip.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/shared/memzip/make-memzip.py b/shared/memzip/make-memzip.py index 76fa368748b..c060745e6cf 100755 --- a/shared/memzip/make-memzip.py +++ b/shared/memzip/make-memzip.py @@ -9,6 +9,8 @@ import argparse import os +import pathlib +import shutil import subprocess import sys @@ -63,10 +65,20 @@ def main(): parser.add_argument(dest="source_dir", default="memzip_files") args = parser.parse_args(sys.argv[1:]) + output_zip = pathlib.Path(args.zip_filename) + if output_zip.suffix != ".zip": + args.zip_filename = output_zip.with_suffix(".zip") + output_c = pathlib.Path(args.c_filename) + if output_c.suffix != ".c": + args.c_filename = output_c.with_suffix(".c") + print("args.zip_filename =", args.zip_filename) print("args.c_filename =", args.c_filename) print("args.source_dir =", args.source_dir) + if not shutil.which("zip"): + raise FileNotFoundError("zip archiver not available") + create_zip(args.zip_filename, args.source_dir) create_c_from_file(args.c_filename, args.zip_filename) From 531c80dc0e29ca092925145542d6cae0236eb24d Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sun, 14 Jun 2026 12:18:06 +0200 Subject: [PATCH 295/635] tools/mpy_ld.py: Do not share build directory across architectures. This commit modifies the native modules build system to use different directories for different architectures. Previously, the natmod build system would unconditionally put all build data into a single directory (usually "$(PWD)/build" unless overridden), and the static library runtime cache into another directory ("$(PWD)/.mpy_ld_cache"). That works if building is always done for a single architecture or if a full clean is performed before switching architectures, which sometimes is not wanted (collecting the runtime cache may take quite some time depending on the module complexity, for example). With these changes, both the build directory and the runtime cache directories are marked with the name of the architecture they target, so for example "$(PWD)/build" becomes "$(PWD)/build_x64" (the same happens to the cache directory name). Signed-off-by: Alessandro Gatti --- .gitignore | 1 + py/dynruntime.mk | 4 ++-- tools/ar_util.py | 18 ++++++++++++++++-- tools/mpy_ld.py | 3 +++ 4 files changed, 22 insertions(+), 4 deletions(-) diff --git a/.gitignore b/.gitignore index 56616426fb2..b17423ca050 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ build/ build-*/ docs/genrst/ +.mpy_ld_cache-*/ # Test failure outputs and intermediate artefacts tests/results/* diff --git a/py/dynruntime.mk b/py/dynruntime.mk index 3902acbd0b3..b5f6747cc99 100644 --- a/py/dynruntime.mk +++ b/py/dynruntime.mk @@ -1,7 +1,7 @@ # Makefile fragment for generating native .mpy files from C source # MPY_DIR must be set to the top of the MicroPython source tree -BUILD ?= build +BUILD ?= build-$(ARCH) ECHO = @echo RM = /bin/rm @@ -39,7 +39,7 @@ MPY_CROSS_FLAGS += -march=$(ARCH) SRC_O += $(addprefix $(BUILD)/, $(patsubst %.c,%.o,$(filter %.c,$(SRC))) $(patsubst %.S,%.o,$(filter %.S,$(SRC)))) SRC_MPY += $(addprefix $(BUILD)/, $(patsubst %.py,%.mpy,$(filter %.py,$(SRC)))) -CLEAN_EXTRA += $(MOD).mpy .mpy_ld_cache +CLEAN_EXTRA += $(MOD).mpy .mpy_ld_cache-$(ARCH) ################################################################################ # Architecture configuration diff --git a/tools/ar_util.py b/tools/ar_util.py index b90d3790314..4eb41c93654 100644 --- a/tools/ar_util.py +++ b/tools/ar_util.py @@ -39,6 +39,10 @@ Archive = None +DEFAULT_CACHE_BASE_PATH = ".mpy_ld_cache" +DEFAULT_CACHE_PREFIX = "ar_" + + class PickleCache: def __init__(self, path, prefix=""): self.path = path @@ -63,11 +67,21 @@ def load(self, key): return pickle.load(f) -def cached(key, cache): +PICKLE_CACHE = None + + +def init_cache(path, prefix): + global PICKLE_CACHE + PICKLE_CACHE = PickleCache(path, prefix) + + +def cached(key, provider): def decorator(func): @functools.wraps(func) def wrapper(*args, **kwargs): cache_key = key(*args, **kwargs) + cache = provider() + assert cache is not None try: d = cache.load(cache_key) if d["key"] != cache_key: @@ -114,7 +128,7 @@ def _cache_key(self): sha.update(bytes.fromhex("00000000000000000000000000000001")) return sha.hexdigest() - @cached(key=_cache_key, cache=PickleCache(path=".mpy_ld_cache", prefix="ar_")) + @cached(key=_cache_key, provider=lambda: PICKLE_CACHE) def load_symbols(self): print("Loading", self.fn) objs = defaultdict(lambda: {"def": set(), "undef": set(), "weak": set()}) diff --git a/tools/mpy_ld.py b/tools/mpy_ld.py index f406cd54ec1..f86c27930e2 100755 --- a/tools/mpy_ld.py +++ b/tools/mpy_ld.py @@ -1548,6 +1548,9 @@ def do_link(args): load_object_file(env, f, fn) if args.libs: + ar_util.init_cache( + f"{ar_util.DEFAULT_CACHE_BASE_PATH}-{args.arch}", ar_util.DEFAULT_CACHE_PREFIX + ) # Load archive info archives = [] for item in args.libs: From 6bbeec244bc676809a20e78b670770ccc2d0b6f0 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Wed, 17 Jun 2026 17:47:14 +0200 Subject: [PATCH 296/635] py/dynruntime.mk: Use the final file name for intermediate outputs. This commit makes a minor change to the native module build scripts, to make the intermediate MPY file keep the same file name it will have once the final pre-processing step takes place. A MPY file will retain its file name as the first QSTR entry in the file, and before these changes the name being written would be the one used for the intermediate MPY output file (ie. "$BUILDDIR/$MODNAME.native.mpy"). The `mpy-tool.py` preprocessing pass would keep that string intact but rename the file, so things wouldn't match in error tracebacks. Signed-off-by: Alessandro Gatti --- py/dynruntime.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/py/dynruntime.mk b/py/dynruntime.mk index b5f6747cc99..b2e3ffff986 100644 --- a/py/dynruntime.mk +++ b/py/dynruntime.mk @@ -237,11 +237,11 @@ $(BUILD)/%.mpy: %.py $(Q)$(MPY_CROSS) $(MPY_CROSS_FLAGS) -o $@ $< # Build native .mpy from object files -$(BUILD)/$(MOD).native.mpy: $(SRC_O) +$(BUILD)/$(MOD).mpy: $(SRC_O) $(ECHO) "LINK $<" $(Q)$(MPY_LD) --arch $(ARCH) --qstrs $(CONFIG_H) $(MPY_LD_FLAGS) -o $@ $^ # Build final .mpy from all intermediate .mpy files -$(MOD).mpy: $(BUILD)/$(MOD).native.mpy $(SRC_MPY) +$(MOD).mpy: $(BUILD)/$(MOD).mpy $(SRC_MPY) $(ECHO) "GEN $@" $(Q)$(MPY_TOOL) --merge -o $@ $^ From b49f098cfbc7f7dfbd4b41d56f8a242f54c512bb Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sun, 14 Jun 2026 12:29:45 +0200 Subject: [PATCH 297/635] tools/mpy_ld.py: Allow overriding the internal MPY file name. This commit adds an option to the MPY linker to brand generated file with a custom internal file name rather than the raw output path provided in the command line. MPY files, as part of their preambles, will contain a path name as the first entry in the constant string pool. However that may contain unneeded data (ie. sometimes the plain file name is enough) or it may have sensitive data in there (if an alternate build path is provided it may contain product code names or client names which should probably not be disclosed). Until now there was no provision to let users use a different internal path name. A new option was added to `mpy_ld.py`: "--source-name" which, if passed, will write the given string in the module file. If said option is not provided, generated MPY files will still carry the raw command line output path but stripped of all leading path segments. The example natmod makefiles have been updated to always provide that option whenever the final file name on the filesystem wouldn't match the internal MPY file name. Signed-off-by: Alessandro Gatti --- examples/natmod/btree/Makefile | 6 +++++- examples/natmod/deflate/Makefile | 6 +++++- examples/natmod/framebuf/Makefile | 6 +++++- examples/natmod/heapq/Makefile | 6 +++++- examples/natmod/random/Makefile | 6 +++++- examples/natmod/re/Makefile | 6 +++++- tools/mpy_ld.py | 16 +++++++++++++--- 7 files changed, 43 insertions(+), 9 deletions(-) diff --git a/examples/natmod/btree/Makefile b/examples/natmod/btree/Makefile index 4ded62bafde..7f4349e2b84 100644 --- a/examples/natmod/btree/Makefile +++ b/examples/natmod/btree/Makefile @@ -2,7 +2,8 @@ MPY_DIR = ../../.. # Name of module (different to built-in btree so it can coexist) -MOD = btree_$(ARCH) +MOD_BASE = btree +MOD = $(MOD_BASE)_$(ARCH) # Source files (.c or .py) SRC = btree_c.c @@ -44,6 +45,9 @@ ifeq ($(ARCH),armv6m) LINK_RUNTIME = 1 endif +# Strip the architecture name from the internal filename. +MPY_LD_FLAGS = "--source-name=$(MOD_BASE).mpy" + include $(MPY_DIR)/py/dynruntime.mk # btree needs gnu99 defined diff --git a/examples/natmod/deflate/Makefile b/examples/natmod/deflate/Makefile index 0574bbaf412..a76f8c843bd 100644 --- a/examples/natmod/deflate/Makefile +++ b/examples/natmod/deflate/Makefile @@ -2,7 +2,8 @@ MPY_DIR = ../../.. # Name of module (different to built-in uzlib so it can coexist) -MOD = deflate_$(ARCH) +MOD_BASE = deflate +MOD = $(MOD_BASE)_$(ARCH) # Source files (.c or .py) SRC = deflate.c @@ -21,4 +22,7 @@ LINK_RUNTIME = 1 MPY_EXTERN_SYM_FILE=$(MPY_DIR)/ports/esp8266/boards/eagle.rom.addr.v6.ld endif +# Strip the architecture name from the internal filename. +MPY_LD_FLAGS = "--source-name=$(MOD_BASE).mpy" + include $(MPY_DIR)/py/dynruntime.mk diff --git a/examples/natmod/framebuf/Makefile b/examples/natmod/framebuf/Makefile index a86efef41f4..ed0a795dc00 100644 --- a/examples/natmod/framebuf/Makefile +++ b/examples/natmod/framebuf/Makefile @@ -2,7 +2,8 @@ MPY_DIR = ../../.. # Name of module (different to built-in framebuf so it can coexist) -MOD = framebuf_$(ARCH) +MOD_BASE = framebuf +MOD = $(MOD_BASE)_$(ARCH) # Source files (.c or .py) SRC = framebuf.c @@ -19,4 +20,7 @@ ifeq ($(ARCH),xtensa) MPY_EXTERN_SYM_FILE=$(MPY_DIR)/ports/esp8266/boards/eagle.rom.addr.v6.ld endif +# Strip the architecture name from the internal filename. +MPY_LD_FLAGS = "--source-name=$(MOD_BASE).mpy" + include $(MPY_DIR)/py/dynruntime.mk diff --git a/examples/natmod/heapq/Makefile b/examples/natmod/heapq/Makefile index 345359abb3c..494284e0838 100644 --- a/examples/natmod/heapq/Makefile +++ b/examples/natmod/heapq/Makefile @@ -2,7 +2,8 @@ MPY_DIR = ../../.. # Name of module (different to built-in heapq so it can coexist) -MOD = heapq_$(ARCH) +MOD_BASE = heapq +MOD = $(MOD_BASE)_$(ARCH) # Source files (.c or .py) SRC = heapq.c @@ -10,4 +11,7 @@ SRC = heapq.c # Architecture to build for (x86, x64, armv7m, xtensa, xtensawin, rv32imc, rv64imc) ARCH = x64 +# Strip the architecture name from the internal filename. +MPY_LD_FLAGS = "--source-name=$(MOD_BASE).mpy" + include $(MPY_DIR)/py/dynruntime.mk diff --git a/examples/natmod/random/Makefile b/examples/natmod/random/Makefile index 27d8ec935fe..cf0e6c04bb2 100644 --- a/examples/natmod/random/Makefile +++ b/examples/natmod/random/Makefile @@ -2,7 +2,8 @@ MPY_DIR = ../../.. # Name of module (different to built-in random so it can coexist) -MOD = random_$(ARCH) +MOD_BASE = random +MOD = $(MOD_BASE)_$(ARCH) # Source files (.c or .py) SRC = random.c @@ -19,4 +20,7 @@ ifeq ($(ARCH),$(filter $(ARCH),armv6m armv7m)) LINK_RUNTIME = 1 endif +# Strip the architecture name from the internal filename. +MPY_LD_FLAGS = "--source-name=$(MOD_BASE).mpy" + include $(MPY_DIR)/py/dynruntime.mk diff --git a/examples/natmod/re/Makefile b/examples/natmod/re/Makefile index c5f05e64ab4..a82847d98f8 100644 --- a/examples/natmod/re/Makefile +++ b/examples/natmod/re/Makefile @@ -2,7 +2,8 @@ MPY_DIR = ../../.. # Name of module (different to built-in re so it can coexist) -MOD = re_$(ARCH) +MOD_BASE = re +MOD = $(MOD_BASE)_$(ARCH) # Source files (.c or .py) SRC = re.c @@ -15,4 +16,7 @@ ifeq ($(ARCH),armv6m) LINK_RUNTIME = 1 endif +# Strip the architecture name from the internal filename. +MPY_LD_FLAGS = "--source-name=$(MOD_BASE).mpy" + include $(MPY_DIR)/py/dynruntime.mk diff --git a/tools/mpy_ld.py b/tools/mpy_ld.py index f86c27930e2..05c915fbc41 100755 --- a/tools/mpy_ld.py +++ b/tools/mpy_ld.py @@ -1386,7 +1386,7 @@ def write_reloc(self, base, offset, dest, n): self.write_uint(n) -def build_mpy(env, fmpy, native_qstr_vals, arch_flags): +def build_mpy(env, fmpy, internal_name, native_qstr_vals, arch_flags): # Rewrite the entry trampoline if the proper value isn't known earlier, and # ensure the trampoline size remains the same. if env.arch.delayed_entry_offset: @@ -1424,7 +1424,7 @@ def build_mpy(env, fmpy, native_qstr_vals, arch_flags): out.write_uint(0) # MPY: qstr table - out.write_qstr(fmpy) # filename + out.write_qstr(internal_name) # filename for q in native_qstr_vals: out.write_qstr(q) @@ -1567,7 +1567,14 @@ def do_link(args): load_object_file(env, f, obj_name) link_objects(env, len(native_qstr_vals)) - build_mpy(env, args.output, native_qstr_vals, args.arch_flags) + if args.source_name: + internal_name = args.source_name + else: + import pathlib + + path = pathlib.Path(args.output) + internal_name = path.name + build_mpy(env, args.output, internal_name, native_qstr_vals, args.arch_flags) except LinkError as er: print("LinkError:", er.args[0]) sys.exit(1) @@ -1655,6 +1662,9 @@ def main(): ) cmd_parser.add_argument("--arch", default="x64", help="architecture") cmd_parser.add_argument("--arch-flags", default=None, help="optional architecture flags") + cmd_parser.add_argument( + "--source-name", default=None, help="override the file name written to the .mpy file" + ) cmd_parser.add_argument("--preprocess", action="store_true", help="preprocess source files") cmd_parser.add_argument("--qstrs", default=None, help="file defining additional qstrs") cmd_parser.add_argument( From c0a8bc316371d48faf25f9693ef9cdd38fabbad1 Mon Sep 17 00:00:00 2001 From: Phil Howard Date: Wed, 13 Aug 2025 16:33:14 +0100 Subject: [PATCH 298/635] all: Remove MICROPY_PY_LWIP_PPP. MICROPY_PY_LWIP_PPP is used in only one place and is generally set to the value of MICROPY_PY_NETWORK_PPP_LWIP. Remove the former. extmod/lwip-include/lwipopts_common.h: Replace MICROPY_PY_LWIP_PPP with MICROPY_PY_NETWORK_PPP_LWIP. ports/mimxrt/mpconfigport.h: Remove redundant MICROPY_PY_LWIP_PPP. ports/rp2/mpconfigport.h: Remove redundant MICROPY_PY_LWIP_PPP, default MICROPY_PY_NETWORK_PPP_LWIP to MICROPY_PY_LWIP. ports/stm32/mpconfigport.h: Remove redundant MICROPY_PY_LWIP_PPP. Signed-off-by: Phil Howard --- extmod/lwip-include/lwipopts_common.h | 2 +- ports/mimxrt/mpconfigport.h | 1 - ports/rp2/mpconfigport.h | 1 - ports/stm32/mpconfigport.h | 1 - 4 files changed, 1 insertion(+), 4 deletions(-) diff --git a/extmod/lwip-include/lwipopts_common.h b/extmod/lwip-include/lwipopts_common.h index 8cb1acfe2ca..8717d7d3210 100644 --- a/extmod/lwip-include/lwipopts_common.h +++ b/extmod/lwip-include/lwipopts_common.h @@ -60,7 +60,7 @@ #define LWIP_MDNS_RESPONDER 1 #define LWIP_IGMP 1 -#if MICROPY_PY_LWIP_PPP +#if MICROPY_PY_NETWORK_PPP_LWIP #define PPP_SUPPORT 1 #define PAP_SUPPORT 1 #define CHAP_SUPPORT 1 diff --git a/ports/mimxrt/mpconfigport.h b/ports/mimxrt/mpconfigport.h index bd9adf46640..d0489bc2513 100644 --- a/ports/mimxrt/mpconfigport.h +++ b/ports/mimxrt/mpconfigport.h @@ -165,7 +165,6 @@ uint32_t trng_random_u32(void); #ifndef MICROPY_PY_NETWORK_PPP_LWIP #define MICROPY_PY_NETWORK_PPP_LWIP (MICROPY_PY_LWIP) #endif -#define MICROPY_PY_LWIP_PPP (MICROPY_PY_NETWORK_PPP_LWIP) #ifndef MICROPY_PY_BLUETOOTH_ENABLE_CENTRAL_MODE #define MICROPY_PY_BLUETOOTH_ENABLE_CENTRAL_MODE (1) diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index 0bfaf6098ad..8cb4ab4226e 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -198,7 +198,6 @@ #define MICROPY_VFS_FAT (1) #define MICROPY_VFS_ROM (MICROPY_HW_ROMFS_BYTES > 0) #define MICROPY_SSL_MBEDTLS (1) -#define MICROPY_PY_LWIP_PPP (MICROPY_PY_NETWORK_PPP_LWIP) // Hardware timer alarm index. Available range 0-3. // Number 3 is currently used by pico-sdk alarm pool (PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM) diff --git a/ports/stm32/mpconfigport.h b/ports/stm32/mpconfigport.h index 4c257edb42b..71dd3e2cc4d 100644 --- a/ports/stm32/mpconfigport.h +++ b/ports/stm32/mpconfigport.h @@ -109,7 +109,6 @@ #define MICROPY_PY_TIME_GMTIME_LOCALTIME_MKTIME (1) #define MICROPY_PY_TIME_TIME_TIME_NS (1) #define MICROPY_PY_TIME_INCLUDEFILE "ports/stm32/modtime.c" -#define MICROPY_PY_LWIP_PPP (MICROPY_PY_NETWORK_PPP_LWIP) #ifndef MICROPY_PY_MACHINE #define MICROPY_PY_MACHINE (1) #define MICROPY_PY_MACHINE_INCLUDEFILE "ports/stm32/modmachine.c" From 533a154c8aa9eee5bfb975f99eb82fd29de7d9d6 Mon Sep 17 00:00:00 2001 From: Phil Howard Date: Wed, 18 Dec 2024 14:08:05 +0000 Subject: [PATCH 299/635] rp2: Enable PPP for Pico W. mpconfigport.h: Default MICROPY_PY_NETWORK_PPP_LWIP to 1. Signed-off-by: Phil Howard --- ports/rp2/mpconfigport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index 8cb4ab4226e..ae40d1e8090 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -240,7 +240,7 @@ #endif #ifndef MICROPY_PY_NETWORK_PPP_LWIP -#define MICROPY_PY_NETWORK_PPP_LWIP (0) +#define MICROPY_PY_NETWORK_PPP_LWIP (MICROPY_PY_LWIP) #endif #endif From abaf6d05c4d2ff48869ba71d84476dc632698d9d Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 22 Jun 2026 13:47:10 +1000 Subject: [PATCH 300/635] tools/codeformat.py: Include more C source files in code formatting. This updates the PATHS to include: - everything under `extmod/` - everything under `py/` (in case one day there are subdirs there...) - everything under `shared/` This makes sure that any C source files added anywhere under these directories will be formatted. Signed-off-by: Damien George --- tools/codeformat.py | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/tools/codeformat.py b/tools/codeformat.py index 3bec6c28044..8d88963dafb 100755 --- a/tools/codeformat.py +++ b/tools/codeformat.py @@ -36,18 +36,12 @@ PATHS = [ "drivers/**/*.[ch]", "examples/**/*.[ch]", - "extmod/*.[ch]", - "extmod/btstack/*.[ch]", - "extmod/nimble/**/*.[ch]", + "extmod/**/*.[ch]", "lib/mbedtls_errors/tester.c", - "shared/libc/*.[ch]", - "shared/netutils/*.[ch]", - "shared/timeutils/*.[ch]", - "shared/runtime/*.[ch]", - "shared/tinyusb/*.[ch]", "mpy-cross/*.[ch]", "ports/**/*.[ch]", - "py/*.[ch]", + "py/**/*.[ch]", + "shared/**/*.[ch]", ] EXCLUSIONS = [ From 34417ddb1c03808da2df577c49126e947c2832b9 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 22 Jun 2026 13:49:00 +1000 Subject: [PATCH 301/635] all: Apply code formatting to new paths. These need to be formatted due to the parent commit. Signed-off-by: Damien George --- extmod/berkeley-db/berkeley_db_config_port.h | 2 +- extmod/littlefs-include/lfs2_defines.h | 2 +- shared/memzip/lexermemzip.c | 4 +- shared/memzip/memzip.c | 3 +- shared/memzip/memzip.h | 78 ++++++++++---------- 5 files changed, 43 insertions(+), 46 deletions(-) diff --git a/extmod/berkeley-db/berkeley_db_config_port.h b/extmod/berkeley-db/berkeley_db_config_port.h index 41e4acd81e8..749beb537e9 100644 --- a/extmod/berkeley-db/berkeley_db_config_port.h +++ b/extmod/berkeley-db/berkeley_db_config_port.h @@ -3,7 +3,7 @@ #define __DBINTERFACE_PRIVATE 1 #define mpool_error printf #define abort abort_ -#define virt_fd_t void* +#define virt_fd_t void * #ifdef MICROPY_BERKELEY_DB_DEFPSIZE #define DEFPSIZE MICROPY_BERKELEY_DB_DEFPSIZE diff --git a/extmod/littlefs-include/lfs2_defines.h b/extmod/littlefs-include/lfs2_defines.h index 4ae566f508a..072fd46c32c 100644 --- a/extmod/littlefs-include/lfs2_defines.h +++ b/extmod/littlefs-include/lfs2_defines.h @@ -9,4 +9,4 @@ #define LFS2_CRC(crc, buffer, size) uzlib_crc32(buffer, size, crc) #endif -#endif \ No newline at end of file +#endif diff --git a/shared/memzip/lexermemzip.c b/shared/memzip/lexermemzip.c index 1915a04c01e..a31fc7f1cdc 100644 --- a/shared/memzip/lexermemzip.c +++ b/shared/memzip/lexermemzip.c @@ -5,8 +5,7 @@ #include "py/mperrno.h" #include "memzip.h" -mp_lexer_t *mp_lexer_new_from_file(qstr filename) -{ +mp_lexer_t *mp_lexer_new_from_file(qstr filename) { void *data; size_t len; @@ -16,4 +15,3 @@ mp_lexer_t *mp_lexer_new_from_file(qstr filename) return mp_lexer_new_from_str_len(filename, (const char *)data, (mp_uint_t)len, 0); } - diff --git a/shared/memzip/memzip.c b/shared/memzip/memzip.c index 3fbea8e1e91..32fd27ffeb4 100644 --- a/shared/memzip/memzip.c +++ b/shared/memzip/memzip.c @@ -65,8 +65,7 @@ bool memzip_is_dir(const char *filename) { } -MEMZIP_RESULT memzip_locate(const char *filename, void **data, size_t *len) -{ +MEMZIP_RESULT memzip_locate(const char *filename, void **data, size_t *len) { const MEMZIP_FILE_HDR *file_hdr = memzip_find_file_header(filename); if (file_hdr == NULL) { return MZ_NO_FILE; diff --git a/shared/memzip/memzip.h b/shared/memzip/memzip.h index 667e2df7e13..fe27d9584a3 100644 --- a/shared/memzip/memzip.h +++ b/shared/memzip/memzip.h @@ -3,17 +3,17 @@ #define MEMZIP_FILE_HEADER_SIGNATURE 0x04034b50 typedef struct { - uint32_t signature; - uint16_t version; - uint16_t flags; - uint16_t compression_method; - uint16_t last_mod_time; - uint16_t last_mod_date; - uint32_t crc32; - uint32_t compressed_size; - uint32_t uncompressed_size; - uint16_t filename_len; - uint16_t extra_len; + uint32_t signature; + uint16_t version; + uint16_t flags; + uint16_t compression_method; + uint16_t last_mod_time; + uint16_t last_mod_date; + uint32_t crc32; + uint32_t compressed_size; + uint32_t uncompressed_size; + uint16_t filename_len; + uint16_t extra_len; /* char filename[filename_len] */ /* uint8_t extra[extra_len] */ @@ -23,22 +23,22 @@ typedef struct #define MEMZIP_CENTRAL_DIRECTORY_SIGNATURE 0x02014b50 typedef struct { - uint32_t signature; - uint16_t version_made_by; - uint16_t version_read_with; - uint16_t flags; - uint16_t compression_method; - uint16_t last_mod_time; - uint16_t last_mod_date; - uint32_t crc32; - uint32_t compressed_size; - uint32_t uncompressed_size; - uint16_t filename_len; - uint16_t extra_len; - uint16_t disk_num; - uint16_t internal_file_attributes; - uint32_t external_file_attributes; - uint32_t file_header_offset; + uint32_t signature; + uint16_t version_made_by; + uint16_t version_read_with; + uint16_t flags; + uint16_t compression_method; + uint16_t last_mod_time; + uint16_t last_mod_date; + uint32_t crc32; + uint32_t compressed_size; + uint32_t uncompressed_size; + uint16_t filename_len; + uint16_t extra_len; + uint16_t disk_num; + uint16_t internal_file_attributes; + uint32_t external_file_attributes; + uint32_t file_header_offset; /* char filename[filename_len] */ /* uint8_t extra[extra_len] */ @@ -48,14 +48,14 @@ typedef struct #define MEMZIP_END_OF_CENTRAL_DIRECTORY_SIGNATURE 0x06054b50 typedef struct { - uint32_t signature; - uint16_t disk_num; - uint16_t central_directory_disk; - uint16_t num_central_directories_this_disk; - uint16_t total_central_directories; - uint32_t central_directory_size; - uint32_t central_directory_offset; - uint16_t comment_len; + uint32_t signature; + uint16_t disk_num; + uint16_t central_directory_disk; + uint16_t num_central_directories_this_disk; + uint16_t total_central_directories; + uint32_t central_directory_size; + uint32_t central_directory_offset; + uint16_t comment_len; /* char comment[comment_len] */ @@ -71,10 +71,10 @@ typedef enum { } MEMZIP_RESULT; typedef struct { - uint32_t file_size; - uint16_t last_mod_date; - uint16_t last_mod_time; - uint8_t is_dir; + uint32_t file_size; + uint16_t last_mod_date; + uint16_t last_mod_time; + uint8_t is_dir; } MEMZIP_FILE_INFO; From b67ac7354afff3e12cb73b37d13b8f0a7a631d6e Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 18 Jun 2026 14:53:51 +1000 Subject: [PATCH 302/635] Revert "rp2: Build with nano.specs for newlib-nano.". This reverts commit 6552836c2c6a9833992f9d9e7229b5235386fa20. Signed-off-by: Angus Gratton --- ports/rp2/CMakeLists.txt | 9 --------- ports/rp2/mbedtls/mbedtls_config_port.h | 1 - ports/rp2/mbedtls/mbedtls_port.c | 9 --------- 3 files changed, 19 deletions(-) diff --git a/ports/rp2/CMakeLists.txt b/ports/rp2/CMakeLists.txt index e1ac04a8b96..5b99b396f4a 100644 --- a/ports/rp2/CMakeLists.txt +++ b/ports/rp2/CMakeLists.txt @@ -532,13 +532,6 @@ target_compile_options(${MICROPY_TARGET} PRIVATE -Wall -Werror -g # always include debug information in the ELF - - # pico-sdk already passes --specs=nosys.specs to stub out syscall handlers, - # passing nano.specs as well means that newlib-nano libc functions will be used - # (note this is mostly a linker option, but should be passed to the compiler as - # well to add the newlib-nano header to the search path. Currently this happens - # inconsistently as pico-sdk files aren't built with this option.) - --specs=nano.specs ) target_link_options(${MICROPY_TARGET} PRIVATE @@ -546,8 +539,6 @@ target_link_options(${MICROPY_TARGET} PRIVATE -Wl,--wrap=runtime_init_clocks -Wl,--print-memory-usage -Wl,--cref - # see note about nano.specs, above - --specs=nano.specs ) if(DEFINED PICO_FLASH_SIZE_BYTES) diff --git a/ports/rp2/mbedtls/mbedtls_config_port.h b/ports/rp2/mbedtls/mbedtls_config_port.h index 0b0004dadde..b3f19f3a07d 100644 --- a/ports/rp2/mbedtls/mbedtls_config_port.h +++ b/ports/rp2/mbedtls/mbedtls_config_port.h @@ -34,7 +34,6 @@ time_t rp2_rtctime_seconds(time_t *timer); #define MBEDTLS_PLATFORM_TIME_MACRO rp2_rtctime_seconds #define MBEDTLS_PLATFORM_MS_TIME_ALT mbedtls_ms_time -#define MBEDTLS_PLATFORM_GMTIME_R_ALT 1 // Set MicroPython-specific options. #define MICROPY_MBEDTLS_CONFIG_BARE_METAL (1) diff --git a/ports/rp2/mbedtls/mbedtls_port.c b/ports/rp2/mbedtls/mbedtls_port.c index 1c5e228f0ef..391d51f4a1e 100644 --- a/ports/rp2/mbedtls/mbedtls_port.c +++ b/ports/rp2/mbedtls/mbedtls_port.c @@ -47,13 +47,4 @@ mbedtls_ms_time_t mbedtls_ms_time(void) { current_ms = rp2_rtctime_seconds(tv) * 1000; return current_ms; } - -struct tm *mbedtls_platform_gmtime_r(const mbedtls_time_t *tt, struct tm *tm_buf) { - // Default mbedTLS platform implementation calls gmtime() here. This is - // unnecessary as this function signature already matches gmtime_r(), and - // additionally on newlib-nano gmtime() tries to malloc the reent buffer on - // demand - which will fail. - return gmtime_r(tt, tm_buf); -} - #endif From e1c1a9bd05b9aa9176fa843b02275eea1623bbc7 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 26 Feb 2025 17:34:50 +1100 Subject: [PATCH 303/635] windows: Double the stack size allowance on windows port. This seems like it's only really a problem on Debug builds, but I think can't hurt to increase it on all windows builds. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/unix/stack_size.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/ports/unix/stack_size.h b/ports/unix/stack_size.h index f6159bb69d5..95ec502b0f8 100644 --- a/ports/unix/stack_size.h +++ b/ports/unix/stack_size.h @@ -46,8 +46,15 @@ #define UNIX_STACK_MUL_SANITIZERS 1 #endif -// Double the stack size for 64-bit builds, plus additional scaling -#define UNIX_STACK_MULTIPLIER ((sizeof(void *) / 4) * UNIX_STACK_MUL_ARM * UNIX_STACK_MUL_SANITIZERS) +#if defined(_MSC_VER) +// Similarly Windows seems to require more stack +#define UNIX_STACK_MUL_WINDOWS 2 +#else +#define UNIX_STACK_MUL_WINDOWS 1 +#endif + +// Double the stack size for 64-bit builds, plus additional scalings +#define UNIX_STACK_MULTIPLIER ((sizeof(void *) / 4) * (UNIX_STACK_MUL_ARM)*(UNIX_STACK_MUL_SANITIZERS)*(UNIX_STACK_MUL_WINDOWS)) #endif // UNIX_STACK_MULTIPLIER From 8551369138eba8cf068cb17f1b55cb4b9f43491d Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 23 Jul 2025 11:16:57 +1000 Subject: [PATCH 304/635] stm32/adc: Set values in array from smallint. This removes the last usage of mp_binary_set_val_array_from_int(). It will be a little slower, but shouldn't be measurably so compared to the ADC sampling. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/stm32/adc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/ports/stm32/adc.c b/ports/stm32/adc.c index ec55175af73..993327ced1c 100644 --- a/ports/stm32/adc.c +++ b/ports/stm32/adc.c @@ -738,11 +738,12 @@ static mp_obj_t adc_read_timed(mp_obj_t self_in, mp_obj_t buf_in, mp_obj_t freq_ // read value uint value = self->handle.Instance->DR; - // store value in buffer + // value is max 12 bits wide. If the array is 8-bit then shift down to fit + // (otherwise it will fit in any array typecode) if (typesize == 1) { value >>= 4; } - mp_binary_set_val_array_from_int(bufinfo.typecode, bufinfo.buf, index, value); + mp_binary_set_val_array(bufinfo.typecode, bufinfo.buf, index, MP_OBJ_NEW_SMALL_INT(value)); } // turn the ADC off @@ -846,11 +847,12 @@ static mp_obj_t adc_read_timed_multi(mp_obj_t adc_array_in, mp_obj_t buf_array_i // read value value = adc->handle.Instance->DR; - // store values in buffer + // value is max 12 bits wide. If the array is 8-bit then shift down to fit + // (otherwise it will fit in any array typecode) if (typesize == 1) { value >>= 4; } - mp_binary_set_val_array_from_int(bufinfo.typecode, bufptrs[array_index], elem_index, value); + mp_binary_set_val_array(bufinfo.typecode, bufptrs[array_index], elem_index, MP_OBJ_NEW_SMALL_INT(value)); } } From c4fa8cb3091e0a7699a5ec196227324c47402701 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 23 Jul 2025 15:17:08 +1000 Subject: [PATCH 305/635] tools/ci: Don't include unittest tests in the merged .mpy. If >1 unittest-enabled module is included, the results of the merged module won't match (as it runs some previously registered tests again). Signed-off-by: Angus Gratton --- tools/ci.sh | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/ci.sh b/tools/ci.sh index 4fe4bae6622..a24349f6f47 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -755,6 +755,12 @@ function ci_unix_coverage_run_mpy_merge_tests { # Compile a selection of tests to .mpy and execute them, collecting the output. # None of the tests should SKIP. for inpy in $mptop/tests/basics/[acdel]*.py; do + if grep -q "import unittest" $inpy; then + # Merging >1 unittest-enabled module leads to unexpected + # results, as each file runs all previously registered unittest cases + echo "SKIPPING $inpy" + continue + fi test=$(basename $inpy .py) echo $test outmpy=$outdir/$test.mpy From e00daa3a507857d25295ebf322e9c20cf5c5df16 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 24 Jun 2026 15:30:11 +1000 Subject: [PATCH 306/635] py/binary,objint: Add overflow checks and int.to_bytes(signed=True). This PR was originally a cherry-pick of CircuitPython commits 095c8440, d103ac1d, c592bd61 and 8664a65. However, substantial additional changes so the implementation has diverged a lot from CircuitPython's: - Keep CPython >= 3.11 defaults for int.to_bytes(), consistent with 80c5e76 and 0b432b3. - Refactors to reduce the code size impact of this change. Various code paths are now funneled into new function mp_obj_int_to_bytes() and existing function mp_binary_set_int(), except where a simple assignment is used for performance reasons (i.e. array, moductypes). - Keep the MicroPython behaviour of not overflow checking assignments to arrays, bytearrays, etc. - but enable overflow checks as part of MicroPython V2.0. - Update tests to work with the new behaviour (similar to CPython) and add coverage for new code and some corner cases. Some tests are converted to unittest so we can easily verify both current and V2.0 overflow. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- docs/library/builtins.rst | 6 +- extmod/moductypes.c | 4 +- ports/unix/coverage.c | 13 --- ports/unix/modffi.c | 2 +- py/binary.c | 112 ++++++++++++++------- py/binary.h | 3 +- py/mpz.c | 24 +++-- py/obj.c | 2 +- py/objint.c | 70 +++++-------- py/objint.h | 6 +- py/objint_impl.h | 98 ++++++++++++++++++ py/objint_longlong.c | 122 ++++++++++++++++------- py/objint_mpz.c | 26 +++-- tests/basics/array_int_repr.py | 85 ++++++++++++++++ tests/basics/array_limits_intbig.py | 119 ++++++++++++++++++++++ tests/basics/int_bytes.py | 45 +++++---- tests/basics/int_bytes_int64.py | 19 +--- tests/basics/int_bytes_intbig.py | 75 +++++++++----- tests/cpydiff/types_int_to_bytes.py | 16 --- tests/extmod/uctypes_array_load_store.py | 78 ++++++++++++++- tests/ports/unix/extra_coverage.py.exp | 3 - 21 files changed, 689 insertions(+), 239 deletions(-) create mode 100644 py/objint_impl.h create mode 100644 tests/basics/array_int_repr.py create mode 100644 tests/basics/array_limits_intbig.py delete mode 100644 tests/cpydiff/types_int_to_bytes.py diff --git a/docs/library/builtins.rst b/docs/library/builtins.rst index b5d08ba7fed..8fb8f03080c 100644 --- a/docs/library/builtins.rst +++ b/docs/library/builtins.rst @@ -79,15 +79,11 @@ Functions and types In MicroPython, `byteorder` parameter must be positional (this is compatible with CPython). - .. method:: to_bytes(size, byteorder) + .. method:: to_bytes(size, byteorder, /, *, signed=False) In MicroPython, `byteorder` parameter must be positional (this is compatible with CPython). - .. note:: The optional ``signed`` kwarg from CPython is not supported. - MicroPython currently converts negative integers as signed, - and positive as unsigned. (:ref:`Details `.) - .. function:: isinstance() .. function:: issubclass() diff --git a/extmod/moductypes.c b/extmod/moductypes.c index 7cac41dbcfc..38a94aaea1b 100644 --- a/extmod/moductypes.c +++ b/extmod/moductypes.c @@ -463,8 +463,8 @@ static mp_obj_t uctypes_struct_attr_op(mp_obj_t self_in, qstr attr, mp_obj_t set if (self->flags == LAYOUT_NATIVE) { set_aligned_basic(val_type & 6, self->addr + offset, val); } else { - mp_binary_set_int(GET_SCALAR_SIZE(val_type & 7), self->flags == LAYOUT_BIG_ENDIAN, - self->addr + offset, val); + size_t item_size = GET_SCALAR_SIZE(val_type & 7); + mp_binary_set_int(item_size, self->addr + offset, item_size, val, self->flags == LAYOUT_BIG_ENDIAN); } return set_val; // just !MP_OBJ_NULL } diff --git a/ports/unix/coverage.c b/ports/unix/coverage.c index e85539f39a6..44db193012e 100644 --- a/ports/unix/coverage.c +++ b/ports/unix/coverage.c @@ -740,19 +740,6 @@ static mp_obj_t extra_coverage(void) { mp_emitter_warning(MP_PASS_CODE_SIZE, "test"); } - // binary - { - mp_printf(&mp_plat_print, "# binary\n"); - - // call function with float and double typecodes - float far[1]; - double dar[1]; - mp_binary_set_val_array_from_int('f', far, 0, 123); - mp_printf(&mp_plat_print, "%.0f\n", (double)far[0]); - mp_binary_set_val_array_from_int('d', dar, 0, 456); - mp_printf(&mp_plat_print, "%.0lf\n", dar[0]); - } - // VM { mp_printf(&mp_plat_print, "# VM\n"); diff --git a/ports/unix/modffi.c b/ports/unix/modffi.c index b469e932e0d..c16d40ad3b4 100644 --- a/ports/unix/modffi.c +++ b/ports/unix/modffi.c @@ -446,7 +446,7 @@ static unsigned long long ffi_get_int_value(mp_obj_t o) { return MP_OBJ_SMALL_INT_VALUE(o); } else { unsigned long long res; - mp_obj_int_to_bytes_impl(o, MP_ENDIANNESS_BIG, sizeof(res), (byte *)&res); + mp_obj_int_to_bytes(o, sizeof(res), (byte *)&res, MP_ENDIANNESS_BIG, false, false); return res; } } diff --git a/py/binary.c b/py/binary.c index ef2857b4318..bd39efa76b4 100644 --- a/py/binary.c +++ b/py/binary.c @@ -42,6 +42,10 @@ #define alignof(type) offsetof(struct { char c; type t; }, t) #endif +// MicroPython V1.x truncates integers when writing into arrays, +// MicroPython V2 will raise OverflowError in these cases, same as CPython +#define OVERFLOW_CHECKS MICROPY_PREVIEW_VERSION_2 + size_t mp_binary_get_size(char struct_type, char val_type, size_t *palign) { size_t size = 0; int align = 1; @@ -376,7 +380,21 @@ mp_obj_t mp_binary_get_val(char struct_type, char val_type, byte *p_base, byte * } } -void mp_binary_set_int(size_t val_sz, bool big_endian, byte *dest, mp_uint_t val) { +void mp_binary_set_int(size_t dest_sz, byte *dest, size_t val_sz, mp_uint_t val, bool big_endian) { + if (dest_sz > val_sz) { + // zero/sign extension if needed + int c = ((mp_int_t)val < 0) ? 0xff : 0x00; + memset(dest, c, dest_sz); + + // big endian: write val_sz bytes at end of 'dest' + if (big_endian) { + dest += dest_sz - val_sz; + } + } else if (dest_sz < val_sz) { + // truncate 'val' into 'dest' + val_sz = dest_sz; + } + if (MP_ENDIANNESS_LITTLE && !big_endian) { memcpy(dest, &val, val_sz); } else if (MP_ENDIANNESS_BIG && big_endian) { @@ -442,36 +460,33 @@ void mp_binary_set_val(char struct_type, char val_type, mp_obj_t val_in, byte *p val = fp_dp.i64; } else { int be = struct_type == '>'; - mp_binary_set_int(sizeof(uint32_t), be, p, fp_dp.i32[MP_ENDIANNESS_BIG ^ be]); + mp_binary_set_int(sizeof(uint32_t), p, sizeof(uint32_t), fp_dp.i32[MP_ENDIANNESS_BIG ^ be], be); + // Now fall through and copy the second word, below p += sizeof(uint32_t); + size = sizeof(uint32_t); val = fp_dp.i32[MP_ENDIANNESS_LITTLE ^ be]; } break; } #endif default: + // Typecode is a standard integer #if MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_NONE if (mp_obj_is_exact_type(val_in, &mp_type_int)) { - mp_obj_int_to_bytes_impl(val_in, struct_type == '>', size, p); + // Note: overflow checks are disabled in this code path but enabled for V2 in mp_binary_set_val_array() + mp_obj_int_to_bytes(val_in, size, p, struct_type == '>', is_signed(val_type), false); return; } #endif - val = mp_obj_get_int(val_in); - // zero/sign extend if needed - if (MP_BYTES_PER_OBJ_WORD < 8 && size > sizeof(val)) { - int c = (mp_int_t)val < 0 ? 0xff : 0x00; - memset(p, c, size); - if (struct_type == '>') { - p += size - sizeof(val); - } - } - break; + break; // Fall through to mp_binary_set_int } - mp_binary_set_int(MIN((size_t)size, sizeof(val)), struct_type == '>', p, val); + mp_binary_set_int(size, p, sizeof(val), val, struct_type == '>'); } +static void mp_binary_set_val_array_from_int(char typecode, void *p, size_t index, mp_int_t val); + void mp_binary_set_val_array(char typecode, void *p, size_t index, mp_obj_t val_in) { switch (typecode) { #if MICROPY_PY_BUILTINS_FLOAT @@ -488,12 +503,25 @@ void mp_binary_set_val_array(char typecode, void *p, size_t index, mp_obj_t val_ ((mp_obj_t *)p)[index] = val_in; break; #endif + // In all remaining cases the type code is an integer default: #if MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_NONE if (mp_obj_is_exact_type(val_in, &mp_type_int)) { size_t size = mp_binary_get_size('@', typecode, NULL); - mp_obj_int_to_bytes_impl(val_in, MP_ENDIANNESS_BIG, - size, (uint8_t *)p + index * size); + p = (uint8_t *)p + index * size; + byte *dest; + #if OVERFLOW_CHECKS + // If mp_obj_int_to_bytes() might overflow then need to write into a temporary buffer first + assert(size <= sizeof(uint64_t)); + uint64_t temp_buf; + dest = (uint8_t *)&temp_buf; + #else + dest = p; + #endif + mp_obj_int_to_bytes(val_in, size, dest, MP_ENDIANNESS_BIG, is_signed(typecode), OVERFLOW_CHECKS); + #if OVERFLOW_CHECKS + memcpy(p, dest, size); + #endif return; } #endif @@ -501,47 +529,54 @@ void mp_binary_set_val_array(char typecode, void *p, size_t index, mp_obj_t val_ } } -void mp_binary_set_val_array_from_int(char typecode, void *p, size_t index, mp_int_t val) { +#if OVERFLOW_CHECKS +#define SET_VAL_AS(TYPE, IS_SIGNED) do { \ + TYPE tmp = val; \ + if ((mp_int_t)tmp == val && (IS_SIGNED || val >= 0)) { \ + ((TYPE *)p)[index] = tmp; \ + } else { \ + goto raise; \ + } \ +} while (0) +#else +#define SET_VAL_AS(TYPE, _IS_SIGNED) do { \ + ((TYPE *)p)[index] = val; \ +} while (0) +#endif + +static void mp_binary_set_val_array_from_int(char typecode, void *p, size_t index, mp_int_t val) { switch (typecode) { case 'b': - ((signed char *)p)[index] = val; + SET_VAL_AS(signed char, true); break; case BYTEARRAY_TYPECODE: case 'B': - ((unsigned char *)p)[index] = val; + SET_VAL_AS(unsigned char, false); break; case 'h': - ((short *)p)[index] = val; + SET_VAL_AS(short, true); break; case 'H': - ((unsigned short *)p)[index] = val; + SET_VAL_AS(unsigned short, false); break; case 'i': - ((int *)p)[index] = val; + SET_VAL_AS(int, true); break; case 'I': - ((unsigned int *)p)[index] = val; + SET_VAL_AS(unsigned int, false); break; case 'l': - ((long *)p)[index] = val; + SET_VAL_AS(long, true); break; case 'L': - ((unsigned long *)p)[index] = val; + SET_VAL_AS(unsigned long, false); break; #if MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_NONE case 'q': - ((long long *)p)[index] = val; + SET_VAL_AS(long long, true); break; case 'Q': - ((unsigned long long *)p)[index] = val; - break; - #endif - #if MICROPY_PY_BUILTINS_FLOAT - case 'f': - ((float *)p)[index] = (float)val; - break; - case 'd': - ((double *)p)[index] = (double)val; + SET_VAL_AS(unsigned long long, false); break; #endif // Extension to CPython: array of pointers @@ -551,4 +586,11 @@ void mp_binary_set_val_array_from_int(char typecode, void *p, size_t index, mp_i break; #endif } + + return; + + #if OVERFLOW_CHECKS +raise: + mp_raise_msg(&mp_type_OverflowError, MP_ERROR_TEXT("integer out of range")); + #endif } diff --git a/py/binary.h b/py/binary.h index 5c645bcaaa9..851dc50110e 100644 --- a/py/binary.h +++ b/py/binary.h @@ -37,10 +37,9 @@ size_t mp_binary_get_size(char struct_type, char val_type, size_t *palign); mp_obj_t mp_binary_get_val_array(char typecode, void *p, size_t index); void mp_binary_set_val_array(char typecode, void *p, size_t index, mp_obj_t val_in); -void mp_binary_set_val_array_from_int(char typecode, void *p, size_t index, mp_int_t val); mp_obj_t mp_binary_get_val(char struct_type, char val_type, byte *p_base, byte **ptr); void mp_binary_set_val(char struct_type, char val_type, mp_obj_t val_in, byte *p_base, byte **ptr); long long mp_binary_get_int(size_t size, bool is_signed, bool big_endian, const byte *src); -void mp_binary_set_int(size_t val_sz, bool big_endian, byte *dest, mp_uint_t val); +void mp_binary_set_int(size_t dest_sz, byte *dest, size_t val_sz, mp_uint_t val, bool big_endian); #endif // MICROPY_INCLUDED_PY_BINARY_H diff --git a/py/mpz.c b/py/mpz.c index 5a4d7d27d94..d8fca0adf95 100644 --- a/py/mpz.c +++ b/py/mpz.c @@ -1598,16 +1598,17 @@ bool mpz_as_bytes(const mpz_t *z, bool big_endian, bool as_signed, size_t len, b b += len; } mpz_dig_t *zdig = z->dig; + byte fill_byte = z->neg ? 0xFF : 0x00; int bits = 0; mpz_dbl_dig_t d = 0; mpz_dbl_dig_t carry = 1; + mpz_dig_t val = 0; size_t olen = len; // bytes in output buffer - bool ok = true; for (size_t zlen = z->len; zlen > 0; --zlen) { bits += DIG_SIZE; d = (d << DIG_SIZE) | *zdig++; for (; bits >= 8; bits -= 8, d >>= 8) { - mpz_dig_t val = d; + val = d; if (z->neg) { val = (~val & 0xff) + carry; carry = val >> 8; @@ -1615,7 +1616,9 @@ bool mpz_as_bytes(const mpz_t *z, bool big_endian, bool as_signed, size_t len, b if (!olen) { // Buffer is full, only OK if all remaining bytes are zeroes - ok = ok && ((byte)val == 0); + if ((byte)val != fill_byte) { + return false; + } continue; } @@ -1628,16 +1631,17 @@ bool mpz_as_bytes(const mpz_t *z, bool big_endian, bool as_signed, size_t len, b } } - if (as_signed && olen == 0 && len > 0) { - // If output exhausted then ensure there was enough space for the sign bit - byte most_sig = big_endian ? buf[0] : buf[len - 1]; - ok = ok && (bool)(most_sig & 0x80) == (bool)z->neg; - } else { + // Check if the most significant bit is set incorrectly for a signed value + if (olen == 0 && as_signed && ((val & 0x80) != (fill_byte & 0x80))) { + return false; + } + + if (olen > 0) { // fill remainder of buf with zero/sign extension of the integer - memset(big_endian ? buf : b, z->neg ? 0xff : 0x00, olen); + memset(big_endian ? buf : b, fill_byte, olen); } - return ok; + return true; } #if MICROPY_PY_BUILTINS_FLOAT diff --git a/py/obj.c b/py/obj.c index 26a912fc682..252e7372fcf 100644 --- a/py/obj.c +++ b/py/obj.c @@ -338,7 +338,7 @@ long long mp_obj_get_ll(mp_const_obj_t arg) { return MP_OBJ_SMALL_INT_VALUE(arg); } else { long long res; - mp_obj_int_to_bytes_impl((mp_obj_t)arg, MP_ENDIANNESS_BIG, sizeof(res), (byte *)&res); + mp_obj_int_to_bytes((mp_obj_t)arg, sizeof(res), (byte *)&res, MP_ENDIANNESS_BIG, false, false); return res; } } diff --git a/py/objint.c b/py/objint.c index cd966352999..ea5a0477aff 100644 --- a/py/objint.c +++ b/py/objint.c @@ -30,7 +30,7 @@ #include "py/parsenum.h" #include "py/smallint.h" -#include "py/objint.h" +#include "py/objint_impl.h" #include "py/objstr.h" #include "py/runtime.h" #include "py/binary.h" @@ -99,8 +99,8 @@ static mp_fp_as_int_class_t mp_classify_fp_as_int(mp_float_t val) { #elif MICROPY_FLOAT_IMPL == MICROPY_FLOAT_IMPL_DOUBLE e = u.i[MP_ENDIANNESS_LITTLE]; #endif -#define MP_FLOAT_SIGN_SHIFT_I32 ((MP_FLOAT_FRAC_BITS + MP_FLOAT_EXP_BITS) % 32) -#define MP_FLOAT_EXP_SHIFT_I32 (MP_FLOAT_FRAC_BITS % 32) + #define MP_FLOAT_SIGN_SHIFT_I32 ((MP_FLOAT_FRAC_BITS + MP_FLOAT_EXP_BITS) % 32) + #define MP_FLOAT_EXP_SHIFT_I32 (MP_FLOAT_FRAC_BITS % 32) if (e & (1U << MP_FLOAT_SIGN_SHIFT_I32)) { #if MICROPY_FLOAT_IMPL == MICROPY_FLOAT_IMPL_DOUBLE @@ -205,10 +205,10 @@ static const uint8_t log_base2_floor[] = { 3, 3, 3, 3, 3, 3, 3, 4, /* if needed, these are the values for higher bases - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 5 + 4, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4, 5 */ }; @@ -374,6 +374,10 @@ mp_int_t mp_obj_int_get_checked(mp_const_obj_t self_in) { return MP_OBJ_SMALL_INT_VALUE(self_in); } +void mp_obj_int_to_bytes(mp_obj_t self_in, size_t buf_len, byte *buf, bool big_endian, bool is_signed, bool overflow_check) { + mp_obj_small_int_to_bytes(MP_OBJ_SMALL_INT_VALUE(self_in), buf_len, buf, big_endian, is_signed, overflow_check); +} + #endif // MICROPY_LONGINT_IMPL == MICROPY_LONGINT_IMPL_NONE // This dispatcher function is expected to be independent of the implementation of long int @@ -427,55 +431,35 @@ static mp_obj_t int_from_bytes(size_t n_args, const mp_obj_t *args) { static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(int_from_bytes_fun_obj, 2, 4, int_from_bytes); static MP_DEFINE_CONST_CLASSMETHOD_OBJ(int_from_bytes_obj, MP_ROM_PTR(&int_from_bytes_fun_obj)); -static mp_obj_t int_to_bytes(size_t n_args, const mp_obj_t *args) { - // TODO: Support signed (currently behaves as if signed=(val < 0)) - bool overflow; +static mp_obj_t int_to_bytes(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + enum { ARG_length, ARG_byteorder, ARG_signed }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_length, MP_ARG_INT, { .u_int = 1 } }, + { MP_QSTR_byteorder, MP_ARG_OBJ, { .u_rom_obj = MP_ROM_QSTR(MP_QSTR_big) } }, + { MP_QSTR_signed, MP_ARG_KW_ONLY | MP_ARG_BOOL, {.u_bool = false} }, + }; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + mp_obj_t self = pos_args[0]; - mp_int_t dlen = n_args < 2 ? 1 : mp_obj_get_int(args[1]); + mp_int_t dlen = args[ARG_length].u_int; if (dlen < 0) { mp_raise_ValueError(NULL); } - bool big_endian = n_args < 3 || args[2] != MP_OBJ_NEW_QSTR(MP_QSTR_little); vstr_t vstr; vstr_init_len(&vstr, dlen); byte *data = (byte *)vstr.buf; - #if MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_NONE - if (!mp_obj_is_small_int(args[0])) { - overflow = !mp_obj_int_to_bytes_impl(args[0], big_endian, dlen, data); - } else - #endif - { - mp_int_t val = MP_OBJ_SMALL_INT_VALUE(args[0]); - int slen = 0; // Number of bytes to represent val - - // This logic has a twin in objint_longlong.c - if (val > 0) { - slen = (sizeof(mp_int_t) * 8 - mp_clz_mpi(val) + 7) / 8; - } else if (val < -1) { - slen = (sizeof(mp_int_t) * 8 - mp_clz_mpi(~val) + 8) / 8; - } else { - // clz of 0 is defined, so 0 and -1 map to 0 and 1 - slen = -val; - } - - if (slen <= dlen) { - memset(data, val < 0 ? 0xFF : 0x00, dlen); - mp_binary_set_int(slen, big_endian, data + (big_endian ? (dlen - slen) : 0), val); - overflow = false; - } else { - overflow = true; - } - } + bool big_endian = args[ARG_byteorder].u_obj != MP_OBJ_NEW_QSTR(MP_QSTR_little); + bool signed_ = args[ARG_signed].u_bool; - if (overflow) { - mp_raise_msg(&mp_type_OverflowError, MP_ERROR_TEXT("buffer too small")); - } + mp_obj_int_to_bytes(self, dlen, data, big_endian, signed_, true); return mp_obj_new_bytes_from_vstr(&vstr); } -static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(int_to_bytes_obj, 1, 4, int_to_bytes); +static MP_DEFINE_CONST_FUN_OBJ_KW(int_to_bytes_obj, 1, int_to_bytes); static const mp_rom_map_elem_t int_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_from_bytes), MP_ROM_PTR(&int_from_bytes_obj) }, diff --git a/py/objint.h b/py/objint.h index 28930e35adb..f6a551ea961 100644 --- a/py/objint.h +++ b/py/objint.h @@ -53,10 +53,12 @@ char *mp_obj_int_formatted(char **buf, size_t *buf_size, size_t *fmt_size, mp_co int base, const char *prefix, char base_char, char comma); char *mp_obj_int_formatted_impl(char **buf, size_t *buf_size, size_t *fmt_size, mp_const_obj_t self_in, int base, const char *prefix, char base_char, char comma); + mp_int_t mp_obj_int_hash(mp_obj_t self_in); mp_obj_t mp_obj_int_from_bytes_impl(bool big_endian, size_t len, const byte *buf); -// Returns true if 'self_in' fit into 'len' bytes of 'buf' without overflowing, 'buf' is truncated otherwise. -bool mp_obj_int_to_bytes_impl(mp_obj_t self_in, bool big_endian, size_t len, byte *buf); +// Write an integer to a byte sequence. +// If overflow_check is true, raises OverflowError if 'self_in' doesn't fit. If false, truncate to fit. +void mp_obj_int_to_bytes(mp_obj_t self_in, size_t buf_len, byte *buf, bool big_endian, bool is_signed, bool overflow_check); int mp_obj_int_sign(mp_obj_t self_in); mp_obj_t mp_obj_int_unary_op(mp_unary_op_t op, mp_obj_t o_in); mp_obj_t mp_obj_int_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in); diff --git a/py/objint_impl.h b/py/objint_impl.h new file mode 100644 index 00000000000..b1af4d6244d --- /dev/null +++ b/py/objint_impl.h @@ -0,0 +1,98 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Angus Gratton + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* This header provides some inline implementations of functions used by multiple objint*.c + files. + + Implementations here should only be called by one of the objint*.c files. If + called from more than one place in a single firmware, place into objint.c and + define in objint.h + */ +#ifndef MICROPY_INCLUDED_PY_OBJINT_IMPL_H +#define MICROPY_INCLUDED_PY_OBJINT_IMPL_H + +#include "py/binary.h" +#include "py/objint.h" +#include "py/runtime.h" + +static void mp_obj_int_raise_to_bytes_overflow_error(size_t nbytes) { + mp_raise_msg_varg(&mp_type_OverflowError, MP_ERROR_TEXT("value would overflow a %d byte buffer"), nbytes); +} + +static void mp_obj_int_raise_unsigned_negative_overflow_error(void) { + mp_raise_msg_varg(&mp_type_OverflowError, MP_ERROR_TEXT("can't convert negative int to unsigned")); +} + +static void mp_obj_small_int_buffer_overflow_check(mp_int_t val, size_t nbytes, bool is_signed) { + // Fast path for zero. + if (val == 0) { + return; + } + + if (!is_signed && val < 0) { + // Trying to store negative values in unsigned bytes + mp_obj_int_raise_unsigned_negative_overflow_error(); + } + + if (nbytes >= sizeof(val)) { + // All N bit small integers fit in an unsigned N bit integer. + // This case prevents shifting too far below. + return; + } + + if (nbytes == 0) { + // Can't fit a non-negative value in 0 bytes (prevents negative left shift, below) + goto raise; + } + + if (is_signed) { + mp_int_t edge = ((mp_int_t)1 << (nbytes * 8 - 1)); + if (-edge <= val && val < edge) { + return; + } + // Out of range, fall through to raise. + } else { + // Unsigned. We already know val >= 0. + mp_int_t edge = ((mp_int_t)1 << (nbytes * 8)); + if (val < edge) { + return; + } + // Fall through to raise. + } + +raise: + mp_obj_int_raise_to_bytes_overflow_error(nbytes); +} + +static inline void mp_obj_small_int_to_bytes(mp_int_t val, size_t buf_len, byte *buf, bool big_endian, bool is_signed, bool overflow_check) { + if (overflow_check) { + mp_obj_small_int_buffer_overflow_check(val, buf_len, is_signed); + } + mp_binary_set_int(buf_len, buf, sizeof(val), val, big_endian); + +} + +#endif // MICROPY_INCLUDED_PY_OBJINT_IMPL_H diff --git a/py/objint_longlong.c b/py/objint_longlong.c index e16fd526581..a00e634b317 100644 --- a/py/objint_longlong.c +++ b/py/objint_longlong.c @@ -29,7 +29,7 @@ #include #include "py/smallint.h" -#include "py/objint.h" +#include "py/objint_impl.h" #include "py/runtime.h" #include "py/misc.h" @@ -62,42 +62,6 @@ mp_obj_t mp_obj_int_from_bytes_impl(bool big_endian, size_t len, const byte *buf return mp_obj_new_int_from_ll(value); } -bool mp_obj_int_to_bytes_impl(mp_obj_t self_in, bool big_endian, size_t len, byte *buf) { - assert(mp_obj_is_exact_type(self_in, &mp_type_int)); - mp_obj_int_t *self = self_in; - long long val = self->val; - size_t slen; // Number of bytes to represent val - - // This logic has a twin in objint.c - if (val > 0) { - slen = (sizeof(long long) * 8 - mp_clzll(val) + 7) / 8; - } else if (val < -1) { - slen = (sizeof(long long) * 8 - mp_clzll(~val) + 8) / 8; - } else { - // clz of 0 is defined, so 0 and -1 map to 0 and 1 - slen = -val; - } - - if (slen > len) { - return false; // Would overflow - // TODO: Determine whether to copy and truncate, as some callers probably expect this...? - } - - if (big_endian) { - byte *b = buf + len; - while (b > buf) { - *--b = val; - val >>= 8; - } - } else { - for (; len > 0; --len) { - *buf++ = val; - val >>= 8; - } - } - return true; -} - int mp_obj_int_sign(mp_obj_t self_in) { mp_longint_impl_t val; if (mp_obj_is_small_int(self_in)) { @@ -362,4 +326,88 @@ mp_float_t mp_obj_int_as_float_impl(mp_obj_t self_in) { } #endif +// Same as the general mp_small_int_buffer_overflow_check() in objint_impl.h, but using 64-bit integers +static void longint_buffer_overflow_check(mp_longint_impl_t val, size_t nbytes, bool is_signed) { + // Fast path for zero. + if (val == 0) { + return; + } + + if (!is_signed && val < 0) { + // Trying to store negative values in unsigned bytes + mp_obj_int_raise_unsigned_negative_overflow_error(); + } + + if (nbytes >= sizeof(val)) { + // All non-negative N bit signed integers fit in an unsigned N bit integer. + // This case prevents shifting too far below. + return; + } + + if (nbytes == 0) { + // Can't fit a non-zero value in 0 bytes (prevents negative left shift below) + goto raise; + } + + if (is_signed) { + mp_longint_impl_t edge = 1LL << (nbytes * 8 - 1); + if (-edge <= val && val < edge) { + return; + } + // Out of range, fall through to failure. + } else { + // Unsigned. We already know val >= 0. + mp_longint_impl_t edge = 1LL << (nbytes * 8); + if (val < edge) { + return; + } + // Fall through to failure. + } + +raise: + mp_obj_int_raise_to_bytes_overflow_error(nbytes); +} + +static void longint_to_bytes(long long val, bool big_endian, size_t len, byte *buf) { + MP_STATIC_ASSERT(sizeof(mp_uint_t) == 4); + mp_uint_t lower = val; + mp_uint_t upper = (val >> 32); + + if (big_endian) { + if (len > 4) { + // write the least significant 4 bytes at the end + mp_binary_set_int(4, buf + len - 4, sizeof(lower), lower, true); + // write most significant bytes at the start, extending if necessary + mp_binary_set_int(len - 4, buf, sizeof(upper), upper, true); + } else { + mp_binary_set_int(len, buf, sizeof(lower), lower, true); + } + } else { + // write the least significant 4 bytes at the start + mp_binary_set_int(len > 4 ? len - 4 : len, buf, sizeof(lower), lower, false); + if (len > 4) { + // write the most significant bytes at the end, extending if necessary + mp_binary_set_int(len - 4, buf + 4, sizeof(upper), upper, false); + } + } +} + +void mp_obj_int_to_bytes(mp_obj_t self_in, size_t buf_len, byte *buf, bool big_endian, bool is_signed, bool overflow_check) { + mp_longint_impl_t val; + if (mp_obj_is_exact_type(self_in, &mp_type_int)) { + const mp_obj_int_t *self = MP_OBJ_TO_PTR(self_in); + val = self->val; + } else { + // self_in is either a smallint, or another type convertible to mp_int_t (i.e. bool) + val = mp_obj_get_int(self_in); + } + + // Note: to save code size we don't call mp_obj_small_int_to_bytes() here, + // as the longint implementation is very similar + if (overflow_check) { + longint_buffer_overflow_check(val, buf_len, is_signed); + } + longint_to_bytes(val, big_endian, buf_len, buf); +} + #endif diff --git a/py/objint_mpz.c b/py/objint_mpz.c index ea4e409a257..045afd5fd00 100644 --- a/py/objint_mpz.c +++ b/py/objint_mpz.c @@ -30,7 +30,7 @@ #include "py/parsenumbase.h" #include "py/smallint.h" -#include "py/objint.h" +#include "py/objint_impl.h" #include "py/runtime.h" #if MICROPY_PY_BUILTINS_FLOAT @@ -112,12 +112,6 @@ mp_obj_t mp_obj_int_from_bytes_impl(bool big_endian, size_t len, const byte *buf return MP_OBJ_FROM_PTR(o); } -bool mp_obj_int_to_bytes_impl(mp_obj_t self_in, bool big_endian, size_t len, byte *buf) { - assert(mp_obj_is_exact_type(self_in, &mp_type_int)); - mp_obj_int_t *self = MP_OBJ_TO_PTR(self_in); - return mpz_as_bytes(&self->mpz, big_endian, self->mpz.neg, len, buf); -} - int mp_obj_int_sign(mp_obj_t self_in) { if (mp_obj_is_small_int(self_in)) { mp_int_t val = MP_OBJ_SMALL_INT_VALUE(self_in); @@ -470,4 +464,22 @@ mp_float_t mp_obj_int_as_float_impl(mp_obj_t self_in) { } #endif +void mp_obj_int_to_bytes(mp_obj_t self_in, size_t buf_len, byte *buf, bool big_endian, bool is_signed, bool overflow_check) { + if (mp_obj_is_exact_type(self_in, &mp_type_int)) { + const mp_obj_int_t *self = MP_OBJ_TO_PTR(self_in); + const mpz_t *mpz = &self->mpz; + if (overflow_check && !is_signed && mpz->neg) { + mp_obj_int_raise_unsigned_negative_overflow_error(); + } + if (!mpz_as_bytes(mpz, big_endian, is_signed, buf_len, buf) && overflow_check) { + mp_obj_int_raise_to_bytes_overflow_error(buf_len); + } + } else { + // self_in is either a smallint, or another type convertible to mp_int_t (i.e. bool) + mp_int_t val = mp_obj_get_int(self_in); + mp_obj_small_int_to_bytes(val, buf_len, buf, big_endian, is_signed, overflow_check); + } +} + + #endif diff --git a/tests/basics/array_int_repr.py b/tests/basics/array_int_repr.py new file mode 100644 index 00000000000..55a2d5998eb --- /dev/null +++ b/tests/basics/array_int_repr.py @@ -0,0 +1,85 @@ +# Test array integer representations in memory +# +# This has to be a unit test because correct internal representation depends on +# native endianness +# +# These test cases should pass on both CPython and MicroPython. + +try: + from array import array + from sys import byteorder +except ImportError: + print("SKIP") + raise SystemExit + +try: + import unittest +except MemoryError: + print("SKIP-TOO-LARGE") # some small boards can't fit unittest in RAM + raise SystemExit + +# Ports without bigint support don't support typecode 'q' +try: + array("q", []) + array_has_typecode_q = True +except: + array_has_typecode_q = False + + +class TestIntReprs(unittest.TestCase): + def _test_repr(self, typecode, values): + # create an array with the specified typecode and list of values + a = array(typecode, values) + a_hex = memoryview(a).hex() + print(a, a_hex) + + self.assertEqual(len(a_hex) % len(values), 0) + # no array.itemsize in MicroPython, so calculate item size + sz = len(a_hex) // 2 // len(values) + if hasattr(a, "itemsize"): + self.assertEqual(a.itemsize, sz) + + # build alternative hex representation of the array using int.to_bytes() + # on each value + values_hex = "" + for v in values: + v_bytes = v.to_bytes(sz, byteorder=byteorder, signed=typecode.islower()) + values_hex += v_bytes.hex() + + # compare with the raw array contents + self.assertEqual(a_hex, values_hex) + + def test_smaller_ints(self): + for typecode, initialiser in ( + ("b", [1, -1, 120, -120]), + ("B", [1, 5, 220]), + ("h", [5, -1, 32_000, -32_000]), + ("H", [5, 1, 32_000, 65_535]), + ("i", [5, -1, 32_000, -32_000]), # CPython only guarantees min 2 bytes, C style! + ("I", [5, 1, 32_000, 65_535]), + ("l", [5, -1, 2_000_000, -2_000_000, 0x7FFF_FFFF]), + ("L", [5, 1, 65_536, 2_000_000, 0x7FFF_FFFF, 0xFFFF_FFFF]), + ): + self._test_repr(typecode, initialiser) + + @unittest.skipIf(not array_has_typecode_q, "port has no bigint support") + def test_bigints(self): + # Note: need to be careful not to write any literal expressions that can't be compiled on non-bigint MP + a = 0x1FFF_FFF + b = 62 + + try: + # this calculation will trigger OverflowError if bigint is set to long long + max_uint64 = [2 ** (b + 1)] + except OverflowError: + max_uint64 = [] + + for typecode, initialiser in ( + ("q", [a * 5, -a * 10, 2**b, (2**b) * -1]), + ("Q", [a * 5, a * 10, 2**b, (2**b) - 1, (2**b) + 1] + max_uint64), + ): + self._test_repr(typecode, initialiser) + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/basics/array_limits_intbig.py b/tests/basics/array_limits_intbig.py new file mode 100644 index 00000000000..b21d4752fd3 --- /dev/null +++ b/tests/basics/array_limits_intbig.py @@ -0,0 +1,119 @@ +# Test behaviour when array module is provided out of bounds values +# +# This test is intended to also pass on CPython. + +try: + from array import array +except ImportError: + print("SKIP") + raise SystemExit + +try: + import unittest +except MemoryError: + print("SKIP-TOO-LARGE") # some small boards can't fit unittest in RAM + raise SystemExit + + +# MicroPython V2.0 will enforce bounds on items (same as CPython), V1.x truncates +# +# Note: once 1 +import sys try: import uctypes @@ -13,14 +14,81 @@ print("SKIP") raise SystemExit +try: + import unittest +except MemoryError: + print("SKIP-TOO-LARGE") # some small boards can't fit unittest in RAM + raise SystemExit + +# MicroPython V2.0 will enforce bounds on bytearray setters, V1.x truncates +is_v2 = hasattr(sys.implementation, "_v2") + N = 5 +PLACEHOLDER = 99 + + +class Test(unittest.TestCase): + def test_native_endian(self): + self._test_endian("NATIVE") + + def test_little_endian(self): + self._test_endian("LITTLE_ENDIAN") + + def test_big_endian(self): + self._test_endian("BIG_ENDIAN") -for endian in ("NATIVE", "LITTLE_ENDIAN", "BIG_ENDIAN"): - for type_ in ("INT8", "UINT8", "INT16", "UINT16", "INT32", "UINT32", "INT64", "UINT64"): - desc = {"arr": (uctypes.ARRAY | 0, getattr(uctypes, type_) | N)} + def _test_endian(self, endian): + for item_type in ( + "INT8", + "UINT8", + "INT16", + "UINT16", + "INT32", + "UINT32", + "INT64", + "UINT64", + ): + print(endian, item_type) + self._test_endian_type(endian, item_type) + + def _test_endian_type(self, endian, item_type): + print("Testing array of", item_type, "with", endian, "endianness") + desc = {"arr": (uctypes.ARRAY | 0, getattr(uctypes, item_type) | N)} + print(repr(desc)) sz = uctypes.sizeof(desc) data = bytearray(sz) + print(sz, repr((uctypes.addressof(data), desc, getattr(uctypes, endian)))) s = uctypes.struct(uctypes.addressof(data), desc, getattr(uctypes, endian)) + is_unsigned = item_type.startswith("U") + item_sz = uctypes.sizeof({"": getattr(uctypes, item_type)}) + + for i in range(N): + n = i - 2 + print(i, n) + # uctypes returns a bytearray for arrays of type UINT8, MicroPython V2 will + # enforce bounds checks on these so we can't assign a negative value + if is_v2 and isinstance(s.arr, bytearray) and n < 0: + print("placeholder value", n) + with self.assertRaises(OverflowError): + s.arr[i] = n + s.arr[i] = PLACEHOLDER + n = PLACEHOLDER + else: + s.arr[i] = n + + print(endian, item_type, sz, *(s.arr[i] for i in range(N))) + for i in range(N): - s.arr[i] = i - 2 - print(endian, type_, sz, *(s.arr[i] for i in range(N))) + n = i - 2 + if is_v2 and isinstance(s.arr, bytearray) and n < 0: + # The code above has swapped in PLACEHOLDER for this value + n = PLACEHOLDER + elif is_unsigned and n < 0: + # other types of unsigned uctypes arrays will "cast" negative values to unsigned + n = n & ((1 << (item_sz * 8)) - 1) + + self.assertEqual(s.arr[i], n) + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/ports/unix/extra_coverage.py.exp b/tests/ports/unix/extra_coverage.py.exp index f856a9dcd2a..a89457f5161 100644 --- a/tests/ports/unix/extra_coverage.py.exp +++ b/tests/ports/unix/extra_coverage.py.exp @@ -144,9 +144,6 @@ TypeError: can't convert NoneType to int TypeError: can't convert NoneType to int ValueError: \$ Warning: test -# binary -123 -456 # VM 2 1 # scheduler From e6380fa15a4ddea6a80aeb557c159bc89c9507b1 Mon Sep 17 00:00:00 2001 From: Damien George Date: Sat, 6 Jun 2026 00:52:46 +1000 Subject: [PATCH 307/635] py/makeqstrdefs.py: Filter out unneeded lines from qstr.i.last early on. Generated `qstr.i.last` files (output from the "pp" phase) can be very large due to inclusion of large HAL headers. Yet only a small amount of this data is actually needed by the "split" phase of `makeqstrdefs.py`. This commit improves the situation by filtering out unneeded lines as early as possible: in the "pp" phase the C preprocessor runs, its output is parsed via a pipe connection, and only those lines that are needed are written out to the `qstr.i.last` file. When the "split" phase runs it then sees only the necessary lines (it does further regex filtering to get exactly the lines it needs for the given mode). Windows already does this filtering (it does not use `makeqstrdefs.py` for the preprocessor phase) in its `ConcatPreProcFiles` function, and that was added long ago in 29c8c8aecb3409e57a43256f8fe5cb25de1e9856. This change significantly reduces the output build size and improves the build speed: - stm32 BOARD=PYBV10: build output goes from 152M down to 32M, and build is 10% faster (29s down to 26s). Building all stm32 boards, the total build size goes from about 11GB down to about 2.5GB. - rp2 BOARD=RPI_PICO: build output goes from 87M down to 39M, and build is about 5% faster (23s down to 21.6s). - esp32 BOARD=ESP32_GENERIC: build output goes from 307M down to 230M, and build is about 6% faster (101s down to 95s). Tested all three ports above, that the files in build/genhdr are equivalent (except of course `qstr.i.last`), and that PYBV10 is binary equivalent before and after this change. Signed-off-by: Damien George --- py/makeqstrdefs.py | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/py/makeqstrdefs.py b/py/makeqstrdefs.py index dd514c7033d..6998d1ea2bd 100644 --- a/py/makeqstrdefs.py +++ b/py/makeqstrdefs.py @@ -57,10 +57,30 @@ def preprocess(): except OSError: pass + # These regex's are used to filter the preprocessed data, keeping only those lines + # that are subsequently needed by the `process_file` step. The regexs are kept + # short so they are as efficient as possible. (The stm32 port needs symbols of the + # form `micropy_hw_xxx` so they are also kept.) + re_line_file = re.compile(rb"^#(?:line)?\s+\d+\s\"") + re_mp_info = re.compile(rb"MP_COMP|MP_QSTR|MP_REGI|micropy_hw") + def pp(flags): def run(files): try: - return subprocess.check_output(args.pp + flags + files) + filtered_lines = [] + with subprocess.Popen(args.pp + flags + files, stdout=subprocess.PIPE) as proc: + recent_file = None + for line in proc.stdout: + if line.isspace(): + pass + elif re_line_file.match(line): + recent_file = line + elif re_mp_info.search(line): + if recent_file: + filtered_lines.append(recent_file) + recent_file = None + filtered_lines.append(line) + return b"".join(filtered_lines) except subprocess.CalledProcessError as er: raise PreprocessorError(str(er)) From e62bd4139edac55ad37c239b4eeb65ac78cffe01 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 10 Jun 2026 13:03:32 +1000 Subject: [PATCH 308/635] tests/run-tests.py: Add --trace-output option for board targets. This adds a new `--trace-output` option to `run-tests.py` which mimics the same option already in `run-multitests.py`. Using it, the output from the test running on a board is printed to stdout as it is received. This allows easier debugging of tests, to see the output in real time. For tests that have complicated run parameters, eg using via-mpy or needing a target wiring script, running them standalone (eg with `mpremote`) is not possible, so using `run-tests.py` becomes mandatory, hence the need to easily see the output without having to view the result file separately at the end. It's also useful to watch tests that pass but are long running. Signed-off-by: Damien George --- tests/run-tests.py | 3 +++ tests/test_utils.py | 36 ++++++++++++++++++++++++++++++++---- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/tests/run-tests.py b/tests/run-tests.py index 0763d91f153..83c8d2a6e72 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -1214,6 +1214,9 @@ def main(): run-tests.py -e async -i async_foo - include all, exclude async, yet still include async_foo """, ) + cmd_parser.add_argument( + "-c", "--trace-output", action="store_true", help="trace test output while running" + ) cmd_parser.add_argument( "-t", "--test-instance", default="unix", help="the MicroPython instance to test" ) diff --git a/tests/test_utils.py b/tests/test_utils.py index 2d5c2da47ef..40546b3cec2 100644 --- a/tests/test_utils.py +++ b/tests/test_utils.py @@ -271,24 +271,52 @@ def run_script_on_remote_target(pyb, args, test_file, is_special, requires_targe if had_crash: return True, script + # See if the output should be traced (printed to stdout), but not for feature_check tests. + trace_output = args.trace_output and "feature_check" not in test_file + if trace_output: + print(f"TRACE: {test_file}") + + # Function to collect output data as the test is run. + output_mupy = bytearray() + + def data_consumer(data): + if data == b"\x04": + # End of stream. + return + if trace_output: + # Print out the data as it's received. + sys.stdout.buffer.write(data) + sys.stdout.buffer.flush() + output_mupy.extend(data) + try: pyb.enter_raw_repl(timeout_overall=TEST_ENTER_RAW_REPL_TIMEOUT) + + # Inject target wiring if needed by the test. if requires_target_wiring and pyb.target_wiring_script: pyb.exec_( "import sys;sys.modules['target_wiring']=__build_class__(lambda:exec(" + repr(pyb.target_wiring_script) + "),'target_wiring')" ) - output_mupy = pyb.exec_(script, timeout=TEST_TIMEOUT) + + # Execute the test, and collect the output. + pyb.exec_(script, timeout=TEST_TIMEOUT, data_consumer=data_consumer) except pyboard.PyboardError as e: had_crash = True if not is_special and e.args[0] == "exception": - if prepend_start_test and e.args[1] == b"" and b"MemoryError" in e.args[2]: + no_output = len(output_mupy) == 0 + data_consumer(e.args[1]) + data_consumer(e.args[2]) + if prepend_start_test and no_output and b"MemoryError" in e.args[2]: output_mupy = b"SKIP-TOO-LARGE\n" else: - output_mupy = e.args[1] + e.args[2] + b"CRASH" + output_mupy += b"CRASH" else: - output_mupy = bytes(e.args[0], "ascii") + b"\nCRASH" + data_consumer(bytes(e.args[0], "ascii") + b"\n") + output_mupy += b"CRASH" + + output_mupy = bytes(output_mupy) if prepend_start_test: if output_mupy.startswith(b"START TEST\r\n"): From b5a681ce60ef67deb0a274193d06fa8219c1ec34 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 10 Jun 2026 12:48:44 +1000 Subject: [PATCH 309/635] extmod/modmachine: Provide machine.SDCard entry for ports to use. Similar to other classes in the `machine` module, `SDCard` is now there for a port to use if it enables MICROPY_PY_MACHINE_SDCARD. Signed-off-by: Damien George --- extmod/modmachine.c | 3 +++ extmod/modmachine.h | 1 + 2 files changed, 4 insertions(+) diff --git a/extmod/modmachine.c b/extmod/modmachine.c index 60107a9020c..c4a08918faa 100644 --- a/extmod/modmachine.c +++ b/extmod/modmachine.c @@ -231,6 +231,9 @@ static const mp_rom_map_elem_t machine_module_globals_table[] = { #if MICROPY_PY_MACHINE_PWM { MP_ROM_QSTR(MP_QSTR_PWM), MP_ROM_PTR(&machine_pwm_type) }, #endif + #if MICROPY_PY_MACHINE_SDCARD + { MP_ROM_QSTR(MP_QSTR_SDCard), MP_ROM_PTR(&machine_sdcard_type) }, + #endif #if MICROPY_PY_MACHINE_SPI { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&machine_spi_type) }, #endif diff --git a/extmod/modmachine.h b/extmod/modmachine.h index baa1d384565..d21c6e6d364 100644 --- a/extmod/modmachine.h +++ b/extmod/modmachine.h @@ -217,6 +217,7 @@ extern const mp_obj_type_t machine_pin_type; extern const mp_obj_type_t machine_pinbase_type; extern const mp_obj_type_t machine_pwm_type; extern const mp_obj_type_t machine_rtc_type; +extern const mp_obj_type_t machine_sdcard_type; extern const mp_obj_type_t machine_signal_type; extern const mp_obj_type_t machine_spi_type; extern const mp_obj_type_t machine_timer_type; From 628864b52800bc065cb65551e41a2362a186bb6d Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 10 Jun 2026 12:49:46 +1000 Subject: [PATCH 310/635] mimxrt/modmachine: Remove now-duplicate SDCard entry. This is now provided by the common one in `extmod/modmachine.c`. Signed-off-by: Damien George --- ports/mimxrt/modmachine.c | 6 ------ ports/mimxrt/modmachine.h | 1 - ports/mimxrt/msc_disk.c | 2 ++ ports/mimxrt/sdcard.c | 1 + 4 files changed, 3 insertions(+), 7 deletions(-) diff --git a/ports/mimxrt/modmachine.c b/ports/mimxrt/modmachine.c index be1be9cd083..452d045f68f 100644 --- a/ports/mimxrt/modmachine.c +++ b/ports/mimxrt/modmachine.c @@ -50,11 +50,6 @@ #define MICROPY_PY_MACHINE_LED_ENTRY #endif -#if MICROPY_PY_MACHINE_SDCARD -#define MICROPY_PY_MACHINE_SDCARD_ENTRY { MP_ROM_QSTR(MP_QSTR_SDCard), MP_ROM_PTR(&machine_sdcard_type) }, -#else -#define MICROPY_PY_MACHINE_SDCARD_ENTRY -#endif #if MICROPY_PY_MACHINE_QECNT #define MICROPY_PY_MACHINE_ENCODER_ENTRY { MP_ROM_QSTR(MP_QSTR_Encoder), MP_ROM_PTR(&machine_encoder_type) }, #define MICROPY_PY_MACHINE_COUNTER_ENTRY { MP_ROM_QSTR(MP_QSTR_Counter), MP_ROM_PTR(&machine_counter_type) }, @@ -68,7 +63,6 @@ { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&machine_pin_type) }, \ { MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&machine_timer_type) }, \ { MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&machine_rtc_type) }, \ - MICROPY_PY_MACHINE_SDCARD_ENTRY \ MICROPY_PY_MACHINE_ENCODER_ENTRY \ MICROPY_PY_MACHINE_COUNTER_ENTRY \ \ diff --git a/ports/mimxrt/modmachine.h b/ports/mimxrt/modmachine.h index ee5c1523bb2..f3816af6f31 100644 --- a/ports/mimxrt/modmachine.h +++ b/ports/mimxrt/modmachine.h @@ -29,7 +29,6 @@ #include "py/obj.h" -extern const mp_obj_type_t machine_sdcard_type; extern const mp_obj_type_t machine_can_type; void machine_adc_init(void); diff --git a/ports/mimxrt/msc_disk.c b/ports/mimxrt/msc_disk.c index c3801f481e6..b3a3cc3ac34 100644 --- a/ports/mimxrt/msc_disk.c +++ b/ports/mimxrt/msc_disk.c @@ -29,7 +29,9 @@ #include BOARD_FLASH_OPS_HEADER_H #include "stdlib.h" #include "modmimxrt.h" + #if MICROPY_PY_MACHINE_SDCARD +#include "extmod/modmachine.h" #include "sdcard.h" #ifndef MICROPY_HW_SDCARD_SDMMC diff --git a/ports/mimxrt/sdcard.c b/ports/mimxrt/sdcard.c index 5428d328abe..49686a6c23c 100644 --- a/ports/mimxrt/sdcard.c +++ b/ports/mimxrt/sdcard.c @@ -25,6 +25,7 @@ */ #include "py/mphal.h" +#include "extmod/modmachine.h" #if MICROPY_PY_MACHINE_SDCARD From 344cfc4465583c0450701d09577c531c9c4e498b Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 10 Jun 2026 12:50:28 +1000 Subject: [PATCH 311/635] esp32: Rename MICROPY_HW_ENABLE_SDCARD to MICROPY_PY_MACHINE_SDCARD. To unify this with other ports, and to enable the common `machine.SDCard` entry in `extmod/modmachine.c`. Signed-off-by: Damien George --- ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h | 2 +- ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h | 2 +- ports/esp32/machine_sdcard.c | 8 +++----- ports/esp32/modmachine.c | 7 ------- ports/esp32/modmachine.h | 1 - ports/esp32/mpconfigport.h | 4 ++-- 6 files changed, 7 insertions(+), 17 deletions(-) diff --git a/ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h index 60f27420f73..d721393b09d 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_C2/mpconfigboard.h @@ -8,7 +8,7 @@ #define MICROPY_HW_MCU_NAME "ESP32-C2" #endif -#define MICROPY_HW_ENABLE_SDCARD (0) +#define MICROPY_PY_MACHINE_SDCARD (0) #define MICROPY_PY_MACHINE_I2S (0) #define MICROPY_BOARD_STARTUP GENERIC_C2_board_startup diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h index 9cfb8b92403..05805a5fbdd 100644 --- a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h @@ -11,7 +11,7 @@ #define MICROPY_PY_ESPNOW (0) -#define MICROPY_HW_ENABLE_SDCARD (1) +#define MICROPY_PY_MACHINE_SDCARD (1) #define MICROPY_HW_SDMMC_LDO_CHAN_ID (4) #ifndef USB_SERIAL_JTAG_PACKET_SZ_BYTES diff --git a/ports/esp32/machine_sdcard.c b/ports/esp32/machine_sdcard.c index e8fcf859758..68e8a2b145a 100644 --- a/ports/esp32/machine_sdcard.c +++ b/ports/esp32/machine_sdcard.c @@ -29,9 +29,10 @@ #include "py/runtime.h" #include "py/mphal.h" #include "py/mperrno.h" +#include "extmod/modmachine.h" #include "extmod/vfs_fat.h" -#if MICROPY_HW_ENABLE_SDCARD +#if MICROPY_PY_MACHINE_SDCARD #if SOC_SDMMC_HOST_SUPPORTED #include "driver/sdmmc_host.h" @@ -57,9 +58,6 @@ // Hosts are de-inited in __del__. Slots do not need de-initing. // -// Forward declaration -const mp_obj_type_t machine_sdcard_type; - typedef struct _sdcard_obj_t { mp_obj_base_t base; mp_int_t flags; @@ -584,4 +582,4 @@ MP_DEFINE_CONST_OBJ_TYPE( locals_dict, &machine_sdcard_locals_dict ); -#endif // MICROPY_HW_ENABLE_SDCARD +#endif // MICROPY_PY_MACHINE_SDCARD diff --git a/ports/esp32/modmachine.c b/ports/esp32/modmachine.c index c0c45f948b2..b0335520417 100644 --- a/ports/esp32/modmachine.c +++ b/ports/esp32/modmachine.c @@ -40,12 +40,6 @@ #include "modmachine.h" #include "machine_rtc.h" -#if MICROPY_HW_ENABLE_SDCARD -#define MICROPY_PY_MACHINE_SDCARD_ENTRY { MP_ROM_QSTR(MP_QSTR_SDCard), MP_ROM_PTR(&machine_sdcard_type) }, -#else -#define MICROPY_PY_MACHINE_SDCARD_ENTRY -#endif - #if SOC_TOUCH_SENSOR_SUPPORTED #define MICROPY_PY_MACHINE_TOUCH_PAD_ENTRY { MP_ROM_QSTR(MP_QSTR_TouchPad), MP_ROM_PTR(&machine_touchpad_type) }, #else @@ -56,7 +50,6 @@ { MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&machine_lightsleep_obj) }, \ \ { MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&machine_timer_type) }, \ - MICROPY_PY_MACHINE_SDCARD_ENTRY \ { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&machine_pin_type) }, \ MICROPY_PY_MACHINE_TOUCH_PAD_ENTRY \ { MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&machine_rtc_type) }, \ diff --git a/ports/esp32/modmachine.h b/ports/esp32/modmachine.h index 12e0d680024..60005323c3e 100644 --- a/ports/esp32/modmachine.h +++ b/ports/esp32/modmachine.h @@ -11,7 +11,6 @@ typedef enum { extern const mp_obj_type_t machine_touchpad_type; extern const mp_obj_type_t machine_dac_type; -extern const mp_obj_type_t machine_sdcard_type; void machine_init(void); void machine_deinit(void); diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index a77e13cf3f5..a6a7bd325e2 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -192,8 +192,8 @@ #ifndef MICROPY_PY_NETWORK_WLAN #define MICROPY_PY_NETWORK_WLAN (1) #endif -#ifndef MICROPY_HW_ENABLE_SDCARD -#define MICROPY_HW_ENABLE_SDCARD (1) +#ifndef MICROPY_PY_MACHINE_SDCARD +#define MICROPY_PY_MACHINE_SDCARD (1) #endif #ifndef MICROPY_HW_SDMMC_DEFAULT_SLOT #if CONFIG_IDF_TARGET_ESP32P4 From ab710e3e48f59633fa5365b5d78a5be4e16f158c Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 10 Jun 2026 12:51:39 +1000 Subject: [PATCH 312/635] renesas-ra: Rename MICROPY_HW_HAS_SDHI_CARD-> MICROPY_PY_MACHINE_SDCARD. To unify this with other ports, and to enable the common `machine.SDCard` entry in `extmod/modmachine.c`. Signed-off-by: Damien George --- ports/renesas-ra/boards/VK_RA6M5/mpconfigboard.h | 2 +- ports/renesas-ra/machine_sdcard.c | 4 ++-- ports/renesas-ra/modmachine.c | 7 ------- ports/renesas-ra/modmachine.h | 1 - ports/renesas-ra/mpconfigboard_common.h | 4 ++-- 5 files changed, 5 insertions(+), 13 deletions(-) diff --git a/ports/renesas-ra/boards/VK_RA6M5/mpconfigboard.h b/ports/renesas-ra/boards/VK_RA6M5/mpconfigboard.h index f5daf06b5b8..17300fdc051 100644 --- a/ports/renesas-ra/boards/VK_RA6M5/mpconfigboard.h +++ b/ports/renesas-ra/boards/VK_RA6M5/mpconfigboard.h @@ -13,6 +13,7 @@ #define MICROPY_PY_UHEAPQ (1) #define MICROPY_PY_UTIMEQ (1) #define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only +#define MICROPY_PY_MACHINE_SDCARD (1) // peripheral config #define MICROPY_HW_ENABLE_RTC (1) @@ -21,7 +22,6 @@ #define MICROPY_HW_HAS_FLASH (1) #define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) #define MICROPY_HW_HAS_QSPI_FLASH (1) -#define MICROPY_HW_HAS_SDHI_CARD (1) // board config diff --git a/ports/renesas-ra/machine_sdcard.c b/ports/renesas-ra/machine_sdcard.c index ec3033a8a34..ffe1db0363e 100644 --- a/ports/renesas-ra/machine_sdcard.c +++ b/ports/renesas-ra/machine_sdcard.c @@ -28,12 +28,12 @@ #include "py/runtime.h" #include "py/mphal.h" #include "py/mperrno.h" -#include "modmachine.h" +#include "extmod/modmachine.h" #include "extmod/vfs.h" #include "hal_data.h" #include "led.h" -#if MICROPY_HW_HAS_SDHI_CARD +#if MICROPY_PY_MACHINE_SDCARD #define CARD_HOLDER 1000 // 500 ms #define CARD_OPERATION 200 // 100 ms diff --git a/ports/renesas-ra/modmachine.c b/ports/renesas-ra/modmachine.c index c23ce7e4695..058c916e469 100644 --- a/ports/renesas-ra/modmachine.c +++ b/ports/renesas-ra/modmachine.c @@ -55,12 +55,6 @@ #define PYB_RESET_WDT (3) #define PYB_RESET_DEEPSLEEP (4) -#if MICROPY_HW_HAS_SDHI_CARD -#define MICROPY_PY_MACHINE_SDCARD_ENTRY { MP_ROM_QSTR(MP_QSTR_SDCard), MP_ROM_PTR(&machine_sdcard_type) }, -#else -#define MICROPY_PY_MACHINE_SDCARD_ENTRY -#endif - #define MICROPY_PY_MACHINE_EXTRA_GLOBALS \ { MP_ROM_QSTR(MP_QSTR_info), MP_ROM_PTR(&machine_info_obj) }, \ { MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&machine_lightsleep_obj) }, \ @@ -71,7 +65,6 @@ \ { MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&machine_rtc_type) }, \ { MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&machine_timer_type) }, \ - MICROPY_PY_MACHINE_SDCARD_ENTRY \ \ { MP_ROM_QSTR(MP_QSTR_PWRON_RESET), MP_ROM_INT(PYB_RESET_POWER_ON) }, \ { MP_ROM_QSTR(MP_QSTR_HARD_RESET), MP_ROM_INT(PYB_RESET_HARD) }, \ diff --git a/ports/renesas-ra/modmachine.h b/ports/renesas-ra/modmachine.h index e64b6cc3d7a..aa0d5428e7d 100644 --- a/ports/renesas-ra/modmachine.h +++ b/ports/renesas-ra/modmachine.h @@ -31,7 +31,6 @@ extern const mp_obj_type_t machine_touchpad_type; extern const mp_obj_type_t machine_dac_type; -extern const mp_obj_type_t machine_sdcard_type; void machine_init(void); void machine_deinit(void); diff --git a/ports/renesas-ra/mpconfigboard_common.h b/ports/renesas-ra/mpconfigboard_common.h index a1aa4c0539e..280dd84a24b 100644 --- a/ports/renesas-ra/mpconfigboard_common.h +++ b/ports/renesas-ra/mpconfigboard_common.h @@ -70,8 +70,8 @@ #endif // Whether to enable access to SDCARD, through SDHI controller -#ifndef MICROPY_HW_HAS_SDHI_CARD -#define MICROPY_HW_HAS_SDHI_CARD (0) +#ifndef MICROPY_PY_MACHINE_SDCARD +#define MICROPY_PY_MACHINE_SDCARD (0) #endif // Whether to enable the RTC, exposed as pyb.RTC From b5ca38553ea6447df133b60afde86909f10724c7 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 10 Jun 2026 13:01:35 +1000 Subject: [PATCH 313/635] stm32: Enable machine.SDCard if board has pyb.SDCard. This aligns the stm32 port with other ports that have `machine.SDCard`. The same `SDCard` class is used for this and the existing `pyb.SDCard`, and its API matches the standard one. Signed-off-by: Damien George --- ports/stm32/modpyb.c | 2 +- ports/stm32/mpconfigport.h | 1 + ports/stm32/sdcard.c | 4 ++-- ports/stm32/sdcard.h | 2 +- ports/stm32/usb.c | 4 ++-- ports/stm32/usbd_msc_interface.c | 10 +++++----- 6 files changed, 12 insertions(+), 11 deletions(-) diff --git a/ports/stm32/modpyb.c b/ports/stm32/modpyb.c index a985fa39da3..27283adb554 100644 --- a/ports/stm32/modpyb.c +++ b/ports/stm32/modpyb.c @@ -226,7 +226,7 @@ static const mp_rom_map_elem_t pyb_module_globals_table[] = { #if MICROPY_PY_PYB_LEGACY { MP_ROM_QSTR(MP_QSTR_SD), MP_ROM_PTR(&pyb_sdcard_obj) }, // now obsolete #endif - { MP_ROM_QSTR(MP_QSTR_SDCard), MP_ROM_PTR(&pyb_sdcard_type) }, + { MP_ROM_QSTR(MP_QSTR_SDCard), MP_ROM_PTR(&machine_sdcard_type) }, #endif #if MICROPY_HW_ENABLE_MMCARD { MP_ROM_QSTR(MP_QSTR_MMCard), MP_ROM_PTR(&pyb_mmcard_type) }, diff --git a/ports/stm32/mpconfigport.h b/ports/stm32/mpconfigport.h index 71dd3e2cc4d..79933ee7ff8 100644 --- a/ports/stm32/mpconfigport.h +++ b/ports/stm32/mpconfigport.h @@ -144,6 +144,7 @@ #define MICROPY_PY_MACHINE_I2S_RING_BUF (1) #define MICROPY_PY_MACHINE_PWM (1) #define MICROPY_PY_MACHINE_PWM_INCLUDEFILE "ports/stm32/machine_pwm.c" +#define MICROPY_PY_MACHINE_SDCARD (MICROPY_HW_ENABLE_SDCARD) #define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_MACHINE_SPI_MSB (SPI_FIRSTBIT_MSB) #define MICROPY_PY_MACHINE_SPI_LSB (SPI_FIRSTBIT_LSB) diff --git a/ports/stm32/sdcard.c b/ports/stm32/sdcard.c index 93c1bc61977..caa6f9ecb9b 100644 --- a/ports/stm32/sdcard.c +++ b/ports/stm32/sdcard.c @@ -742,7 +742,7 @@ int sdcard_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blo // There are singleton SDCard/MMCard objects #if MICROPY_HW_ENABLE_SDCARD -const mp_obj_base_t pyb_sdcard_obj = {&pyb_sdcard_type}; +const mp_obj_base_t pyb_sdcard_obj = {&machine_sdcard_type}; #endif #if MICROPY_HW_ENABLE_MMCARD const mp_obj_base_t pyb_mmcard_obj = {&pyb_mmcard_type}; @@ -923,7 +923,7 @@ static MP_DEFINE_CONST_DICT(pyb_sdcard_locals_dict, pyb_sdcard_locals_dict_table #if MICROPY_HW_ENABLE_SDCARD MP_DEFINE_CONST_OBJ_TYPE( - pyb_sdcard_type, + machine_sdcard_type, MP_QSTR_SDCard, MP_TYPE_FLAG_NONE, make_new, pyb_sdcard_make_new, diff --git a/ports/stm32/sdcard.h b/ports/stm32/sdcard.h index 6dbf269707c..2efdcc6d8b1 100644 --- a/ports/stm32/sdcard.h +++ b/ports/stm32/sdcard.h @@ -41,7 +41,7 @@ uint64_t sdcard_get_capacity_in_bytes(void); int sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blocks); int sdcard_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks); -extern const struct _mp_obj_type_t pyb_sdcard_type; +extern const struct _mp_obj_type_t machine_sdcard_type; extern const struct _mp_obj_type_t pyb_mmcard_type; extern const struct _mp_obj_base_t pyb_sdcard_obj; diff --git a/ports/stm32/usb.c b/ports/stm32/usb.c index c17d049124f..e2778e43f7c 100644 --- a/ports/stm32/usb.c +++ b/ports/stm32/usb.c @@ -298,7 +298,7 @@ bool pyb_usb_dev_init(int dev_id, uint16_t vid, uint16_t pid, uint8_t mode, size switch (pyb_usb_storage_medium) { #if MICROPY_HW_ENABLE_SDCARD case PYB_USB_STORAGE_MEDIUM_SDCARD: - msc_unit_default[0] = &pyb_sdcard_type; + msc_unit_default[0] = &machine_sdcard_type; break; #endif default: @@ -557,7 +557,7 @@ static mp_obj_t pyb_usb_mode(size_t n_args, const mp_obj_t *pos_args, mp_map_t * const mp_obj_type_t *type = mp_obj_get_type(items[i]); if (type == &pyb_flash_type #if MICROPY_HW_ENABLE_SDCARD - || type == &pyb_sdcard_type + || type == &machine_sdcard_type #endif #if MICROPY_HW_ENABLE_MMCARD || type == &pyb_mmcard_type diff --git a/ports/stm32/usbd_msc_interface.c b/ports/stm32/usbd_msc_interface.c index 29bf46aaa66..d8c63360a99 100644 --- a/ports/stm32/usbd_msc_interface.c +++ b/ports/stm32/usbd_msc_interface.c @@ -111,7 +111,7 @@ void usbd_msc_init_lu(size_t lu_n, const void *lu_data) { bool usbd_msc_lu_includes_sdcard(void) { for (int i = 0; i < usbd_msc_lu_num; i++) { - if (usbd_msc_lu_data[i] == &pyb_sdcard_type) { + if (usbd_msc_lu_data[i] == &machine_sdcard_type) { return true; } } @@ -144,7 +144,7 @@ static int lu_ioctl(uint8_t lun, int op, uint32_t *data) { return -1; } #if MICROPY_HW_ENABLE_SDCARD - } else if (lu == &pyb_sdcard_type + } else if (lu == &machine_sdcard_type #if MICROPY_HW_ENABLE_MMCARD || lu == &pyb_mmcard_type #endif @@ -228,7 +228,7 @@ static int usbd_msc_Inquiry(uint8_t lun, const uint8_t *params, uint8_t *data_ou #if MICROPY_HW_ENABLE_SDCARD const void *lu = usbd_msc_lu_data[lun]; if (len == sizeof(usbd_msc_inquiry_data)) { - if (lu == &pyb_sdcard_type) { + if (lu == &machine_sdcard_type) { memcpy(data_out + 24, "SDCard", sizeof("SDCard") - 1); } #if MICROPY_HW_ENABLE_MMCARD @@ -300,7 +300,7 @@ static int8_t usbd_msc_Read(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16 storage_read_blocks(buf, blk_addr, blk_len); return 0; #if MICROPY_HW_ENABLE_SDCARD - } else if (lu == &pyb_sdcard_type + } else if (lu == &machine_sdcard_type #if MICROPY_HW_ENABLE_MMCARD || lu == &pyb_mmcard_type #endif @@ -324,7 +324,7 @@ static int8_t usbd_msc_Write(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint1 storage_write_blocks(buf, blk_addr, blk_len); return 0; #if MICROPY_HW_ENABLE_SDCARD - } else if (lu == &pyb_sdcard_type + } else if (lu == &machine_sdcard_type #if MICROPY_HW_ENABLE_MMCARD || lu == &pyb_mmcard_type #endif From d5b8149dff25b3e40ca2d931b2d00bba29044a0b Mon Sep 17 00:00:00 2001 From: Francesco Pace Date: Fri, 12 Jun 2026 19:39:08 +0200 Subject: [PATCH 314/635] esp32: Add Wi-Fi CSI (Channel State Information) support. Add a minimal `network.WLAN` CSI API for ESP32 builds with CSI enabled. Also enable ESP-IDF CSI support in the standard generic `ESP32`, `ESP32-C3`, `ESP32-S3`, `ESP32-C5`, and `ESP32-C6` board definitions. Signed-off-by: Francesco Pace --- docs/library/network.WLAN.rst | 101 +++++ examples/esp32_wifi_csi/README.md | 39 ++ examples/esp32_wifi_csi/csi_basic.py | 122 ++++++ .../esp32_wifi_csi/csi_turbulence_monitor.py | 147 +++++++ .../boards/ESP32_GENERIC/mpconfigboard.cmake | 3 + .../ESP32_GENERIC_C3/mpconfigboard.cmake | 3 + .../ESP32_GENERIC_C5/mpconfigboard.cmake | 4 +- .../ESP32_GENERIC_C6/mpconfigboard.cmake | 4 + .../ESP32_GENERIC_S3/mpconfigboard.cmake | 4 +- ports/esp32/boards/sdkconfig.csi | 2 + ports/esp32/esp32_common.cmake | 1 + ports/esp32/main.c | 7 + ports/esp32/mpconfigport.h | 12 + ports/esp32/network_wlan.c | 12 + ports/esp32/network_wlan_csi.c | 403 ++++++++++++++++++ ports/esp32/network_wlan_csi.h | 45 ++ 16 files changed, 907 insertions(+), 2 deletions(-) create mode 100644 examples/esp32_wifi_csi/README.md create mode 100644 examples/esp32_wifi_csi/csi_basic.py create mode 100644 examples/esp32_wifi_csi/csi_turbulence_monitor.py create mode 100644 ports/esp32/boards/sdkconfig.csi create mode 100644 ports/esp32/network_wlan_csi.c create mode 100644 ports/esp32/network_wlan_csi.h diff --git a/docs/library/network.WLAN.rst b/docs/library/network.WLAN.rst index 7df796b3929..4e60d918125 100644 --- a/docs/library/network.WLAN.rst +++ b/docs/library/network.WLAN.rst @@ -149,6 +149,107 @@ Methods bandwidth (ESP32 Only.) WiFi channel bandwidth. See `WLAN.BANDWIDTH_20` and others. ============= =========== +CSI Methods (ESP32 only) +------------------------ + +.. note:: + These methods are only available on ESP32 builds with CSI support enabled. + The standard generic ESP32, ESP32-C3, ESP32-C5, ESP32-C6, and ESP32-S3 + board definitions enable this in their default configuration. Other builds + need ``CONFIG_ESP_WIFI_CSI_ENABLED=y`` in the ESP-IDF configuration. + +Channel State Information (CSI) provides per-packet physical layer channel data +derived from received Wi-Fi frames. CSI capture requires an active Wi-Fi +connection and incoming traffic to the device. Without traffic, no CSI frames +will be captured. + +Other Espressif CSI options are hard-coded to defaults intended for connected +station capture. + +.. method:: WLAN.csi_enable(buffer_size=16) + + Enable CSI capture and allocate a circular buffer for received frames. + + The optional ``buffer_size`` argument sets the number of frames stored before + new incoming frames are dropped. Larger values reduce drops at the cost of RAM. The + exact maximum depends on the build, but it is limited by the underlying + ringbuffer implementation to roughly 100 frames. + + Raises ``OSError`` if CSI cannot be enabled, for example if Wi-Fi is not + active or the ESP-IDF rejects the configuration. + + Example:: + + import network + import time + + wlan = network.WLAN(network.WLAN.IF_STA) + wlan.active(True) + wlan.config(protocol=network.MODE_11B | network.MODE_11G | network.MODE_11N) + wlan.config(pm=wlan.PM_NONE) + wlan.connect("SSID", "password") + + while not wlan.isconnected(): + time.sleep_ms(100) + + wlan.csi_enable(buffer_size=32) + +.. method:: WLAN.csi_disable() + + Disable CSI capture and clean up resources. + +.. method:: WLAN.csi_read([result]) + + Read a CSI frame from the buffer. + + **Returns:** A list containing CSI frame data, or ``None`` if no frames are + available. + + If the optional ``result`` argument is provided, it must be a previous list + returned by `WLAN.csi_read()`. The list will be updated in place and + returned again. This reduces heap churn in busy read loops by reusing the + existing list object and, when the captured frame fits, the existing CSI + data ``bytearray``. + + **Frame list fields (in order):** + + * **0 - rssi** (int): Received signal strength in dBm + * **1 - channel** (int): Wi-Fi channel number + * **2 - mac** (bytes): Source MAC address (6 bytes) + * **3 - timestamp** (int): Timestamp in microseconds + * **4 - local_timestamp** (int): Local timestamp from Wi-Fi hardware + * **5 - data** (bytearray): CSI raw data (I/Q components as int8_t values) + * **6 - rate** (int): Data rate + * **7 - sig_mode** (int): Signal mode (legacy, HT, VHT) + * **8 - mcs** (int): Modulation and Coding Scheme index + * **9 - cwb** (int): Channel bandwidth + * **10 - smoothing** (int): Smoothing applied + * **11 - not_sounding** (int): Not sounding frame + * **12 - aggregation** (int): Aggregation + * **13 - stbc** (int): STBC + * **14 - fec_coding** (int): FEC coding + * **15 - sgi** (int): Short GI + * **16 - noise_floor** (int): Background noise level in dBm + * **17 - ampdu_cnt** (int): AMPDU count + * **18 - secondary_channel** (int): Secondary channel + * **19 - ant** (int): Antenna + * **20 - sig_len** (int): Signal length + * **21 - rx_state** (int): RX state + + Some metadata fields may be ``0`` on targets where ESP-IDF does not provide + the corresponding value in the public CSI receive structure. + +.. method:: WLAN.csi_available() + + Get the number of CSI frames available in the buffer. + +.. method:: WLAN.csi_dropped() + + Get the number of CSI frames dropped due to buffer overflow. + Frames are dropped when the buffer is full and new frames arrive faster than + they can be read. Increase ``buffer_size`` in ``csi_enable()`` to reduce + drops. + Constants --------- diff --git a/examples/esp32_wifi_csi/README.md b/examples/esp32_wifi_csi/README.md new file mode 100644 index 00000000000..ca8824785e4 --- /dev/null +++ b/examples/esp32_wifi_csi/README.md @@ -0,0 +1,39 @@ +# ESP32 Wi-Fi CSI Examples + +These examples show how to use Wi-Fi CSI on supported ESP32 builds. + +For API details, firmware requirements, and the meaning of the frame fields, see +the main `network.WLAN` documentation. + +## Before running + +- Use a firmware build with `MICROPY_PY_NETWORK_WLAN_CSI` enabled. +- Update `WIFI_SSID` and `WIFI_PASSWORD` in the example file. +- Make sure the ESP32 receives Wi-Fi traffic after connecting, otherwise no CSI + frames will be captured. A simple way to generate traffic is: + +```bash +ping -i 0.1 +``` + +## Running an example + +Run examples from the MicroPython repository root: + +```bash +mpremote connect /dev/ttyUSB0 run examples/esp32_wifi_csi/csi_basic.py +mpremote connect /dev/ttyUSB0 run examples/esp32_wifi_csi/csi_turbulence_monitor.py +``` + +Replace `/dev/ttyUSB0` with the serial device for your board. + +## Included examples + +### `csi_basic.py` + +Connects to Wi-Fi, enables CSI, and prints basic frame information. + +### `csi_turbulence_monitor.py` + +Reads CSI frames and computes a simple turbulence metric from selected +subcarriers. diff --git a/examples/esp32_wifi_csi/csi_basic.py b/examples/esp32_wifi_csi/csi_basic.py new file mode 100644 index 00000000000..817e6edd721 --- /dev/null +++ b/examples/esp32_wifi_csi/csi_basic.py @@ -0,0 +1,122 @@ +""" +Basic CSI (Channel State Information) example for ESP32. + +This example demonstrates how to: +1. Connect to a WiFi network +2. Configure WiFi protocol for CSI capture +3. Enable CSI capture +4. Read and display CSI frames + +Requirements: +- ESP32, ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C5, or ESP32-C6 +- Active WiFi connection +- CSI enabled in firmware build (MICROPY_PY_NETWORK_WLAN_CSI) + +Usage: + # From MicroPython project root directory: + mpremote connect /dev/cu.usbmodem11401 run examples/esp32_wifi_csi/csi_basic.py + +Author: Francesco Pace +""" + +import network +import time + +# WiFi credentials - CHANGE THESE! +WIFI_SSID = "your-ssid" +WIFI_PASSWORD = "your-password" + + +def connect_wifi(): + """Connect to WiFi""" + print(f"Connecting to WiFi '{WIFI_SSID}'...") + + wlan = network.WLAN(network.WLAN.IF_STA) + if wlan.active(): + wlan.active(False) + time.sleep(1) + + wlan.active(True) + time.sleep(3) + + # Configure WiFi protocol for 802.11b/g/n only. + wlan.config(protocol=network.MODE_11B | network.MODE_11G | network.MODE_11N) + wlan.config(pm=wlan.PM_NONE) + + # Connect to WiFi + wlan.connect(WIFI_SSID, WIFI_PASSWORD) + + timeout = 30 + while not wlan.isconnected() and timeout > 0: + time.sleep(1) + timeout -= 1 + + if not wlan.isconnected(): + raise Exception("WiFi connection failed") + + print(f"✅ Connected - IP: {wlan.ifconfig()[0]}") + + print("\nEnabling CSI capture...") + wlan.csi_enable(buffer_size=32) + + return wlan + + +def main(): + # Create WLAN interface + wlan = connect_wifi() + + print("\n" + "=" * 50) + print("CSI Basic Example") + print("=" * 50) + + print("\n⚠️ IMPORTANT: CSI requires active Wi-Fi traffic directed to this device.") + print(" Generate traffic from another device using:") + print(f" ping -i 0.1 {wlan.ifconfig()[0]}") + print("\nPress Ctrl+C to stop\n") + + frame_count = 0 + frame = None + try: + while True: + # Check if frames are available + available = wlan.csi_available() + if available > 0: + print(f"\n[{frame_count}] {available} frame(s) available") + + frame = wlan.csi_read(frame) + if frame: + frame_count += 1 + + # Display frame information + print(f" RSSI: {frame[0]} dBm") # rssi + print(f" Channel: {frame[1]}") # channel + print(f" MAC: {frame[2].hex()}") # mac + print(f" CSI data length: {len(frame[5])} bytes") # data + print(f" Timestamp: {frame[3]} us") # timestamp + print(f" Rate: {frame[6]}") # rate + print(f" MCS: {frame[8]}") # mcs + + # Display first few CSI samples + csi_data = frame[5] # data + if len(csi_data) > 0: + print(f" First 10 CSI samples: {list(csi_data[:10])}") + + # Check for dropped frames + dropped = wlan.csi_dropped() + if dropped > 0: + print(f" ⚠️ Dropped frames: {dropped}") + else: + # No frames available, wait a bit + time.sleep(0.1) + + except KeyboardInterrupt: + print("\n\nStopping CSI capture...") + wlan.csi_disable() + print("CSI disabled") + print(f"\nTotal frames captured: {frame_count}") + print(f"Total dropped: {wlan.csi_dropped()}") + + +if __name__ == "__main__": + main() diff --git a/examples/esp32_wifi_csi/csi_turbulence_monitor.py b/examples/esp32_wifi_csi/csi_turbulence_monitor.py new file mode 100644 index 00000000000..ea2b152ce25 --- /dev/null +++ b/examples/esp32_wifi_csi/csi_turbulence_monitor.py @@ -0,0 +1,147 @@ +""" +CSI-based turbulence monitor example for ESP32. + +This example demonstrates how to use CSI data to calculate turbulence by analyzing +changes in the channel state information over time. + +The basic principle: +- CSI data represents the channel response between transmitter and receiver +- Physical objects and environmental changes affect the Wi-Fi signal propagation +- Channel variations cause changes in CSI amplitude across subcarriers +- By calculating the standard deviation of subcarrier amplitudes, we measure spatial turbulence + +Requirements: +- ESP32, ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C5, or ESP32-C6 +- Active WiFi connection with consistent traffic +- CSI enabled in firmware build +- Router/AP should be in a fixed position + +Usage: + # From MicroPython project root directory: + mpremote connect /dev/cu.usbmodem11401 run examples/esp32_wifi_csi/csi_turbulence_monitor.py + +Author: Francesco Pace +""" + +import network +import time +import math +import gc + +# Configuration +WIFI_SSID = "your-ssid" # CHANGE THESE! +WIFI_PASSWORD = "your-password" # CHANGE THESE! +CSI_BUFFER_SIZE = 16 +SELECTED_SUBCARRIERS = [47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58] + + +def connect_wifi(): + """Connect to WiFi""" + print(f"Connecting to WiFi '{WIFI_SSID}'...") + + wlan = network.WLAN(network.WLAN.IF_STA) + if wlan.active(): + wlan.active(False) + time.sleep(1) + + wlan.active(True) + time.sleep(3) + + # Configure WiFi protocol for 802.11b/g/n only. + wlan.config(protocol=network.MODE_11B | network.MODE_11G | network.MODE_11N) + wlan.config(pm=wlan.PM_NONE) + + wlan.connect(WIFI_SSID, WIFI_PASSWORD) + + timeout = 30 + while not wlan.isconnected() and timeout > 0: + time.sleep(1) + timeout -= 1 + + if not wlan.isconnected(): + raise Exception("WiFi connection failed") + + print(f"✅ Connected - IP: {wlan.ifconfig()[0]}") + + wlan.csi_enable(buffer_size=CSI_BUFFER_SIZE) + print(f"✅ CSI enabled (buffer: {CSI_BUFFER_SIZE})\n") + + return wlan + + +def calculate_turbulence(csi_data, subcarriers): + """Calculate spatial turbulence (standard deviation of subcarrier amplitudes)""" + if len(csi_data) < 2: + return 0.0 + + sum_amp = 0.0 + sum_sq = 0.0 + count = 0 + + for sc_idx in subcarriers: + i = sc_idx * 2 + if i + 1 < len(csi_data): + real = csi_data[i] + imag = csi_data[i + 1] + amplitude = math.sqrt(real * real + imag * imag) + sum_amp += amplitude + sum_sq += amplitude * amplitude + count += 1 + + if count < 2: + return 0.0 + + mean = sum_amp / count + variance = (sum_sq / count) - (mean * mean) + return math.sqrt(max(0.0, variance)) + + +def main(): + print("\n" + "=" * 60) + print("Turbulence Monitor") + print("=" * 60 + "\n") + + wlan = connect_wifi() + + packets = 0 + frame = None + csi_length_logged = False + print("Starting CSI processing...\n") + + try: + while True: + frame = wlan.csi_read(frame) + + if frame: + csi_data = frame[5] # data field + data_len = len(csi_data) + + # Log CSI data length on first packet + if not csi_length_logged: + print(f"ℹ️ CSI data length: {data_len} bytes ({data_len // 2} subcarriers)\n") + csi_length_logged = True + + # Use only first 128 bytes (or less if data is shorter) + csi_data = csi_data[:128] + + turbulence = calculate_turbulence(csi_data, SELECTED_SUBCARRIERS) + + packets += 1 + print(f"📊 Pkts: {packets:6d} | Turbulence: {turbulence:6.2f}") + + if packets % 100 == 0: + gc.collect() + else: + time.sleep_us(100) + + except KeyboardInterrupt: + print("\n\nStopping...") + + finally: + wlan.csi_disable() + print(f"\nTotal packets: {packets}") + print("=" * 60) + + +if __name__ == "__main__": + main() diff --git a/ports/esp32/boards/ESP32_GENERIC/mpconfigboard.cmake b/ports/esp32/boards/ESP32_GENERIC/mpconfigboard.cmake index c60906b23c7..d3230993967 100644 --- a/ports/esp32/boards/ESP32_GENERIC/mpconfigboard.cmake +++ b/ports/esp32/boards/ESP32_GENERIC/mpconfigboard.cmake @@ -1 +1,4 @@ include(boards/mpconfigboard_esp32_common.cmake) + +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.csi) diff --git a/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.cmake b/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.cmake index 659141bda2c..63da7acebb6 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.cmake +++ b/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.cmake @@ -1 +1,4 @@ include(boards/mpconfigboard_esp32c3_common.cmake) + +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.csi) diff --git a/ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.cmake b/ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.cmake index d91807c3058..9a917cfcfe5 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.cmake +++ b/ports/esp32/boards/ESP32_GENERIC_C5/mpconfigboard.cmake @@ -1,4 +1,6 @@ include(boards/mpconfigboard_esp32c5_common.cmake) list(APPEND SDKCONFIG_DEFAULTS - boards/sdkconfig.flash_qio_80m) + boards/sdkconfig.flash_qio_80m + boards/sdkconfig.csi +) diff --git a/ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.cmake b/ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.cmake index b9b53141896..2fabfa19798 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.cmake +++ b/ports/esp32/boards/ESP32_GENERIC_C6/mpconfigboard.cmake @@ -1 +1,5 @@ include(boards/mpconfigboard_esp32c6_common.cmake) + +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.csi +) diff --git a/ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.cmake b/ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.cmake index b3771cad763..8703e2494b5 100644 --- a/ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.cmake +++ b/ports/esp32/boards/ESP32_GENERIC_S3/mpconfigboard.cmake @@ -1,4 +1,6 @@ include(boards/mpconfigboard_esp32s3_common.cmake) list(APPEND SDKCONFIG_DEFAULTS - boards/sdkconfig.flash_qio_80m) + boards/sdkconfig.flash_qio_80m + boards/sdkconfig.csi +) diff --git a/ports/esp32/boards/sdkconfig.csi b/ports/esp32/boards/sdkconfig.csi new file mode 100644 index 00000000000..18841d6bfe7 --- /dev/null +++ b/ports/esp32/boards/sdkconfig.csi @@ -0,0 +1,2 @@ +# Enable ESP-IDF Wi-Fi CSI support. +CONFIG_ESP_WIFI_CSI_ENABLED=y diff --git a/ports/esp32/esp32_common.cmake b/ports/esp32/esp32_common.cmake index 95fa2c9de88..62726a0b6a5 100644 --- a/ports/esp32/esp32_common.cmake +++ b/ports/esp32/esp32_common.cmake @@ -129,6 +129,7 @@ list(APPEND MICROPY_SOURCE_PORT network_lan.c network_ppp.c network_wlan.c + network_wlan_csi.c mpnimbleport.c modsocket.c lwip_patch.c diff --git a/ports/esp32/main.c b/ports/esp32/main.c index 12835f313e7..8c3c79008ef 100644 --- a/ports/esp32/main.c +++ b/ports/esp32/main.c @@ -64,6 +64,9 @@ #include "modesp32.h" #include "modmachine.h" #include "modnetwork.h" +#if MICROPY_PY_NETWORK_WLAN_CSI +#include "network_wlan_csi.h" +#endif #if MICROPY_BLUETOOTH_NIMBLE #include "extmod/modbluetooth.h" @@ -190,6 +193,10 @@ void mp_task(void *pvParameter) { MP_STATE_PORT(espnow_singleton) = NULL; #endif + #if MICROPY_PY_NETWORK_WLAN_CSI + wifi_csi_deinit(); + #endif + // Deinit uart before timers, as esp32 uart // depends on a timer instance #if MICROPY_PY_MACHINE_UART diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index a6a7bd325e2..789c8210b71 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -195,6 +195,18 @@ #ifndef MICROPY_PY_MACHINE_SDCARD #define MICROPY_PY_MACHINE_SDCARD (1) #endif +#ifndef MICROPY_PY_NETWORK_WLAN_CSI +#define MICROPY_PY_NETWORK_WLAN_CSI (CONFIG_ESP_WIFI_CSI_ENABLED) +#endif +#if MICROPY_PY_NETWORK_WLAN_CSI +// CSI_DEFAULT_BUFFER_SIZE is used in network_wlan_csi.c +#ifndef MICROPY_PY_NETWORK_WLAN_CSI_DEFAULT_BUFFER_SIZE +#define MICROPY_PY_NETWORK_WLAN_CSI_DEFAULT_BUFFER_SIZE (16) +#endif +#endif +#ifndef MICROPY_HW_ENABLE_SDCARD +#define MICROPY_HW_ENABLE_SDCARD (1) +#endif #ifndef MICROPY_HW_SDMMC_DEFAULT_SLOT #if CONFIG_IDF_TARGET_ESP32P4 #define MICROPY_HW_SDMMC_DEFAULT_SLOT (0) diff --git a/ports/esp32/network_wlan.c b/ports/esp32/network_wlan.c index fce6dae8f74..85493dff570 100644 --- a/ports/esp32/network_wlan.c +++ b/ports/esp32/network_wlan.c @@ -41,6 +41,10 @@ #include "modnetwork.h" #include "esp_wifi.h" + +#if MICROPY_PY_NETWORK_WLAN_CSI +#include "network_wlan_csi.h" +#endif #include "esp_log.h" #include "esp_psram.h" #if !CONFIG_ESP_HOSTED_ENABLED @@ -783,6 +787,14 @@ static const mp_rom_map_elem_t wlan_if_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_ifconfig), MP_ROM_PTR(&esp_network_ifconfig_obj) }, { MP_ROM_QSTR(MP_QSTR_ipconfig), MP_ROM_PTR(&esp_nic_ipconfig_obj) }, + #if MICROPY_PY_NETWORK_WLAN_CSI + { MP_ROM_QSTR(MP_QSTR_csi_enable), MP_ROM_PTR(&network_wlan_csi_enable_obj) }, + { MP_ROM_QSTR(MP_QSTR_csi_disable), MP_ROM_PTR(&network_wlan_csi_disable_obj) }, + { MP_ROM_QSTR(MP_QSTR_csi_read), MP_ROM_PTR(&network_wlan_csi_read_obj) }, + { MP_ROM_QSTR(MP_QSTR_csi_dropped), MP_ROM_PTR(&network_wlan_csi_dropped_obj) }, + { MP_ROM_QSTR(MP_QSTR_csi_available), MP_ROM_PTR(&network_wlan_csi_available_obj) }, + #endif + // Constants { MP_ROM_QSTR(MP_QSTR_IF_STA), MP_ROM_INT(WIFI_IF_STA)}, { MP_ROM_QSTR(MP_QSTR_IF_AP), MP_ROM_INT(WIFI_IF_AP)}, diff --git a/ports/esp32/network_wlan_csi.c b/ports/esp32/network_wlan_csi.c new file mode 100644 index 00000000000..8e94495f6db --- /dev/null +++ b/ports/esp32/network_wlan_csi.c @@ -0,0 +1,403 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Francesco Pace + * Copyright (c) 2025 MicroPython CSI Module Contributors + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mphal.h" +#include "py/objarray.h" +#include "py/objlist.h" +#include "py/runtime.h" +#include "py/ringbuf.h" + +#if MICROPY_PY_NETWORK_WLAN_CSI + +#include "esp_timer.h" +#include "esp_wifi.h" +#include "network_wlan_csi.h" +#include "modnetwork.h" +#include +#include + +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 +#define WIFI_CSI_RXCTRL_V2 (1) +#else +#define WIFI_CSI_RXCTRL_V2 (0) +#endif + +#define CSI_MAX_DATA_LEN (512) + +typedef struct { + uint32_t timestamp_us; + uint32_t local_timestamp; + uint16_t len; + uint16_t sig_len; + int8_t rssi; + uint8_t rate; + int8_t noise_floor; + uint8_t channel; + uint8_t ampdu_cnt; + uint8_t rx_state; + uint8_t sig_mode : 2; + uint8_t mcs : 5; + uint8_t cwb : 1; + uint8_t smoothing : 1; + uint8_t not_sounding : 1; + uint8_t aggregation : 1; + uint8_t stbc : 2; + uint8_t fec_coding : 1; + uint8_t sgi : 1; + uint8_t secondary_channel : 2; + uint8_t ant : 2; + uint8_t _reserved : 1; + uint8_t mac[6]; + int8_t data[CSI_MAX_DATA_LEN]; +} csi_frame_t; + +// ringbuf_t uses uint16_t for the byte size, so keep the Python-visible limit +// within the maximum addressable ringbuffer capacity. +#define CSI_MAX_BUFFER_SIZE ((UINT16_MAX - 1) / sizeof(csi_frame_t)) + +typedef struct { + ringbuf_t ringbuffer; + uint16_t buffer_size; + volatile uint32_t dropped; +} csi_state_t; + +static csi_state_t *wifi_csi_get_state(void) { + csi_state_t *state = (csi_state_t *)MP_STATE_PORT(csi_state); + if (state == NULL) { + state = m_new_obj(csi_state_t); + memset(state, 0, sizeof(*state)); + state->buffer_size = MICROPY_PY_NETWORK_WLAN_CSI_DEFAULT_BUFFER_SIZE; + MP_STATE_PORT(csi_state) = state; + } + return state; +} + +static void IRAM_ATTR wifi_csi_rx_cb(void *ctx, wifi_csi_info_t *info) { + (void)ctx; + + csi_state_t *state = (csi_state_t *)MP_STATE_PORT(csi_state); + if (state == NULL || state->ringbuffer.buf == NULL) { + return; + } + + // Keep this static to avoid putting a large frame on the ISR stack. + static csi_frame_t frame; + + #if WIFI_CSI_RXCTRL_V2 + frame.rssi = info->rx_ctrl.rssi; + frame.rate = info->rx_ctrl.rate; + #else + frame.rssi = info->rx_ctrl.rssi; + frame.rate = info->rx_ctrl.rate; + frame.sig_mode = info->rx_ctrl.sig_mode; + frame.mcs = info->rx_ctrl.mcs; + frame.cwb = info->rx_ctrl.cwb; + frame.smoothing = info->rx_ctrl.smoothing; + frame.not_sounding = info->rx_ctrl.not_sounding; + frame.aggregation = info->rx_ctrl.aggregation; + frame.stbc = info->rx_ctrl.stbc; + frame.fec_coding = info->rx_ctrl.fec_coding; + frame.sgi = info->rx_ctrl.sgi; + frame.ampdu_cnt = info->rx_ctrl.ampdu_cnt; + frame.secondary_channel = info->rx_ctrl.secondary_channel; + frame.ant = info->rx_ctrl.ant; + #endif + + frame.noise_floor = info->rx_ctrl.noise_floor; + frame.channel = info->rx_ctrl.channel; + frame.local_timestamp = info->rx_ctrl.timestamp; + frame.sig_len = info->rx_ctrl.sig_len; + frame.rx_state = info->rx_ctrl.rx_state; + memcpy(frame.mac, info->mac, sizeof(frame.mac)); + frame.timestamp_us = (uint32_t)esp_timer_get_time(); + + if (info->buf != NULL && info->len > 0) { + frame.len = info->len > CSI_MAX_DATA_LEN ? CSI_MAX_DATA_LEN : info->len; + memcpy(frame.data, info->buf, frame.len); + } else { + frame.len = 0; + } + + if (ringbuf_put_bytes(&state->ringbuffer, (uint8_t *)&frame, sizeof(frame)) != 0) { + state->dropped++; + } +} + +#if WIFI_CSI_RXCTRL_V2 +static void wifi_csi_build_config(wifi_csi_config_t *config) { + *config = (wifi_csi_config_t) { + .enable = 1, + .acquire_csi_legacy = 1, + .acquire_csi_ht20 = 1, + .acquire_csi_ht40 = 0, + .acquire_csi_su = 0, + .acquire_csi_mu = 0, + .acquire_csi_dcm = 0, + .acquire_csi_beamformed = 0, + .val_scale_cfg = 0, + .dump_ack_en = 0, + }; + #if CONFIG_IDF_TARGET_ESP32C6 + config->acquire_csi_he_stbc = 0; + #endif +} +#else +static void wifi_csi_build_config(wifi_csi_config_t *config) { + *config = (wifi_csi_config_t) { + .lltf_en = 0, + .htltf_en = 1, + .stbc_htltf2_en = 0, + .ltf_merge_en = 0, + .channel_filter_en = 0, + .manu_scale = 0, + .shift = 0, + .dump_ack_en = 0, + }; +} +#endif + +static esp_err_t wifi_csi_enable(csi_state_t *state) { + if (state->ringbuffer.buf != NULL) { + return ESP_ERR_INVALID_STATE; + } + + wifi_csi_config_t config; + wifi_csi_build_config(&config); + + esp_err_t err = esp_wifi_set_csi_config(&config); + if (err != ESP_OK) { + return err; + } + + ringbuf_alloc(&state->ringbuffer, sizeof(csi_frame_t) * state->buffer_size); + state->dropped = 0; + + err = esp_wifi_set_csi_rx_cb(wifi_csi_rx_cb, NULL); + if (err != ESP_OK) { + m_del(uint8_t, state->ringbuffer.buf, state->ringbuffer.size); + state->ringbuffer.buf = NULL; + state->ringbuffer.size = 0; + return err; + } + + err = esp_wifi_set_csi(true); + if (err != ESP_OK) { + esp_wifi_set_csi_rx_cb(NULL, NULL); + m_del(uint8_t, state->ringbuffer.buf, state->ringbuffer.size); + state->ringbuffer.buf = NULL; + state->ringbuffer.size = 0; + return err; + } + + return ESP_OK; +} + +static esp_err_t wifi_csi_disable(csi_state_t *state) { + if (state == NULL || state->ringbuffer.buf == NULL) { + return ESP_OK; + } + + esp_err_t err = esp_wifi_set_csi(false); + if (err != ESP_OK) { + return err; + } + + err = esp_wifi_set_csi_rx_cb(NULL, NULL); + if (err != ESP_OK) { + return err; + } + + m_del(uint8_t, state->ringbuffer.buf, state->ringbuffer.size); + state->ringbuffer.buf = NULL; + state->ringbuffer.size = 0; + state->ringbuffer.iget = 0; + state->ringbuffer.iput = 0; + state->dropped = 0; + return ESP_OK; +} + +void wifi_csi_deinit(void) { + csi_state_t *state = (csi_state_t *)MP_STATE_PORT(csi_state); + if (state == NULL) { + return; + } + + if (state->ringbuffer.buf != NULL) { + esp_wifi_set_csi(false); + esp_wifi_set_csi_rx_cb(NULL, NULL); + m_del(uint8_t, state->ringbuffer.buf, state->ringbuffer.size); + } + + m_del_obj(csi_state_t, state); + MP_STATE_PORT(csi_state) = NULL; +} + +static bool wifi_csi_read_frame(csi_frame_t *frame) { + csi_state_t *state = (csi_state_t *)MP_STATE_PORT(csi_state); + if (state == NULL || state->ringbuffer.buf == NULL) { + return false; + } + + mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION(); + int result = ringbuf_get_bytes(&state->ringbuffer, (uint8_t *)frame, sizeof(*frame)); + MICROPY_END_ATOMIC_SECTION(atomic_state); + return result == 0; +} + +static mp_obj_list_t *network_wlan_csi_get_result_list(mp_obj_t result_in) { + mp_obj_list_t *result = mp_obj_list_optional_arg(result_in, 22); + if (result->items[5] == MP_OBJ_NULL) { + result->items[5] = mp_const_none; + } else if (result->items[5] != mp_const_none && !mp_obj_is_type(result->items[5], &mp_type_bytearray)) { + mp_raise_TypeError(MP_ERROR_TEXT("result data must be bytearray")); + } + + return result; +} + +static mp_obj_array_t *network_wlan_csi_update_data(mp_obj_t *data_obj, const csi_frame_t *frame) { + mp_obj_array_t *data = NULL; + if (*data_obj != mp_const_none) { + data = MP_OBJ_TO_PTR(*data_obj); + size_t capacity = data->len + data->free; + if (capacity < frame->len) { + data = NULL; + } + } + + if (data == NULL) { + *data_obj = mp_obj_new_bytearray(frame->len, frame->data); + data = MP_OBJ_TO_PTR(*data_obj); + return data; + } + + memcpy(data->items, frame->data, frame->len); + size_t capacity = data->len + data->free; + data->len = frame->len; + data->free = capacity - frame->len; + return data; +} + +static mp_obj_t network_wlan_csi_enable(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { + (void)args[0]; + + static const mp_arg_t allowed_args[] = { + { MP_QSTR_buffer_size, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = MICROPY_PY_NETWORK_WLAN_CSI_DEFAULT_BUFFER_SIZE} }, + }; + + mp_arg_val_t parsed_args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, parsed_args); + + mp_int_t buffer_size = parsed_args[0].u_int; + if (buffer_size < 1 || buffer_size > CSI_MAX_BUFFER_SIZE) { + mp_raise_ValueError(MP_ERROR_TEXT("buffer_size out of range")); + } + + csi_state_t *state = wifi_csi_get_state(); + if (state->ringbuffer.buf != NULL) { + esp_exceptions(ESP_ERR_INVALID_STATE); + } + state->buffer_size = buffer_size; + esp_exceptions(wifi_csi_enable(state)); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(network_wlan_csi_enable_obj, 1, network_wlan_csi_enable); + +static mp_obj_t network_wlan_csi_disable(mp_obj_t self_in) { + (void)self_in; + csi_state_t *state = (csi_state_t *)MP_STATE_PORT(csi_state); + if (state != NULL) { + esp_exceptions(wifi_csi_disable(state)); + } + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_1(network_wlan_csi_disable_obj, network_wlan_csi_disable); + +static mp_obj_t network_wlan_csi_read(size_t n_args, const mp_obj_t *args) { + (void)args[0]; + + csi_frame_t frame; + if (!wifi_csi_read_frame(&frame)) { + return mp_const_none; + } + + mp_obj_list_t *result = network_wlan_csi_get_result_list(n_args > 1 ? args[1] : mp_const_none); + + result->items[0] = MP_OBJ_NEW_SMALL_INT(frame.rssi); + result->items[1] = MP_OBJ_NEW_SMALL_INT(frame.channel); + result->items[2] = mp_obj_new_bytes(frame.mac, sizeof(frame.mac)); + result->items[3] = mp_obj_new_int(frame.timestamp_us); + result->items[4] = mp_obj_new_int(frame.local_timestamp); + + mp_obj_array_t *csi_data = network_wlan_csi_update_data(&result->items[5], &frame); + csi_data->typecode = 'b'; + + result->items[6] = MP_OBJ_NEW_SMALL_INT(frame.rate); + result->items[7] = MP_OBJ_NEW_SMALL_INT(frame.sig_mode); + result->items[8] = MP_OBJ_NEW_SMALL_INT(frame.mcs); + result->items[9] = MP_OBJ_NEW_SMALL_INT(frame.cwb); + result->items[10] = MP_OBJ_NEW_SMALL_INT(frame.smoothing); + result->items[11] = MP_OBJ_NEW_SMALL_INT(frame.not_sounding); + result->items[12] = MP_OBJ_NEW_SMALL_INT(frame.aggregation); + result->items[13] = MP_OBJ_NEW_SMALL_INT(frame.stbc); + result->items[14] = MP_OBJ_NEW_SMALL_INT(frame.fec_coding); + result->items[15] = MP_OBJ_NEW_SMALL_INT(frame.sgi); + result->items[16] = MP_OBJ_NEW_SMALL_INT(frame.noise_floor); + result->items[17] = MP_OBJ_NEW_SMALL_INT(frame.ampdu_cnt); + result->items[18] = MP_OBJ_NEW_SMALL_INT(frame.secondary_channel); + result->items[19] = MP_OBJ_NEW_SMALL_INT(frame.ant); + result->items[20] = MP_OBJ_NEW_SMALL_INT(frame.sig_len); + result->items[21] = MP_OBJ_NEW_SMALL_INT(frame.rx_state); + return MP_OBJ_FROM_PTR(result); +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(network_wlan_csi_read_obj, 1, 2, network_wlan_csi_read); + +static mp_obj_t network_wlan_csi_dropped(mp_obj_t self_in) { + (void)self_in; + csi_state_t *state = (csi_state_t *)MP_STATE_PORT(csi_state); + return mp_obj_new_int(state == NULL ? 0 : state->dropped); +} +MP_DEFINE_CONST_FUN_OBJ_1(network_wlan_csi_dropped_obj, network_wlan_csi_dropped); + +static mp_obj_t network_wlan_csi_available(mp_obj_t self_in) { + (void)self_in; + + csi_state_t *state = (csi_state_t *)MP_STATE_PORT(csi_state); + if (state == NULL || state->ringbuffer.buf == NULL) { + return MP_OBJ_NEW_SMALL_INT(0); + } + + mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION(); + size_t available = ringbuf_avail(&state->ringbuffer); + MICROPY_END_ATOMIC_SECTION(atomic_state); + return MP_OBJ_NEW_SMALL_INT(available / sizeof(csi_frame_t)); +} +MP_DEFINE_CONST_FUN_OBJ_1(network_wlan_csi_available_obj, network_wlan_csi_available); + +MP_REGISTER_ROOT_POINTER(void *csi_state); + +#endif // MICROPY_PY_NETWORK_WLAN_CSI diff --git a/ports/esp32/network_wlan_csi.h b/ports/esp32/network_wlan_csi.h new file mode 100644 index 00000000000..9ce9c2029ee --- /dev/null +++ b/ports/esp32/network_wlan_csi.h @@ -0,0 +1,45 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Francesco Pace + * Copyright (c) 2025 MicroPython CSI Module Contributors + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_ESP32_NETWORK_WLAN_CSI_H +#define MICROPY_INCLUDED_ESP32_NETWORK_WLAN_CSI_H + +#include "py/obj.h" + +#if MICROPY_PY_NETWORK_WLAN_CSI + +void wifi_csi_deinit(void); + +MP_DECLARE_CONST_FUN_OBJ_KW(network_wlan_csi_enable_obj); +MP_DECLARE_CONST_FUN_OBJ_1(network_wlan_csi_disable_obj); +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(network_wlan_csi_read_obj); +MP_DECLARE_CONST_FUN_OBJ_1(network_wlan_csi_dropped_obj); +MP_DECLARE_CONST_FUN_OBJ_1(network_wlan_csi_available_obj); + +#endif // MICROPY_PY_NETWORK_WLAN_CSI + +#endif // MICROPY_INCLUDED_ESP32_NETWORK_WLAN_CSI_H From 051112596cb26bcb42efb6968e7855ddbeb5bf50 Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Tue, 23 Jun 2026 00:49:17 +0200 Subject: [PATCH 315/635] esp32/boards/SEEED_XIAO_ESP32C3: Add new board definition. Add a board definition for the Seeed Studio XIAO ESP32C3 (ESP32-C3 with 4MB flash). The REPL is on the native USB Serial/JTAG interface, leaving UART0 free for the application. Signed-off-by: Pavel Revak --- .../boards/SEEED_XIAO_ESP32C3/board.json | 23 +++++++++++++++++++ .../SEEED_XIAO_ESP32C3/mpconfigboard.cmake | 1 + .../boards/SEEED_XIAO_ESP32C3/mpconfigboard.h | 13 +++++++++++ .../esp32/boards/SEEED_XIAO_ESP32C3/pins.csv | 15 ++++++++++++ 4 files changed, 52 insertions(+) create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32C3/board.json create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32C3/mpconfigboard.cmake create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32C3/mpconfigboard.h create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32C3/pins.csv diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C3/board.json b/ports/esp32/boards/SEEED_XIAO_ESP32C3/board.json new file mode 100644 index 00000000000..2eda8983ffb --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C3/board.json @@ -0,0 +1,23 @@ +{ + "deploy": [ + "../deploy_nativeusb.md" + ], + "deploy_options": { + "flash_offset": "0" + }, + "docs": "", + "features": [ + "BLE", + "WiFi", + "USB", + "USB-C", + "Battery Charging" + ], + "images": [ + "seeed_xiao_esp32c3.jpg" + ], + "mcu": "esp32c3", + "product": "XIAO ESP32C3", + "url": "https://www.seeedstudio.com/Seeed-XIAO-ESP32C3-p-5431.html", + "vendor": "Seeed Studio" +} diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C3/mpconfigboard.cmake b/ports/esp32/boards/SEEED_XIAO_ESP32C3/mpconfigboard.cmake new file mode 100644 index 00000000000..659141bda2c --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C3/mpconfigboard.cmake @@ -0,0 +1 @@ +include(boards/mpconfigboard_esp32c3_common.cmake) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C3/mpconfigboard.h b/ports/esp32/boards/SEEED_XIAO_ESP32C3/mpconfigboard.h new file mode 100644 index 00000000000..c9149db96ba --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C3/mpconfigboard.h @@ -0,0 +1,13 @@ +#define MICROPY_HW_BOARD_NAME "Seeed XIAO ESP32C3" +#define MICROPY_HW_MCU_NAME "ESP32-C3" + +// REPL is on the native USB Serial/JTAG interface; the hardware UART is left +// free for the application. To put the REPL on UART0, define +// MICROPY_HW_ENABLE_UART_REPL. + +#define MICROPY_HW_I2C0_SCL (7) +#define MICROPY_HW_I2C0_SDA (6) + +#define MICROPY_HW_SPI1_MOSI (10) +#define MICROPY_HW_SPI1_MISO (9) +#define MICROPY_HW_SPI1_SCK (8) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C3/pins.csv b/ports/esp32/boards/SEEED_XIAO_ESP32C3/pins.csv new file mode 100644 index 00000000000..e5cc8eca8d8 --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C3/pins.csv @@ -0,0 +1,15 @@ +D0,GPIO2 +D1,GPIO3 +D2,GPIO4 +D3,GPIO5 +D4,GPIO6 +D5,GPIO7 +D6,GPIO21 +D7,GPIO20 +D8,GPIO8 +D9,GPIO9 +D10,GPIO10 +A0,GPIO2 +A1,GPIO3 +A2,GPIO4 +BOOT,GPIO9 From 9e76ed1a9c587b9611ec78d62e9d65e7da855c30 Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Tue, 23 Jun 2026 00:49:17 +0200 Subject: [PATCH 316/635] esp32/boards/SEEED_XIAO_ESP32C5: Add new board definition. Add a board definition for the Seeed Studio XIAO ESP32C5 (ESP32-C5 with 8MB flash and 8MB quad SPIRAM). The REPL is on the native USB Serial/JTAG interface, leaving UART0 free for the application. Signed-off-by: Pavel Revak --- .../boards/SEEED_XIAO_ESP32C5/board.json | 25 +++++++++++++++++++ .../SEEED_XIAO_ESP32C5/mpconfigboard.cmake | 5 ++++ .../boards/SEEED_XIAO_ESP32C5/mpconfigboard.h | 15 +++++++++++ .../esp32/boards/SEEED_XIAO_ESP32C5/pins.csv | 14 +++++++++++ 4 files changed, 59 insertions(+) create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32C5/board.json create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32C5/mpconfigboard.cmake create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32C5/mpconfigboard.h create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32C5/pins.csv diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C5/board.json b/ports/esp32/boards/SEEED_XIAO_ESP32C5/board.json new file mode 100644 index 00000000000..5762f74373d --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C5/board.json @@ -0,0 +1,25 @@ +{ + "deploy": [ + "../deploy_nativeusb.md" + ], + "deploy_options": { + "flash_offset": "0" + }, + "docs": "", + "features": [ + "BLE", + "External Flash", + "External RAM", + "WiFi", + "USB", + "USB-C", + "Battery Charging" + ], + "images": [ + "seeed_xiao_esp32c5.jpg" + ], + "mcu": "esp32c5", + "product": "XIAO ESP32C5", + "url": "https://wiki.seeedstudio.com/xiao_esp32c5_getting_started/", + "vendor": "Seeed Studio" +} diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C5/mpconfigboard.cmake b/ports/esp32/boards/SEEED_XIAO_ESP32C5/mpconfigboard.cmake new file mode 100644 index 00000000000..fec1df470b1 --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C5/mpconfigboard.cmake @@ -0,0 +1,5 @@ +include(boards/mpconfigboard_esp32c5_common.cmake) + +# XIAO ESP32C5 has 8MB flash and 8MB quad SPIRAM (enabled by the common config). +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.flash_qio_80m) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C5/mpconfigboard.h b/ports/esp32/boards/SEEED_XIAO_ESP32C5/mpconfigboard.h new file mode 100644 index 00000000000..3dcecf363c9 --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C5/mpconfigboard.h @@ -0,0 +1,15 @@ +#define MICROPY_HW_BOARD_NAME "Seeed XIAO ESP32C5" +#define MICROPY_HW_MCU_NAME "ESP32-C5" + +#define MICROPY_PY_MACHINE_I2S (0) + +// REPL is on the native USB Serial/JTAG interface; the hardware UART is left +// free for the application. To put the REPL on UART0, define +// MICROPY_HW_ENABLE_UART_REPL. + +#define MICROPY_HW_I2C0_SCL (24) +#define MICROPY_HW_I2C0_SDA (23) + +#define MICROPY_HW_SPI1_MOSI (10) +#define MICROPY_HW_SPI1_MISO (9) +#define MICROPY_HW_SPI1_SCK (8) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32C5/pins.csv b/ports/esp32/boards/SEEED_XIAO_ESP32C5/pins.csv new file mode 100644 index 00000000000..dc6b565611c --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32C5/pins.csv @@ -0,0 +1,14 @@ +D0,GPIO1 +D1,GPIO0 +D2,GPIO25 +D3,GPIO7 +D4,GPIO23 +D5,GPIO24 +D6,GPIO11 +D7,GPIO12 +D8,GPIO8 +D9,GPIO9 +D10,GPIO10 +A0,GPIO1 +LED,GPIO27 +BOOT,GPIO28 From 9d3881f43a9ca5442d625b3911acc641c078eb5c Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Tue, 23 Jun 2026 00:49:16 +0200 Subject: [PATCH 317/635] esp32/boards/SEEED_XIAO_ESP32S3: Add new board definition. Add a board definition for the Seeed Studio XIAO ESP32S3 (ESP32-S3 with 8MB flash and 8MB octal SPIRAM). The REPL is on the native USB interface, leaving UART0 free for the application. The same firmware also runs on the XIAO ESP32S3 Plus: the flash size is auto-detected, and the Plus's extra pins (D11-D19) are included in pins.csv, which does not affect the standard board. Signed-off-by: Pavel Revak --- .../boards/SEEED_XIAO_ESP32S3/board.json | 25 ++++++++++++++++++ .../esp32/boards/SEEED_XIAO_ESP32S3/board.md | 9 +++++++ .../SEEED_XIAO_ESP32S3/mpconfigboard.cmake | 8 ++++++ .../boards/SEEED_XIAO_ESP32S3/mpconfigboard.h | 12 +++++++++ .../esp32/boards/SEEED_XIAO_ESP32S3/pins.csv | 26 +++++++++++++++++++ 5 files changed, 80 insertions(+) create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32S3/board.json create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32S3/board.md create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.cmake create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h create mode 100644 ports/esp32/boards/SEEED_XIAO_ESP32S3/pins.csv diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32S3/board.json b/ports/esp32/boards/SEEED_XIAO_ESP32S3/board.json new file mode 100644 index 00000000000..9fafc7bca2b --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32S3/board.json @@ -0,0 +1,25 @@ +{ + "deploy": [ + "../deploy_nativeusb.md" + ], + "deploy_options": { + "flash_offset": "0" + }, + "docs": "", + "features": [ + "BLE", + "External Flash", + "External RAM", + "WiFi", + "USB", + "USB-C", + "Battery Charging" + ], + "images": [ + "seeed_xiao_esp32s3.jpg" + ], + "mcu": "esp32s3", + "product": "XIAO ESP32S3", + "url": "https://www.seeedstudio.com/XIAO-ESP32S3-p-5627.html", + "vendor": "Seeed Studio" +} diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32S3/board.md b/ports/esp32/boards/SEEED_XIAO_ESP32S3/board.md new file mode 100644 index 00000000000..0a74b29ec9e --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32S3/board.md @@ -0,0 +1,9 @@ +This firmware works on both the Seeed Studio XIAO ESP32S3 and the XIAO +ESP32S3 Plus. + +The Plus variant has 16MiB of flash (versus 8MiB on the standard board) and +exposes additional GPIO pins (D11-D19). The flash size is auto-detected and +the extra pins are included in the pin definitions, so the same firmware runs +on both boards. + +For more information see the [Seeed Studio XIAO ESP32S3 wiki](https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/). diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.cmake b/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.cmake new file mode 100644 index 00000000000..0feb5d1f5b5 --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.cmake @@ -0,0 +1,8 @@ +include(boards/mpconfigboard_esp32s3_common.cmake) + +# XIAO ESP32S3 has 8MB flash and 8MB octal SPIRAM. +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.flash_qio_80m + boards/sdkconfig.240mhz + boards/sdkconfig.spiram_oct +) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h b/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h new file mode 100644 index 00000000000..94c8b534162 --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h @@ -0,0 +1,12 @@ +#define MICROPY_HW_BOARD_NAME "Seeed XIAO ESP32S3" +#define MICROPY_HW_MCU_NAME "ESP32-S3" + +// REPL is on the native USB-CDC interface; the hardware UART is left free for +// the application. To put the REPL on UART0, define MICROPY_HW_ENABLE_UART_REPL. + +#define MICROPY_HW_I2C0_SCL (6) +#define MICROPY_HW_I2C0_SDA (5) + +#define MICROPY_HW_SPI1_MOSI (9) +#define MICROPY_HW_SPI1_MISO (8) +#define MICROPY_HW_SPI1_SCK (7) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32S3/pins.csv b/ports/esp32/boards/SEEED_XIAO_ESP32S3/pins.csv new file mode 100644 index 00000000000..8e58112d057 --- /dev/null +++ b/ports/esp32/boards/SEEED_XIAO_ESP32S3/pins.csv @@ -0,0 +1,26 @@ +D0,GPIO1 +D1,GPIO2 +D2,GPIO3 +D3,GPIO4 +D4,GPIO5 +D5,GPIO6 +D6,GPIO43 +D7,GPIO44 +D8,GPIO7 +D9,GPIO8 +D10,GPIO9 +D11,GPIO38 +D12,GPIO39 +D13,GPIO40 +D14,GPIO41 +D15,GPIO42 +D16,GPIO10 +D17,GPIO13 +D18,GPIO12 +D19,GPIO11 +A0,GPIO1 +A1,GPIO2 +A2,GPIO3 +A3,GPIO4 +LED,GPIO21 +BOOT,GPIO0 From 292b3e60112e18276e6682d71a8e22db0945336e Mon Sep 17 00:00:00 2001 From: robert-hh Date: Thu, 21 May 2026 20:18:38 +0200 Subject: [PATCH 318/635] esp32/machine_i2c: Set default for new I2C driver at esp-idf >= v5.5.2. By default the new I2C driver is enabled for esp-idf version >= 5.5.2. With v5.5.2 and up the the additional bus probing is not needed any more. It was needed because transfers to a non-existing address caused an error message to be printed instead of just returning an error code. With esp-idf v5.5.2 it returns just an error code. For 0-length writes as being used by i2c.scan(), an additional code path using i2c_master_execute_defined_operations() is needed to avoid an error message. Tested with a Generic ESP32 and esp-idf v5.5.1, v5.5.2 and v5.5.4. Tested as well using the new driver with v5.5.1. Tested V5.5.2 with Generic ESP32, ESP32S2, ESP32S3, ESP32C2, ESP32C3, ESP32C5, ESP32C6, ESP32P4. Driving an external device as I2C controller. There is a slight inconsistency: reading 0 bytes from a non-existing address return an empty bytes object and does not raise an error. Writing 0 bytes to a non-existing address returns an error. That case is used by i2c.scan(). Signed-off-by: robert-hh --- ports/esp32/machine_i2c.c | 43 +++++++++++++++++++------------------- ports/esp32/mpconfigport.h | 6 +++--- 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/ports/esp32/machine_i2c.c b/ports/esp32/machine_i2c.c index 2c59849d301..4c87e6d6b49 100644 --- a/ports/esp32/machine_i2c.c +++ b/ports/esp32/machine_i2c.c @@ -31,14 +31,6 @@ #include "extmod/modmachine.h" #include "machine_i2c.h" -#if MICROPY_HW_ESP_NEW_I2C_DRIVER -#include "driver/i2c_master.h" -#else -#include "driver/i2c.h" -#include "esp_clk_tree.h" -#include "hal/i2c_ll.h" -#endif - #if MICROPY_PY_MACHINE_I2C || MICROPY_PY_MACHINE_SOFTI2C #define I2C_DEFAULT_TIMEOUT_US (50000) // 50ms @@ -47,6 +39,7 @@ // option is set. #if MICROPY_HW_ESP_NEW_I2C_DRIVER +#include "driver/i2c_master.h" typedef struct _machine_hw_i2c_obj_t { mp_obj_base_t base; @@ -118,12 +111,15 @@ static uint8_t *create_transfer_buffer(size_t n, mp_machine_i2c_buf_t *bufs, siz int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_machine_i2c_buf_t *bufs, unsigned int flags) { machine_hw_i2c_obj_t *self = MP_OBJ_TO_PTR(self_in); - // Probe the address to see if any device responds. + // Probe the address to see if any device responds for esp-idf < v5.5.4. // This test uses a fixed scl freq of 100_000. - esp_err_t err = i2c_master_probe(self->bus_handle, addr, self->timeout_us / 1000); + esp_err_t err = ESP_OK; + #if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 2) + err = i2c_master_probe(self->bus_handle, addr, self->timeout_us / 1000); if (err != ESP_OK) { return -MP_ENODEV; // No device at address, return immediately } + #endif #if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) // Using ".device_address = I2C_DEVICE_ADDRESS_NOT_USED," below @@ -187,20 +183,21 @@ int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_ } } err = i2c_master_transmit(dev_handle, buf, len, self->timeout_us / 1000); - // Use i2c_master_execute_defined_operations() instead of - // i2c_master_transmit(), allowing for len == 0. - // That will be needed for scan() when dropping i2c_master_probe() is possible, - // after https://github.com/espressif/esp-idf/issues/17543 backported to supported versions - // i2c_operation_job_t i2c_ops[] = { - // { .command = I2C_MASTER_CMD_START }, - // { .command = I2C_MASTER_CMD_WRITE, .write = { .ack_check = true, .data = buf, .total_bytes = len } }, - // { .command = I2C_MASTER_CMD_STOP }, // Stop is still mandatory - // }; - // err = i2c_master_execute_defined_operations(dev_handle, i2c_ops, 3, self->timeout_us / 1000); } if (n > 1) { m_del(uint8_t, buf, len); } + #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 2) + } else if (!(flags & MP_MACHINE_I2C_FLAG_READ)) { + // Write operation with len=0, bufs->buf = NULL, used by i2c.scan(). + // Use i2c_master_execute_defined_operations() allowing for len == 0. + i2c_operation_job_t i2c_ops[] = { + { .command = I2C_MASTER_CMD_START }, + { .command = I2C_MASTER_CMD_WRITE, .write = { .ack_check = true, .data = NULL, .total_bytes = 0 } }, + { .command = I2C_MASTER_CMD_STOP }, // Stop is still mandatory + }; + err = i2c_master_execute_defined_operations(dev_handle, i2c_ops, 3, self->timeout_us / 1000); + #endif } #if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) // Remove the temporary handle. @@ -208,7 +205,7 @@ int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_ #endif // Map errors - if (err == ESP_FAIL) { + if (err == ESP_FAIL || err == ESP_ERR_INVALID_STATE) { return -MP_ENODEV; } if (err == ESP_ERR_TIMEOUT) { @@ -222,6 +219,10 @@ int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_ #else +#include "driver/i2c.h" +#include "esp_clk_tree.h" +#include "hal/i2c_ll.h" + #if SOC_I2C_SUPPORT_XTAL #if CONFIG_XTAL_FREQ > 0 #define I2C_SCLK_FREQ (CONFIG_XTAL_FREQ * 1000000) diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index 789c8210b71..20827cf81e7 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -146,6 +146,9 @@ #define MICROPY_PY_MACHINE_I2C_TARGET_INCLUDEFILE "ports/esp32/machine_i2c_target.c" #define MICROPY_PY_MACHINE_I2C_TARGET_MAX (2) #endif +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 2) && !defined(MICROPY_HW_ESP_NEW_I2C_DRIVER) +#define MICROPY_HW_ESP_NEW_I2C_DRIVER (1) +#endif #define MICROPY_PY_MACHINE_SOFTI2C (1) #define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_MACHINE_SOFTSPI (1) @@ -216,9 +219,6 @@ #endif #define MICROPY_HW_SOFTSPI_MIN_DELAY (0) #define MICROPY_HW_SOFTSPI_MAX_BAUDRATE (esp_rom_get_cpu_ticks_per_us() * 1000000 / 200) // roughly -#ifndef MICROPY_HW_ESP_NEW_I2C_DRIVER -#define MICROPY_HW_ESP_NEW_I2C_DRIVER (0) -#endif #define MICROPY_PY_SSL (MICROPY_PY_NETWORK) #define MICROPY_SSL_MBEDTLS (MICROPY_PY_SSL) #define MICROPY_PY_WEBSOCKET (MICROPY_PY_NETWORK) From 57219fcb6de2c417a62eb7e765041253418aff56 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Sun, 24 May 2026 11:00:07 +0200 Subject: [PATCH 319/635] esp32/machine_i2c: Restrict the new I2C driver to esp-idf >=v5.5.2. If the new driver is enabled for versions previous to v5.5.2, an error is raised and compilation aborted. Signed-off-by: robert-hh --- ports/esp32/machine_i2c.c | 49 +++++++-------------------------------- 1 file changed, 9 insertions(+), 40 deletions(-) diff --git a/ports/esp32/machine_i2c.c b/ports/esp32/machine_i2c.c index 4c87e6d6b49..2be596af197 100644 --- a/ports/esp32/machine_i2c.c +++ b/ports/esp32/machine_i2c.c @@ -41,12 +41,14 @@ #if MICROPY_HW_ESP_NEW_I2C_DRIVER #include "driver/i2c_master.h" +#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 2) +#error The new I2C driver requires esp-idf >= v5.5.2 +#endif + typedef struct _machine_hw_i2c_obj_t { mp_obj_base_t base; i2c_master_bus_handle_t bus_handle; - #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) i2c_master_dev_handle_t dev_handle; - #endif uint8_t port : 8; gpio_num_t scl : 8; gpio_num_t sda : 8; @@ -58,12 +60,10 @@ static machine_hw_i2c_obj_t machine_hw_i2c_obj[I2C_NUM_MAX]; static void machine_hw_i2c_init(machine_hw_i2c_obj_t *self, bool first_init) { - #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) if (!first_init && self->dev_handle) { i2c_master_bus_rm_device(self->dev_handle); self->dev_handle = NULL; } - #endif if (!first_init && self->bus_handle) { i2c_del_master_bus(self->bus_handle); @@ -79,14 +79,12 @@ static void machine_hw_i2c_init(machine_hw_i2c_obj_t *self, bool first_init) { .flags.enable_internal_pullup = true, }; ESP_ERROR_CHECK(i2c_new_master_bus(&bus_cfg, &self->bus_handle)); - #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) i2c_device_config_t dev_cfg = { .dev_addr_length = I2C_ADDR_BIT_LEN_7, .device_address = 0, // Will be replaced .scl_speed_hz = self->freq, }; ESP_ERROR_CHECK(i2c_master_bus_add_device(self->bus_handle, &dev_cfg, &self->dev_handle)); - #endif } static uint8_t *create_transfer_buffer(size_t n, mp_machine_i2c_buf_t *bufs, size_t *len_ptr) { @@ -111,31 +109,8 @@ static uint8_t *create_transfer_buffer(size_t n, mp_machine_i2c_buf_t *bufs, siz int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_machine_i2c_buf_t *bufs, unsigned int flags) { machine_hw_i2c_obj_t *self = MP_OBJ_TO_PTR(self_in); - // Probe the address to see if any device responds for esp-idf < v5.5.4. - // This test uses a fixed scl freq of 100_000. esp_err_t err = ESP_OK; - #if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 2) - err = i2c_master_probe(self->bus_handle, addr, self->timeout_us / 1000); - if (err != ESP_OK) { - return -MP_ENODEV; // No device at address, return immediately - } - #endif - - #if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) - // Using ".device_address = I2C_DEVICE_ADDRESS_NOT_USED," below - // allows to write the address separately using the - // i2c_master_execute_defined_operations() API. - i2c_device_config_t dev_cfg = { - .dev_addr_length = I2C_ADDR_BIT_LEN_7, - .device_address = addr, - .scl_speed_hz = self->freq, - }; - i2c_master_dev_handle_t dev_handle; - err = i2c_master_bus_add_device(self->bus_handle, &dev_cfg, &dev_handle); - #else - #define dev_handle self->dev_handle - err = i2c_master_device_change_address(dev_handle, addr, self->timeout_us / 1000); - #endif + err = i2c_master_device_change_address(self->dev_handle, addr, self->timeout_us / 1000); if (err != ESP_OK) { return -MP_ENODEV; } @@ -151,7 +126,7 @@ int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_ // create a large buffer if needed buf = create_transfer_buffer(n - 1, bufs + 1, &len); // Do a write then read - err = i2c_master_transmit_receive(dev_handle, bufs[0].buf, bufs[0].len, buf, len, self->timeout_us / 1000); + err = i2c_master_transmit_receive(self->dev_handle, bufs[0].buf, bufs[0].len, buf, len, self->timeout_us / 1000); // Copy the data back if needed starting with the second buffer. if (n > 2) { len = 0; @@ -166,7 +141,7 @@ int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_ buf = create_transfer_buffer(n, bufs, &len); // Transfer data and copy it from/to the buffers as needed. if (flags & MP_MACHINE_I2C_FLAG_READ) { - err = i2c_master_receive(dev_handle, buf, len, self->timeout_us / 1000); + err = i2c_master_receive(self->dev_handle, buf, len, self->timeout_us / 1000); if (n > 1) { len = 0; for (size_t i = 0; i < n; ++i) { @@ -182,12 +157,11 @@ int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_ len += bufs[i].len; } } - err = i2c_master_transmit(dev_handle, buf, len, self->timeout_us / 1000); + err = i2c_master_transmit(self->dev_handle, buf, len, self->timeout_us / 1000); } if (n > 1) { m_del(uint8_t, buf, len); } - #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 2) } else if (!(flags & MP_MACHINE_I2C_FLAG_READ)) { // Write operation with len=0, bufs->buf = NULL, used by i2c.scan(). // Use i2c_master_execute_defined_operations() allowing for len == 0. @@ -196,13 +170,8 @@ int machine_hw_i2c_transfer(mp_obj_base_t *self_in, uint16_t addr, size_t n, mp_ { .command = I2C_MASTER_CMD_WRITE, .write = { .ack_check = true, .data = NULL, .total_bytes = 0 } }, { .command = I2C_MASTER_CMD_STOP }, // Stop is still mandatory }; - err = i2c_master_execute_defined_operations(dev_handle, i2c_ops, 3, self->timeout_us / 1000); - #endif + err = i2c_master_execute_defined_operations(self->dev_handle, i2c_ops, 3, self->timeout_us / 1000); } - #if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) - // Remove the temporary handle. - i2c_master_bus_rm_device(dev_handle); - #endif // Map errors if (err == ESP_FAIL || err == ESP_ERR_INVALID_STATE) { From cd9ac95cd3f99d35058681448ee449c675e256b9 Mon Sep 17 00:00:00 2001 From: Damien George Date: Sat, 30 May 2026 18:56:01 +1000 Subject: [PATCH 320/635] py/stream: Use MP_SEEK_xxx constants instead of SEEK_xxx. The `MP_SEEK_xxx` constants are defined in `py/stream.h` exactly for use by `py/stream.c` so that it doesn't depend on the C library. Signed-off-by: Damien George --- py/stream.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/py/stream.c b/py/stream.c index 19c5cbb2d79..4d71964e7a3 100644 --- a/py/stream.c +++ b/py/stream.c @@ -461,13 +461,13 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_stream___exit___obj, 4, 4, mp_stream___ex static mp_obj_t stream_seek(size_t n_args, const mp_obj_t *args) { // TODO: Could be uint64 mp_off_t offset = mp_obj_get_int(args[1]); - int whence = SEEK_SET; + int whence = MP_SEEK_SET; if (n_args == 3) { whence = mp_obj_get_int(args[2]); } // In POSIX, it's error to seek before end of stream, we enforce it here. - if (whence == SEEK_SET && offset < 0) { + if (whence == MP_SEEK_SET && offset < 0) { mp_raise_OSError(MP_EINVAL); } @@ -484,7 +484,7 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_stream_seek_obj, 2, 3, stream_seek); static mp_obj_t stream_tell(mp_obj_t self) { mp_obj_t offset = MP_OBJ_NEW_SMALL_INT(0); - mp_obj_t whence = MP_OBJ_NEW_SMALL_INT(SEEK_CUR); + mp_obj_t whence = MP_OBJ_NEW_SMALL_INT(MP_SEEK_CUR); const mp_obj_t args[3] = {self, offset, whence}; return stream_seek(3, args); } From 13f6a4978c3a8947470f97b5d25c59a7c1b29e1e Mon Sep 17 00:00:00 2001 From: Damien George Date: Sat, 30 May 2026 18:57:55 +1000 Subject: [PATCH 321/635] extmod: Use MP_SEEK_xxx constants where applicable. Instead of magic numbers + a comment. Signed-off-by: Damien George --- extmod/vfs_fat_file.c | 6 +++--- extmod/vfs_rom_file.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/extmod/vfs_fat_file.c b/extmod/vfs_fat_file.c index 887249b663c..f376a940c24 100644 --- a/extmod/vfs_fat_file.c +++ b/extmod/vfs_fat_file.c @@ -103,15 +103,15 @@ static mp_uint_t file_obj_ioctl(mp_obj_t o_in, mp_uint_t request, uintptr_t arg, struct mp_stream_seek_t *s = (struct mp_stream_seek_t *)(uintptr_t)arg; switch (s->whence) { - case 0: // SEEK_SET + case MP_SEEK_SET: f_lseek(&self->fp, s->offset); break; - case 1: // SEEK_CUR + case MP_SEEK_CUR: f_lseek(&self->fp, f_tell(&self->fp) + s->offset); break; - case 2: // SEEK_END + case MP_SEEK_END: f_lseek(&self->fp, f_size(&self->fp) + s->offset); break; } diff --git a/extmod/vfs_rom_file.c b/extmod/vfs_rom_file.c index 57aca8c5dc7..6d7c47111f5 100644 --- a/extmod/vfs_rom_file.c +++ b/extmod/vfs_rom_file.c @@ -110,11 +110,11 @@ static mp_uint_t vfs_rom_file_ioctl(mp_obj_t o_in, mp_uint_t request, uintptr_t switch (request) { case MP_STREAM_SEEK: { struct mp_stream_seek_t *s = (struct mp_stream_seek_t *)arg; - if (s->whence == 0) { // SEEK_SET + if (s->whence == MP_SEEK_SET) { self->file_offset = (size_t)s->offset; - } else if (s->whence == 1) { // SEEK_CUR + } else if (s->whence == MP_SEEK_CUR) { self->file_offset += s->offset; - } else { // SEEK_END + } else { // MP_SEEK_END self->file_offset = self->file_size + s->offset; } if (self->file_offset > self->file_size) { From 249b46893fa0c5bebf9ca2276f974cf945e21406 Mon Sep 17 00:00:00 2001 From: Damien George Date: Sat, 30 May 2026 18:58:25 +1000 Subject: [PATCH 322/635] ports: Remove SEEK_xxx constants from custom unistd.h files. They are no longer needed. Signed-off-by: Damien George --- ports/pic16bit/unistd.h | 3 --- ports/powerpc/unistd.h | 3 --- 2 files changed, 6 deletions(-) diff --git a/ports/pic16bit/unistd.h b/ports/pic16bit/unistd.h index 23c5e54c753..d218e3bd676 100644 --- a/ports/pic16bit/unistd.h +++ b/ports/pic16bit/unistd.h @@ -3,9 +3,6 @@ // XC16 compiler doesn't seem to have unistd.h file -#define SEEK_SET 0 -#define SEEK_CUR 1 - typedef int ssize_t; #endif // MICROPY_INCLUDED_PIC16BIT_UNISTD_H diff --git a/ports/powerpc/unistd.h b/ports/powerpc/unistd.h index 88e3b27218a..8359e3694d0 100644 --- a/ports/powerpc/unistd.h +++ b/ports/powerpc/unistd.h @@ -28,9 +28,6 @@ // powerpc gcc compiler doesn't seem to have unistd.h file -#define SEEK_SET 0 -#define SEEK_CUR 1 - typedef int ssize_t; #endif // MICROPY_INCLUDED_POWERPC_UNISTD_H From a1beceefac9cd3d80f090e8fbd81f7b84e0d0a40 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 4 Jun 2026 22:54:43 +1000 Subject: [PATCH 323/635] py/runtime: Only build mp_raise_recursion_depth when STACK_CHECK is on. This helper function is used only by the C stack control functions (in `py/cstack.c` and `py/stackctrl.c`) and not by pystack. Similarly the qstr message is only used by this `mp_raise_recursion_depth()` function. (`mp_raise_recursion_depth()` is also used by the VM in strict stacless mode when pystack is disabled, but for that configuration one should anyway be enabling C stack checking.) Signed-off-by: Damien George --- py/qstrdefs.h | 2 ++ py/runtime.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/py/qstrdefs.h b/py/qstrdefs.h index 96d4ece6149..3c20666ab13 100644 --- a/py/qstrdefs.h +++ b/py/qstrdefs.h @@ -53,7 +53,9 @@ Q({:#x}) Q({:#b}) Q( ) Q(\n) +#if MICROPY_STACK_CHECK Q(maximum recursion depth exceeded) +#endif Q() Q() Q() diff --git a/py/runtime.c b/py/runtime.c index 618e9b5ae41..e17ca12393a 100644 --- a/py/runtime.c +++ b/py/runtime.c @@ -1779,7 +1779,7 @@ MP_NORETURN void mp_raise_OSError_with_filename(int errno_, const char *filename nlr_raise(mp_obj_exception_make_new(&mp_type_OSError, 2, 0, args)); } -#if MICROPY_STACK_CHECK || MICROPY_ENABLE_PYSTACK +#if MICROPY_STACK_CHECK MP_NORETURN void mp_raise_recursion_depth(void) { mp_raise_type_arg(&mp_type_RuntimeError, MP_OBJ_NEW_QSTR(MP_QSTR_maximum_space_recursion_space_depth_space_exceeded)); } From 9dd1849455e4d54231ff4ceb4f4fe742aef7bdbf Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 5 Jun 2026 16:46:37 +1000 Subject: [PATCH 324/635] mpy-cross/main: Remove unused mp_verbose_flag. This variable does nothing in mpy-cross because: - `MICROPY_DEBUG_PRINTERS` is not enabled, so the relevant code in `py/compile.c` that uses `mp_verbose_flag` is unused. - Even if `MICROPY_DEBUG_PRINTERS` was enabled, nothing happens because mpy-cross has `MP_PLAT_PRINT_STRN` defined to do nothing. - `MICROPY_PY_MICROPYTHON_MEM_INFO` is not enabled. So remove it. But keep the `-v` CLI option to not break existing uses of mpy-cross, and keep it compatible with the CLI options of the unix port. Signed-off-by: Damien George --- mpy-cross/main.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/mpy-cross/main.c b/mpy-cross/main.c index c5ef86acd6b..a89151a1c7a 100644 --- a/mpy-cross/main.c +++ b/mpy-cross/main.c @@ -49,7 +49,6 @@ static asm_rv32_backend_options_t rv32_options = { 0 }; // Command line options, with their defaults static uint emit_opt = MP_EMIT_OPT_NONE; -mp_uint_t mp_verbose_flag = 0; #if MICROPY_ENABLE_SOURCE_LINE static bool include_source_lines = true; @@ -340,7 +339,7 @@ MP_NOINLINE int main_(int argc, char **argv) { "; mpy-cross emitting mpy v" MP_STRINGIFY(MPY_VERSION) "." MP_STRINGIFY(MPY_SUB_VERSION) "\n"); return 0; } else if (strcmp(argv[a], "-v") == 0) { - mp_verbose_flag++; + // This verbose option doesn't currently do anything. } else if (strncmp(argv[a], "-O", 2) == 0) { if (unichar_isdigit(argv[a][2])) { MP_STATE_VM(mp_optimise_value) = argv[a][2] & 0xf; @@ -482,12 +481,6 @@ MP_NOINLINE int main_(int argc, char **argv) { int ret = compile_and_save(input_file, output_file, source_file); - #if MICROPY_PY_MICROPYTHON_MEM_INFO - if (mp_verbose_flag) { - mp_micropython_mem_info(0, NULL); - } - #endif - mp_deinit(); return ret & 0xff; From 552fd21b283ffe7231ec95e9d3ad8ce2e5524e71 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 5 Jun 2026 16:50:07 +1000 Subject: [PATCH 325/635] py/mpstate: Move mp_verbose_flag to MP_STATE_VM struct. This stray global variable doesn't really belong in `py/emitglue.c` because it's currently only used by `py/compile.c`. So move it to the state context struct alongside the related compiler settings. Signed-off-by: Damien George --- ports/unix/main.c | 6 +++--- py/compile.c | 2 +- py/emitglue.c | 4 ---- py/misc.h | 2 -- py/mpstate.h | 3 +++ py/runtime.c | 3 +++ shared/runtime/pyexec.c | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/ports/unix/main.c b/ports/unix/main.c index 9e9704aa801..8f42d4f56dc 100644 --- a/ports/unix/main.c +++ b/ports/unix/main.c @@ -142,7 +142,7 @@ static int execute_from_lexer(int source_kind, const void *source, mp_parse_inpu #if defined(MICROPY_UNIX_COVERAGE) // allow to print the parse tree in the coverage build - if (mp_verbose_flag >= 3) { + if (MP_STATE_VM(mp_verbose_flag) >= 3) { printf("----------------\n"); mp_parse_node_print(&mp_plat_print, parse_tree.root, 0); printf("----------------\n"); @@ -661,7 +661,7 @@ MP_NOINLINE int main_(int argc, char **argv) { a += 1; #if MICROPY_DEBUG_PRINTERS } else if (strcmp(argv[a], "-v") == 0) { - mp_verbose_flag++; + MP_STATE_VM(mp_verbose_flag)++; #endif } else if (strncmp(argv[a], "-O", 2) == 0) { if (unichar_isdigit(argv[a][2])) { @@ -720,7 +720,7 @@ MP_NOINLINE int main_(int argc, char **argv) { #endif #if MICROPY_PY_MICROPYTHON_MEM_INFO - if (mp_verbose_flag) { + if (MP_STATE_VM(mp_verbose_flag)) { mp_micropython_mem_info(0, NULL); } #endif diff --git a/py/compile.c b/py/compile.c index 37a3e6d32c4..263f4567678 100644 --- a/py/compile.c +++ b/py/compile.c @@ -3654,7 +3654,7 @@ void mp_compile_to_raw_code(mp_parse_tree_t *parse_tree, qstr source_file, bool #if MICROPY_DEBUG_PRINTERS // now that the module context is valid, the raw codes can be printed - if (mp_verbose_flag >= 2) { + if (MP_STATE_VM(mp_verbose_flag) >= 2) { for (scope_t *s = comp->scope_head; s != NULL; s = s->next) { mp_raw_code_t *rc = s->raw_code; if (rc->kind == MP_CODE_BYTECODE) { diff --git a/py/emitglue.c b/py/emitglue.c index 9526acac805..390f5f93a1a 100644 --- a/py/emitglue.c +++ b/py/emitglue.c @@ -48,10 +48,6 @@ #define DEBUG_OP_printf(...) (void)0 #endif -#if MICROPY_DEBUG_PRINTERS -mp_uint_t mp_verbose_flag = 0; -#endif - mp_raw_code_t *mp_emit_glue_new_raw_code(void) { mp_raw_code_t *rc = m_new0(mp_raw_code_t, 1); rc->kind = MP_CODE_RESERVED; diff --git a/py/misc.h b/py/misc.h index 2fe0f11796b..7afa01789bc 100644 --- a/py/misc.h +++ b/py/misc.h @@ -262,8 +262,6 @@ void vstr_vprintf(vstr_t *vstr, const char *fmt, va_list ap); int DEBUG_printf(const char *fmt, ...); -extern mp_uint_t mp_verbose_flag; - /** float internals *************/ #if MICROPY_PY_BUILTINS_FLOAT diff --git a/py/mpstate.h b/py/mpstate.h index 7662813b72a..004593496e2 100644 --- a/py/mpstate.h +++ b/py/mpstate.h @@ -234,6 +234,9 @@ typedef struct _mp_state_vm_t { #if MICROPY_EMIT_NATIVE uint8_t default_emit_opt; // one of MP_EMIT_OPT_xxx #endif + #if MICROPY_DEBUG_PRINTERS + mp_uint_t mp_verbose_flag; + #endif #endif // size of the emergency exception buf, if it's dynamically allocated diff --git a/py/runtime.c b/py/runtime.c index e17ca12393a..173b0a4ac21 100644 --- a/py/runtime.c +++ b/py/runtime.c @@ -105,6 +105,9 @@ void mp_init(void) { #if MICROPY_EMIT_NATIVE MP_STATE_VM(default_emit_opt) = MP_EMIT_OPT_NONE; #endif + #if MICROPY_DEBUG_PRINTERS + MP_STATE_VM(mp_verbose_flag) = 0; + #endif #endif // init global module dict diff --git a/shared/runtime/pyexec.c b/shared/runtime/pyexec.c index b217f301118..112ae8761b4 100644 --- a/shared/runtime/pyexec.c +++ b/shared/runtime/pyexec.c @@ -111,7 +111,7 @@ static int parse_compile_execute(const void *source, mp_parse_input_kind_t input mp_parse_tree_t parse_tree = mp_parse(lex, input_kind); #if defined(MICROPY_UNIX_COVERAGE) // allow to print the parse tree in the coverage build - if (mp_verbose_flag >= 3) { + if (MP_STATE_VM(mp_verbose_flag) >= 3) { printf("----------------\n"); mp_parse_node_print(&mp_plat_print, parse_tree.root, 0); printf("----------------\n"); From b5c6ce36ad59d7709868988aa2e5bc101a572178 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 23 Jun 2026 14:47:33 +1000 Subject: [PATCH 326/635] extmod/machine_wdt: Allow any object as the id for machine.WDT. So ports can support strings if they want to. Signed-off-by: Damien George --- extmod/machine_wdt.c | 6 +++--- ports/cc3200/mods/machine_wdt.c | 4 ++-- ports/esp32/machine_wdt.c | 4 ++-- ports/esp8266/machine_wdt.c | 17 ++++++++--------- ports/mimxrt/machine_wdt.c | 3 ++- ports/rp2/machine_wdt.c | 3 ++- ports/samd/machine_wdt.c | 3 ++- ports/stm32/machine_wdt.c | 3 ++- ports/zephyr/machine_wdt.c | 4 ++-- 9 files changed, 25 insertions(+), 22 deletions(-) diff --git a/extmod/machine_wdt.c b/extmod/machine_wdt.c index fcef1bda250..cd18a819045 100644 --- a/extmod/machine_wdt.c +++ b/extmod/machine_wdt.c @@ -31,7 +31,7 @@ #include "extmod/modmachine.h" // The port must provide implementations of these low-level WDT functions. -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms); +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id, mp_int_t timeout_ms); static void mp_machine_wdt_feed(machine_wdt_obj_t *self); #if MICROPY_PY_MACHINE_WDT_TIMEOUT_MS static void mp_machine_wdt_timeout_ms_set(machine_wdt_obj_t *self_in, mp_int_t timeout_ms); @@ -43,7 +43,7 @@ static void mp_machine_wdt_timeout_ms_set(machine_wdt_obj_t *self_in, mp_int_t t static mp_obj_t machine_wdt_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { enum { ARG_id, ARG_timeout }; static const mp_arg_t allowed_args[] = { - { MP_QSTR_id, MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_id, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_INT(0)} }, { MP_QSTR_timeout, MP_ARG_INT, {.u_int = 5000} }, }; @@ -52,7 +52,7 @@ static mp_obj_t machine_wdt_make_new(const mp_obj_type_t *type, size_t n_args, s mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); // Create WDT instance. - machine_wdt_obj_t *self = mp_machine_wdt_make_new_instance(args[ARG_id].u_int, args[ARG_timeout].u_int); + machine_wdt_obj_t *self = mp_machine_wdt_make_new_instance(args[ARG_id].u_obj, args[ARG_timeout].u_int); return MP_OBJ_FROM_PTR(self); } diff --git a/ports/cc3200/mods/machine_wdt.c b/ports/cc3200/mods/machine_wdt.c index 58ecc1b5334..16a1786c0c5 100644 --- a/ports/cc3200/mods/machine_wdt.c +++ b/ports/cc3200/mods/machine_wdt.c @@ -84,8 +84,8 @@ void pybwdt_sl_alive (void) { /******************************************************************************/ // MicroPython bindings -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms) { - if (id != 0) { +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id, mp_int_t timeout_ms) { + if (id != MP_OBJ_NEW_SMALL_INT(0)) { mp_raise_OSError(MP_ENODEV); } if (timeout_ms < PYBWDT_MIN_TIMEOUT_MS) { diff --git a/ports/esp32/machine_wdt.c b/ports/esp32/machine_wdt.c index 06bdc9d1018..faefdd62648 100644 --- a/ports/esp32/machine_wdt.c +++ b/ports/esp32/machine_wdt.c @@ -39,8 +39,8 @@ static machine_wdt_obj_t wdt_default = { {&machine_wdt_type}, 0 }; -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms) { - if (id != 0) { +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id, mp_int_t timeout_ms) { + if (id != MP_OBJ_NEW_SMALL_INT(0)) { mp_raise_ValueError(NULL); } diff --git a/ports/esp8266/machine_wdt.c b/ports/esp8266/machine_wdt.c index f9399e63ad3..39cd24bac3d 100644 --- a/ports/esp8266/machine_wdt.c +++ b/ports/esp8266/machine_wdt.c @@ -36,20 +36,19 @@ typedef struct _machine_wdt_obj_t { static machine_wdt_obj_t wdt_default = {{&machine_wdt_type}}; -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms) { +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id, mp_int_t timeout_ms) { + if (id != MP_OBJ_NEW_SMALL_INT(0)) { + mp_raise_ValueError(NULL); + } + // The timeout on ESP8266 is fixed, so raise an exception if the argument is not the default. if (timeout_ms != 5000) { mp_raise_ValueError(NULL); } - switch (id) { - case 0: - ets_loop_dont_feed_sw_wdt = 1; - system_soft_wdt_feed(); - return &wdt_default; - default: - mp_raise_ValueError(NULL); - } + ets_loop_dont_feed_sw_wdt = 1; + system_soft_wdt_feed(); + return &wdt_default; } static void mp_machine_wdt_feed(machine_wdt_obj_t *self) { diff --git a/ports/mimxrt/machine_wdt.c b/ports/mimxrt/machine_wdt.c index 24945efbfba..b96cca7a35b 100644 --- a/ports/mimxrt/machine_wdt.c +++ b/ports/mimxrt/machine_wdt.c @@ -38,8 +38,9 @@ typedef struct _machine_wdt_obj_t { static const machine_wdt_obj_t machine_wdt = {{&machine_wdt_type}}; -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms) { +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_int_t timeout_ms) { // Verify the WDT id. + mp_int_t id = mp_obj_get_int(id_obj); if (id != 0) { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%d) doesn't exist"), id); } diff --git a/ports/rp2/machine_wdt.c b/ports/rp2/machine_wdt.c index 9cc955810c6..b6cf3f9a22d 100644 --- a/ports/rp2/machine_wdt.c +++ b/ports/rp2/machine_wdt.c @@ -38,8 +38,9 @@ typedef struct _machine_wdt_obj_t { static const machine_wdt_obj_t machine_wdt = {{&machine_wdt_type}}; -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms) { +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_int_t timeout_ms) { // Verify the WDT id. + mp_int_t id = mp_obj_get_int(id_obj); if (id != 0) { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%d) doesn't exist"), id); } diff --git a/ports/samd/machine_wdt.c b/ports/samd/machine_wdt.c index 301abbe90c7..625a52ec9ac 100644 --- a/ports/samd/machine_wdt.c +++ b/ports/samd/machine_wdt.c @@ -76,9 +76,10 @@ static void set_timeout(uint32_t timeout) { #endif } -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms) { +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_int_t timeout_ms) { #if defined(MCU_SAMD51) // Verify the WDT id. SAMD51 only, saving a few bytes for SAMD21 + mp_int_t id = mp_obj_get_int(id_obj); if (id != 0) { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%d) doesn't exist"), id); } diff --git a/ports/stm32/machine_wdt.c b/ports/stm32/machine_wdt.c index 4789b85a609..20bd3c503d7 100644 --- a/ports/stm32/machine_wdt.c +++ b/ports/stm32/machine_wdt.c @@ -39,7 +39,8 @@ typedef struct _machine_wdt_obj_t { static const machine_wdt_obj_t machine_wdt = {{&machine_wdt_type}}; -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms) { +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_int_t timeout_ms) { + mp_int_t id = mp_obj_get_int(id_obj); if (id != 0) { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%d) doesn't exist"), id); } diff --git a/ports/zephyr/machine_wdt.c b/ports/zephyr/machine_wdt.c index 7c5e6337ca3..bd36b1988a9 100644 --- a/ports/zephyr/machine_wdt.c +++ b/ports/zephyr/machine_wdt.c @@ -45,8 +45,8 @@ static machine_wdt_obj_t wdt_default = { {&machine_wdt_type}, NULL, -1 }; -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_int_t id, mp_int_t timeout_ms) { - if (id != 0) { +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id, mp_int_t timeout_ms) { + if (id != MP_OBJ_NEW_SMALL_INT(0)) { mp_raise_ValueError(MP_ERROR_TEXT("invalid WDT id")); } From ad64bb17f9f98507536605d61d9f5c5230ea7f9a Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 23 Jun 2026 15:09:53 +1000 Subject: [PATCH 327/635] stm32/machine_wdt: Support strings to reference WDT instance. On the stm32 port, `machine.WDT()` now accepts `id=0` and `id="IWDG"` to access the independent watchdog. Signed-off-by: Damien George --- ports/stm32/machine_wdt.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/ports/stm32/machine_wdt.c b/ports/stm32/machine_wdt.c index 20bd3c503d7..98c0505cd89 100644 --- a/ports/stm32/machine_wdt.c +++ b/ports/stm32/machine_wdt.c @@ -39,12 +39,7 @@ typedef struct _machine_wdt_obj_t { static const machine_wdt_obj_t machine_wdt = {{&machine_wdt_type}}; -static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_int_t timeout_ms) { - mp_int_t id = mp_obj_get_int(id_obj); - if (id != 0) { - mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%d) doesn't exist"), id); - } - +static machine_wdt_obj_t *make_iwdt(mp_int_t timeout_ms) { // compute prescaler int32_t timeout = timeout_ms; uint32_t prescaler; @@ -78,6 +73,24 @@ static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_i return (machine_wdt_obj_t *)&machine_wdt; } +static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_int_t timeout_ms) { + if (mp_obj_is_str(id_obj)) { + qstr qst = mp_obj_str_get_qstr(id_obj); + if (qst == MP_QSTR_IWDG) { + return make_iwdt(timeout_ms); + } else { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%q) doesn't exist"), qst); + } + } else { + mp_int_t id = mp_obj_get_int(id_obj); + if (id == 0) { + return make_iwdt(timeout_ms); + } else { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%d) doesn't exist"), id); + } + } +} + static void mp_machine_wdt_feed(machine_wdt_obj_t *self) { (void)self; IWDG->KR = 0xaaaa; From cc0e275647afa57a7415150ac306810038e0ff89 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 17 Jun 2026 13:19:23 +1000 Subject: [PATCH 328/635] stm32/machine_wdt: Implement WWDG watchdog peripheral. This adds support for the STM32 WWDG peripheral, through the standard `machine.WDT()` class interface. It's accessed as peripheral id "WWDG". The maximum timeout is quite limited on this watchdog due to the limited prescale values, for example: - STM32F4 at 168MHz: 49ms max timeout (at 96MHz it's 87ms max) - STM32F7 at 216MHz: 38ms max timeout - STM32N6 at 800MHz: 167ms max timeout - STM32WB at 64MHz: 524ms max timeout Signed-off-by: Damien George --- ports/stm32/boards/stm32f0xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32f4xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32f7xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32g0xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32g4xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32h5xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32h7xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32l0xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32l1xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32l4xx_hal_conf_base.h | 1 + ports/stm32/boards/stm32u5xx_hal_conf_base.h | 1 + ports/stm32/machine_wdt.c | 74 ++++++++++++++++++-- 12 files changed, 80 insertions(+), 5 deletions(-) diff --git a/ports/stm32/boards/stm32f0xx_hal_conf_base.h b/ports/stm32/boards/stm32f0xx_hal_conf_base.h index d60fb9eaf7d..2097fcda523 100644 --- a/ports/stm32/boards/stm32f0xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32f0xx_hal_conf_base.h @@ -84,6 +84,7 @@ #include "stm32f0xx_hal_usart.h" #include "stm32f0xx_hal_wwdg.h" #include "stm32f0xx_ll_adc.h" +#include "stm32f0xx_ll_bus.h" #include "stm32f0xx_ll_rtc.h" #include "stm32f0xx_ll_usart.h" diff --git a/ports/stm32/boards/stm32f4xx_hal_conf_base.h b/ports/stm32/boards/stm32f4xx_hal_conf_base.h index 59d73a3028c..241b07a1808 100644 --- a/ports/stm32/boards/stm32f4xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32f4xx_hal_conf_base.h @@ -97,6 +97,7 @@ #include "stm32f4xx_hal_usart.h" #include "stm32f4xx_hal_wwdg.h" #include "stm32f4xx_ll_adc.h" +#include "stm32f4xx_ll_bus.h" #include "stm32f4xx_ll_pwr.h" #include "stm32f4xx_ll_rtc.h" #include "stm32f4xx_ll_usart.h" diff --git a/ports/stm32/boards/stm32f7xx_hal_conf_base.h b/ports/stm32/boards/stm32f7xx_hal_conf_base.h index 26908f2ebb3..a1558703b43 100644 --- a/ports/stm32/boards/stm32f7xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32f7xx_hal_conf_base.h @@ -93,6 +93,7 @@ #include "stm32f7xx_hal_usart.h" #include "stm32f7xx_hal_wwdg.h" #include "stm32f7xx_ll_adc.h" +#include "stm32f7xx_ll_bus.h" #include "stm32f7xx_ll_pwr.h" #include "stm32f7xx_ll_rtc.h" #include "stm32f7xx_ll_usart.h" diff --git a/ports/stm32/boards/stm32g0xx_hal_conf_base.h b/ports/stm32/boards/stm32g0xx_hal_conf_base.h index 5ddcb0fa434..4abeeae636b 100644 --- a/ports/stm32/boards/stm32g0xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32g0xx_hal_conf_base.h @@ -94,6 +94,7 @@ #include "stm32g0xx_hal_uart.h" #include "stm32g0xx_hal_usart.h" #include "stm32g0xx_hal_wwdg.h" +#include "stm32g0xx_ll_bus.h" #include "stm32g0xx_ll_lpuart.h" #include "stm32g0xx_ll_rtc.h" #include "stm32g0xx_ll_usart.h" diff --git a/ports/stm32/boards/stm32g4xx_hal_conf_base.h b/ports/stm32/boards/stm32g4xx_hal_conf_base.h index e6f24c21a49..71834c7f5da 100644 --- a/ports/stm32/boards/stm32g4xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32g4xx_hal_conf_base.h @@ -119,6 +119,7 @@ #include "stm32g4xx_hal_usart.h" #include "stm32g4xx_hal_wwdg.h" #include "stm32g4xx_ll_adc.h" +#include "stm32g4xx_ll_bus.h" #include "stm32g4xx_ll_rtc.h" #include "stm32g4xx_ll_usart.h" #include "stm32g4xx_ll_lpuart.h" diff --git a/ports/stm32/boards/stm32h5xx_hal_conf_base.h b/ports/stm32/boards/stm32h5xx_hal_conf_base.h index c40fc708559..2e3877b85ee 100644 --- a/ports/stm32/boards/stm32h5xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32h5xx_hal_conf_base.h @@ -96,6 +96,7 @@ #include "stm32h5xx_hal_usart.h" #include "stm32h5xx_hal_wwdg.h" #include "stm32h5xx_ll_adc.h" +#include "stm32h5xx_ll_bus.h" #include "stm32h5xx_ll_lpuart.h" #include "stm32h5xx_ll_pwr.h" #include "stm32h5xx_ll_rcc.h" diff --git a/ports/stm32/boards/stm32h7xx_hal_conf_base.h b/ports/stm32/boards/stm32h7xx_hal_conf_base.h index 1953ba020b8..cfad516de1e 100644 --- a/ports/stm32/boards/stm32h7xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32h7xx_hal_conf_base.h @@ -94,6 +94,7 @@ #include "stm32h7xx_hal_usart.h" #include "stm32h7xx_hal_wwdg.h" #include "stm32h7xx_ll_adc.h" +#include "stm32h7xx_ll_bus.h" #include "stm32h7xx_ll_lpuart.h" #include "stm32h7xx_ll_pwr.h" #include "stm32h7xx_ll_rcc.h" diff --git a/ports/stm32/boards/stm32l0xx_hal_conf_base.h b/ports/stm32/boards/stm32l0xx_hal_conf_base.h index e33c0b2a1be..28774ef5013 100644 --- a/ports/stm32/boards/stm32l0xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32l0xx_hal_conf_base.h @@ -85,6 +85,7 @@ #include "stm32l0xx_hal_usart.h" #include "stm32l0xx_hal_wwdg.h" #include "stm32l0xx_ll_adc.h" +#include "stm32l0xx_ll_bus.h" #include "stm32l0xx_ll_lpuart.h" #include "stm32l0xx_ll_rtc.h" #include "stm32l0xx_ll_usart.h" diff --git a/ports/stm32/boards/stm32l1xx_hal_conf_base.h b/ports/stm32/boards/stm32l1xx_hal_conf_base.h index d23453b27a6..a75b01e32f9 100644 --- a/ports/stm32/boards/stm32l1xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32l1xx_hal_conf_base.h @@ -91,6 +91,7 @@ #include "stm32l1xx_hal_wwdg.h" #include "stm32l1xx_hal_exti.h" #include "stm32l1xx_ll_adc.h" +#include "stm32l1xx_ll_bus.h" #include "stm32l1xx_ll_pwr.h" #include "stm32l1xx_ll_rtc.h" #include "stm32l1xx_ll_usart.h" diff --git a/ports/stm32/boards/stm32l4xx_hal_conf_base.h b/ports/stm32/boards/stm32l4xx_hal_conf_base.h index 9ee895229f9..437d55fb654 100644 --- a/ports/stm32/boards/stm32l4xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32l4xx_hal_conf_base.h @@ -93,6 +93,7 @@ #include "stm32l4xx_hal_usart.h" #include "stm32l4xx_hal_wwdg.h" #include "stm32l4xx_ll_adc.h" +#include "stm32l4xx_ll_bus.h" #include "stm32l4xx_ll_lpuart.h" #include "stm32l4xx_ll_rtc.h" #include "stm32l4xx_ll_usart.h" diff --git a/ports/stm32/boards/stm32u5xx_hal_conf_base.h b/ports/stm32/boards/stm32u5xx_hal_conf_base.h index be7ea524639..a22ed8d32b5 100644 --- a/ports/stm32/boards/stm32u5xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32u5xx_hal_conf_base.h @@ -163,6 +163,7 @@ #include "stm32u5xx_hal_ramcfg.h" #include "stm32u5xx_hal_mdf.h" #include "stm32u5xx_hal_xspi.h" +#include "stm32u5xx_ll_bus.h" #include "stm32u5xx_ll_usart.h" #include "stm32u5xx_ll_lpuart.h" #include "stm32u5xx_ll_rtc.h" diff --git a/ports/stm32/machine_wdt.c b/ports/stm32/machine_wdt.c index 98c0505cd89..7b497b0ab22 100644 --- a/ports/stm32/machine_wdt.c +++ b/ports/stm32/machine_wdt.c @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2016-2023 Damien P. George + * Copyright (c) 2016-2026 Damien P. George * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,13 +31,76 @@ #if defined(STM32H7) #define IWDG (IWDG1) +#define WWDG (WWDG1) #endif +#if defined(WWDG_CFR_WDGTB_2) +#define WWDG_PRESCALER_MAX (7U) +#else +#define WWDG_PRESCALER_MAX (3U) +#endif +#define WWDG_COUNTER_MAX (64U) + typedef struct _machine_wdt_obj_t { mp_obj_base_t base; + __IO uint32_t *feed_register; + uint32_t feed_value; } machine_wdt_obj_t; -static const machine_wdt_obj_t machine_wdt = {{&machine_wdt_type}}; +static const machine_wdt_obj_t machine_iwdt = {{&machine_wdt_type}, &IWDG->KR, 0xaaaa}; +static machine_wdt_obj_t machine_wwdt = {{&machine_wdt_type}, &WWDG->CR, 0}; + +#if defined(STM32H7) +// This is not provided by the HAL, so define it here. +static uint32_t HAL_RCC_GetPCLK3Freq(void) { + return LL_RCC_CALC_PCLK3_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB3Prescaler()); +} +#endif + +static machine_wdt_obj_t *make_wwdt(mp_int_t timeout_ms) { + // WWDG is clocked from PCLKx divided by 4096. + uint32_t pclk; + #if defined(STM32H7) + pclk = HAL_RCC_GetPCLK3Freq(); + #else + pclk = HAL_RCC_GetPCLK1Freq(); + #endif + + // Compute the number of ticks corresponding to the requested millisecond timeout. + uint64_t timeout_ticks = (uint64_t)timeout_ms * (uint64_t)(pclk / 1000U) / 4096ULL; + + // Increase the prescaler to try and get timeout_ticks below its maximum value. + uint32_t prescaler = 0; + while (prescaler < WWDG_PRESCALER_MAX && timeout_ticks > WWDG_COUNTER_MAX) { + ++prescaler; + timeout_ticks = (timeout_ticks + 1) / 2; + } + + // Check that the timeout is within range of the peripheral limits. + if (timeout_ticks <= 0) { + mp_raise_ValueError(MP_ERROR_TEXT("WDT timeout too short")); + } else if (timeout_ticks > WWDG_COUNTER_MAX) { + unsigned int max_timeout_ms = WWDG_COUNTER_MAX * 4096U * (1U << WWDG_PRESCALER_MAX) / (HAL_RCC_GetPCLK1Freq() / 1000U); + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT timeout too long, max %ums"), max_timeout_ms); + } + + // Compute the value that will feed the WWDG. + machine_wwdt.feed_value = WWDG_CR_WDGA | (0x3f + timeout_ticks) << WWDG_CR_T_Pos; + + // Initialise and start the WWDG. + #if defined(STM32H7) + LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_WWDG1); + #if defined(RCC_GCR_WW1RSC) + LL_RCC_WWDG1_EnableSystemReset(); + #endif + #else + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG); + #endif + WWDG->CFR = prescaler << WWDG_CFR_WDGTB_Pos | 0x7f << WWDG_CFR_W_Pos; + WWDG->CR = machine_wwdt.feed_value; + + return &machine_wwdt; +} static machine_wdt_obj_t *make_iwdt(mp_int_t timeout_ms) { // compute prescaler @@ -70,7 +133,7 @@ static machine_wdt_obj_t *make_iwdt(mp_int_t timeout_ms) { // start the watch dog IWDG->KR = 0xcccc; - return (machine_wdt_obj_t *)&machine_wdt; + return (machine_wdt_obj_t *)&machine_iwdt; } static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_int_t timeout_ms) { @@ -78,6 +141,8 @@ static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_i qstr qst = mp_obj_str_get_qstr(id_obj); if (qst == MP_QSTR_IWDG) { return make_iwdt(timeout_ms); + } else if (qst == MP_QSTR_WWDG) { + return make_wwdt(timeout_ms); } else { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%q) doesn't exist"), qst); } @@ -92,6 +157,5 @@ static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_i } static void mp_machine_wdt_feed(machine_wdt_obj_t *self) { - (void)self; - IWDG->KR = 0xaaaa; + *self->feed_register = self->feed_value; } From fa1ec09126ed75aa4ab2d19281a9036b0106e3eb Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 23 Jun 2026 15:32:40 +1000 Subject: [PATCH 329/635] stm32/machine_wdt: Support up to 4 watchdogs on H7. Dual-core H7 MCUs have 2x IWDG and 2x WWDG peripherals, and this commit adds support for them all. Signed-off-by: Damien George --- ports/stm32/machine_wdt.c | 79 ++++++++++++++++++++++++++++----------- 1 file changed, 57 insertions(+), 22 deletions(-) diff --git a/ports/stm32/machine_wdt.c b/ports/stm32/machine_wdt.c index 7b497b0ab22..017873f13eb 100644 --- a/ports/stm32/machine_wdt.c +++ b/ports/stm32/machine_wdt.c @@ -32,6 +32,13 @@ #if defined(STM32H7) #define IWDG (IWDG1) #define WWDG (WWDG1) +#if defined(DUAL_CORE) +#define DUAL_WDG (1) +#endif +#endif + +#ifndef DUAL_WDG +#define DUAL_WDG (0) #endif #if defined(WWDG_CFR_WDGTB_2) @@ -50,6 +57,11 @@ typedef struct _machine_wdt_obj_t { static const machine_wdt_obj_t machine_iwdt = {{&machine_wdt_type}, &IWDG->KR, 0xaaaa}; static machine_wdt_obj_t machine_wwdt = {{&machine_wdt_type}, &WWDG->CR, 0}; +#if DUAL_WDG +static const machine_wdt_obj_t machine_iwdt2 = {{&machine_wdt_type}, &IWDG2->KR, 0xaaaa}; +static machine_wdt_obj_t machine_wwdt2 = {{&machine_wdt_type}, &WWDG2->CR, 0}; +#endif + #if defined(STM32H7) // This is not provided by the HAL, so define it here. static uint32_t HAL_RCC_GetPCLK3Freq(void) { @@ -57,11 +69,18 @@ static uint32_t HAL_RCC_GetPCLK3Freq(void) { } #endif -static machine_wdt_obj_t *make_wwdt(mp_int_t timeout_ms) { +static machine_wdt_obj_t *make_wwdt(machine_wdt_obj_t *self, WWDG_TypeDef *wwdg, mp_int_t timeout_ms) { // WWDG is clocked from PCLKx divided by 4096. uint32_t pclk; #if defined(STM32H7) - pclk = HAL_RCC_GetPCLK3Freq(); + #if DUAL_WDG + if (wwdg == WWDG2) { + pclk = HAL_RCC_GetPCLK1Freq(); + } else + #endif + { + pclk = HAL_RCC_GetPCLK3Freq(); + } #else pclk = HAL_RCC_GetPCLK1Freq(); #endif @@ -85,24 +104,34 @@ static machine_wdt_obj_t *make_wwdt(mp_int_t timeout_ms) { } // Compute the value that will feed the WWDG. - machine_wwdt.feed_value = WWDG_CR_WDGA | (0x3f + timeout_ticks) << WWDG_CR_T_Pos; + self->feed_value = WWDG_CR_WDGA | (0x3f + timeout_ticks) << WWDG_CR_T_Pos; - // Initialise and start the WWDG. + // Enable WWDG clock. #if defined(STM32H7) - LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_WWDG1); - #if defined(RCC_GCR_WW1RSC) - LL_RCC_WWDG1_EnableSystemReset(); + #if DUAL_WDG + if (wwdg == WWDG2) { + LL_APB3_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG2); + LL_RCC_WWDG2_EnableSystemReset(); + } else #endif + { + LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_WWDG1); + #if defined(RCC_GCR_WW1RSC) + LL_RCC_WWDG1_EnableSystemReset(); + #endif + } #else LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG); #endif - WWDG->CFR = prescaler << WWDG_CFR_WDGTB_Pos | 0x7f << WWDG_CFR_W_Pos; - WWDG->CR = machine_wwdt.feed_value; - return &machine_wwdt; + // Initialise and start the WWDG. + wwdg->CFR = prescaler << WWDG_CFR_WDGTB_Pos | 0x7f << WWDG_CFR_W_Pos; + wwdg->CR = self->feed_value; + + return self; } -static machine_wdt_obj_t *make_iwdt(mp_int_t timeout_ms) { +static machine_wdt_obj_t *make_iwdt(const machine_wdt_obj_t *self, IWDG_TypeDef *iwdg, mp_int_t timeout_ms) { // compute prescaler int32_t timeout = timeout_ms; uint32_t prescaler; @@ -119,37 +148,43 @@ static machine_wdt_obj_t *make_iwdt(mp_int_t timeout_ms) { timeout -= 1; // set the reload register - while (IWDG->SR & 2) { + while (iwdg->SR & 2) { } - IWDG->KR = 0x5555; - IWDG->RLR = timeout; + iwdg->KR = 0x5555; + iwdg->RLR = timeout; // set the prescaler - while (IWDG->SR & 1) { + while (iwdg->SR & 1) { } - IWDG->KR = 0x5555; - IWDG->PR = prescaler; + iwdg->KR = 0x5555; + iwdg->PR = prescaler; // start the watch dog - IWDG->KR = 0xcccc; + iwdg->KR = 0xcccc; - return (machine_wdt_obj_t *)&machine_iwdt; + return (machine_wdt_obj_t *)self; } static machine_wdt_obj_t *mp_machine_wdt_make_new_instance(mp_obj_t id_obj, mp_int_t timeout_ms) { if (mp_obj_is_str(id_obj)) { qstr qst = mp_obj_str_get_qstr(id_obj); if (qst == MP_QSTR_IWDG) { - return make_iwdt(timeout_ms); + return make_iwdt(&machine_iwdt, IWDG, timeout_ms); } else if (qst == MP_QSTR_WWDG) { - return make_wwdt(timeout_ms); + return make_wwdt(&machine_wwdt, WWDG, timeout_ms); + #if DUAL_WDG + } else if (qst == MP_QSTR_IWDG2) { + return make_iwdt(&machine_iwdt2, IWDG2, timeout_ms); + } else if (qst == MP_QSTR_WWDG2) { + return make_wwdt(&machine_wwdt2, WWDG2, timeout_ms); + #endif } else { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%q) doesn't exist"), qst); } } else { mp_int_t id = mp_obj_get_int(id_obj); if (id == 0) { - return make_iwdt(timeout_ms); + return make_iwdt(&machine_iwdt, IWDG, timeout_ms); } else { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("WDT(%d) doesn't exist"), id); } From daf9858bb4e5458b2b0cadc9a97d36b4e81a141e Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 17 Jun 2026 13:31:02 +1000 Subject: [PATCH 330/635] docs/library/machine.WDT: Mention stm32 WWDG in WDT docs. Signed-off-by: Damien George --- docs/library/machine.WDT.rst | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/docs/library/machine.WDT.rst b/docs/library/machine.WDT.rst index cf77df96320..8ab249678fb 100644 --- a/docs/library/machine.WDT.rst +++ b/docs/library/machine.WDT.rst @@ -25,8 +25,18 @@ Constructors Create a WDT object and start it. The timeout must be given in milliseconds. Once it is running the timeout cannot be changed and the WDT cannot be stopped either. - Notes: On the esp8266 a timeout cannot be specified, it is determined by the underlying system. - On rp2040 devices, the maximum timeout is 8388 ms. + Notes: + + - On the esp8266 port a timeout cannot be specified, it is determined by the underlying + system. + + - On rp2040 devices the maximum timeout is 8388 ms. + + - On the stm32 port the default ``id=0`` is the IWDG, which can also be specified by + an id of ``"IWDG"``. Use an id of ``"WWDG"`` to access the WWDG peripheral. + For dual-core STM32H7 MCUs there are also ``"IWDG2"`` and ``"WWDG2"``. + The WWDG has a very limited maximum timeout across all MCUs, of around 100ms (but + it depends heavily on the APB clock). Methods ------- From fdb1b7e03fc2b2a8f112f66a9a0e724181c3029f Mon Sep 17 00:00:00 2001 From: Howard Lovatt Date: Wed, 24 Jun 2026 11:44:46 +1000 Subject: [PATCH 331/635] docs/library/machine.Signal: Document __call__ method. Add documentation for callable Signal objects and their usage. Signed-off-by: Howard Lovatt --- docs/library/machine.Signal.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/library/machine.Signal.rst b/docs/library/machine.Signal.rst index 1e1fcb5483a..46f487b0d29 100644 --- a/docs/library/machine.Signal.rst +++ b/docs/library/machine.Signal.rst @@ -114,6 +114,12 @@ Methods to logical 0. For inverted/active-low signal, active status corresponds to logical 0, while inactive - to logical 1. +.. method:: Signal.__call__([x]) + + Signal objects are callable. The call method provides a (fast) shortcut to set + and get the value of the pin. It is equivalent to Signal.value([x]). + See :meth:`Signal.value` for more details. + .. method:: Signal.on() Activate signal. From d9544b1860bd167d23d3e1a2d9a507aa4eded9a5 Mon Sep 17 00:00:00 2001 From: Matt Trentini Date: Wed, 24 Jun 2026 12:17:43 +1000 Subject: [PATCH 332/635] docs/library/machine.CAN: Add port availability note. Signed-off-by: Matt Trentini --- docs/library/machine.CAN.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/library/machine.CAN.rst b/docs/library/machine.CAN.rst index 0da26b90167..1cf37330f05 100644 --- a/docs/library/machine.CAN.rst +++ b/docs/library/machine.CAN.rst @@ -24,6 +24,8 @@ errors. .. note:: The planned ``can`` and ``aiocan`` micropython-lib modules will be the recommended way to use CAN with MicroPython. +Availability: **STM32, MIMXRT** + Constructor ----------- From bd5ecab0762aa269b8b842af3b9be2193ad49350 Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Wed, 24 Jun 2026 22:56:17 +0200 Subject: [PATCH 333/635] esp32/machine_uart: Make default UART pins board-configurable. Previously the default TX/RX pins for each UART were hard-coded in a switch statement, so a board could not change them. This is inconsistent with machine.SPI and machine.I2C, which already take board-level defaults via MICROPY_HW_SPIn_* and MICROPY_HW_I2Cn_*, and with the rp2 and stm32 ports, which already use MICROPY_HW_UARTn_TX/RX. Move the default pins into machine_uart.h as MICROPY_HW_UARTn_TX/RX (and MICROPY_HW_LP_UART0_TX/RX) defines that a board can override in its mpconfigboard.h, and replace the switch with a table indexed by the UART number. The existing default pin values are unchanged, so behaviour is the same for all current boards. In addition: - UART3 and UART4 (e.g. on the ESP32-P4) now get default pins instead of being left uninitialised, and can be assigned from a board. - The LP UART default pins are taken from the IDF (LP_U0TXD_GPIO_NUM / LP_U0RXD_GPIO_NUM), which is correct on all chips (for example 14/15 on the ESP32-P4 rather than 5/4). Signed-off-by: Pavel Revak --- ports/esp32/machine_uart.c | 71 +++++++++++++---------------- ports/esp32/machine_uart.h | 91 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+), 40 deletions(-) create mode 100644 ports/esp32/machine_uart.h diff --git a/ports/esp32/machine_uart.c b/ports/esp32/machine_uart.c index 5b9cd02c4a4..1bcdae4e8a0 100644 --- a/ports/esp32/machine_uart.c +++ b/ports/esp32/machine_uart.c @@ -39,6 +39,7 @@ #include "py/mperrno.h" #include "py/mphal.h" #include "uart.h" +#include "machine_uart.h" #include "machine_timer.h" #if SOC_UART_SUPPORT_XTAL_CLK @@ -61,6 +62,30 @@ #define RXIDLE_TIMER_MIN (machine_timer_freq_hz() * 5 / 10000) // 500us minimum rxidle time #define UART_QUEUE_SIZE (3) +typedef struct _machine_uart_default_pins_t { + gpio_num_t tx; + gpio_num_t rx; +} machine_uart_default_pins_t; + +// Indexed by uart_port_t. The LP UART (if present) follows the HP UARTs in +// the enum, so a single table indexed by UART_NUM_MAX covers all of them. +static const machine_uart_default_pins_t machine_uart_default_pins[UART_NUM_MAX] = { + [UART_NUM_0] = { MICROPY_HW_UART0_TX, MICROPY_HW_UART0_RX }, + [UART_NUM_1] = { MICROPY_HW_UART1_TX, MICROPY_HW_UART1_RX }, + #if SOC_UART_HP_NUM > 2 + [UART_NUM_2] = { MICROPY_HW_UART2_TX, MICROPY_HW_UART2_RX }, + #endif + #if SOC_UART_HP_NUM > 3 + [UART_NUM_3] = { MICROPY_HW_UART3_TX, MICROPY_HW_UART3_RX }, + #endif + #if SOC_UART_HP_NUM > 4 + [UART_NUM_4] = { MICROPY_HW_UART4_TX, MICROPY_HW_UART4_RX }, + #endif + #if SOC_UART_LP_NUM >= 1 + [LP_UART_NUM_0] = { MICROPY_HW_LP_UART0_TX, MICROPY_HW_LP_UART0_RX }, + #endif +}; + enum { RXIDLE_INACTIVE, RXIDLE_STANDBY, @@ -270,46 +295,12 @@ static void mp_machine_uart_init_helper(machine_uart_obj_t *self, size_t n_args, self->uart_queue = NULL; self->rxidle_state = RXIDLE_INACTIVE; - // Set the MicroPython default UART pins. These may be overwritten with - // caller-provided pins, below - switch (self->uart_num) { - case UART_NUM_0: - self->rx = UART_PIN_NO_CHANGE; // GPIO 3 - self->tx = UART_PIN_NO_CHANGE; // GPIO 1 - break; - case UART_NUM_1: - #if CONFIG_IDF_TARGET_ESP32 && CONFIG_SPIRAM - // ESP32 usually uses pins 9 and 10 for SPIRAM bus, so avoid those pins as defaults. - self->rx = 4; - self->tx = 5; - #else - self->rx = 9; - self->tx = 10; - #endif - break; - #if SOC_UART_HP_NUM > 2 - case UART_NUM_2: - self->rx = 16; - self->tx = 17; - break; - #endif - #if SOC_UART_LP_NUM >= 1 - case LP_UART_NUM_0: - self->rx = 4; - self->tx = 5; - break; - #endif - #if SOC_UART_HP_NUM > 3 - case UART_NUM_3: - break; - #endif - #if SOC_UART_HP_NUM > 4 - case UART_NUM_4: - break; - #endif - case UART_NUM_MAX: - assert(0); // Range is checked in mp_machine_uart_make_new, value should be unreachable - } + // Set the MicroPython default UART pins, overridable per board via + // MICROPY_HW_UARTn_TX/RX. These may be overwritten with caller-provided + // pins, below. The valid range of uart_num is checked in + // mp_machine_uart_make_new. + self->tx = machine_uart_default_pins[self->uart_num].tx; + self->rx = machine_uart_default_pins[self->uart_num].rx; } else { // wait for all data to be transmitted before changing settings uart_wait_tx_done(self->uart_num, pdMS_TO_TICKS(1000)); diff --git a/ports/esp32/machine_uart.h b/ports/esp32/machine_uart.h new file mode 100644 index 00000000000..d2196d68f97 --- /dev/null +++ b/ports/esp32/machine_uart.h @@ -0,0 +1,91 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016-2025 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_ESP32_MACHINE_UART_H +#define MICROPY_INCLUDED_ESP32_MACHINE_UART_H + +#include "driver/uart.h" +#include "soc/uart_pins.h" + +// Default UART pins. A board may override any of these in its mpconfigboard.h +// to match the pins it actually breaks out, consistent with the existing +// MICROPY_HW_SPIn_* and MICROPY_HW_I2Cn_* board defaults. Pins left at +// UART_PIN_NO_CHANGE keep the IDF/hardware default routing. + +// UART0 is normally the REPL/console. Keep the hardware default pins, which is +// what the IDF assigns per chip (U0TXD_GPIO_NUM / U0RXD_GPIO_NUM). +#ifndef MICROPY_HW_UART0_TX +#define MICROPY_HW_UART0_TX (UART_PIN_NO_CHANGE) +#define MICROPY_HW_UART0_RX (UART_PIN_NO_CHANGE) +#endif + +// UART1 historical MicroPython default pins. +#ifndef MICROPY_HW_UART1_TX +#if CONFIG_IDF_TARGET_ESP32 && CONFIG_SPIRAM +// On ESP32 pins 9 and 10 are normally used by the SPIRAM bus, so when SPIRAM is +// enabled fall back to pins that do not collide with it. +#define MICROPY_HW_UART1_TX (5) +#define MICROPY_HW_UART1_RX (4) +#else +#define MICROPY_HW_UART1_TX (10) +#define MICROPY_HW_UART1_RX (9) +#endif +#endif + +#if SOC_UART_HP_NUM > 2 +// UART2 historical MicroPython default pins. +#ifndef MICROPY_HW_UART2_TX +#define MICROPY_HW_UART2_TX (17) +#define MICROPY_HW_UART2_RX (16) +#endif +#endif + +#if SOC_UART_HP_NUM > 3 +// UART3 (e.g. ESP32-P4) has no historical or IOMUX default pins; leave it at +// UART_PIN_NO_CHANGE so a board can assign it via MICROPY_HW_UART3_TX/RX. +#ifndef MICROPY_HW_UART3_TX +#define MICROPY_HW_UART3_TX (UART_PIN_NO_CHANGE) +#define MICROPY_HW_UART3_RX (UART_PIN_NO_CHANGE) +#endif +#endif + +#if SOC_UART_HP_NUM > 4 +#ifndef MICROPY_HW_UART4_TX +#define MICROPY_HW_UART4_TX (UART_PIN_NO_CHANGE) +#define MICROPY_HW_UART4_RX (UART_PIN_NO_CHANGE) +#endif +#endif + +#if SOC_UART_LP_NUM >= 1 +// LP UART: use the IDF per-chip IOMUX pins, which are correct on all chips +// (e.g. 5/4 on C5/C6 but 14/15 on P4). +#ifndef MICROPY_HW_LP_UART0_TX +#define MICROPY_HW_LP_UART0_TX (LP_U0TXD_GPIO_NUM) +#define MICROPY_HW_LP_UART0_RX (LP_U0RXD_GPIO_NUM) +#endif +#endif + +#endif // MICROPY_INCLUDED_ESP32_MACHINE_UART_H From 225b7ac2907de970f13ec5fe806b2fece1802340 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 29 Jun 2026 13:24:10 +0930 Subject: [PATCH 334/635] py/nlrpowerpc: Don't clobber base register. A bug was exposed by commit 2757acf6ed1f ("py/nlr: Implement jump callbacks.") which added nlr_call_jump_callbacks() to MP_NLR_JUMP_HEAD. The arm64 backend fixed this in commit b02a5fa10aba ("py/nlraarch64: Fix dangerous use of input register."). Fix powerpc nlr_jump to use r4 as the base register in the asm block, which avoids GCC choosing a register for %0 that will be overwritten. This fixes both the ppc64 and ppc32 nlr_jump variants. Signed-off-by: Joel Stanley --- py/nlrpowerpc.c | 98 +++++++++++++++++++++++++------------------------ 1 file changed, 50 insertions(+), 48 deletions(-) diff --git a/py/nlrpowerpc.c b/py/nlrpowerpc.c index cf140400e68..ec1c62cf346 100644 --- a/py/nlrpowerpc.c +++ b/py/nlrpowerpc.c @@ -82,33 +82,34 @@ MP_NORETURN void nlr_jump(void *val) { MP_NLR_JUMP_HEAD(val, top) __asm__ volatile ( - "ld 3, 0x0(%0) ;" + "mr 4, %0 ;" + "ld 3, 0x0(4) ;" "cmpdi 3, 0x4eed ; " // Check canary "bne . ; " - "ld 0, 0x08(%0) ;" - "ld 1, 0x10(%0) ;" - "ld 2, 0x18(%0) ;" - "ld 14, 0x20(%0) ;" - "ld 15, 0x28(%0) ;" - "ld 16, 0x30(%0) ;" - "ld 17, 0x38(%0) ;" - "ld 18, 0x40(%0) ;" - "ld 19, 0x48(%0) ;" - "ld 20, 0x50(%0) ;" - "ld 21, 0x58(%0) ;" - "ld 22, 0x60(%0) ;" - "ld 23, 0x68(%0) ;" - "ld 24, 0x70(%0) ;" - "ld 25, 0x78(%0) ;" - "ld 26, 0x80(%0) ;" - "ld 27, 0x88(%0) ;" - "ld 28, 0x90(%0) ;" - "ld 29, 0x98(%0) ;" - "ld 30, 0xA0(%0) ;" - "ld 31, 0xA8(%0) ;" - "ld 3, 0xB0(%0) ;" + "ld 0, 0x08(4) ;" + "ld 1, 0x10(4) ;" + "ld 2, 0x18(4) ;" + "ld 14, 0x20(4) ;" + "ld 15, 0x28(4) ;" + "ld 16, 0x30(4) ;" + "ld 17, 0x38(4) ;" + "ld 18, 0x40(4) ;" + "ld 19, 0x48(4) ;" + "ld 20, 0x50(4) ;" + "ld 21, 0x58(4) ;" + "ld 22, 0x60(4) ;" + "ld 23, 0x68(4) ;" + "ld 24, 0x70(4) ;" + "ld 25, 0x78(4) ;" + "ld 26, 0x80(4) ;" + "ld 27, 0x88(4) ;" + "ld 28, 0x90(4) ;" + "ld 29, 0x98(4) ;" + "ld 30, 0xA0(4) ;" + "ld 31, 0xA8(4) ;" + "ld 3, 0xB0(4) ;" "mtcr 3 ;" - "ld 3, 0xB8(%0) ;" + "ld 3, 0xB8(4) ;" "mtlr 3 ; " "li 3, 1;" "blr ;" @@ -171,33 +172,34 @@ MP_NORETURN void nlr_jump(void *val) { MP_NLR_JUMP_HEAD(val, top) __asm__ volatile ( - "l 3, 0x0(%0) ;" + "mr 4, %0 ;" + "l 3, 0x0(4) ;" "cmpdi 3, 0x4eed ; " // Check canary "bne . ; " - "l 0, 0x04(%0) ;" - "l 1, 0x08(%0) ;" - "l 2, 0x0c(%0) ;" - "l 14, 0x10(%0) ;" - "l 15, 0x14(%0) ;" - "l 16, 0x18(%0) ;" - "l 17, 0x1c(%0) ;" - "l 18, 0x20(%0) ;" - "l 19, 0x24(%0) ;" - "l 20, 0x28(%0) ;" - "l 21, 0x2c(%0) ;" - "l 22, 0x30(%0) ;" - "l 23, 0x34(%0) ;" - "l 24, 0x38(%0) ;" - "l 25, 0x3c(%0) ;" - "l 26, 0x40(%0) ;" - "l 27, 0x44(%0) ;" - "l 28, 0x48(%0) ;" - "l 29, 0x4c(%0) ;" - "l 30, 0x50(%0) ;" - "l 31, 0x54(%0) ;" - "l 3, 0x58(%0) ;" + "l 0, 0x04(4) ;" + "l 1, 0x08(4) ;" + "l 2, 0x0c(4) ;" + "l 14, 0x10(4) ;" + "l 15, 0x14(4) ;" + "l 16, 0x18(4) ;" + "l 17, 0x1c(4) ;" + "l 18, 0x20(4) ;" + "l 19, 0x24(4) ;" + "l 20, 0x28(4) ;" + "l 21, 0x2c(4) ;" + "l 22, 0x30(4) ;" + "l 23, 0x34(4) ;" + "l 24, 0x38(4) ;" + "l 25, 0x3c(4) ;" + "l 26, 0x40(4) ;" + "l 27, 0x44(4) ;" + "l 28, 0x48(4) ;" + "l 29, 0x4c(4) ;" + "l 30, 0x50(4) ;" + "l 31, 0x54(4) ;" + "l 3, 0x58(4) ;" "mtcr 3 ;" - "l 3, 0x5c(%0) ;" + "l 3, 0x5c(4) ;" "mtlr 3 ; " "li 3, 1;" "blr ;" From 562d6be3651b60b8741c278b913179a49d054414 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 29 Jun 2026 16:37:31 +0930 Subject: [PATCH 335/635] py/nlrpowerpc: Add r4 to the nlr_push asm clobber list. nlr_push uses r4 as a scratch register but did not declare it clobbered. GCC was free to place one of the input operands (%0 or %1) in r4. No bug was observed due to this so the fix is for correctness and to guard against future bugs. Signed-off-by: Joel Stanley --- py/nlrpowerpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/py/nlrpowerpc.c b/py/nlrpowerpc.c index ec1c62cf346..cb94473968d 100644 --- a/py/nlrpowerpc.c +++ b/py/nlrpowerpc.c @@ -72,7 +72,7 @@ unsigned int nlr_push(nlr_buf_t *nlr) { "bctr ;" : : "r" (&nlr->regs), "r" (nlr) - : + : "r4" ); return 0; @@ -162,7 +162,7 @@ unsigned int nlr_push(nlr_buf_t *nlr) { "bctr ;" : : "r" (&nlr->regs), "r" (nlr) - : + : "r4" ); return 0; From f452dabd413ab5539c89a9b228bc94756836cebc Mon Sep 17 00:00:00 2001 From: Phil Howard Date: Tue, 23 Jun 2026 09:23:31 +0100 Subject: [PATCH 336/635] rp2: Run vm/gc/parse from SRAM by fixing linker object suffix. The linker scripts exclude py/gc.c, py/vm.c and py/parse.c from flash so they execute from faster SRAM, but the EXCLUDE_FILE patterns used a ".obj" suffix whereas CMake names objects ".c.o". The patterns matched nothing, so these files silently ran from XIP flash and the optimisation had no effect. Use the correct ".o" suffix, anchored with "py/" so that "py/gc.c.o" does not also match "py/modgc.c.o". On RP2350 this relocates ~10 KB of .text into SRAM and improves perfbench by ~16% (mean). Signed-off-by: Phil Howard --- ports/rp2/memmap_mp_rp2040.ld | 2 +- ports/rp2/memmap_mp_rp2350.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/rp2/memmap_mp_rp2040.ld b/ports/rp2/memmap_mp_rp2040.ld index df19f2d6d9e..9b925045701 100644 --- a/ports/rp2/memmap_mp_rp2040.ld +++ b/ports/rp2/memmap_mp_rp2040.ld @@ -70,7 +70,7 @@ SECTIONS * FLASH ... we will include any thing excluded here in .data below by default */ *(.init) /* Change for MicroPython... exclude gc.c, parse.c, vm.c from flash */ - *(EXCLUDE_FILE(*libgcc.a: *libc.a: *lib_a-mem*.o *libm.a: *gc.c.obj *vm.c.obj *parse.c.obj) .text*) + *(EXCLUDE_FILE(*libgcc.a: *libc.a: *lib_a-mem*.o *libm.a: *py/gc.c.o *py/vm.c.o *py/parse.c.o) .text*) *(.fini) /* Pull all c'tors into .text */ *crtbegin.o(.ctors) diff --git a/ports/rp2/memmap_mp_rp2350.ld b/ports/rp2/memmap_mp_rp2350.ld index 69994cee125..6af4c48ccf8 100644 --- a/ports/rp2/memmap_mp_rp2350.ld +++ b/ports/rp2/memmap_mp_rp2350.ld @@ -62,7 +62,7 @@ SECTIONS *(.init) *libgcc.a:cmse_nonsecure_call.o /* Change for MicroPython... exclude gc.c, parse.c, vm.c from flash */ - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a: *gc.c.obj *vm.c.obj *parse.c.obj) .text*) + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a: *py/gc.c.o *py/vm.c.o *py/parse.c.o) .text*) *(.fini) /* Pull all c'tors into .text */ *crtbegin.o(.ctors) From 765df7400f919704b9627750ebd5e6487f833355 Mon Sep 17 00:00:00 2001 From: EngineerWill Date: Wed, 1 Jul 2026 17:18:00 +0800 Subject: [PATCH 337/635] esp32/boards: Add WAVESHARE_ESP32_S3_PICO board configuration. Signed-off-by: eng33 --- .../boards/WAVESHARE_ESP32_S3_PICO/board.json | 23 ++++++++++++++ .../boards/WAVESHARE_ESP32_S3_PICO/board.md | 1 + .../mpconfigboard.cmake | 5 +++ .../WAVESHARE_ESP32_S3_PICO/mpconfigboard.h | 8 +++++ .../boards/WAVESHARE_ESP32_S3_PICO/pins.csv | 31 +++++++++++++++++++ 5 files changed, 68 insertions(+) create mode 100644 ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/board.json create mode 100644 ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/board.md create mode 100644 ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/mpconfigboard.cmake create mode 100644 ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/mpconfigboard.h create mode 100644 ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/pins.csv diff --git a/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/board.json b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/board.json new file mode 100644 index 00000000000..b100ed4d2d0 --- /dev/null +++ b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/board.json @@ -0,0 +1,23 @@ +{ + "deploy": [ + "../deploy.md" + ], + "deploy_options": { + "flash_offset": "0" + }, + "docs": "", + "features": [ + "BLE", + "External Flash", + "External RAM", + "WiFi" + ], + "images": [ + "waveshare_esp32_s3_pico.jpg" + ], + "mcu": "esp32s3", + "product": "Waveshare ESP32-S3-Pico", + "thumbnail": "", + "url": "https://www.waveshare.com/ESP32-S3-Pico.htm", + "vendor": "Waveshare" +} diff --git a/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/board.md b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/board.md new file mode 100644 index 00000000000..8cd6324e798 --- /dev/null +++ b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/board.md @@ -0,0 +1 @@ +The following files are firmware for the Waveshare ESP32-S3-Pico. diff --git a/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/mpconfigboard.cmake b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/mpconfigboard.cmake new file mode 100644 index 00000000000..53375032304 --- /dev/null +++ b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/mpconfigboard.cmake @@ -0,0 +1,5 @@ +include(boards/mpconfigboard_esp32s3_common.cmake) + +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.flash_qio_80m +) diff --git a/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/mpconfigboard.h b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/mpconfigboard.h new file mode 100644 index 00000000000..0f20a49a60d --- /dev/null +++ b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/mpconfigboard.h @@ -0,0 +1,8 @@ +#define MICROPY_HW_BOARD_NAME "Waveshare ESP32-S3-Pico" +#define MICROPY_HW_MCU_NAME "ESP32-S3" + +#define MICROPY_HW_I2C0_SCL (7) +#define MICROPY_HW_I2C0_SDA (6) + +// Enable UART REPL for modules that have an external USB-UART and don't use native USB. +#define MICROPY_HW_ENABLE_UART_REPL (1) diff --git a/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/pins.csv b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/pins.csv new file mode 100644 index 00000000000..7e601b96429 --- /dev/null +++ b/ports/esp32/boards/WAVESHARE_ESP32_S3_PICO/pins.csv @@ -0,0 +1,31 @@ +D0,GPIO11 +D1,GPIO12 +D2,GPIO13 +D3,GPIO14 +D4,GPIO15 +D5,GPIO16 +D6,GPIO17 +D7,GPIO18 +D8,GPIO33 +D9,GPIO34 +D10,GPIO35 +D11,GPIO36 +D12,GPIO37 +D13,GPIO38 +D14,GPIO39 +D15,GPIO40 +D16,GPIO42 +D17,GPIO41 +D18,GPIO1 +D19,GPIO2 +D20,GPIO4 +D21,GPIO5 +D22,GPIO6 +D26,GPIO7 +D27,GPIO8 +D28,GPIO9 +A1,GPIO7 +A2,GPIO8 +A3,GPIO9 +RGB_PIN,GPIO21 +USB_ADC,GPIO3 From 235f356db7eb1fc9751d8e96dadec4aab4e6ae2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Fri, 1 May 2026 16:02:14 +0200 Subject: [PATCH 338/635] tests/extmod/machine_timer: Reorganize and update supported platforms. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Daniël van de Giessen --- tests/extmod/machine_hard_timer.py | 45 ------- tests/extmod/machine_hard_timer.py.exp | 16 --- tests/extmod/machine_soft_timer.py | 43 ------- tests/extmod/machine_soft_timer.py.exp | 4 - tests/extmod/machine_timer.py | 167 +++++++++++++++++++------ tests/extmod/machine_timer.py.exp | 16 --- 6 files changed, 129 insertions(+), 162 deletions(-) delete mode 100644 tests/extmod/machine_hard_timer.py delete mode 100644 tests/extmod/machine_hard_timer.py.exp delete mode 100644 tests/extmod/machine_soft_timer.py delete mode 100644 tests/extmod/machine_soft_timer.py.exp delete mode 100644 tests/extmod/machine_timer.py.exp diff --git a/tests/extmod/machine_hard_timer.py b/tests/extmod/machine_hard_timer.py deleted file mode 100644 index 8fe42ea8508..00000000000 --- a/tests/extmod/machine_hard_timer.py +++ /dev/null @@ -1,45 +0,0 @@ -import sys - -try: - from machine import Timer - from time import sleep_ms -except: - print("SKIP") - raise SystemExit - -if sys.platform == "esp8266": - timer = Timer(0) -else: - # Hardware timers are not implemented. - print("SKIP") - raise SystemExit - -# Test both hard and soft IRQ handlers and both one-shot and periodic -# timers. We adjust period in tests/extmod/machine_soft_timer.py, so try -# adjusting freq here instead. The heap should be locked in hard callbacks -# and unlocked in soft callbacks. - - -def callback(t): - print("callback", mode[1], kind[1], freq, end=" ") - try: - allocate = bytearray(1) - print("unlocked") - except MemoryError: - print("locked") - - -modes = [(Timer.ONE_SHOT, "one-shot"), (Timer.PERIODIC, "periodic")] -kinds = [(False, "soft"), (True, "hard")] - -for mode in modes: - for kind in kinds: - for freq in 50, 25: - timer.init( - mode=mode[0], - freq=freq, - hard=kind[0], - callback=callback, - ) - sleep_ms(90) - timer.deinit() diff --git a/tests/extmod/machine_hard_timer.py.exp b/tests/extmod/machine_hard_timer.py.exp deleted file mode 100644 index 26cdc644fdd..00000000000 --- a/tests/extmod/machine_hard_timer.py.exp +++ /dev/null @@ -1,16 +0,0 @@ -callback one-shot soft 50 unlocked -callback one-shot soft 25 unlocked -callback one-shot hard 50 locked -callback one-shot hard 25 locked -callback periodic soft 50 unlocked -callback periodic soft 50 unlocked -callback periodic soft 50 unlocked -callback periodic soft 50 unlocked -callback periodic soft 25 unlocked -callback periodic soft 25 unlocked -callback periodic hard 50 locked -callback periodic hard 50 locked -callback periodic hard 50 locked -callback periodic hard 50 locked -callback periodic hard 25 locked -callback periodic hard 25 locked diff --git a/tests/extmod/machine_soft_timer.py b/tests/extmod/machine_soft_timer.py deleted file mode 100644 index 4c0611caedf..00000000000 --- a/tests/extmod/machine_soft_timer.py +++ /dev/null @@ -1,43 +0,0 @@ -# test "soft" machine.Timer (no hardware ID) -import sys - -try: - import time, machine - - machine.Timer -except: - print("SKIP") - raise SystemExit - -if sys.platform in ("esp32", "esp8266", "nrf"): - print("SKIP") # TODO: Implement soft timers for esp32/esp8266/nrf ports - raise SystemExit - -# create and deinit -t = machine.Timer(freq=1) -t.deinit() - -# deinit again -t.deinit() - -# create 2 and deinit -t = machine.Timer(freq=1) -t2 = machine.Timer(freq=1) -t.deinit() -t2.deinit() - -# create 2 and deinit in different order -t = machine.Timer(freq=1) -t2 = machine.Timer(freq=1) -t2.deinit() -t.deinit() - -# create one-shot timer with callback and wait for it to print (should be just once) -t = machine.Timer(period=1, mode=machine.Timer.ONE_SHOT, callback=lambda t: print("one-shot")) -time.sleep_ms(5) -t.deinit() - -# create periodic timer with callback and wait for it to print -t = machine.Timer(period=4, mode=machine.Timer.PERIODIC, callback=lambda t: print("periodic")) -time.sleep_ms(14) -t.deinit() diff --git a/tests/extmod/machine_soft_timer.py.exp b/tests/extmod/machine_soft_timer.py.exp deleted file mode 100644 index 2dd85ba67d3..00000000000 --- a/tests/extmod/machine_soft_timer.py.exp +++ /dev/null @@ -1,4 +0,0 @@ -one-shot -periodic -periodic -periodic diff --git a/tests/extmod/machine_timer.py b/tests/extmod/machine_timer.py index ef97ea4e949..a8f33bfa030 100644 --- a/tests/extmod/machine_timer.py +++ b/tests/extmod/machine_timer.py @@ -1,5 +1,3 @@ -import sys - try: from machine import Timer from time import sleep_ms @@ -7,42 +5,135 @@ print("SKIP") raise SystemExit -if sys.platform in ("esp32", "esp8266", "nrf"): - # Software timers aren't implemented on the esp32 and esp8266 ports. - # The nrf port doesn't support selection of hard and soft callbacks, - # and only allows Timer(period=N), not Timer(freq=N). +import sys + +if sys.platform == "nrf": + # Note: The nrf port supports machine.Timer, but is not compatible: It lacks + # the .init() method and freq argument, the period argument is microseconds + # instead milliseconds, and the ONE_SHOT constant is named ONESHOT. print("SKIP") raise SystemExit -else: - timer_id = -1 - -# Test both hard and soft IRQ handlers and both one-shot and periodic -# timers. We adjust period in tests/extmod/machine_soft_timer.py, so try -# adjusting freq here instead. The heap should be locked in hard callbacks -# and unlocked in soft callbacks. - - -def callback(t): - print("callback", mode[1], kind[1], freq, end=" ") - try: - allocate = bytearray(1) - print("unlocked") - except MemoryError: - print("locked") - - -modes = [(Timer.ONE_SHOT, "one-shot"), (Timer.PERIODIC, "periodic")] -kinds = [(False, "soft"), (True, "hard")] - -for mode in modes: - for kind in kinds: - for freq in 50, 25: - timer = Timer( - timer_id, - mode=mode[0], - freq=freq, - hard=kind[0], - callback=callback, + +import unittest + +# Hardware timers are only supported on the esp32 port +SUPPORTS_HARDWARE_TIMERS = sys.platform == "esp32" + +# Hard IRQs are not supported on the esp32 port +SUPPORTS_HARD_IRQ = sys.platform != "esp32" + + +class Test(unittest.TestCase): + def test_virtual_create(self): + self._test_create(-1) + self._test_create_multiple(-1, -1) + + @unittest.skipUnless(SUPPORTS_HARDWARE_TIMERS, "no hardware timers") + def test_hardware_create(self): + self._test_create(0) + self._test_create_multiple(0, 1) + + def test_virtual_softirq(self): + self._test_all_freq_period(-1, Timer.ONE_SHOT, False) + self._test_all_freq_period(-1, Timer.PERIODIC, False) + + @unittest.skipUnless(SUPPORTS_HARD_IRQ, "no hard-irq support") + def test_virtual_hardirq(self): + self._test_all_freq_period(-1, Timer.ONE_SHOT, True) + self._test_all_freq_period(-1, Timer.PERIODIC, True) + + @unittest.skipUnless(SUPPORTS_HARDWARE_TIMERS, "no hardware timers") + def test_hardware_softirq(self): + self._test_all_freq_period(0, Timer.ONE_SHOT, False) + self._test_all_freq_period(0, Timer.PERIODIC, False) + + @unittest.skipUnless(SUPPORTS_HARDWARE_TIMERS, "no hardware timers") + @unittest.skipUnless(SUPPORTS_HARD_IRQ, "no hard-irq support") + def test_hardware_hardirq(self): + self._test_all_freq_period(0, Timer.ONE_SHOT, True) + self._test_all_freq_period(0, Timer.PERIODIC, True) + + def _test_create(self, id): + # create and deinit + t = Timer(id) + t.init(freq=1) + t.deinit() + + # deinit again + t.deinit() + + # init a large number of times to catch bugs like + # https://github.com/micropython/micropython/issues/19162 + for _ in range(256): + t.init(freq=1) + t.deinit() + + def _test_create_multiple(self, *ids): + # create and deinit + timers = [] + for id in ids: + t = Timer(id) + self.assertFalse(t in timers) + t.init(freq=1) + timers.append(t) + for t in timers: + t.deinit() + + # create and deinit in reverse order + timers = [] + for id in ids: + t = Timer(id) + self.assertFalse(t in timers) + t.init(freq=1) + timers.append(t) + for t in reversed(timers): + t.deinit() + + def _test_all_freq_period(self, id, mode, hard): + # test two different freq and period arguments + for period, freq_period_arg in ( + (1000 // 50, {"freq": 50}), + (1000 // 25, {"freq": 25}), + (20, {"period": 20}), + (40, {"period": 40}), + ): + callback_results = [] + + def _callback(_): + try: + allocate = bytearray(1) + locked = False + except MemoryError: + locked = True + callback_results.append(locked) + + t = Timer(id) + t.init( + mode=mode, + callback=_callback, + hard=hard, + **freq_period_arg, ) - sleep_ms(90) - timer.deinit() + + # Note: These sleep durations are such that there is always at least + # 10ms between when the callback fires and we perform our checks, + # thus this test also implicitly checks that timers and/or sleep_ms + # do not drift more than 10ms. + total = 0 + for duration in (0, 10, 20, 40, 20): + sleep_ms(duration) + total += duration + + # number of times the callback should have been called + n = total // period + if mode == Timer.ONE_SHOT: + n = min(n, 1) + + # callback reports whether memory was locked, which + # should equal whether the timer uses hard IRQs + self.assertEqual([hard] * n, callback_results) + t.deinit() + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/extmod/machine_timer.py.exp b/tests/extmod/machine_timer.py.exp deleted file mode 100644 index 26cdc644fdd..00000000000 --- a/tests/extmod/machine_timer.py.exp +++ /dev/null @@ -1,16 +0,0 @@ -callback one-shot soft 50 unlocked -callback one-shot soft 25 unlocked -callback one-shot hard 50 locked -callback one-shot hard 25 locked -callback periodic soft 50 unlocked -callback periodic soft 50 unlocked -callback periodic soft 50 unlocked -callback periodic soft 50 unlocked -callback periodic soft 25 unlocked -callback periodic soft 25 unlocked -callback periodic hard 50 locked -callback periodic hard 50 locked -callback periodic hard 50 locked -callback periodic hard 50 locked -callback periodic hard 25 locked -callback periodic hard 25 locked From 35779273dca5636479ee6c379f3ad679736f362d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Thu, 2 Jul 2026 17:24:02 +0200 Subject: [PATCH 339/635] tests/extmod/machine_timer: Skip virtual timer tests on ESP32. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Daniël van de Giessen --- tests/extmod/machine_timer.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/extmod/machine_timer.py b/tests/extmod/machine_timer.py index a8f33bfa030..c34741f7345 100644 --- a/tests/extmod/machine_timer.py +++ b/tests/extmod/machine_timer.py @@ -19,11 +19,15 @@ # Hardware timers are only supported on the esp32 port SUPPORTS_HARDWARE_TIMERS = sys.platform == "esp32" +# Virtual timers are not supported on the esp32 port +SUPPORTS_VIRTUAL_TIMERS = sys.platform != "esp32" + # Hard IRQs are not supported on the esp32 port SUPPORTS_HARD_IRQ = sys.platform != "esp32" class Test(unittest.TestCase): + @unittest.skipUnless(SUPPORTS_VIRTUAL_TIMERS, "no virtual timers") def test_virtual_create(self): self._test_create(-1) self._test_create_multiple(-1, -1) @@ -33,10 +37,12 @@ def test_hardware_create(self): self._test_create(0) self._test_create_multiple(0, 1) + @unittest.skipUnless(SUPPORTS_VIRTUAL_TIMERS, "no virtual timers") def test_virtual_softirq(self): self._test_all_freq_period(-1, Timer.ONE_SHOT, False) self._test_all_freq_period(-1, Timer.PERIODIC, False) + @unittest.skipUnless(SUPPORTS_VIRTUAL_TIMERS, "no virtual timers") @unittest.skipUnless(SUPPORTS_HARD_IRQ, "no hard-irq support") def test_virtual_hardirq(self): self._test_all_freq_period(-1, Timer.ONE_SHOT, True) From b3fb831906076e38357585ba831b30be7e3c76f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Mon, 4 May 2026 11:08:49 +0200 Subject: [PATCH 340/635] zephyr/machine_timer: Initialize kernel timer structure only once. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Daniël van de Giessen --- ports/zephyr/machine_timer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/ports/zephyr/machine_timer.c b/ports/zephyr/machine_timer.c index 4b660849f67..3cfbafcc0ea 100644 --- a/ports/zephyr/machine_timer.c +++ b/ports/zephyr/machine_timer.c @@ -97,6 +97,10 @@ static mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, // Create the new timer. machine_timer_obj_t *self = mp_obj_malloc_with_finaliser(machine_timer_obj_t, &machine_timer_type); + // Initialize the kernel timer structure + k_timer_init(&self->my_timer, machine_timer_callback, NULL); + k_timer_user_data_set(&self->my_timer, self); + // Add the timer to the linked-list of timers self->next = MP_STATE_PORT(machine_timer_obj_head); MP_STATE_PORT(machine_timer_obj_head) = self; @@ -149,8 +153,6 @@ static mp_obj_t machine_timer_init_helper(machine_timer_obj_t *self, mp_uint_t n self->callback = args[ARG_callback].u_obj; self->ishard = args[ARG_hard].u_bool; - k_timer_init(&self->my_timer, machine_timer_callback, NULL); - k_timer_user_data_set(&self->my_timer, self); k_timer_start(&self->my_timer, K_MSEC(self->period_ms), K_MSEC(self->period_ms)); return mp_const_none; From 4cb7b93470d78fd0522458d1ec2e1d622bc54615 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 19 Jun 2026 13:38:02 +0000 Subject: [PATCH 341/635] github/workflows: Bump actions/checkout from 6 to 7. Bumps [actions/checkout](https://github.com/actions/checkout) from 6 to 7. - [Release notes](https://github.com/actions/checkout/releases) - [Changelog](https://github.com/actions/checkout/blob/main/CHANGELOG.md) - [Commits](https://github.com/actions/checkout/compare/v6...v7) --- updated-dependencies: - dependency-name: actions/checkout dependency-version: '7' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/biome.yml | 2 +- .github/workflows/code_formatting.yml | 2 +- .github/workflows/code_size.yml | 2 +- .github/workflows/codespell.yml | 2 +- .github/workflows/commit_formatting.yml | 2 +- .github/workflows/docs.yml | 2 +- .github/workflows/examples.yml | 2 +- .github/workflows/mpremote.yml | 2 +- .github/workflows/mpy_format.yml | 2 +- .github/workflows/ports.yml | 2 +- .github/workflows/ports_alif.yml | 2 +- .github/workflows/ports_cc3200.yml | 2 +- .github/workflows/ports_esp32.yml | 2 +- .github/workflows/ports_esp8266.yml | 2 +- .github/workflows/ports_mimxrt.yml | 2 +- .github/workflows/ports_nrf.yml | 2 +- .github/workflows/ports_powerpc.yml | 2 +- .github/workflows/ports_qemu.yml | 6 ++-- .github/workflows/ports_renesas-ra.yml | 2 +- .github/workflows/ports_rp2.yml | 2 +- .github/workflows/ports_samd.yml | 2 +- .github/workflows/ports_stm32.yml | 2 +- .github/workflows/ports_unix.yml | 44 ++++++++++++------------- .github/workflows/ports_webassembly.yml | 2 +- .github/workflows/ports_windows.yml | 6 ++-- .github/workflows/ports_zephyr.yml | 2 +- .github/workflows/ruff.yml | 2 +- 27 files changed, 52 insertions(+), 52 deletions(-) diff --git a/.github/workflows/biome.yml b/.github/workflows/biome.yml index 0cde10acc91..eba4e9f3908 100644 --- a/.github/workflows/biome.yml +++ b/.github/workflows/biome.yml @@ -7,7 +7,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout - uses: actions/checkout@v6 + uses: actions/checkout@v7 - name: Setup Biome uses: biomejs/setup-biome@v2 with: diff --git a/.github/workflows/code_formatting.yml b/.github/workflows/code_formatting.yml index 95653d941f9..3fa60c5387c 100644 --- a/.github/workflows/code_formatting.yml +++ b/.github/workflows/code_formatting.yml @@ -10,7 +10,7 @@ jobs: code-formatting: runs-on: ubuntu-22.04 steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 - name: Install packages run: tools/ci.sh c_code_formatting_setup diff --git a/.github/workflows/code_size.yml b/.github/workflows/code_size.yml index 603b598bf00..dc3a47ded26 100644 --- a/.github/workflows/code_size.yml +++ b/.github/workflows/code_size.yml @@ -26,7 +26,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 with: fetch-depth: 100 - name: Install packages diff --git a/.github/workflows/codespell.yml b/.github/workflows/codespell.yml index e3a9c79bd5e..6155a348b5d 100644 --- a/.github/workflows/codespell.yml +++ b/.github/workflows/codespell.yml @@ -6,7 +6,7 @@ jobs: codespell: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 # codespell version should be kept in sync with .pre-commit-config.yml - run: pip install --user codespell==2.4.1 tomli - run: codespell diff --git a/.github/workflows/commit_formatting.yml b/.github/workflows/commit_formatting.yml index 6abc3612a00..997532fde63 100644 --- a/.github/workflows/commit_formatting.yml +++ b/.github/workflows/commit_formatting.yml @@ -10,7 +10,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 with: fetch-depth: 100 - uses: actions/setup-python@v6 diff --git a/.github/workflows/docs.yml b/.github/workflows/docs.yml index 79755b74197..74b6eb3f0f4 100644 --- a/.github/workflows/docs.yml +++ b/.github/workflows/docs.yml @@ -17,7 +17,7 @@ jobs: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 - name: Install Python packages run: pip install -r docs/requirements.txt diff --git a/.github/workflows/examples.yml b/.github/workflows/examples.yml index 4627247fb9f..bbfc93b1f64 100644 --- a/.github/workflows/examples.yml +++ b/.github/workflows/examples.yml @@ -18,6 +18,6 @@ jobs: embedding: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build run: tools/ci.sh embedding_build diff --git a/.github/workflows/mpremote.yml b/.github/workflows/mpremote.yml index ad5dd454905..6df7a2e4956 100644 --- a/.github/workflows/mpremote.yml +++ b/.github/workflows/mpremote.yml @@ -11,7 +11,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 with: # Setting this to zero means fetch all history and tags, # which hatch-vcs can use to discover the version tag. diff --git a/.github/workflows/mpy_format.yml b/.github/workflows/mpy_format.yml index ab668c1cb5e..965bcedc73e 100644 --- a/.github/workflows/mpy_format.yml +++ b/.github/workflows/mpy_format.yml @@ -19,7 +19,7 @@ jobs: test: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh mpy_format_setup - name: Test mpy-tool.py diff --git a/.github/workflows/ports.yml b/.github/workflows/ports.yml index 5e71d4d076a..5da3f2be969 100644 --- a/.github/workflows/ports.yml +++ b/.github/workflows/ports.yml @@ -17,6 +17,6 @@ jobs: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build ports download metadata run: mkdir boards && ./tools/autobuild/build-downloads.py . ./boards diff --git a/.github/workflows/ports_alif.yml b/.github/workflows/ports_alif.yml index 6fb225937a9..e7d1064c97a 100644 --- a/.github/workflows/ports_alif.yml +++ b/.github/workflows/ports_alif.yml @@ -26,7 +26,7 @@ jobs: - alif_ae3_build runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh alif_setup - name: Build ci_${{matrix.ci_func }} diff --git a/.github/workflows/ports_cc3200.yml b/.github/workflows/ports_cc3200.yml index 194483ec218..5f920efda78 100644 --- a/.github/workflows/ports_cc3200.yml +++ b/.github/workflows/ports_cc3200.yml @@ -21,7 +21,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh cc3200_setup - name: Build diff --git a/.github/workflows/ports_esp32.yml b/.github/workflows/ports_esp32.yml index e2d3f3ad64d..d8c1f40e2b0 100644 --- a/.github/workflows/ports_esp32.yml +++ b/.github/workflows/ports_esp32.yml @@ -43,7 +43,7 @@ jobs: ci_func: esp32_build_p4 runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 # Only the newest IDF version will build the ESP-IDF lockfiles correctly, # so we need to disable MICROPY_MAINTAINER_BUILD on older versions. diff --git a/.github/workflows/ports_esp8266.yml b/.github/workflows/ports_esp8266.yml index eb7f59cdc49..156f3181bbc 100644 --- a/.github/workflows/ports_esp8266.yml +++ b/.github/workflows/ports_esp8266.yml @@ -21,7 +21,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh esp8266_setup && tools/ci.sh esp8266_path >> $GITHUB_PATH - name: Build diff --git a/.github/workflows/ports_mimxrt.yml b/.github/workflows/ports_mimxrt.yml index fd80f3f6329..4f171d11474 100644 --- a/.github/workflows/ports_mimxrt.yml +++ b/.github/workflows/ports_mimxrt.yml @@ -24,7 +24,7 @@ jobs: run: working-directory: 'micropython repo' # test build with space in path steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 with: path: 'micropython repo' - name: Install packages diff --git a/.github/workflows/ports_nrf.yml b/.github/workflows/ports_nrf.yml index bec9a5dfb5b..53a5d6139d6 100644 --- a/.github/workflows/ports_nrf.yml +++ b/.github/workflows/ports_nrf.yml @@ -21,7 +21,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh nrf_setup - name: Build diff --git a/.github/workflows/ports_powerpc.yml b/.github/workflows/ports_powerpc.yml index a883d026806..a3186351eb0 100644 --- a/.github/workflows/ports_powerpc.yml +++ b/.github/workflows/ports_powerpc.yml @@ -21,7 +21,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh powerpc_setup - name: Build diff --git a/.github/workflows/ports_qemu.yml b/.github/workflows/ports_qemu.yml index 0ed95dbe5f9..fe9a6287f89 100644 --- a/.github/workflows/ports_qemu.yml +++ b/.github/workflows/ports_qemu.yml @@ -30,7 +30,7 @@ jobs: - thumb_hardfp runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh qemu_setup_arm - name: Build and run test suite ci_qemu_build_arm_${{ matrix.ci_func }} @@ -42,7 +42,7 @@ jobs: build_and_test_rv32: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh qemu_setup_rv32 - name: Build and run test suite @@ -54,7 +54,7 @@ jobs: build_and_test_rv64: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh qemu_setup_rv64 - name: Build and run test suite diff --git a/.github/workflows/ports_renesas-ra.yml b/.github/workflows/ports_renesas-ra.yml index 920691eca70..1e5bfb447e8 100644 --- a/.github/workflows/ports_renesas-ra.yml +++ b/.github/workflows/ports_renesas-ra.yml @@ -21,7 +21,7 @@ jobs: build_renesas_ra_board: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh renesas_ra_setup - name: Build diff --git a/.github/workflows/ports_rp2.yml b/.github/workflows/ports_rp2.yml index ea19e2da7ff..27d6c60a5c5 100644 --- a/.github/workflows/ports_rp2.yml +++ b/.github/workflows/ports_rp2.yml @@ -24,7 +24,7 @@ jobs: run: working-directory: 'micropython repo' # test build with space in path steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 with: path: 'micropython repo' - name: Install packages diff --git a/.github/workflows/ports_samd.yml b/.github/workflows/ports_samd.yml index eb806ceb044..04cddeb76de 100644 --- a/.github/workflows/ports_samd.yml +++ b/.github/workflows/ports_samd.yml @@ -21,7 +21,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh samd_setup - name: Build diff --git a/.github/workflows/ports_stm32.yml b/.github/workflows/ports_stm32.yml index 2ed730eb4e8..095a1906f66 100644 --- a/.github/workflows/ports_stm32.yml +++ b/.github/workflows/ports_stm32.yml @@ -28,7 +28,7 @@ jobs: - stm32_misc_build runs-on: ubuntu-22.04 steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh stm32_setup && tools/ci.sh stm32_path >> $GITHUB_PATH - name: Build ci_${{matrix.ci_func }} diff --git a/.github/workflows/ports_unix.yml b/.github/workflows/ports_unix.yml index 05c1a7773b3..cb70541ced1 100644 --- a/.github/workflows/ports_unix.yml +++ b/.github/workflows/ports_unix.yml @@ -23,7 +23,7 @@ jobs: minimal: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build run: tools/ci.sh unix_minimal_build - name: Run main test suite @@ -35,7 +35,7 @@ jobs: reproducible: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build with reproducible date run: tools/ci.sh unix_minimal_build env: @@ -46,7 +46,7 @@ jobs: standard: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build run: tools/ci.sh unix_standard_build - name: Run main test suite @@ -58,7 +58,7 @@ jobs: standard_v2: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build run: tools/ci.sh unix_standard_v2_build - name: Run main test suite @@ -70,7 +70,7 @@ jobs: standard_terse: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build run: tools/ci.sh unix_standard_terse_build - name: Run main test suite @@ -82,7 +82,7 @@ jobs: coverage: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -121,7 +121,7 @@ jobs: coverage_32bit: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -144,7 +144,7 @@ jobs: nanbox: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -163,7 +163,7 @@ jobs: longlong: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -182,7 +182,7 @@ jobs: float: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build run: tools/ci.sh unix_float_build - name: Run main test suite @@ -194,7 +194,7 @@ jobs: gil_enabled: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build run: tools/ci.sh unix_gil_enabled_build - name: Run main test suite @@ -206,7 +206,7 @@ jobs: stackless_clang: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh unix_clang_setup - name: Build @@ -220,7 +220,7 @@ jobs: float_clang: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh unix_clang_setup - name: Build @@ -234,7 +234,7 @@ jobs: settrace_stackless: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -251,7 +251,7 @@ jobs: repr_b: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -270,7 +270,7 @@ jobs: macos: runs-on: macos-26 steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 with: python-version: '3.8' @@ -285,7 +285,7 @@ jobs: qemu_mips: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -304,7 +304,7 @@ jobs: qemu_arm: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -323,7 +323,7 @@ jobs: qemu_riscv64: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -342,7 +342,7 @@ jobs: qemu_loong64: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -361,7 +361,7 @@ jobs: sanitize_address: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. @@ -386,7 +386,7 @@ jobs: sanitize_undefined: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. diff --git a/.github/workflows/ports_webassembly.yml b/.github/workflows/ports_webassembly.yml index f6619cc8976..ac2050129ef 100644 --- a/.github/workflows/ports_webassembly.yml +++ b/.github/workflows/ports_webassembly.yml @@ -21,7 +21,7 @@ jobs: build: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh webassembly_setup - name: Build diff --git a/.github/workflows/ports_windows.yml b/.github/workflows/ports_windows.yml index 1243366d413..0512c4289de 100644 --- a/.github/workflows/ports_windows.yml +++ b/.github/workflows/ports_windows.yml @@ -55,7 +55,7 @@ jobs: - uses: microsoft/setup-msbuild@v3 with: vs-version: ${{ matrix.vs_version }} - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build mpy-cross.exe run: msbuild mpy-cross\mpy-cross.vcxproj -maxcpucount -property:Configuration=${{ matrix.configuration }} -property:Platform=${{ matrix.platform }} -property:PlatformToolset=${{ matrix.platform_toolset }} - name: Update submodules @@ -122,7 +122,7 @@ jobs: git diffutils path-type: inherit # Remove when setup-python is removed - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Build mpy-cross.exe run: make -C mpy-cross -j2 - name: Update submodules @@ -140,7 +140,7 @@ jobs: cross-build-on-linux: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - name: Install packages run: tools/ci.sh windows_setup - name: Build diff --git a/.github/workflows/ports_zephyr.yml b/.github/workflows/ports_zephyr.yml index 330121d1de6..1459615aae6 100644 --- a/.github/workflows/ports_zephyr.yml +++ b/.github/workflows/ports_zephyr.yml @@ -33,7 +33,7 @@ jobs: docker-images: false tool-cache: true swap-storage: false - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - id: versions name: Read Zephyr version run: source tools/ci.sh && echo "ZEPHYR=$ZEPHYR_VERSION" | tee "$GITHUB_OUTPUT" diff --git a/.github/workflows/ruff.yml b/.github/workflows/ruff.yml index 6a8d4055a91..a5a6fc7e26c 100644 --- a/.github/workflows/ruff.yml +++ b/.github/workflows/ruff.yml @@ -6,7 +6,7 @@ jobs: ruff: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 # ruff version should be kept in sync with .pre-commit-config.yaml & also micropython-lib - run: pipx install ruff==0.11.6 - run: ruff check --output-format=github . From d42edb19f142d3e337f3c3a261e9287a39bc01f9 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Tue, 23 Jun 2026 19:14:21 +0000 Subject: [PATCH 342/635] github/workflows: Bump actions/cache from 5 to 6. Bumps [actions/cache](https://github.com/actions/cache) from 5 to 6. - [Release notes](https://github.com/actions/cache/releases) - [Changelog](https://github.com/actions/cache/blob/main/RELEASES.md) - [Commits](https://github.com/actions/cache/compare/v5...v6) --- updated-dependencies: - dependency-name: actions/cache dependency-version: '6' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/actions/setup_esp32/action.yml | 2 +- .github/workflows/ports_zephyr.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/actions/setup_esp32/action.yml b/.github/actions/setup_esp32/action.yml index 42c44cf76ce..3b5da9eca87 100644 --- a/.github/actions/setup_esp32/action.yml +++ b/.github/actions/setup_esp32/action.yml @@ -19,7 +19,7 @@ runs: - name: Cached ESP-IDF install id: cache_esp_idf - uses: actions/cache@v5 + uses: actions/cache@v6 with: path: | ./esp-idf/ diff --git a/.github/workflows/ports_zephyr.yml b/.github/workflows/ports_zephyr.yml index 1459615aae6..8ed9845927f 100644 --- a/.github/workflows/ports_zephyr.yml +++ b/.github/workflows/ports_zephyr.yml @@ -39,7 +39,7 @@ jobs: run: source tools/ci.sh && echo "ZEPHYR=$ZEPHYR_VERSION" | tee "$GITHUB_OUTPUT" - name: Cached Zephyr Workspace id: cache_workspace - uses: actions/cache@v5 + uses: actions/cache@v6 with: # note that the Zephyr CI docker image is 15GB. At time of writing # GitHub caches are limited to 10GB total for a project. So we only From 21f47c208ed88f903b738128f40327764d5d4971 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 26 Jun 2026 19:08:52 +0200 Subject: [PATCH 343/635] py/emitglue: Refactor cache flushing on AArch32. This commit updates the cache flushing logic for AArch32 targets. Before these changes, when running on Linux the instruction and data caches would be cleared only for AArch32 targets. However, said checks did not trigger properly when running an AArch32 binary on certain AArch64 machines. For example, the Unix port - when built using a 32-bits hard-float toolchain - would work just fine on a Raspberry Pi 3B+ running a 64-bits OS, but the very same binary all of a sudden becomes flaky when handling generated code on a Raspberry Pi 4. These changes aim to generalise cache flushing on Linux, enabling that unconditionally whenever the target binary is built for either AArch32, or for RISC-V. Doing this for RISC-V acts both as a preventative measure for the wide variety of RISC-V chips out there, and may also help explaining some rare crashes seen when testing native modules on certain MilkV-Duo RV64 boards. If a binary targeting Linux is built with a compiler that is either not compatible with GCC's builtins, or it does not provide `__builtin___clear_cache` (too old or just broken), you'll have to provide your own `MP_HAL_CLEAN_DCACHE` implementation. See the cacheflush(2) man page for why a generic fallback solution is not provided. This refactoring also made it required to provide a cache flush callback for QEMU/SABRELITE, which has been generalised to cover all AArch32 targets. Signed-off-by: Alessandro Gatti --- ports/qemu/mphalport.h | 9 +++++++++ ports/unix/mphalport.h | 9 +++++++++ py/emitglue.c | 12 +++++++----- 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/ports/qemu/mphalport.h b/ports/qemu/mphalport.h index 49f14fc8847..13002807dd8 100644 --- a/ports/qemu/mphalport.h +++ b/ports/qemu/mphalport.h @@ -28,3 +28,12 @@ #include "shared/runtime/interrupt_char.h" void mp_hal_get_random(size_t n, uint8_t *buf); + +#if defined(__ARM_32BIT_STATE) +#if __has_builtin(__builtin___clear_cache) +#define MP_HAL_CLEAN_DCACHE(fun_data, fun_len) \ + do { \ + __builtin___clear_cache((void *)fun_data, (char *)fun_data + fun_len); \ + } while (0) +#endif +#endif diff --git a/ports/unix/mphalport.h b/ports/unix/mphalport.h index 5d8004e5e4d..fa8f0f7eb10 100644 --- a/ports/unix/mphalport.h +++ b/ports/unix/mphalport.h @@ -122,5 +122,14 @@ enum { void mp_hal_get_mac(int idx, uint8_t buf[6]); #endif +#if defined(__linux__) && (defined(__ARM_32BIT_STATE) || defined(__riscv)) +#if __has_builtin(__builtin___clear_cache) +#define MP_HAL_CLEAN_DCACHE(fun_data, fun_len) \ + do { \ + __builtin___clear_cache((void *)fun_data, (char *)fun_data + fun_len); \ + } while (0) +#endif +#endif + // Global variable to control compile-only mode. extern bool mp_compile_only; diff --git a/py/emitglue.c b/py/emitglue.c index 390f5f93a1a..4b493c76bdd 100644 --- a/py/emitglue.c +++ b/py/emitglue.c @@ -103,17 +103,20 @@ void mp_emit_glue_assign_native(mp_raw_code_t *rc, mp_raw_code_kind_t kind, cons // Some architectures require flushing/invalidation of the I/D caches, // so that the generated native code which was created in data RAM will // be available for execution from instruction RAM. - #if defined(__thumb__) || defined(__thumb2__) + #if defined(__linux__) && defined(MP_HAL_CLEAN_DCACHE) + // On Linux always flush caches if there's a chance, just in case. + MP_HAL_CLEAN_DCACHE(fun_data, fun_len); + #elif defined(__thumb__) || defined(__thumb2__) #if __ICACHE_PRESENT == 1 // Flush D-cache, so the code emitted is stored in RAM. MP_HAL_CLEAN_DCACHE(fun_data, fun_len); // Invalidate I-cache, so the newly-created code is reloaded from RAM. SCB_InvalidateICache(); #endif + #elif defined(__ARM_32BIT_STATE) && defined(MP_HAL_CLEAN_DCACHE) + // Flush the D-cache. + MP_HAL_CLEAN_DCACHE(fun_data, fun_len); #elif defined(__arm__) - #if (defined(__linux__) && defined(__GNUC__)) || __ARM_ARCH == 7 - __builtin___clear_cache((void *)fun_data, (char *)fun_data + fun_len); - #else // Flush I-cache and D-cache. asm volatile ( "0:" @@ -122,7 +125,6 @@ void mp_emit_glue_assign_native(mp_raw_code_t *rc, mp_raw_code_kind_t kind, cons "mov r0, #0\n" "mcr p15, 0, r0, c7, c7, 0\n" // invalidate I-cache and D-cache : : : "r0", "cc"); - #endif #elif defined(__riscv) && defined(MP_HAL_CLEAN_DCACHE) // Flush the D-cache. MP_HAL_CLEAN_DCACHE(fun_data, fun_len); From 8338f9a9d572bd8b8e3b17eb3a042184a3b6ad1e Mon Sep 17 00:00:00 2001 From: Phil Howard Date: Tue, 30 Jun 2026 11:30:16 +0100 Subject: [PATCH 344/635] rp2: Size IRQ array correctly for 48 pin variants. Use NUM_BANK0_GPIOS to size the pin IRQ array, avoiding a potential leak using IRQs on pins > 30. Signed-off-by: Phil Howard --- ports/rp2/machine_pin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/rp2/machine_pin.c b/ports/rp2/machine_pin.c index 336e6ff5a23..bb770b9db74 100644 --- a/ports/rp2/machine_pin.c +++ b/ports/rp2/machine_pin.c @@ -606,4 +606,4 @@ mp_hal_pin_obj_t mp_hal_get_pin_obj(mp_obj_t obj) { return pin->id; } -MP_REGISTER_ROOT_POINTER(void *machine_pin_irq_obj[30]); +MP_REGISTER_ROOT_POINTER(void *machine_pin_irq_obj[NUM_BANK0_GPIOS]); From 0d326759d23999dc01b51261858f0e3e092ed87e Mon Sep 17 00:00:00 2001 From: Phil Howard Date: Tue, 30 Jun 2026 15:30:43 +0100 Subject: [PATCH 345/635] rp2: Fix RP2350 watchdog time to ~16s. The RP2350 watchdog supports a 16777ms period vs the RP2040s 8388ms. Signed-off-by: Phil Howard --- ports/rp2/machine_wdt.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/ports/rp2/machine_wdt.c b/ports/rp2/machine_wdt.c index b6cf3f9a22d..8d0edd4c2ea 100644 --- a/ports/rp2/machine_wdt.c +++ b/ports/rp2/machine_wdt.c @@ -29,8 +29,14 @@ #include "hardware/watchdog.h" -// The maximum timeout in milliseconds is: 0xffffff / 2 / 1000 +// The maximum timeout is set by the 24-bit watchdog counter and the number of +// ticks it decrements per microsecond (WATCHDOG_XFACTOR): 2 on RP2040, 1 on +// RP2350. So the max in milliseconds is 0xffffff / WATCHDOG_XFACTOR / 1000. +#if PICO_RP2350 +#define WDT_TIMEOUT_MAX 16777 +#else #define WDT_TIMEOUT_MAX 8388 +#endif typedef struct _machine_wdt_obj_t { mp_obj_base_t base; From 4edef8717da3a107e27628b0765040e64a1928d7 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Thu, 14 May 2026 06:12:35 +1000 Subject: [PATCH 346/635] stm32/main: Initialize network subsystem before boot.py. Move mod_network_init() before boot.py execution so that network interfaces can be instantiated in boot.py. Signed-off-by: Andrew Leech --- ports/stm32/main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/ports/stm32/main.c b/ports/stm32/main.c index 6612d354701..1189d317bb8 100644 --- a/ports/stm32/main.c +++ b/ports/stm32/main.c @@ -667,6 +667,12 @@ void stm32_main(uint32_t reset_mode) { pyexec_frozen_module(MICROPY_BOARD_FROZEN_BOOT_FILE, false); #endif + #if MICROPY_PY_NETWORK + // Initialize network subsystem before boot.py so that network + // interfaces can be instantiated in boot.py. + mod_network_init(); + #endif + // Run boot.py (or whatever else a board configures at this stage). if (MICROPY_BOARD_RUN_BOOT_PY(&state) == BOARDCTRL_GOTO_SOFT_RESET_EXIT) { goto soft_reset_exit; From bb6adc60e41f94bdf134256330ce2997d4d9472b Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Thu, 14 May 2026 06:12:47 +1000 Subject: [PATCH 347/635] stm32/eth: Add link detection polling and DHCP hot-plug support. Replace the blocking PHY init and autonegotiation wait in eth_mac_init() with background link polling via eth_phy_link_status_poll(), called from the LWIP poll loop. This allows active(True) to return immediately regardless of cable state, and handles cable hot-plug by detecting link changes, reconfiguring MAC speed/duplex after autonegotiation completes, and restarting DHCP as needed. PHY_BSR is read twice when sampling link status so the IEEE 802.3 latched-low link bit reflects the current state. If autoneg fails to complete within 5s the MAC falls back to 10Mbps Half-Duplex and prints a warning so the symptom is visible. On link-down in DHCP mode the netif's DHCP-assigned IP is cleared before dhcp_stop() so that the link-up restart path triggers a fresh DHCP exchange. Static IPs are preserved since dhcp_supplied_address() gates the clear. The netif is now registered once during eth_init() so status() returns the physical link state before active(True) is called. The active() method returns the interface enabled state rather than link status; use status() for link/cable state. Tested on NUCLEO_H563ZI (LAN8742A, 100Mb RMII) point-to-point with AX88179 USB NIC, and OPENMV_N6 (RTL8211, 1000Mb RGMII). Builds clean on NUCLEO_H563ZI, NUCLEO_F429ZI, NUCLEO_H743ZI, NUCLEO_N657X0. Signed-off-by: Andrew Leech --- ports/stm32/eth.c | 322 +++++++++++++++++++++++++++--------- ports/stm32/eth.h | 2 + ports/stm32/eth_phy.h | 6 + ports/stm32/mpnetworkport.c | 5 + ports/stm32/network_lan.c | 4 +- 5 files changed, 258 insertions(+), 81 deletions(-) diff --git a/ports/stm32/eth.c b/ports/stm32/eth.c index 7baaa89c627..924d751e4cd 100644 --- a/ports/stm32/eth.c +++ b/ports/stm32/eth.c @@ -107,6 +107,7 @@ // Configuration values #define PHY_INIT_TIMEOUT_MS (10000) +#define PHY_AUTONEG_TIMEOUT_MS (5000) // These buffer sizes need to be a multiple of 8 (for STM32N6 at least). #define RX_BUF_SIZE (1528) // includes 4-byte CRC at end @@ -162,6 +163,11 @@ typedef struct _eth_t { uint32_t phy_addr; void (*phy_init)(uint32_t phy_addr); int16_t (*phy_get_link_status)(uint32_t phy_addr); + bool last_link_status; + bool enabled; + bool mac_speed_configured; + uint32_t autoneg_start_ms; + volatile bool mac_reconfig_in_progress; } eth_t; // This struct contains RX and TX buffers shared with the DMA, and they may need @@ -181,6 +187,9 @@ eth_t eth_instance; static void eth_mac_deinit(eth_t *self); static void eth_process_frame(eth_t *self, size_t len, const uint8_t *buf); +static void eth_lwip_init(eth_t *self); +static int eth_phy_init(eth_t *self); +static void eth_dhcp_restart_if_needed(struct netif *netif); void eth_phy_write(uint32_t phy_addr, uint32_t reg, uint32_t val) { #if defined(STM32H5) || defined(STM32H7) || defined(STM32N6) @@ -239,9 +248,18 @@ uint32_t eth_phy_read(uint32_t phy_addr, uint32_t reg) { } int eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type) { + if (self->netif.input != NULL) { + // Already initialised. + return 0; + } mp_hal_get_mac(mac_idx, &self->netif.hwaddr[0]); self->netif.hwaddr_len = 6; self->phy_addr = phy_addr; + self->last_link_status = false; + self->enabled = false; + self->mac_reconfig_in_progress = false; + self->mac_speed_configured = false; + self->autoneg_start_ms = 0; self->phy_init = eth_phy_generic_init; if (phy_type == ETH_PHY_DP83825 || phy_type == ETH_PHY_DP83848) { self->phy_get_link_status = eth_phy_dp838xx_get_link_status; @@ -301,6 +319,10 @@ int eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type) { #else __HAL_RCC_ETH_CLK_ENABLE(); #endif + + // Register netif with LWIP so the interface is visible before active(True). + eth_lwip_init(self); + return 0; } @@ -356,6 +378,11 @@ static int eth_mac_init(eth_t *self) { SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; #endif + // Release ETH peripheral from reset and enable clocks during CPU sleep. + // Note: CLK_SLEEP_ENABLE means clocks stay ON during sleep (not OFF). + // Clocks must continue during sleep to allow the ETH peripheral to receive + // packets and generate interrupts when the CPU enters sleep mode (WFI), + // which is necessary for DHCP and other network traffic. #if defined(STM32H5) __HAL_RCC_ETH_RELEASE_RESET(); @@ -468,52 +495,6 @@ static int eth_mac_init(eth_t *self) { ETH->DMA_CH[TX_DMA_CH].DMACCR &= ~(ETH_DMACxCR_DSL_Msk); #endif - // Reset and initialize the PHY. - self->phy_init(self->phy_addr); - - // Wait for the PHY link to be established - int phy_state = 0; - t0 = mp_hal_ticks_ms(); - while (phy_state != 3) { - if (mp_hal_ticks_ms() - t0 > PHY_INIT_TIMEOUT_MS) { - eth_mac_deinit(self); - return -MP_ETIMEDOUT; - } - uint16_t bcr = eth_phy_read(self->phy_addr, PHY_BCR); - uint16_t bsr = eth_phy_read(self->phy_addr, PHY_BSR); - switch (phy_state) { - case 0: - if (!(bcr & PHY_BCR_SOFT_RESET)) { - phy_state = 1; - } - break; - case 1: - if (bsr & PHY_BSR_LINK_STATUS) { - // Announce all modes - eth_phy_write(self->phy_addr, PHY_ANAR, - PHY_ANAR_SPEED_10HALF | - PHY_ANAR_SPEED_10FULL | - PHY_ANAR_SPEED_100HALF | - PHY_ANAR_SPEED_100FULL | - PHY_ANAR_IEEE802_3); - // Start autonegotiate. - eth_phy_write(self->phy_addr, PHY_BCR, PHY_BCR_AUTONEG_EN); - phy_state = 2; - } - break; - case 2: - if ((bsr & (PHY_BSR_AUTONEG_DONE | PHY_BSR_LINK_STATUS)) - == (PHY_BSR_AUTONEG_DONE | PHY_BSR_LINK_STATUS)) { - phy_state = 3; - } - break; - } - mp_hal_delay_ms(2); - } - - // Get register with link status - uint16_t phy_scsr = self->phy_get_link_status(self->phy_addr); - // Burst mode configuration #if defined(STM32H5) || defined(STM32H7) || defined(STM32N6) ETH->DMASBMR = ETH->DMASBMR & ~ETH_DMASBMR_AAL & ~ETH_DMASBMR_FB; @@ -654,23 +635,15 @@ static int eth_mac_init(eth_t *self) { ETH->MACA0LR = mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]; mp_hal_delay_ms(2); - // Work out the line speed configuration for MACCR. - uint32_t maccr = 0; - if (phy_scsr & PHY_SPEED_100HALF) { - maccr |= ETH_MACCR_FES; - } - if (phy_scsr & PHY_DUPLEX) { - maccr |= ETH_MACCR_DM; - } + // Set MAC control register to a safe default (100Mbps Full Duplex). + // The actual speed/duplex is configured by eth_phy_link_status_poll() once + // PHY autonegotiation completes. + uint32_t maccr = ETH_MACCR_FES | ETH_MACCR_DM; #if defined(STM32N6) - if (!(phy_scsr & PHY_SPEED_1000HALF)) { - maccr |= ETH_MACCR_PS; - } - - maccr |= - ETH_MACCR_IPG_96BIT + maccr |= ETH_MACCR_PS // 100/10Mbit, reconfigured by poll if 1000Mbit negotiated + | ETH_MACCR_IPG_96BIT | ETH_MACCR_SARC_REPADDR0 | ETH_MACCR_IPC | ETH_MACCR_BL_10 @@ -1102,28 +1075,174 @@ static void eth_lwip_init(eth_t *self) { n->name[1] = '0'; netif_add(n, &ipconfig[0], &ipconfig[1], &ipconfig[2], self, eth_netif_init, ethernet_input); netif_set_hostname(n, mod_network_hostname_data); - netif_set_default(n); - netif_set_up(n); dns_setserver(0, &ipconfig[3]); dhcp_set_struct(n, &self->dhcp_struct); - dhcp_start(n); - netif_set_link_up(n); + // netif_set_default(), netif_set_up(), netif_set_link_up() and dhcp_start() + // are deferred. They are called from eth_start() (interface up) and from + // eth_phy_link_status_poll() (link up after autonegotiation). MICROPY_PY_LWIP_EXIT } -static void eth_lwip_deinit(eth_t *self) { - MICROPY_PY_LWIP_ENTER - for (struct netif *netif = netif_list; netif != NULL; netif = netif->next) { - if (netif == &self->netif) { - netif_remove(netif); - netif->ip_addr.addr = 0; - netif->flags = 0; +// Reset the PHY and start autonegotiation. Does not wait for completion. +static int eth_phy_init(eth_t *self) { + self->phy_init(self->phy_addr); + + // Wait for the soft reset to complete (typically a few ms). This is + // bounded; we do not wait for link or autonegotiation here. + uint32_t t0 = mp_hal_ticks_ms(); + while (eth_phy_read(self->phy_addr, PHY_BCR) & PHY_BCR_SOFT_RESET) { + if (mp_hal_ticks_ms() - t0 > 1000) { + return -MP_ETIMEDOUT; } + mp_hal_delay_ms(2); + } + + // Advertise all 10/100 modes. + eth_phy_write(self->phy_addr, PHY_ANAR, + PHY_ANAR_SPEED_10HALF | + PHY_ANAR_SPEED_10FULL | + PHY_ANAR_SPEED_100HALF | + PHY_ANAR_SPEED_100FULL | + PHY_ANAR_IEEE802_3); + + // For gigabit-capable PHYs, also advertise 1000Mbit. + eth_phy_write(self->phy_addr, PHY_1000BTCR, + PHY_1000BTCR_1000HALF | PHY_1000BTCR_1000FULL); + + // Start (or restart) autonegotiation. + eth_phy_write(self->phy_addr, PHY_BCR, PHY_BCR_AUTONEG_EN | PHY_BCR_AUTONEG_RESTART); + + self->autoneg_start_ms = mp_hal_ticks_ms(); + return 0; +} + +// Restart DHCP if no static IP is configured. Used when link comes up, MAC is +// reconfigured, or the interface starts. +static void eth_dhcp_restart_if_needed(struct netif *netif) { + if (netif_is_up(netif) && ip4_addr_isany_val(*netif_ip4_addr(netif))) { + if (netif_dhcp_data(netif) != NULL) { + dhcp_stop(netif); + } + dhcp_start(netif); + } +} + +// Poll PHY link status and react to changes. Called from the lwIP poll loop. +// +// State machine: +// - link down -> link up: mark link up, start DHCP (or use static IP), +// wait for autoneg to complete, then reconfigure MAC speed/duplex. +// - link up -> link down: stop DHCP, mark link down. +// - autoneg complete after link up: configure MAC speed/duplex from PHY. +void eth_phy_link_status_poll(void) { + eth_t *self = ð_instance; + if (!self->enabled) { + return; + } + + // PHY_BSR link status bit is latched-low (IEEE 802.3): read twice to get + // the current state (first read clears any latched events). + (void)eth_phy_read(self->phy_addr, PHY_BSR); + uint16_t bsr = eth_phy_read(self->phy_addr, PHY_BSR); + bool current_link_status = (bsr & PHY_BSR_LINK_STATUS) != 0; + + // Handle link up/down transitions. + if (current_link_status != self->last_link_status) { + self->last_link_status = current_link_status; + struct netif *netif = &self->netif; + MICROPY_PY_LWIP_ENTER + if (current_link_status) { + netif_set_link_up(netif); + self->mac_speed_configured = false; + self->autoneg_start_ms = mp_hal_ticks_ms(); + eth_dhcp_restart_if_needed(netif); + } else { + netif_set_link_down(netif); + self->mac_speed_configured = false; + if (netif_dhcp_data(netif) != NULL) { + if (dhcp_supplied_address(netif)) { + // DHCP assigned this IP: clear it so DHCP restarts on link-up. + ip4_addr_set_zero(&netif->ip_addr); + } + dhcp_stop(netif); + } + } + MICROPY_PY_LWIP_EXIT + } + + // If link is up but MAC speed/duplex not yet configured, check if + // autonegotiation has completed. + if (current_link_status && !self->mac_speed_configured) { + // Re-verify link is still up before proceeding (it may have dropped). + if (!self->last_link_status) { + return; + } + + bsr = eth_phy_read(self->phy_addr, PHY_BSR); + bool autoneg_timeout = (mp_hal_ticks_ms() - self->autoneg_start_ms) > PHY_AUTONEG_TIMEOUT_MS; + + if (!(bsr & PHY_BSR_AUTONEG_DONE) && !autoneg_timeout) { + return; + } + + // Read negotiated speed/duplex. + uint16_t phy_speed = self->phy_get_link_status(self->phy_addr); + if (autoneg_timeout && phy_speed == 0) { + // Couldn't read speed; fall back to 10Mbps Half-Duplex. + phy_speed = PHY_SPEED_10HALF; + mp_printf(&mp_plat_print, "ETH: Autonegotiation timeout, using 10Mbps Half-Duplex\n"); + } + + self->mac_reconfig_in_progress = true; + + uint32_t maccr = ETH->MACCR; + // Stop TX/RX before changing speed/duplex. + maccr &= ~(ETH_MACCR_TE | ETH_MACCR_RE); + ETH->MACCR = maccr; + + #if defined(STM32N6) + // N6: PS=1 selects 10/100Mbit, FES selects 100 vs 10. PS=0 selects 1000Mbit. + maccr &= ~(ETH_MACCR_FES | ETH_MACCR_DM | ETH_MACCR_PS); + if (phy_speed == PHY_SPEED_1000FULL) { + maccr |= ETH_MACCR_DM; + } else if (phy_speed == PHY_SPEED_1000HALF) { + // All bits clear (default). + } else if (phy_speed == PHY_SPEED_100FULL) { + maccr |= ETH_MACCR_FES | ETH_MACCR_PS | ETH_MACCR_DM; + } else if (phy_speed == PHY_SPEED_100HALF) { + maccr |= ETH_MACCR_FES | ETH_MACCR_PS; + } else if (phy_speed == PHY_SPEED_10FULL) { + maccr |= ETH_MACCR_PS | ETH_MACCR_DM; + } else { + maccr |= ETH_MACCR_PS; + } + #else + maccr &= ~(ETH_MACCR_FES | ETH_MACCR_DM); + if (phy_speed == PHY_SPEED_100FULL) { + maccr |= ETH_MACCR_FES | ETH_MACCR_DM; + } else if (phy_speed == PHY_SPEED_100HALF) { + maccr |= ETH_MACCR_FES; + } else if (phy_speed == PHY_SPEED_10FULL) { + maccr |= ETH_MACCR_DM; + } + // else 10HALF: both bits clear. + #endif + + ETH->MACCR = maccr; + ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE; + + self->mac_reconfig_in_progress = false; + self->mac_speed_configured = true; + + // MAC was reconfigured; restart DHCP if needed. + struct netif *netif = &self->netif; + MICROPY_PY_LWIP_ENTER + eth_dhcp_restart_if_needed(netif); + MICROPY_PY_LWIP_EXIT } - MICROPY_PY_LWIP_EXIT } static void eth_process_frame(eth_t *self, size_t len, const uint8_t *buf) { @@ -1155,30 +1274,73 @@ int eth_link_status(eth_t *self) { return 2; // link no-ip; } } else { - if (eth_phy_read(self->phy_addr, PHY_BSR) & PHY_BSR_LINK_STATUS) { - return 1; // link up + // When enabled, use the cached link status from the background poll. + // When not enabled, do a direct PHY read (with double-read to flush + // the IEEE 802.3 latched-low link status bit). + bool physical_link_up; + if (self->enabled) { + physical_link_up = self->last_link_status; } else { - return 0; // link down + (void)eth_phy_read(self->phy_addr, PHY_BSR); + physical_link_up = (eth_phy_read(self->phy_addr, PHY_BSR) & PHY_BSR_LINK_STATUS) != 0; } + return physical_link_up ? 1 : 0; } } -int eth_start(eth_t *self) { - eth_lwip_deinit(self); +bool eth_is_enabled(eth_t *self) { + return self->enabled; +} - // Make sure Eth is Not in low power mode. +int eth_start(eth_t *self) { + // Make sure Eth is not in low power mode. eth_low_power_mode(self, false); int ret = eth_mac_init(self); if (ret < 0) { return ret; } - eth_lwip_init(self); + + // Initialise the PHY (resets and starts autonegotiation, non-blocking). + ret = eth_phy_init(self); + if (ret < 0) { + eth_mac_deinit(self); + return ret; + } + + MICROPY_PY_LWIP_ENTER + struct netif *n = &self->netif; + netif_set_default(n); + netif_set_up(n); + MICROPY_PY_LWIP_EXIT + + self->enabled = true; + self->last_link_status = false; + self->mac_speed_configured = false; + + // Run an initial poll so that if the link is already up, autoneg can + // start being observed immediately. + eth_phy_link_status_poll(); + return 0; } int eth_stop(eth_t *self) { - eth_lwip_deinit(self); + self->enabled = false; + self->last_link_status = false; + self->mac_speed_configured = false; + + MICROPY_PY_LWIP_ENTER + struct netif *n = &self->netif; + if (netif_dhcp_data(n) != NULL) { + dhcp_stop(n); + } + netif_set_link_down(n); + netif_set_down(n); + MICROPY_PY_LWIP_EXIT + + // Put PHY into low-power mode. + eth_low_power_mode(self, true); eth_mac_deinit(self); return 0; } diff --git a/ports/stm32/eth.h b/ports/stm32/eth.h index 6556f4a7c10..c3ae20168a2 100644 --- a/ports/stm32/eth.h +++ b/ports/stm32/eth.h @@ -41,8 +41,10 @@ int eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type); void eth_set_trace(eth_t *self, uint32_t value); struct netif *eth_netif(eth_t *self); int eth_link_status(eth_t *self); +bool eth_is_enabled(eth_t *self); int eth_start(eth_t *self); int eth_stop(eth_t *self); void eth_low_power_mode(eth_t *self, bool enable); +void eth_phy_link_status_poll(void); #endif // MICROPY_INCLUDED_STM32_ETH_H diff --git a/ports/stm32/eth_phy.h b/ports/stm32/eth_phy.h index 7d4bf4c4689..f3f8e6e31d9 100644 --- a/ports/stm32/eth_phy.h +++ b/ports/stm32/eth_phy.h @@ -35,6 +35,7 @@ #define PHY_BCR (0x0000) #define PHY_BCR_SOFT_RESET (0x8000) #define PHY_BCR_AUTONEG_EN (0x1000) +#define PHY_BCR_AUTONEG_RESTART (0x0200) #define PHY_BCR_POWER_DOWN (0x0800U) #undef PHY_BSR @@ -50,6 +51,11 @@ #define PHY_ANAR_SPEED_100FULL (0x0100) #define PHY_ANAR_IEEE802_3 (0x0001) +// 1000BASE-T Control Register (gigabit advertisement). +#define PHY_1000BTCR (0x0009) +#define PHY_1000BTCR_1000HALF (0x0100) +#define PHY_1000BTCR_1000FULL (0x0200) + #define PHY_SPEED_10HALF (0x01) #define PHY_SPEED_100HALF (0x02) #define PHY_SPEED_1000HALF (0x04) diff --git a/ports/stm32/mpnetworkport.c b/ports/stm32/mpnetworkport.c index 6db3e91ba90..fbe1febe801 100644 --- a/ports/stm32/mpnetworkport.c +++ b/ports/stm32/mpnetworkport.c @@ -32,6 +32,7 @@ #include "py/runtime.h" #include "py/mphal.h" #include "shared/netutils/netutils.h" +#include "eth.h" #include "systick.h" #include "pendsv.h" #include "extmod/modnetwork.h" @@ -70,6 +71,10 @@ static void pyb_lwip_poll(void) { wiznet5k_poll(); #endif + #if defined(MICROPY_HW_ETH_MDC) + eth_phy_link_status_poll(); + #endif + // Run the lwIP internal updates sys_check_timeouts(); diff --git a/ports/stm32/network_lan.c b/ports/stm32/network_lan.c index ea03329add4..53c6e32f76c 100644 --- a/ports/stm32/network_lan.c +++ b/ports/stm32/network_lan.c @@ -78,7 +78,9 @@ static mp_obj_t network_lan_make_new(const mp_obj_type_t *type, size_t n_args, s static mp_obj_t network_lan_active(size_t n_args, const mp_obj_t *args) { network_lan_obj_t *self = MP_OBJ_TO_PTR(args[0]); if (n_args == 1) { - return mp_obj_new_bool(eth_link_status(self->eth)); + // Returns interface enabled state (not link status) + // Use status() to check link/cable connection state + return mp_obj_new_bool(eth_is_enabled(self->eth)); } else { int ret; if (mp_obj_is_true(args[1])) { From caa9a4734e89cf48504d4960f522147f577bd14c Mon Sep 17 00:00:00 2001 From: "Kwabena W. Agyeman" Date: Fri, 5 Jun 2026 19:19:49 -0700 Subject: [PATCH 348/635] stm32: Add support for FDCAN on the STM32N6. N6 is basically the same as H7 with respect to the FDCAN peripheral, and it is configured to use the same buffer settings as H7. That allows a second CAN peripheral to work (eventually, once support is added), with one CAN allocated 50% of buffer resources. Signed-off-by: Kwabena W. Agyeman Signed-off-by: Damien George --- ports/stm32/Makefile | 2 +- ports/stm32/boards/stm32n657_af.csv | 8 ++++---- ports/stm32/can.h | 4 ++-- ports/stm32/fdcan.c | 23 +++++++++++++++++------ ports/stm32/main.c | 1 + ports/stm32/mpconfigboard_common.h | 2 +- ports/stm32/mpconfigport.h | 2 +- ports/stm32/pin_defs_stm32.h | 10 ++++++++++ 8 files changed, 37 insertions(+), 15 deletions(-) diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 195287b5a72..75a4eb5ee3c 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -421,7 +421,7 @@ endif ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f0 f4 f7)) HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_, hal_can.c) -else ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),g0 g4 h7)) +else ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),g0 g4 h7 n6)) HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_, hal_fdcan.c) else ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),l4)) HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/Legacy/stm32$(MCU_SERIES)xx_, hal_can.c) diff --git a/ports/stm32/boards/stm32n657_af.csv b/ports/stm32/boards/stm32n657_af.csv index b269d0497c6..4a7ad20e6d6 100644 --- a/ports/stm32/boards/stm32n657_af.csv +++ b/ports/stm32/boards/stm32n657_af.csv @@ -8,8 +8,8 @@ PortA,PA5 , , , , PortA,PA8 , , , , , , , , , , , , , , , , ,ADC12_INP5 PortA,PA9 , , , , , , , , , , , , , , , , ,ADC12_INP10 PortA,PA10, , , , , , , , , , , , , , , , ,ADC12_INP11/ADC12_INN10 -PortA,PA11, , , , , ,SPI2_NSS ,CAN1_RXFD , ,UART4_RX , , , , , , , ,ADC12_INP12/ADC12_INN11 -PortA,PA12, , , , , ,SPI2_SCK ,CAN1_TXFD , ,UART4_TX , , , , , , , ,ADC12_INP13/ADC12_INN12 +PortA,PA11, , , , , ,SPI2_NSS ,CAN1_RX , ,UART4_RX , , , , , , , ,ADC12_INP12/ADC12_INN11 +PortA,PA12, , , , , ,SPI2_SCK ,CAN1_TX , ,UART4_TX , , , , , , , ,ADC12_INP13/ADC12_INN12 PortB,PB4 , , , , , , , , , , , ,SDMMC2_D3 , , , , , PortB,PB6 , , , , , ,SPI4_MISO , ,TIM15_CH1 , , , , , , , , , PortB,PB7 , , , , , ,SPI4_MOSI , ,TIM15_CH2 , , , , , , , , , @@ -36,8 +36,8 @@ PortE,PE5 , , , , PortE,PE6 , , , , , , , ,USART1_RX , , , , , , , , , PortE,PE7 , , , , , , , , ,UART7_RX , , , , , , , , PortE,PE8 , , , , , , , , ,UART7_TX , , , , , , , , -PortE,PE11, , , , , ,SPI4_NSS ,CAN3_TXFD , , , , , , , , , , -PortE,PE12, , , , , ,SPI4_SCK ,CAN3_RXFD , , , , , , , , , , +PortE,PE11, , , , , ,SPI4_NSS ,CAN3_TX , , , , , , , , , , +PortE,PE12, , , , , ,SPI4_SCK ,CAN3_RX , , , , , , , , , , PortE,PE13, , , , ,I2C4_SCL , , , , , , , , , , , , PortE,PE14, , , , ,I2C4_SDA , , , , , , , , , , , , PortE,PE15, , , , , ,SPI5_SCK , , , , , , , , , , , diff --git a/ports/stm32/can.h b/ports/stm32/can.h index ff73e1a74d2..588a225ef36 100644 --- a/ports/stm32/can.h +++ b/ports/stm32/can.h @@ -62,7 +62,7 @@ #if defined(STM32G4) #define CAN_HW_MAX_STD_FILTER 28 #define CAN_HW_MAX_EXT_FILTER 8 -#elif defined(STM32H7) +#elif defined(STM32H7) || defined(STM32N6) // The RAM filtering section is configured for 64 x 1 word elements for 11-bit standard // identifiers, and 31 x 2 words elements for 29-bit extended identifiers. // The total number of words reserved for the filtering per FDCAN instance is 126 words. @@ -123,7 +123,7 @@ typedef struct { unsigned rx_fifo1_pending; } can_counters_t; -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32N6) #define CAN_TX_QUEUE_LEN 16 #else // FDCAN STM32G4, bxCAN diff --git a/ports/stm32/fdcan.c b/ports/stm32/fdcan.c index a7fcf7330b1..8dba12f7c7a 100644 --- a/ports/stm32/fdcan.c +++ b/ports/stm32/fdcan.c @@ -53,17 +53,22 @@ #define FDCAN_IT_RX_FULL_MASK (FDCAN_IT_RX_FIFO0_FULL | FDCAN_IT_RX_FIFO1_FULL) #define FDCAN_IT_RX_MESSAGE_LOST_MASK (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | FDCAN_IT_RX_FIFO1_MESSAGE_LOST) -#if defined(STM32H7) -// adaptations for H7 to G4 naming convention in HAL +#if defined(STM32H7) || defined(STM32N6) +// adaptations for H7/N6 to G4 naming convention in HAL #define FDCAN_IT_GROUP_RX_FIFO0 (FDCAN_ILS_RF0NL | FDCAN_ILS_RF0FL | FDCAN_ILS_RF0LL) +#if defined(STM32H7) #define FDCAN_IT_GROUP_BIT_LINE_ERROR (FDCAN_ILS_EPE | FDCAN_ILS_ELOE) #define FDCAN_IT_GROUP_PROTOCOL_ERROR (FDCAN_ILS_ARAE | FDCAN_ILS_PEDE | FDCAN_ILS_PEAE | FDCAN_ILS_WDIE | FDCAN_ILS_BOE | FDCAN_ILS_EWE) +#else +#define FDCAN_IT_GROUP_BIT_LINE_ERROR (FDCAN_ILS_EPL | FDCAN_ILS_ELOL) +#define FDCAN_IT_GROUP_PROTOCOL_ERROR (FDCAN_ILS_ARAL | FDCAN_ILS_PEDL | FDCAN_ILS_PEAL | FDCAN_ILS_WDIL | FDCAN_ILS_BOL | FDCAN_ILS_EWL) +#endif #define FDCAN_IT_GROUP_RX_FIFO1 (FDCAN_ILS_RF1NL | FDCAN_ILS_RF1FL | FDCAN_ILS_RF1LL) // The dedicated Message RAM should be 2560 words, but the way it's defined in stm32h7xx_hal_fdcan.c // as (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) limits the usable number of words to 2559 words. #define FDCAN_MESSAGE_RAM_SIZE (2560 - 1) -#endif // STM32H7 +#endif // STM32H7 || STM32N6 #if defined(STM32G4) // These HAL APIs are not implemented for STM32G4, so we implement them here... @@ -146,7 +151,7 @@ bool can_init(CAN_HandleTypeDef *can, int can_id, can_tx_mode_t tx_mode, uint32_ init->DataTimeSeg1 = 1; init->DataTimeSeg2 = 1; init->TxFifoQueueMode = fifo_queue_mode; - #elif defined(STM32H7) + #elif defined(STM32H7) || defined(STM32N6) // The dedicated FDCAN RAM is 2560 32-bit words and shared between the FDCAN instances. // To support 2 FDCAN instances simultaneously, the Message RAM is divided in half by // setting the second FDCAN memory offset to half the RAM size. With this configuration, @@ -189,7 +194,7 @@ bool can_init(CAN_HandleTypeDef *can, int can_id, can_tx_mode_t tx_mode, uint32_ init->RxFifo0ElmtSize = FDCAN_DATA_BYTES_64; init->RxFifo1ElmtsNbr = 24; init->RxFifo1ElmtSize = FDCAN_DATA_BYTES_64; - #endif // STM32H7 + #endif // STM32H7 || STM32N6 const machine_pin_obj_t *pins[2]; @@ -316,7 +321,9 @@ void can_clearfilter(FDCAN_HandleTypeDef *can, uint32_t f, bool is_extid) { uint32_t can_get_source_freq(void) { // Find CAN kernel clock - #if defined(STM32H7) + #if defined(STM32N6) + return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN); + #elif defined(STM32H7) switch (__HAL_RCC_GET_FDCAN_SOURCE()) { case RCC_FDCANCLKSOURCE_HSE: return HSE_VALUE; @@ -362,7 +369,11 @@ static void encode_datalength(CanTxMsgTypeDef *txmsg) { size_t len_bytes = txmsg->DataLength; for (mp_uint_t i = 0; i < MP_ARRAY_SIZE(DLCtoBytes); i++) { if (len_bytes <= DLCtoBytes[i]) { + #if defined(STM32N6) + txmsg->DataLength = i; + #else txmsg->DataLength = (i << 16); + #endif return; } } diff --git a/ports/stm32/main.c b/ports/stm32/main.c index 1189d317bb8..fae361af276 100644 --- a/ports/stm32/main.c +++ b/ports/stm32/main.c @@ -420,6 +420,7 @@ void stm32_main(uint32_t reset_mode) { // Enable some APB peripherals during sleep. LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_ALL); // I2C, I3C, LPTIM, SPI, TIM, UART, WWDG + LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN); // FDCAN LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_ALL); // SAI, SPI, TIM, UART LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_ALL); // I2C, LPTIM, LPUART, RTC, SPI #endif diff --git a/ports/stm32/mpconfigboard_common.h b/ports/stm32/mpconfigboard_common.h index 30314a38a59..3b8b644f2cd 100644 --- a/ports/stm32/mpconfigboard_common.h +++ b/ports/stm32/mpconfigboard_common.h @@ -743,7 +743,7 @@ void mp_usbd_ll_init(void); // Enable CAN if there are any peripherals defined #if defined(MICROPY_HW_CAN1_TX) || defined(MICROPY_HW_CAN2_TX) || defined(MICROPY_HW_CAN3_TX) #define MICROPY_HW_ENABLE_CAN (1) -#if defined(STM32G0) || defined(STM32G4) || defined(STM32H7) +#if defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32N6) #define MICROPY_HW_ENABLE_FDCAN (1) // define for MCUs with FDCAN #endif #else diff --git a/ports/stm32/mpconfigport.h b/ports/stm32/mpconfigport.h index 79933ee7ff8..ea1b73bece0 100644 --- a/ports/stm32/mpconfigport.h +++ b/ports/stm32/mpconfigport.h @@ -122,7 +122,7 @@ #define MICROPY_PY_MACHINE_BITSTREAM (1) #endif #ifndef MICROPY_PY_MACHINE_CAN -#if defined(MICROPY_HW_CAN1_TX) || defined(MICROPY_HW_CAN2_TX) +#if defined(MICROPY_HW_CAN1_TX) || defined(MICROPY_HW_CAN2_TX) || defined(MICROPY_HW_CAN3_TX) #define MICROPY_PY_MACHINE_CAN (1) #else #define MICROPY_PY_MACHINE_CAN (0) diff --git a/ports/stm32/pin_defs_stm32.h b/ports/stm32/pin_defs_stm32.h index 645ec5b2df5..1020381abb8 100644 --- a/ports/stm32/pin_defs_stm32.h +++ b/ports/stm32/pin_defs_stm32.h @@ -133,6 +133,16 @@ enum { #define GPIO_AF9_CAN2 GPIO_AF9_FDCAN2 #endif +#if defined(STM32N6) +// Make N6 FDCAN more like CAN +#define CAN1 FDCAN1 +#define CAN2 FDCAN2 +#define CAN3 FDCAN3 +#define GPIO_AF6_CAN1 GPIO_AF6_FDCAN1 +#define GPIO_AF6_CAN2 GPIO_AF6_FDCAN2 +#define GPIO_AF6_CAN3 GPIO_AF6_FDCAN3 +#endif + enum { PIN_ADC1 = (1 << 0), PIN_ADC2 = (1 << 1), From 34fcee1cfffbc304bf0cda006b8986518b5c5011 Mon Sep 17 00:00:00 2001 From: "Kwabena W. Agyeman" Date: Fri, 5 Jun 2026 19:20:17 -0700 Subject: [PATCH 349/635] stm32/boards/OPENMV_N6: Enable FDCAN on the OpenMV N6. Signed-off-by: Kwabena W. Agyeman Signed-off-by: Damien George --- ports/stm32/boards/OPENMV_N6/mpconfigboard.h | 9 +++++++++ ports/stm32/boards/OPENMV_N6/pins.csv | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/ports/stm32/boards/OPENMV_N6/mpconfigboard.h b/ports/stm32/boards/OPENMV_N6/mpconfigboard.h index 0d63ff22478..2cee30ea339 100644 --- a/ports/stm32/boards/OPENMV_N6/mpconfigboard.h +++ b/ports/stm32/boards/OPENMV_N6/mpconfigboard.h @@ -77,6 +77,15 @@ #define MICROPY_HW_SPI4_MISO (pyb_pin_SPI4_MISO) #define MICROPY_HW_SPI4_MOSI (pyb_pin_SPI4_MOSI) +// FDCAN bus +#define MICROPY_HW_CAN1_NAME "FDCAN1" +#define MICROPY_HW_CAN1_TX (pyb_pin_CAN1_TX) +#define MICROPY_HW_CAN1_RX (pyb_pin_CAN1_RX) +// Support is not yet added for FDCAN CAN3 (see fdcan.c for details) +// #define MICROPY_HW_CAN3_NAME "FDCAN3" +// #define MICROPY_HW_CAN3_TX (pyb_pin_CAN3_TX) +// #define MICROPY_HW_CAN3_RX (pyb_pin_CAN3_RX) + // USER is pulled high, and pressing the button makes the input go low. #define MICROPY_HW_USRSW_PIN (pyb_pin_BUTTON) #define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) diff --git a/ports/stm32/boards/OPENMV_N6/pins.csv b/ports/stm32/boards/OPENMV_N6/pins.csv index 2ca075a154a..7c36181c016 100644 --- a/ports/stm32/boards/OPENMV_N6/pins.csv +++ b/ports/stm32/boards/OPENMV_N6/pins.csv @@ -13,6 +13,8 @@ SPI2_CS,PA11 SPI2_SCK,PA12 UART4_RX,PA11 UART4_TX,PA12 +CAN1_RX,PA11 +CAN1_TX,PA12 P3,PA11 P2,PA12 ,PA13 @@ -92,6 +94,8 @@ SPI4_CS,PE11 SPI4_SCK,PE12 P15,PE11 P16,PE12 +CAN3_TX,PE11 +CAN3_RX,PE12 I2C4_SCL,PE13 I2C4_SDA,PE14 ,PE15 From 3ecd415ac6f96510d3147e2a79b0eb96ab76bbda Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 12 Jun 2026 10:28:22 +1000 Subject: [PATCH 350/635] tests/ports/stm32/pyb_can.py: Update test to run on STM32N6. Changes: - Use the same deep-tx-queue logic as the STM32H7. - Use `time.sleep_ms()` instead of `pyb.delay()` (the latter is not available on all stm32 boards). This test now passes on OPENMV_N6. Signed-off-by: Damien George --- tests/ports/stm32/pyb_can.py | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/tests/ports/stm32/pyb_can.py b/tests/ports/stm32/pyb_can.py index a1a3ac2cbd1..e8214d8e47b 100644 --- a/tests/ports/stm32/pyb_can.py +++ b/tests/ports/stm32/pyb_can.py @@ -8,14 +8,16 @@ import micropython import pyb import sys +import time # Classic CAN (aka bxCAN) hardware has a different filter API # and some different behaviours to newer FDCAN hardware IS_CLASSIC = hasattr(CAN, "MASK16") -# STM32H7 series has a gold-plated FDCAN peripheral with much deeper TX Queue +# STM32H7/STM32N6 series have a gold-plated FDCAN peripheral with much deeper TX Queue # than all other parts -IS_H7 = (not IS_CLASSIC) and "STM32H7" in str(sys.implementation) +sys_impl = str(sys.implementation) +HAS_DEEP_TXQ = (not IS_CLASSIC) and ("STM32H7" in sys_impl or "STM32N6" in sys_impl) # test we can correctly create by id (2 handled in can2.py test) for bus in (-1, 0, 1, 4): @@ -52,7 +54,7 @@ can.setfilter(0, CAN.MASK, 0, (0, 0), extframe=False) can.send("abcd", 123, timeout=5000) -pyb.delay(10) # For FDCAN, needs some time to send +time.sleep_ms(10) # For FDCAN, needs some time to send print("any+info", can.any(0), can.info()) print(can.recv(0)) @@ -168,7 +170,7 @@ except ValueError: print("failed") else: - pyb.delay(10) + time.sleep_ms(10) r = can.recv(0) if r[0] == 0x7FF + 1 and r[4] == b"abcde": print("extframe passed") @@ -190,13 +192,13 @@ can.setfilter(0, CAN.MASK, 0, (filter_id, filter_mask), extframe=True) can.send("ok", id_ok, timeout=5, extframe=True) - pyb.delay(10) + time.sleep_ms(10) if can.any(0): msg = can.recv(0) print((hex(filter_id), hex(filter_mask), hex(msg[0]), msg[1], msg[4])) can.send("fail", id_fail, timeout=5, extframe=True) - pyb.delay(10) + time.sleep_ms(10) if can.any(0): msg = can.recv(0) print((hex(filter_id), hex(filter_mask), hex(msg[0]), msg[1], msg[4])) @@ -227,10 +229,10 @@ can.send("abcde", 2, timeout=0) can.send("abcde", 3, timeout=0) can.send("abcde", 4, timeout=0) - if not IS_H7: + if not HAS_DEEP_TXQ: can.send("abcde", 5, timeout=0) else: - # Hack around the STM32H7's deeper transmit queue by pretending this call failed + # Hack around a deep transmit queue by pretending this call failed # (STM32G4 will fail here, using otherwise the same code, so there is still some test coverage.) print("send fail ok") except OSError as e: @@ -240,7 +242,7 @@ else: print("send fail not ok", e) -pyb.delay(500) +time.sleep_ms(500) while can.any(0): print(can.recv(0)) From 644d03bb547d8fcd4729fbee043c35a9b260dfc5 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 12 Jun 2026 10:33:19 +1000 Subject: [PATCH 351/635] stm32/fdcan: Initialise all entries in FDCAN_InitTypeDef struct. These aren't technically needed, but good to make sure they are populated. Signed-off-by: Damien George --- ports/stm32/fdcan.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/ports/stm32/fdcan.c b/ports/stm32/fdcan.c index 8dba12f7c7a..afec60e3c87 100644 --- a/ports/stm32/fdcan.c +++ b/ports/stm32/fdcan.c @@ -137,6 +137,11 @@ bool can_init(CAN_HandleTypeDef *can, int can_id, can_tx_mode_t tx_mode, uint32_ init->NominalTimeSeg1 = bs1; // NominalTimeSeg1 = Propagation_segment + Phase_segment_1 init->NominalTimeSeg2 = bs2; + init->DataPrescaler = 1; + init->DataSyncJumpWidth = 1; + init->DataTimeSeg1 = 1; + init->DataTimeSeg2 = 1; + init->AutoRetransmission = ENABLE; init->TransmitPause = DISABLE; init->ProtocolException = ENABLE; @@ -146,10 +151,6 @@ bool can_init(CAN_HandleTypeDef *can, int can_id, can_tx_mode_t tx_mode, uint32_ #if defined(STM32G4) init->ClockDivider = FDCAN_CLOCK_DIV1; - init->DataPrescaler = 1; - init->DataSyncJumpWidth = 1; - init->DataTimeSeg1 = 1; - init->DataTimeSeg2 = 1; init->TxFifoQueueMode = fifo_queue_mode; #elif defined(STM32H7) || defined(STM32N6) // The dedicated FDCAN RAM is 2560 32-bit words and shared between the FDCAN instances. @@ -190,6 +191,7 @@ bool can_init(CAN_HandleTypeDef *can, int can_id, can_tx_mode_t tx_mode, uint32_ // 2 words header + 16 words data field (to support up to 64 bytes of data). // The total number of words reserved for the Rx FIFOs per FDCAN instance is 864 words. init->RxBuffersNbr = 0; + init->RxBufferSize = FDCAN_DATA_BYTES_64; init->RxFifo0ElmtsNbr = 24; init->RxFifo0ElmtSize = FDCAN_DATA_BYTES_64; init->RxFifo1ElmtsNbr = 24; From 964803ab744297c82a9fc3cd0c71c6cf60eec6d2 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Thu, 14 May 2026 17:08:45 +1000 Subject: [PATCH 352/635] nrf: Restore interrupt-based I2C with nrfx v3. The nrfx v3 update changed the TWI/TWIM xfer flag encoding (NOSTOP now collides with POSTINC) and the SUSPEND/repeated-start behaviour (disable between bursts releases the bus, breaking readfrom_mem/writeto_mem). Signed-off-by: Andrew Leech --- ports/nrf/modules/machine/i2c.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/ports/nrf/modules/machine/i2c.c b/ports/nrf/modules/machine/i2c.c index e2b7a19a27d..2a45f80efff 100644 --- a/ports/nrf/modules/machine/i2c.c +++ b/ports/nrf/modules/machine/i2c.c @@ -69,6 +69,8 @@ #define NRFX_TWI_EVT_DATA_NACK NRFX_TWIM_EVT_DATA_NACK #define NRFX_TWI_EVT_BUS_ERROR NRFX_TWIM_EVT_BUS_ERROR +#define NRFX_TWI_FLAG_TX_NO_STOP NRFX_TWIM_FLAG_TX_NO_STOP + #define NRF_TWI_FREQ_100K NRF_TWIM_FREQ_100K #define NRF_TWI_FREQ_250K NRF_TWIM_FREQ_250K #define NRF_TWI_FREQ_400K NRF_TWIM_FREQ_400K @@ -157,6 +159,7 @@ mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, siz config.frequency = freq; config.hold_bus_uninit = false; + config.interrupt_priority = 6; // First reset the TWI nrfx_twi_uninit(&self->p_twi); @@ -182,7 +185,8 @@ int machine_hard_i2c_transfer_single(mp_obj_base_t *self_in, uint16_t addr, size err_code = nrfx_twi_xfer(&self->p_twi, &desc, 0); } else { nrfx_twi_xfer_desc_t desc = NRFX_TWI_XFER_DESC_TX(addr, buf, len); - err_code = nrfx_twi_xfer(&self->p_twi, &desc, (flags & MP_MACHINE_I2C_FLAG_STOP) == 0); + uint32_t xfer_flags = (flags & MP_MACHINE_I2C_FLAG_STOP) ? 0 : NRFX_TWI_FLAG_TX_NO_STOP; + err_code = nrfx_twi_xfer(&self->p_twi, &desc, xfer_flags); transfer_ret = len; } @@ -198,8 +202,7 @@ int machine_hard_i2c_transfer_single(mp_obj_base_t *self_in, uint16_t addr, size return -MP_ETIMEDOUT; } - // Poll for transfer completion with timeout (timeout=0 means no timeout, - // the loop relies on MICROPY_EVENT_POLL_HOOK for Ctrl-C). + // Poll until xfer_done (timeout=0 means wait forever). mp_uint_t start = mp_hal_ticks_us(); while (!self->xfer_done) { if (self->timeout > 0 && (mp_hal_ticks_us() - start) >= self->timeout) { @@ -207,10 +210,14 @@ int machine_hard_i2c_transfer_single(mp_obj_base_t *self_in, uint16_t addr, size nrfx_twi_enable(&self->p_twi); return -MP_ETIMEDOUT; } - MICROPY_EVENT_POLL_HOOK; + mp_event_wait_ms(1); } - nrfx_twi_disable(&self->p_twi); + // Leave the peripheral SUSPENDED (enabled, bus held) after a NOSTOP TX + // so the next xfer issues a repeated START. Disabling would release SDA. + if (flags & (MP_MACHINE_I2C_FLAG_READ | MP_MACHINE_I2C_FLAG_STOP)) { + nrfx_twi_disable(&self->p_twi); + } if (self->xfer_evt == NRFX_TWI_EVT_ADDRESS_NACK) { return -MP_ENODEV; From c864b8b7758018d81a2a0f6740e906a3e57ac3e5 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 9 Jun 2026 15:45:38 +0200 Subject: [PATCH 353/635] py: Fix build with no error detail reporting enabled. This commit fixes two build errors occurring when building any modern port with error detail reporting is not enabled (ie. `MICROPY_ERROR_REPORTING` is set to `MICROPY_ERROR_REPORTING_NONE` when building). Signed-off-by: Alessandro Gatti --- py/emitnative.c | 2 ++ py/nativeglue.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/py/emitnative.c b/py/emitnative.c index 7bf50fbde80..7533f8374f1 100644 --- a/py/emitnative.c +++ b/py/emitnative.c @@ -204,6 +204,7 @@ typedef enum { VTYPE_BUILTIN_CAST = 0x70 | MP_NATIVE_TYPE_OBJ, } vtype_kind_t; +#if MICROPY_ERROR_REPORTING != MICROPY_ERROR_REPORTING_NONE static qstr vtype_to_qstr(vtype_kind_t vtype) { switch (vtype) { case VTYPE_PYOBJ: @@ -227,6 +228,7 @@ static qstr vtype_to_qstr(vtype_kind_t vtype) { return MP_QSTR_None; } } +#endif typedef struct _stack_info_t { vtype_kind_t vtype; diff --git a/py/nativeglue.c b/py/nativeglue.c index e4aa635cf1c..e9164ee4c20 100644 --- a/py/nativeglue.c +++ b/py/nativeglue.c @@ -320,7 +320,11 @@ const mp_fun_table_t mp_fun_table = { gc_realloc, mp_printf, mp_vprintf, + #if MICROPY_ERROR_REPORTING == MICROPY_ERROR_REPORTING_NONE + NULL, + #else mp_raise_msg, + #endif mp_obj_get_type, mp_obj_new_str, mp_obj_new_bytes, From 2fb658e787198188ae1984a9b081faadc86c89c4 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 9 Jun 2026 15:48:09 +0200 Subject: [PATCH 354/635] tests/feature_check/target_info.py: Work with error reporting disabled. This commit updates the target info reporting script to work correctly even when error reporting is disabled, effectively skipping any error message attached to exceptions. The code expected the exception message to be an empty string, but it is `None` instead, making the script fail and the test runner not able to execute tests. Signed-off-by: Alessandro Gatti --- tests/feature_check/target_info.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/feature_check/target_info.py b/tests/feature_check/target_info.py index ed91b27b775..acd6a04d81c 100644 --- a/tests/feature_check/target_info.py +++ b/tests/feature_check/target_info.py @@ -40,6 +40,6 @@ try: (lambda: 0)(0) except TypeError as er: - error_reporting = {0: "none", 27: "terse", 54: "normal", 56: "detailed"}[len(er.value)] + error_reporting = {0: "none", 27: "terse", 54: "normal", 56: "detailed"}[len(er.value or "")] print(platform, arch, arch_flags, build, thread, float_prec, len("α") == 1, error_reporting) From 3be043f5c131c3562a479e7cf2649ae80e80f51f Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 9 Jun 2026 17:12:58 +0200 Subject: [PATCH 355/635] tests/run-tests.py: Update tests skip list for no detailed errors. This commit updates the list of tests to skip if the error message level is "none", adding `extmod/asyncio_gather_notimpl.py`. `extmod/asyncio_gather_notimpl.py` in its current form depends on runtime exceptions to have different error messages to identify certain situations. Since when the interpreter is configured to report errors with no details except for the exception type, this test cannot be relied upon in this case. Signed-off-by: Alessandro Gatti --- tests/run-tests.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tests/run-tests.py b/tests/run-tests.py index 83c8d2a6e72..d5a0fbd9a9a 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -197,8 +197,8 @@ # Tests to skip when MICROPY_ERROR_REPORTING is at a certain level. error_reporting_tests_to_skip = { - # Skip at level MICROPY_ERROR_REPORTING_NONE. - "none": ( + # Skip at level MICROPY_ERROR_REPORTING_TERSE. + "terse": ( "cmdline/repl_paste.py", # This test needs updates before being removed from this list. "extmod/vfs_blockdev_invalid.py", @@ -209,8 +209,10 @@ "misc/sys_settrace_features.py", ), } -# Skip at level MICROPY_ERROR_REPORTING_TERSE. -error_reporting_tests_to_skip["terse"] = error_reporting_tests_to_skip["none"] +# Skip at level MICROPY_ERROR_REPORTING_NONE. +error_reporting_tests_to_skip["none"] = error_reporting_tests_to_skip["terse"] + ( + "extmod/asyncio_gather_notimpl.py", +) # Tests with known intermittent failures. These tests still run, but failures # are reclassified as "ignored" instead of "fail" so they don't affect the CI From 91199cbb96dc01d49b3114253c23ca74c92205b5 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 9 Jun 2026 17:06:23 +0200 Subject: [PATCH 356/635] tests/basics: Fix tests with no error details. This commit updates `basics/deque_micropython`, `basics/generator_pend_throw`, `basics/int_64_basics`, and `basics/subclass_native_exc_new` tests to also pass even if the interpreter was built with no detailed error messages. Originally the tests assumed the error messages level was always higher than `MICROPY_ERROR_REPORTING_NONE`, and thus expected a particular string pattern to appear in certain errors' output. Signed-off-by: Alessandro Gatti --- tests/basics/deque_micropython.py | 10 +++++----- tests/basics/deque_micropython.py.exp | 10 +++++----- tests/basics/generator_pend_throw.py | 4 ++-- tests/basics/generator_pend_throw.py.exp | 4 ++-- tests/basics/int_64_basics.py | 4 ++-- tests/basics/subclass_native_exc_new.py | 4 ++-- tests/basics/subclass_native_exc_new.py.exp | 4 ++-- 7 files changed, 20 insertions(+), 20 deletions(-) diff --git a/tests/basics/deque_micropython.py b/tests/basics/deque_micropython.py index 5f32bbc496a..fb9771fefeb 100644 --- a/tests/basics/deque_micropython.py +++ b/tests/basics/deque_micropython.py @@ -45,12 +45,12 @@ try: d.popleft() except IndexError as e: - print(repr(e)) + print(str(e) or 'empty', len(d)) try: d.pop() except IndexError as e: - print(repr(e)) + print(str(e) or 'empty', len(d)) d.append(5) d.append(6) @@ -58,12 +58,12 @@ try: d.append(7) except IndexError as e: - print(repr(e)) + print(str(e) or 'full', len(d)) try: d.appendleft(8) except IndexError as e: - print(repr(e)) + print(str(e) or 'full', len(d)) print(len(d)) @@ -72,4 +72,4 @@ try: d.popleft() except IndexError as e: - print(repr(e)) + print(str(e) or 'empty', len(d)) diff --git a/tests/basics/deque_micropython.py.exp b/tests/basics/deque_micropython.py.exp index f1ff7b77ac8..7869dc8cacc 100644 --- a/tests/basics/deque_micropython.py.exp +++ b/tests/basics/deque_micropython.py.exp @@ -6,12 +6,12 @@ None 1 2 3 4 -IndexError('empty',) -IndexError('empty',) +empty 0 +empty 0 2 -IndexError('full',) -IndexError('full',) +full 2 +full 2 2 5 6 0 -IndexError('empty',) +empty 0 diff --git a/tests/basics/generator_pend_throw.py b/tests/basics/generator_pend_throw.py index ae8c21189e9..6cecd418dd0 100644 --- a/tests/basics/generator_pend_throw.py +++ b/tests/basics/generator_pend_throw.py @@ -46,7 +46,7 @@ def gen_next(): try: next(g) except Exception as e: - print("raised", repr(e)) + print("raised {} {}".format(type(e), str(e) or "generator already executing")) # Verify that you can't pend_throw from within the running coroutine. @@ -59,7 +59,7 @@ def gen_pend_throw(): try: next(g) except Exception as e: - print("raised", repr(e)) + print("raised {} {}".format(type(e), str(e) or "generator already executing")) # Verify that the pend_throw exception can be ignored. diff --git a/tests/basics/generator_pend_throw.py.exp b/tests/basics/generator_pend_throw.py.exp index 8a3dadfec7a..56fa68be252 100644 --- a/tests/basics/generator_pend_throw.py.exp +++ b/tests/basics/generator_pend_throw.py.exp @@ -3,8 +3,8 @@ raised ValueError() ret was: None raised OSError() -raised ValueError('generator already executing',) -raised ValueError('generator already executing',) +raised generator already executing +raised generator already executing 0 ignore CancelledError 1 diff --git a/tests/basics/int_64_basics.py b/tests/basics/int_64_basics.py index ef76793317e..b9d46c7d701 100644 --- a/tests/basics/int_64_basics.py +++ b/tests/basics/int_64_basics.py @@ -145,12 +145,12 @@ try: print((1 << 48) >> -4) except ValueError as e: - print(e) + print(str(e) or "negative shift count") try: print((1 << 48) << -6) except ValueError as e: - print(e) + print(str(e) or "negative shift count") # Test that the most extreme 64 bit integer values all parse with int() print(int("-9223372036854775807")) diff --git a/tests/basics/subclass_native_exc_new.py b/tests/basics/subclass_native_exc_new.py index a431392eaa4..87be6c76026 100644 --- a/tests/basics/subclass_native_exc_new.py +++ b/tests/basics/subclass_native_exc_new.py @@ -26,7 +26,7 @@ def __new__(cls, *args, **kwargs): raise BadException("bad message") except Exception as bad: # Should be TypeError 'exceptions must derive from BaseException' - print(type(bad), bad.args[0]) + print(type(bad), bad.args or ("exceptions must derive from BaseException",)) try: def gen(): @@ -35,4 +35,4 @@ def gen(): gen().throw(BadException) except Exception as genbad: # Should be TypeError 'exceptions must derive from BaseException' - print(type(genbad), genbad.args[0]) + print(type(genbad), genbad.args or ("exceptions must derive from BaseException",)) diff --git a/tests/basics/subclass_native_exc_new.py.exp b/tests/basics/subclass_native_exc_new.py.exp index 65709b2ccf2..d2b770e8aa1 100644 --- a/tests/basics/subclass_native_exc_new.py.exp +++ b/tests/basics/subclass_native_exc_new.py.exp @@ -1,6 +1,6 @@ GoodException __new__ good message BadException __new__ - exceptions must derive from BaseException + ('exceptions must derive from BaseException',) BadException __new__ - exceptions must derive from BaseException + ('exceptions must derive from BaseException',) From 9207ce1f24da03a959c1f156b4a6ae96060309bb Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 9 Jun 2026 17:19:06 +0200 Subject: [PATCH 357/635] tests/extmod: Fix tests with no error details. This commit updates `extmod/asyncio_cancel_self`, `extmod/cryptolib_aes12_ctr`, `extmod/ssl_cadata`, `extmod/ssl_keycert`, and `extmod/ssl_keycert_pkcs8` tests to also pass even if the interpreter was built with no detailed error messages. Originally the tests assumed the error messages level was always higher than `MICROPY_ERROR_REPORTING_NONE`, and thus expected a particular string pattern to appear in certain errors' output. Signed-off-by: Alessandro Gatti --- tests/extmod/asyncio_cancel_self.py | 2 +- tests/extmod/cryptolib_aes128_ctr.py | 2 +- tests/extmod/ssl_cadata.py | 2 +- tests/extmod/ssl_cadata.py.exp | 2 +- tests/extmod/ssl_keycert.py | 4 ++-- tests/extmod/ssl_keycert.py.exp | 4 ++-- tests/extmod/ssl_keycert_pkcs8.py | 2 +- tests/extmod/ssl_keycert_pkcs8.py.exp | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) diff --git a/tests/extmod/asyncio_cancel_self.py b/tests/extmod/asyncio_cancel_self.py index a437edb5403..3ed3ee88214 100644 --- a/tests/extmod/asyncio_cancel_self.py +++ b/tests/extmod/asyncio_cancel_self.py @@ -25,4 +25,4 @@ async def main(): try: asyncio.run(main()) except RuntimeError as er: - print(er) + print(str(er) or "can't cancel self") diff --git a/tests/extmod/cryptolib_aes128_ctr.py b/tests/extmod/cryptolib_aes128_ctr.py index b5066fb7b48..ee9b503b066 100644 --- a/tests/extmod/cryptolib_aes128_ctr.py +++ b/tests/extmod/cryptolib_aes128_ctr.py @@ -13,7 +13,7 @@ def _new(k, ctr_initial): _new(b"x" * 16, b"x" * 16) except ValueError as e: # is CTR support disabled? - if e.args[0] == "mode": + if len(e.args) == 0 or e.args[0] == "mode": print("SKIP") raise SystemExit raise e diff --git a/tests/extmod/ssl_cadata.py b/tests/extmod/ssl_cadata.py index 21d86b13fb0..2a0f18c57d1 100644 --- a/tests/extmod/ssl_cadata.py +++ b/tests/extmod/ssl_cadata.py @@ -15,4 +15,4 @@ print("SKIP") raise SystemExit except ValueError as er: - print(repr(er)) + print(str(er) or "invalid cert") diff --git a/tests/extmod/ssl_cadata.py.exp b/tests/extmod/ssl_cadata.py.exp index 9f1cf732e33..4a398036501 100644 --- a/tests/extmod/ssl_cadata.py.exp +++ b/tests/extmod/ssl_cadata.py.exp @@ -1 +1 @@ -ValueError('invalid cert',) +invalid cert diff --git a/tests/extmod/ssl_keycert.py b/tests/extmod/ssl_keycert.py index 811515f2676..0bb923dedac 100644 --- a/tests/extmod/ssl_keycert.py +++ b/tests/extmod/ssl_keycert.py @@ -13,7 +13,7 @@ try: ssl.wrap_socket(io.BytesIO(), key=b"!") except ValueError as er: - print(repr(er)) + print(str(er) or "invalid key") # Valid key, no cert try: @@ -26,4 +26,4 @@ try: ssl.wrap_socket(io.BytesIO(), key=key, cert=b"!") except ValueError as er: - print(repr(er)) + print(str(er) or "invalid cert") diff --git a/tests/extmod/ssl_keycert.py.exp b/tests/extmod/ssl_keycert.py.exp index bce95c2b6cd..075abfcde0e 100644 --- a/tests/extmod/ssl_keycert.py.exp +++ b/tests/extmod/ssl_keycert.py.exp @@ -1,3 +1,3 @@ -ValueError('invalid key',) +invalid key TypeError -ValueError('invalid cert',) +invalid cert diff --git a/tests/extmod/ssl_keycert_pkcs8.py b/tests/extmod/ssl_keycert_pkcs8.py index beef7275d81..05a594b34d7 100644 --- a/tests/extmod/ssl_keycert_pkcs8.py +++ b/tests/extmod/ssl_keycert_pkcs8.py @@ -21,4 +21,4 @@ try: ssl.wrap_socket(io.BytesIO(), key=keypkcs8, cert=b"!") except ValueError as er: - print(repr(er)) + print(str(er) or "invalid cert") diff --git a/tests/extmod/ssl_keycert_pkcs8.py.exp b/tests/extmod/ssl_keycert_pkcs8.py.exp index 9f1cf732e33..4a398036501 100644 --- a/tests/extmod/ssl_keycert_pkcs8.py.exp +++ b/tests/extmod/ssl_keycert_pkcs8.py.exp @@ -1 +1 @@ -ValueError('invalid cert',) +invalid cert From 6d87df5944c7fc97182db32c1dd30f6123a20924 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 9 Jun 2026 17:30:39 +0200 Subject: [PATCH 358/635] tests/float/math: Fix tests with no error details. This commit updates `float/math_fun` and `float/math_fun_special` tests to also pass even if the interpreter was built with no detailed error messages. Originally the tests assumed the error messages level was always higher than `MICROPY_ERROR_REPORTING_NONE`, and thus expected a particular string pattern to appear in certain errors' output. Signed-off-by: Alessandro Gatti --- tests/float/math_fun.py | 2 +- tests/float/math_fun_special.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/float/math_fun.py b/tests/float/math_fun.py index 05f8be08fa0..9cc2427ac70 100644 --- a/tests/float/math_fun.py +++ b/tests/float/math_fun.py @@ -43,7 +43,7 @@ ans = "{:.5g}".format(function(value)) except ValueError as e: ans = str(e) - if ans.startswith("expected a "): + if ans.startswith("expected a ") or ans == "": # CPython 3.14 changed messages to be more detailed; convert them back to simple ones ans = "math domain error" print("{}({:.5g}) = {}".format(function_name, value, ans)) diff --git a/tests/float/math_fun_special.py b/tests/float/math_fun_special.py index fcf6175af73..e5432ed32e2 100644 --- a/tests/float/math_fun_special.py +++ b/tests/float/math_fun_special.py @@ -51,7 +51,7 @@ ans = "{:.4g}".format(function(value)) except ValueError as e: ans = str(e) - if ans.startswith("expected a "): + if ans.startswith("expected a ") or ans == "": # CPython 3.14 changed messages to be more detailed; convert them back to simple ones ans = "math domain error" # a tiny error in REPR_C value for 1.5204998778 causes a wrong rounded value From fcd9cca30bbbc1592c56ebc0b29bf8cfedd8d90e Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 9 Jun 2026 17:59:50 +0200 Subject: [PATCH 359/635] tests/stress: Fix tests with no error details. This commit updates `stress/bytecode_limit`, `stress/qstr_limit`, and `stress/qstr_limit_str_modulo` tests to also pass even if the interpreter was built with no detailed error messages. Originally the tests assumed the error messages level was always higher than `MICROPY_ERROR_REPORTING_NONE`, and thus expected a particular string pattern to appear in certain errors' output. Signed-off-by: Alessandro Gatti --- tests/stress/bytecode_limit.py | 2 +- tests/stress/bytecode_limit.py.exp | 2 +- tests/stress/qstr_limit.py | 16 +++++----- tests/stress/qstr_limit.py.exp | 46 +++++++++++++-------------- tests/stress/qstr_limit_str_modulo.py | 2 +- 5 files changed, 34 insertions(+), 34 deletions(-) diff --git a/tests/stress/bytecode_limit.py b/tests/stress/bytecode_limit.py index 0a72b66fa05..7e77cdd5e5a 100644 --- a/tests/stress/bytecode_limit.py +++ b/tests/stress/bytecode_limit.py @@ -23,7 +23,7 @@ print("SKIP") raise SystemExit except RuntimeError as er: - results.append(repr(er)) + results.append("RuntimeError('{}')".format(str(er) or "bytecode overflow")) print(results) # Test changing size of code info (source line/bytecode mapping) due to changing diff --git a/tests/stress/bytecode_limit.py.exp b/tests/stress/bytecode_limit.py.exp index 50511665f00..3f1eb0db4c4 100644 --- a/tests/stress/bytecode_limit.py.exp +++ b/tests/stress/bytecode_limit.py.exp @@ -1,4 +1,4 @@ cond false cond false -["RuntimeError('bytecode overflow',)", "RuntimeError('bytecode overflow',)", 'ok', 'ok'] +["RuntimeError('bytecode overflow')", "RuntimeError('bytecode overflow')", 'ok', 'ok'] [123] diff --git a/tests/stress/qstr_limit.py b/tests/stress/qstr_limit.py index c7bd437f3ad..55b87075df9 100644 --- a/tests/stress/qstr_limit.py +++ b/tests/stress/qstr_limit.py @@ -13,7 +13,7 @@ def make_id(n, base="a"): try: exec(var + "=1", g) except RuntimeError as er: - print("RuntimeError", er, l) + print(str(er) or "name too long", l) continue print(var in g) @@ -27,7 +27,7 @@ def f(**k): try: exec("f({}=1)".format(make_id(l))) except RuntimeError as er: - print("RuntimeError", er, l) + print(str(er) or "name too long", l) # type construction for l in range(254, 259): @@ -35,7 +35,7 @@ def f(**k): try: print(type(id, (), {})) except RuntimeError as er: - print("RuntimeError", er, l) + print(str(er) or "name too long", l) # hasattr, setattr, getattr @@ -49,11 +49,11 @@ class A: try: setattr(a, id, 123) except RuntimeError as er: - print("RuntimeError", er, l) + print(str(er) or "name too long", l) try: print(hasattr(a, id), getattr(a, id)) except RuntimeError as er: - print("RuntimeError", er, l) + print(str(er) or "name too long", l) # format with keys for l in range(254, 259): @@ -61,7 +61,7 @@ class A: try: print(("{" + id + "}").format(**{id: l})) except RuntimeError as er: - print("RuntimeError", er, l) + print(str(er) or "name too long", l) # import module # (different OS's have different results so only run those that are consistent) @@ -71,7 +71,7 @@ class A: except ImportError: print("ok", l) except RuntimeError as er: - print("RuntimeError", er, l) + print(str(er) or "name too long", l) # import package for l in (100, 101, 102, 128, 129): @@ -80,4 +80,4 @@ class A: except ImportError: print("ok", l) except RuntimeError as er: - print("RuntimeError", er, l) + print(str(er) or "name too long", l) diff --git a/tests/stress/qstr_limit.py.exp b/tests/stress/qstr_limit.py.exp index 2349adf220f..5596b54bebd 100644 --- a/tests/stress/qstr_limit.py.exp +++ b/tests/stress/qstr_limit.py.exp @@ -1,38 +1,38 @@ True True -RuntimeError name too long 256 -RuntimeError name too long 257 -RuntimeError name too long 258 +name too long 256 +name too long 257 +name too long 258 {'abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrst': 1} {'abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstu': 1} -RuntimeError name too long 256 -RuntimeError name too long 257 -RuntimeError name too long 258 +name too long 256 +name too long 257 +name too long 258 -RuntimeError name too long 256 -RuntimeError name too long 257 -RuntimeError name too long 258 +name too long 256 +name too long 257 +name too long 258 True 123 True 123 -RuntimeError name too long 256 -RuntimeError name too long 256 -RuntimeError name too long 257 -RuntimeError name too long 257 -RuntimeError name too long 258 -RuntimeError name too long 258 +name too long 256 +name too long 256 +name too long 257 +name too long 257 +name too long 258 +name too long 258 254 255 -RuntimeError name too long 256 -RuntimeError name too long 257 -RuntimeError name too long 258 +name too long 256 +name too long 257 +name too long 258 ok 100 ok 101 -RuntimeError name too long 256 -RuntimeError name too long 257 -RuntimeError name too long 258 +name too long 256 +name too long 257 +name too long 258 ok 100 ok 101 ok 102 -RuntimeError name too long 128 -RuntimeError name too long 129 +name too long 128 +name too long 129 diff --git a/tests/stress/qstr_limit_str_modulo.py b/tests/stress/qstr_limit_str_modulo.py index 90b9f4364ec..c56f23b0a1d 100644 --- a/tests/stress/qstr_limit_str_modulo.py +++ b/tests/stress/qstr_limit_str_modulo.py @@ -18,4 +18,4 @@ def make_id(n, base="a"): try: print(("%(" + id + ")d") % {id: l}) except RuntimeError as er: - print("RuntimeError", er, l) + print("RuntimeError", str(er) or "name too long", l) From 8f741b96357bae5d84d0bc85c7dffe90f7e9d316 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sat, 20 Jun 2026 11:45:36 +0200 Subject: [PATCH 360/635] tests/micropython: Fix tests with no error details. This commit updates `micropython/import_mpy_invalid`, `micropython/import_mpy_native`, and `micropython/viper_error` tests to also pass even if the interpreter was built with no detailed error messages. Originally the tests assumed the error messages level was always higher than `MICROPY_ERROR_REPORTING_NONE`, and thus expected a particular string pattern to appear in certain errors' output. Signed-off-by: Alessandro Gatti --- tests/micropython/import_mpy_invalid.py | 2 +- tests/micropython/import_mpy_native.py | 2 +- tests/micropython/viper_error.py | 63 +++++++++++++------------ tests/micropython/viper_error.py.exp | 56 +++++++++++----------- 4 files changed, 63 insertions(+), 60 deletions(-) diff --git a/tests/micropython/import_mpy_invalid.py b/tests/micropython/import_mpy_invalid.py index f928d45c791..5d7df4fb19c 100644 --- a/tests/micropython/import_mpy_invalid.py +++ b/tests/micropython/import_mpy_invalid.py @@ -63,7 +63,7 @@ def open(self, path, mode): try: __import__(mod) except ValueError as er: - print(mod, "ValueError", er) + print(mod, "ValueError", str(er) or "incompatible .mpy file") # unmount and undo path addition vfs.umount("/userfs") diff --git a/tests/micropython/import_mpy_native.py b/tests/micropython/import_mpy_native.py index b7908b5a629..0d47a20fc32 100644 --- a/tests/micropython/import_mpy_native.py +++ b/tests/micropython/import_mpy_native.py @@ -122,7 +122,7 @@ def open(self, path, mode): __import__(mod) print(mod, "OK") except ValueError as er: - print(mod, "ValueError", er) + print(mod, "ValueError", str(er) or "incompatible .mpy arch") # unmount and undo path addition vfs.umount("/userfs") diff --git a/tests/micropython/viper_error.py b/tests/micropython/viper_error.py index f3186671689..e58a3c59fa0 100644 --- a/tests/micropython/viper_error.py +++ b/tests/micropython/viper_error.py @@ -1,19 +1,19 @@ # test syntax and type errors specific to viper code generation -def test(code): +def test(code, msg): try: exec(code) except (SyntaxError, ViperTypeError, NotImplementedError) as e: - print(repr(e)) + print(type(e), str(e) or msg) # viper: annotations must be identifiers -test("@micropython.viper\ndef f(a:1): pass") -test("@micropython.viper\ndef f() -> 1: pass") +test("@micropython.viper\ndef f(a:1): pass", "annotation must be an identifier") +test("@micropython.viper\ndef f() -> 1: pass", "annotation must be an identifier") # unknown type -test("@micropython.viper\ndef f(x:unknown_type): pass") +test("@micropython.viper\ndef f(x:unknown_type): pass", "unknown type 'unknown_type'") # local used before type known test( @@ -22,7 +22,8 @@ def test(code): def f(): print(x) x = 1 -""" +""", + "local 'x' used before type known", ) # type mismatch storing to local @@ -33,7 +34,8 @@ def f(): x = 1 y = [] x = y -""" +""", + "local 'x' has type 'int' but source is 'object'", ) # can't implicitly convert type to bool @@ -44,51 +46,52 @@ def f(): x = ptr(0) if x: pass -""" +""", + "can't implicitly convert 'ptr' to 'bool'", ) # incorrect return type -test("@micropython.viper\ndef f() -> int: return []") +test("@micropython.viper\ndef f() -> int: return []", "return expected 'int' but got 'object'") # can't do unary op of incompatible type -test("@micropython.viper\ndef f(x:ptr): -x") +test("@micropython.viper\ndef f(x:ptr): -x", "can't do unary op of 'ptr'") # can't do binary op between incompatible types -test("@micropython.viper\ndef f(): 1 + []") -test("@micropython.viper\ndef f(x:int, y:uint): x < y") +test("@micropython.viper\ndef f(): 1 + []", "can't do binary op between 'int' and 'object'") +test("@micropython.viper\ndef f(x:int, y:uint): x < y", "comparison of int and uint") # can't load -test("@micropython.viper\ndef f(): 1[0]") -test("@micropython.viper\ndef f(): 1[x]") +test("@micropython.viper\ndef f(): 1[0]", "can't load from 'int'") +test("@micropython.viper\ndef f(): 1[x]", "can't load from 'int'") # can't store -test("@micropython.viper\ndef f(): 1[0] = 1") -test("@micropython.viper\ndef f(): 1[x] = 1") -test("@micropython.viper\ndef f(x:int): x[0] = x") -test("@micropython.viper\ndef f(x:ptr32): x[0] = None") -test("@micropython.viper\ndef f(x:ptr32): x[x] = None") +test("@micropython.viper\ndef f(): 1[0] = 1", "can't store to 'int'") +test("@micropython.viper\ndef f(): 1[x] = 1", "can't store to 'int'") +test("@micropython.viper\ndef f(x:int): x[0] = x", "can't store to 'int'") +test("@micropython.viper\ndef f(x:ptr32): x[0] = None", "can't store 'None'") +test("@micropython.viper\ndef f(x:ptr32): x[x] = None", "can't store 'None'") # must raise an object -test("@micropython.viper\ndef f(): raise 1") +test("@micropython.viper\ndef f(): raise 1", "must raise an object") # unary ops not implemented -test("@micropython.viper\ndef f(x:int): not x") +test("@micropython.viper\ndef f(x:int): not x", "'not' not implemented") # binary op not implemented -test("@micropython.viper\ndef f(x:uint, y:uint): res = x // y") -test("@micropython.viper\ndef f(x:uint, y:uint): res = x % y") -test("@micropython.viper\ndef f(x:int): res = x in x") +test("@micropython.viper\ndef f(x:uint, y:uint): res = x // y", "div/mod not implemented for uint") +test("@micropython.viper\ndef f(x:uint, y:uint): res = x % y", "div/mod not implemented for uint") +test("@micropython.viper\ndef f(x:int): res = x in x", "binary op not implemented") # raise with 0 or 2 args not implemented -test("@micropython.viper\ndef f():\n try:\n x\n except:\n raise\n") -test("@micropython.viper\ndef f(): raise Exception from Exception") +test("@micropython.viper\ndef f():\n try:\n x\n except:\n raise\n", "native raise") +test("@micropython.viper\ndef f(): raise Exception from Exception", "native raise") # yield (from) not implemented -test("@micropython.viper\ndef f(): yield") -test("@micropython.viper\ndef f(): yield from f") +test("@micropython.viper\ndef f(): yield", "native yield") +test("@micropython.viper\ndef f(): yield from f", "native yield") # passing a ptr to a Python function not implemented -test("@micropython.viper\ndef f(): print(ptr(1))") +test("@micropython.viper\ndef f(): print(ptr(1))", "conversion to object") # cast of a casting identifier not implemented -test("@micropython.viper\ndef f(): int(int)") +test("@micropython.viper\ndef f(): int(int)", "casting") diff --git a/tests/micropython/viper_error.py.exp b/tests/micropython/viper_error.py.exp index 2ae4c2053d9..9b663b8508a 100644 --- a/tests/micropython/viper_error.py.exp +++ b/tests/micropython/viper_error.py.exp @@ -1,28 +1,28 @@ -SyntaxError('annotation must be an identifier',) -SyntaxError('annotation must be an identifier',) -ViperTypeError("unknown type 'unknown_type'",) -ViperTypeError("local 'x' used before type known",) -ViperTypeError("local 'x' has type 'int' but source is 'object'",) -ViperTypeError("can't implicitly convert 'ptr' to 'bool'",) -ViperTypeError("return expected 'int' but got 'object'",) -ViperTypeError("can't do unary op of 'ptr'",) -ViperTypeError("can't do binary op between 'int' and 'object'",) -ViperTypeError('comparison of int and uint',) -ViperTypeError("can't load from 'int'",) -ViperTypeError("can't load from 'int'",) -ViperTypeError("can't store to 'int'",) -ViperTypeError("can't store to 'int'",) -ViperTypeError("can't store to 'int'",) -ViperTypeError("can't store 'None'",) -ViperTypeError("can't store 'None'",) -ViperTypeError('must raise an object',) -ViperTypeError("'not' not implemented",) -ViperTypeError('div/mod not implemented for uint',) -ViperTypeError('div/mod not implemented for uint',) -ViperTypeError('binary op not implemented',) -NotImplementedError('native raise',) -NotImplementedError('native raise',) -NotImplementedError('native yield',) -NotImplementedError('native yield',) -NotImplementedError('conversion to object',) -NotImplementedError('casting',) + annotation must be an identifier + annotation must be an identifier + unknown type 'unknown_type' + local 'x' used before type known + local 'x' has type 'int' but source is 'object' + can't implicitly convert 'ptr' to 'bool' + return expected 'int' but got 'object' + can't do unary op of 'ptr' + can't do binary op between 'int' and 'object' + comparison of int and uint + can't load from 'int' + can't load from 'int' + can't store to 'int' + can't store to 'int' + can't store to 'int' + can't store 'None' + can't store 'None' + must raise an object + 'not' not implemented + div/mod not implemented for uint + div/mod not implemented for uint + binary op not implemented + native raise + native raise + native yield + native yield + conversion to object + casting From d8eb65bb829d42da44f128f1a31466d2e84a2ced Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 9 Jun 2026 15:53:52 +0200 Subject: [PATCH 361/635] tools/ci.sh: Add new Unix target with no error messages. This commit adds a new CI target for the Unix port, which is the `standard` variant being built with no error messages (as in, exceptions won't report anything but the exception type). Even though it won't cover all possible tests failing with no error messages (some occur only in the `coverage` build variant), this should be a good start for preventing new tests to not assume a particular error message level. To make things automated, the new target is also added to the regular CI jobs set in the Unix port's GitHub workflow file. Signed-off-by: Alessandro Gatti --- .github/workflows/ports_unix.yml | 18 +++++++++++++++--- tools/ci.sh | 12 ++++++++++-- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/.github/workflows/ports_unix.yml b/.github/workflows/ports_unix.yml index cb70541ced1..702e0e67caf 100644 --- a/.github/workflows/ports_unix.yml +++ b/.github/workflows/ports_unix.yml @@ -67,14 +67,26 @@ jobs: if: failure() run: tests/run-tests.py --print-failures - standard_terse: + standard_error_terse: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - name: Build - run: tools/ci.sh unix_standard_terse_build + run: tools/ci.sh unix_standard_error_terse_build - name: Run main test suite - run: tools/ci.sh unix_standard_terse_run_tests + run: tools/ci.sh unix_standard_error_terse_run_tests + - name: Print failures + if: failure() + run: tests/run-tests.py --print-failures + + standard_error_none: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v7 + - name: Build + run: tools/ci.sh unix_standard_error_none_build + - name: Run main test suite + run: tools/ci.sh unix_standard_error_none_run_tests - name: Print failures if: failure() run: tests/run-tests.py --print-failures diff --git a/tools/ci.sh b/tools/ci.sh index a24349f6f47..8081b113087 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -721,11 +721,19 @@ function ci_unix_standard_v2_run_tests { ci_unix_run_tests_full_helper standard } -function ci_unix_standard_terse_build { +function ci_unix_standard_error_terse_build { ci_unix_build_helper VARIANT=standard CFLAGS_EXTRA="-DMICROPY_ERROR_REPORTING=MICROPY_ERROR_REPORTING_TERSE" } -function ci_unix_standard_terse_run_tests { +function ci_unix_standard_error_terse_run_tests { + make -C ports/unix VARIANT=standard test +} + +function ci_unix_standard_error_none_build { + ci_unix_build_helper VARIANT=standard CFLAGS_EXTRA="-DMICROPY_ERROR_REPORTING=MICROPY_ERROR_REPORTING_NONE" MICROPY_ROM_TEXT_COMPRESSION=0 +} + +function ci_unix_standard_error_none_run_tests { make -C ports/unix VARIANT=standard test } From c0928f04178c58b45f3e3c7daf7312493672ecc6 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 12 Jun 2026 16:55:10 +1000 Subject: [PATCH 362/635] tests/extmod/vfs_blockdev_invalid.py: Catch only expected exceptions. This allows MemoryError to propagate through and skip the test, eg on esp8266 boards. Signed-off-by: Damien George --- tests/extmod/vfs_blockdev_invalid.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/extmod/vfs_blockdev_invalid.py b/tests/extmod/vfs_blockdev_invalid.py index 0fc1592bda0..3cb97ac3144 100644 --- a/tests/extmod/vfs_blockdev_invalid.py +++ b/tests/extmod/vfs_blockdev_invalid.py @@ -53,6 +53,7 @@ def ioctl(self, op, arg): ERROR_EIO = (OSError, "[Errno 5] EIO") ERROR_EINVAL = (OSError, "[Errno 22] EINVAL") ERROR_TYPE = (TypeError, "can't convert str to int") +ALL_ERROR_TYPES = (OSError, TypeError) def test(vfs_class, test_data): @@ -71,7 +72,7 @@ def test(vfs_class, test_data): try: with fs.open("test", "r") as f: assert error_open is None - except Exception as e: + except ALL_ERROR_TYPES as e: assert error_open is not None assert (type(e), str(e)) == error_open @@ -84,7 +85,7 @@ def test(vfs_class, test_data): assert f.read(1) == "a" assert f.read() == "a" * 63 assert error_read is None - except Exception as e: + except ALL_ERROR_TYPES as e: assert error_read is not None assert (type(e), str(e)) == error_read @@ -96,7 +97,7 @@ def test(vfs_class, test_data): try: vfs.mount(bdev, "/test_ram") assert error_mount is None - except Exception as e: + except ALL_ERROR_TYPES as e: assert error_mount is not None assert (type(e), str(e)) == error_mount finally: From 2b599af4162239b18432639f211729a374621f40 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 12 Jun 2026 16:55:59 +1000 Subject: [PATCH 363/635] tests/extmod_hardware/machine_sdcard_dma_align.py: Allow skip on esp32. Some esp32 boards (eg ESP32_GENERIC_C3) require extra arguments to the SDCard constructor and fail with a ValueError if they aren't provided. Signed-off-by: Damien George --- tests/extmod_hardware/machine_sdcard_dma_align.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/extmod_hardware/machine_sdcard_dma_align.py b/tests/extmod_hardware/machine_sdcard_dma_align.py index 4ac53180aee..5ab7a501930 100644 --- a/tests/extmod_hardware/machine_sdcard_dma_align.py +++ b/tests/extmod_hardware/machine_sdcard_dma_align.py @@ -40,7 +40,7 @@ vfs.mount(sd, MOUNT_POINT) vfs.umount(MOUNT_POINT) del sd -except (OSError, AttributeError): +except (OSError, ValueError, AttributeError): print("SKIP") raise SystemExit From 31aa405924450e9528963cf8cb991ea619af61ec Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Wed, 17 Jun 2026 09:32:28 +0200 Subject: [PATCH 364/635] py/dynruntime.mk: Refactor Picolibc probing for RISC-V targets. This commit moves all Picolibc probing done for RISC-V targets into one single place. Both RV32 and RV64 target sections performed the same standard library probing checks to see whether to use Picolibc or Newlib. Those two directive blocks have been merged in one single place outside of the main target default definition assignments. This should also make things easier when adding Picolibc support to other targets if the need arises, since Picolibc architecture support is extensive enough to cover all supported MicroPython targets. Signed-off-by: Alessandro Gatti --- py/dynruntime.mk | 52 ++++++++++++++++++------------------------------ 1 file changed, 19 insertions(+), 33 deletions(-) diff --git a/py/dynruntime.mk b/py/dynruntime.mk index b2e3ffff986..24947717f14 100644 --- a/py/dynruntime.mk +++ b/py/dynruntime.mk @@ -106,25 +106,28 @@ else ifeq ($(ARCH),rv32imc) # rv32imc CROSS = riscv64-unknown-elf- CFLAGS_ARCH += -march=rv32imac -mabi=ilp32 -mno-relax -# If Picolibc is available then select it explicitly. Ubuntu 24.04 ships its -# bare metal RISC-V toolchain with Picolibc rather than Newlib, and the default -# is "nosys" so a value must be provided. To avoid having per-distro -# workarounds, always select Picolibc if available. -PICOLIBC_SPECS := $(shell $(CROSS)gcc --print-file-name=picolibc.specs) -ifneq ($(PICOLIBC_SPECS),picolibc.specs) -CFLAGS_ARCH += -specs=$(PICOLIBC_SPECS) -USE_PICOLIBC := 1 -PICOLIBC_ARCH := rv32imac -PICOLIBC_ABI := ilp32 -endif - MICROPY_FLOAT_IMPL ?= none +PICOLIBC_BASE := riscv64-unknown-elf +PICOLIBC_TARGET := rv32imac/ilp32 else ifeq ($(ARCH),rv64imc) # rv64imc CROSS = riscv64-unknown-elf- CFLAGS_ARCH += -march=rv64imac -mabi=lp64 -mno-relax +MICROPY_FLOAT_IMPL ?= none +PICOLIBC_BASE := riscv64-unknown-elf +PICOLIBC_TARGET := rv64imac/lp64 + +else +$(error architecture '$(ARCH)' not supported) +endif + +ifneq ($(findstring -musl,$(shell $(CROSS)gcc -dumpmachine)),) +USE_MUSL := 1 +endif + +ifeq ($(ARCH),$(filter $(ARCH),rv32imc rv64imc)) # If Picolibc is available then select it explicitly. Ubuntu 24.04 ships its # bare metal RISC-V toolchain with Picolibc rather than Newlib, and the default # is "nosys" so a value must be provided. To avoid having per-distro @@ -133,18 +136,7 @@ PICOLIBC_SPECS := $(shell $(CROSS)gcc --print-file-name=picolibc.specs) ifneq ($(PICOLIBC_SPECS),picolibc.specs) CFLAGS_ARCH += -specs=$(PICOLIBC_SPECS) USE_PICOLIBC := 1 -PICOLIBC_ARCH := rv64imac -PICOLIBC_ABI := lp64 -endif - -MICROPY_FLOAT_IMPL ?= none - -else -$(error architecture '$(ARCH)' not supported) endif - -ifneq ($(findstring -musl,$(shell $(CROSS)gcc -dumpmachine)),) -USE_MUSL := 1 endif MICROPY_FLOAT_IMPL_UPPER = $(shell echo $(MICROPY_FLOAT_IMPL) | tr '[:lower:]' '[:upper:]') @@ -152,7 +144,7 @@ CFLAGS += $(CFLAGS_ARCH) -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_$(MICROPY_FLOAT ifeq ($(LINK_RUNTIME),1) # All of these picolibc-specific directives are here to work around a -# limitation of Ubuntu 22.04's RISC-V bare metal toolchain. In short, the +# limitation of Ubuntu 24.04's RISC-V bare metal toolchain. In short, the # specific version of GCC in use (10.2.0) does not seem to take into account # extra paths provided by an explicitly passed specs file when performing name # resolution via `--print-file-name`. @@ -163,7 +155,7 @@ ifeq ($(LINK_RUNTIME),1) # flags that are passed to GCC. The `PICOLIBC_ROOT` environment variable is # checked to override the starting point for the library file search, and if # it is not set then the default value is used, assuming that this is running -# on an Ubuntu 22.04 machine. +# on an Ubuntu 24.04 machine. # # This should be revised when the CI base image is updated to a newer Ubuntu # version (that hopefully contains a newer RISC-V compiler) or to another Linux @@ -179,14 +171,8 @@ LIBGCC_PATH := $(realpath $(shell $(CROSS)gcc $(CFLAGS) --print-libgcc-file-name LIBM_PATH := $(realpath $(shell $(CROSS)gcc $(CFLAGS) --print-file-name=$(LIBM_NAME))) ifeq ($(USE_PICOLIBC),1) ifeq ($(LIBM_PATH),) -# The CROSS toolchain prefix usually ends with a dash, but that may not be -# always the case. If the prefix ends with a dash it has to be taken out as -# Picolibc's architecture directory won't have it in its name. GNU Make does -# not have any facility to perform character-level text manipulation so we -# shell out to sed. -CROSS_PREFIX := $(shell echo $(CROSS) | sed -e 's/-$$//') -PICOLIBC_ROOT ?= /usr/lib/picolibc/$(CROSS_PREFIX)/lib -LIBM_PATH := $(PICOLIBC_ROOT)/$(PICOLIBC_ARCH)/$(PICOLIBC_ABI)/$(LIBM_NAME) +PICOLIBC_ROOT ?= /usr/lib/picolibc/$(PICOLIBC_BASE)/lib +LIBM_PATH := $(PICOLIBC_ROOT)/$(PICOLIBC_TARGET)/$(LIBM_NAME) endif endif MPY_LD_FLAGS += $(addprefix -l, $(LIBGCC_PATH) $(LIBM_PATH)) From baeaf864971b07e5c432bce282c3cc2e0da86f19 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Thu, 4 Jun 2026 15:04:05 +0200 Subject: [PATCH 365/635] py/dynruntime.mk: Let natmods be built with Clang. This commit modifies the build rules for native modules in order to remove the dependence on GCC for creating native MPY files. Whilst the Unix port of MicroPython can be built with Clang by overriding the `CC` variable, natmods require a bit more work. GCC builds compilers that are tailored for a single architecture, but Clang takes the opposite approach, so a single binary may target more than one architecture. Architecture selection is, by definition, not compatible between those two compilers. These changes attempt to make things easier to handle when using Clang. Native modules can now be built with something like this: make CC=clang ARCH= CFLAGS_EXTRA='--target=' So, for example building an x86 native module the command line will look something like this: make CC=clang ARCH=x86 CFLAGS_EXTRA='--target=i686-unknown-linux-gnu' Clang and GCC, however, have different tolerances for deviations from the chosen C standard. Whilst GCC doesn't really mind whether a typedef is defined multiple times as long as it is defined to the same value, Clang does raise a warning which is then interpreted as an error. Unfortunately #ifdef/#ifndef does not work with typedefs, and the way native modules are built meant that `py/mpconfig.h` would first include the native module's generated configuration file and then proceed with the rest of the configuration. However, both files attempt to provide aliases for both `mp_int_t` and `mp_uint_t`, and that doesn't really work. Those definitions aren't going to be emitted any longer by the linker, preventing this issue from occurring in the first place. Signed-off-by: Alessandro Gatti --- py/dynruntime.mk | 51 +++++++++++++++++++++++++++++++++++++++--------- tools/mpy_ld.py | 10 ++-------- 2 files changed, 44 insertions(+), 17 deletions(-) diff --git a/py/dynruntime.mk b/py/dynruntime.mk index 24947717f14..e3c9ee4cbd5 100644 --- a/py/dynruntime.mk +++ b/py/dynruntime.mk @@ -2,6 +2,7 @@ # MPY_DIR must be set to the top of the MicroPython source tree BUILD ?= build-$(ARCH) +CC = $(CROSS)gcc ECHO = @echo RM = /bin/rm @@ -123,7 +124,7 @@ else $(error architecture '$(ARCH)' not supported) endif -ifneq ($(findstring -musl,$(shell $(CROSS)gcc -dumpmachine)),) +ifneq ($(findstring -musl,$(shell $(CC) -dumpmachine)),) USE_MUSL := 1 endif @@ -132,15 +133,27 @@ ifeq ($(ARCH),$(filter $(ARCH),rv32imc rv64imc)) # bare metal RISC-V toolchain with Picolibc rather than Newlib, and the default # is "nosys" so a value must be provided. To avoid having per-distro # workarounds, always select Picolibc if available. -PICOLIBC_SPECS := $(shell $(CROSS)gcc --print-file-name=picolibc.specs) +PICOLIBC_SPECS := $(shell $(CC) --print-file-name=picolibc.specs) ifneq ($(PICOLIBC_SPECS),picolibc.specs) +# LLVM toolchains supporting more than one target seem to ignore the `-march` +# flag passed when looking up the specs file, so if your system has Picolibc +# libraries for more than one architectures supported by the compiler the +# lookup will return the first available file. +# +# For example, on Ubuntu 24.02 if you have both `picolibc-aarch64-linux-gnu` +# and `picolibc-riscv64-unknown-elf` packages installed, the Qualcomm LLVM +# toolchain (which supports both AArch64 and RISC-V 64) will always return the +# AArch64 picolibc specs even when building for RISC-V. +ifeq ($(shell grep -q "$(PICOLIBC_BASE)" "$(PICOLIBC_SPECS)"; echo $$?),0) CFLAGS_ARCH += -specs=$(PICOLIBC_SPECS) USE_PICOLIBC := 1 endif endif +endif MICROPY_FLOAT_IMPL_UPPER = $(shell echo $(MICROPY_FLOAT_IMPL) | tr '[:lower:]' '[:upper:]') CFLAGS += $(CFLAGS_ARCH) -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_$(MICROPY_FLOAT_IMPL_UPPER) +CFLAGS += $(CFLAGS_EXTRA) ifeq ($(LINK_RUNTIME),1) # All of these picolibc-specific directives are here to work around a @@ -167,15 +180,37 @@ LIBM_NAME := libc.a else LIBM_NAME := libm.a endif -LIBGCC_PATH := $(realpath $(shell $(CROSS)gcc $(CFLAGS) --print-libgcc-file-name)) -LIBM_PATH := $(realpath $(shell $(CROSS)gcc $(CFLAGS) --print-file-name=$(LIBM_NAME))) +# Clang will output the path to libclang_rt.builtins.a instead. The problem is +# that some symbols are duplicated between the builtins library and libc.a. In +# these cases let's leave it to the user to figure out how to handle this for +# the time being. +TOOLCHAIN_LIBGCC := $(realpath $(shell $(CC) $(CFLAGS) --print-libgcc-file-name)) +ifneq ($(findstring clang,$(shell $(CC) --version)),clang) +LIBGCC_PATH = $(TOOLCHAIN_LIBGCC) +else +ifneq ($(LINK_CLANG_CLANGRT),0) +LIBGCC_PATH = $(TOOLCHAIN_LIBGCC) +else +LIBGCC_PATH = +endif +endif +LIBM_PATH := $(realpath $(shell $(CC) $(CFLAGS) --print-file-name=$(LIBM_NAME))) ifeq ($(USE_PICOLIBC),1) ifeq ($(LIBM_PATH),) PICOLIBC_ROOT ?= /usr/lib/picolibc/$(PICOLIBC_BASE)/lib LIBM_PATH := $(PICOLIBC_ROOT)/$(PICOLIBC_TARGET)/$(LIBM_NAME) endif endif -MPY_LD_FLAGS += $(addprefix -l, $(LIBGCC_PATH) $(LIBM_PATH)) +ifneq ($(LINK_CLANG_LIBC),) +ifeq ($(findstring clang,$(shell $(CC) --version)),clang) +LIBC_PATH := $(realpath $(shell $(CC) $(CFLAGS) --print-file-name=libc.a)) +else +LIBC_PATH = +endif +else +LIBC_PATH = +endif +MPY_LD_FLAGS += $(addprefix -l, $(LIBGCC_PATH) $(LIBM_PATH) $(LIBC_PATH)) endif ifneq ($(MPY_EXTERN_SYM_FILE),) MPY_LD_FLAGS += --externs "$(realpath $(MPY_EXTERN_SYM_FILE))" @@ -184,8 +219,6 @@ ifneq ($(ARCH_FLAGS),) MPY_LD_FLAGS += --arch-flags "$(ARCH_FLAGS)" endif -CFLAGS += $(CFLAGS_EXTRA) - ################################################################################ # Build rules @@ -210,12 +243,12 @@ $(CONFIG_H): $(SRC) # Build .o from .c source files $(BUILD)/%.o: %.c $(CONFIG_H) Makefile $(ECHO) "CC $<" - $(Q)$(CROSS)gcc $(CFLAGS) -o $@ -c $< + $(Q)$(CC) $(CFLAGS) -o $@ -c $< # Build .o from .S source files $(BUILD)/%.o: %.S $(CONFIG_H) Makefile $(ECHO) "AS $<" - $(Q)$(CROSS)gcc $(CFLAGS) -o $@ -c $< + $(Q)$(CC) $(CFLAGS) -o $@ -c $< # Build .mpy from .py source files $(BUILD)/%.mpy: %.py diff --git a/tools/mpy_ld.py b/tools/mpy_ld.py index 05c915fbc41..e40e9858588 100755 --- a/tools/mpy_ld.py +++ b/tools/mpy_ld.py @@ -1510,19 +1510,13 @@ def do_preprocess(args): args.output = args.files[0][:-1] + "config.h" static_qstrs, qstr_vals = extract_qstrs(args.files) with open(args.output, "w") as f: - print( - "#include \n" - "typedef uintptr_t mp_uint_t;\n" - "typedef intptr_t mp_int_t;\n" - "typedef uintptr_t mp_off_t;", - file=f, - ) + print("#include \ntypedef uintptr_t mp_off_t;", file=f) for i, q in enumerate(static_qstrs): print("#define %s (%u)" % (q, i + 1), file=f) for i, q in enumerate(sorted(qstr_vals)): print("#define %s (mp_native_qstr_table[%d])" % (q, i + 1), file=f) print("extern const uint16_t mp_native_qstr_table[];", file=f) - print("extern const mp_uint_t mp_native_obj_table[];", file=f) + print("extern const uintptr_t mp_native_obj_table[];", file=f) def do_link(args): From dd476ce1f63a5a744efd2909407d7b39ba64b304 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sun, 28 Jun 2026 22:32:45 +0200 Subject: [PATCH 366/635] tools/mpy_ld.py: Align the trampoline if requested. This commit updates the entry point trampoline generation, making sure that the requested text segment alignment is taken into account. x86 and x64 object files generated by GCC have no forced section alignment for the text segment, so the trampoline only needs to be generated once as addresses won't move around when the MPY file is assembled. This is not the case for Clang-generated objects, which have a section alignment of 4, and so the address calculation needs to take this into account. As this is still experimental, the trampoline calculation hasn't been generalised into one single block of code. If no section alignment is requested then the old calculation is performed. Signed-off-by: Alessandro Gatti --- tools/mpy_ld.py | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/tools/mpy_ld.py b/tools/mpy_ld.py index e40e9858588..1bdba65c19a 100755 --- a/tools/mpy_ld.py +++ b/tools/mpy_ld.py @@ -459,15 +459,11 @@ def print_sections(self): for sec in self.sections: log(LOG_LEVEL_2, " {:08x} {} size={}".format(sec.addr, sec.name, len(sec.data))) - def find_addr(self, name): + def find_sym(self, name): if name in self.known_syms: - s = self.known_syms[name] - return s.section.addr + s["st_value"] + return self.known_syms[name] raise LinkError("unknown symbol: {}".format(name)) - def find_entry_addr(self): - return self.find_addr("mpy_init") - def build_got_generic(env): env.got_entries = {} @@ -1194,6 +1190,18 @@ def load_object_file(env, f, felf): raise LinkError("\n".join(dup_errors)) +def generate_entry_point_jump(env): + entry_point = env.find_sym("mpy_init") + address = entry_point.section.addr + entry_point["st_value"] + alignment = entry_point.section.alignment + if alignment == 1: + return env.arch.asm_jump(address) + last_jump_length = len(env.arch.asm_jump(address)) + aligned_jump = align_to(last_jump_length, alignment) + jump = env.arch.asm_jump(address + aligned_jump - last_jump_length) + return jump.ljust(align_to(len(jump), alignment), b"\0") + + def link_objects(env, native_qstr_vals_len): # Build GOT information if env.arch.name == "EM_XTENSA": @@ -1289,8 +1297,7 @@ def link_objects(env, native_qstr_vals_len): raise LinkError("\n".join(undef_errors)) # Generate the entry trampoline assuming the offset is already known. - env.entry_point = env.find_entry_addr() - jump = env.arch.asm_jump(env.entry_point) + jump = generate_entry_point_jump(env) env.entry_trampoline_len = len(jump) # Align sections, assign their addresses, and create full_text @@ -1390,7 +1397,7 @@ def build_mpy(env, fmpy, internal_name, native_qstr_vals, arch_flags): # Rewrite the entry trampoline if the proper value isn't known earlier, and # ensure the trampoline size remains the same. if env.arch.delayed_entry_offset: - jump = env.arch.asm_jump(env.find_entry_addr()) + jump = generate_entry_point_jump(env) env.full_text[: len(jump)] = jump assert len(jump) == env.entry_trampoline_len From 818d6a57c4334829eb2b9d322a0304bc1243e738 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 5 Jun 2026 04:16:24 +0200 Subject: [PATCH 367/635] tools/mpy_ld.py: Add support for R_ARM_GOT_PREL relocations. This commit introduces support for the R_ARM_GOT_PREL relocation, found in the text segment of certain Arm native modules. Until now this was not needed, since the only supported compiler for linking native modules was GCC, which did not seem to ever generate such a relocation. With the recent work in making Clang a supported compiler as well, it was quickly found out that such a compiler actually does generate such a relocation type. This relocation seem to be enough to at least make `examples/natmod/features0` link with Clang targeting `armv7m`, and then run the output native module on an appropriate interpreter running under the QEMU MPS2-AN500 target. Signed-off-by: Alessandro Gatti --- tools/mpy_ld.py | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/tools/mpy_ld.py b/tools/mpy_ld.py index 1bdba65c19a..4f161abbe10 100755 --- a/tools/mpy_ld.py +++ b/tools/mpy_ld.py @@ -128,6 +128,7 @@ R_RISCV_TLSDESC_LOAD_LO12 = 63 R_RISCV_TLSDESC_ADD_LO12 = 64 R_RISCV_TLSDESC_CALL = 65 +R_ARM_GOT_PREL = 96 ################################################################################ # Architecture configuration @@ -254,28 +255,28 @@ def __init__( "EM_ARM", MP_NATIVE_ARCH_ARMV6M << 2, 4, - (R_ARM_GOT_BREL,), + (R_ARM_GOT_BREL, R_ARM_GOT_PREL), asm_jump_thumb, ), "armv7m": ArchData( "EM_ARM", MP_NATIVE_ARCH_ARMV7M << 2, 4, - (R_ARM_GOT_BREL,), + (R_ARM_GOT_BREL, R_ARM_GOT_PREL), asm_jump_thumb2, ), "armv7emsp": ArchData( "EM_ARM", MP_NATIVE_ARCH_ARMV7EMSP << 2, 4, - (R_ARM_GOT_BREL,), + (R_ARM_GOT_BREL, R_ARM_GOT_PREL), asm_jump_thumb2, ), "armv7emdp": ArchData( "EM_ARM", MP_NATIVE_ARCH_ARMV7EMDP << 2, 4, - (R_ARM_GOT_BREL,), + (R_ARM_GOT_BREL, R_ARM_GOT_PREL), asm_jump_thumb2, ), "xtensa": ArchData( @@ -681,10 +682,14 @@ def do_relocation_text(env, text_addr, r): # Relcation pointing to GOT reloc = addr = env.got_entries[s.name].offset - elif env.arch.name == "EM_X86_64" and r_info_type in ( - R_X86_64_GOTPCREL, - R_X86_64_REX_GOTPCRELX, - ): + elif ( + env.arch.name == "EM_X86_64" + and r_info_type + in ( + R_X86_64_GOTPCREL, + R_X86_64_REX_GOTPCRELX, + ) + ) or (env.arch.name == "EM_ARM" and r_info_type == R_ARM_GOT_PREL): # Relcation pointing to GOT got_entry = env.got_entries[s.name] addr = env.got_section.addr + got_entry.offset From eb3ef9f2f3a51d45116a4a8b6f3ff36d3f54e123 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sat, 6 Jun 2026 02:30:22 +0200 Subject: [PATCH 368/635] examples/natmod/btree: Fix building with Clang toolchains. This commit fixes building the `btree` module using Clang rather than using GCC, on x86, x64, and ArmV7 targets. The Clang standard library (libc) implementation of `memset` for x86 and x64 depends on functions that have a non-empty data section, which is not currently supported. Therefore we provide our own `memset` implementation that is good enough to let linking succeed for `x86` and `x64` targets. On a more general note, Clang also required some additional flags to disable an extra warning that GCC did not seem to raise. On Arm targets, `memset` is not a builtin of the compiler toolchain, so it has to be fetched from the runtime support library. Signed-off-by: Alessandro Gatti --- examples/natmod/btree/Makefile | 8 ++++++++ examples/natmod/btree/btree_c.c | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/examples/natmod/btree/Makefile b/examples/natmod/btree/Makefile index 7f4349e2b84..7eb445dfd75 100644 --- a/examples/natmod/btree/Makefile +++ b/examples/natmod/btree/Makefile @@ -16,6 +16,7 @@ BERKELEY_DB_CONFIG_FILE ?= \"extmod/berkeley-db/berkeley_db_config_port.h\" CFLAGS += -I$(BTREE_DIR)/include CFLAGS += -DBERKELEY_DB_CONFIG_FILE=$(BERKELEY_DB_CONFIG_FILE) CFLAGS += -Wno-old-style-definition -Wno-sign-compare -Wno-unused-parameter +CFLAGS += -Wno-deprecated-non-prototype SRC += $(addprefix $(realpath $(BTREE_DIR))/,\ btree/bt_close.c \ @@ -48,6 +49,13 @@ endif # Strip the architecture name from the internal filename. MPY_LD_FLAGS = "--source-name=$(MOD_BASE).mpy" +ifeq ($(ARCH),armv7m) +ifeq ($(findstring clang,$(shell $(CC) --version)),clang) +# Link with libclang_rt.builtins.a for memset/memcpy. +LINK_RUNTIME = 1 +endif +endif + include $(MPY_DIR)/py/dynruntime.mk # btree needs gnu99 defined diff --git a/examples/natmod/btree/btree_c.c b/examples/natmod/btree/btree_c.c index 8b541627fcd..7eb3d908513 100644 --- a/examples/natmod/btree/btree_c.c +++ b/examples/natmod/btree/btree_c.c @@ -4,7 +4,7 @@ #include -#if !defined(__linux__) +#if !defined(__linux__) || (defined(__clang__) && (defined(__x86_64__) || defined(__i386__) || __ARM_ARCH == 7)) void *memcpy(void *dst, const void *src, size_t n) { return mp_fun_table.memmove_(dst, src, n); } From 99bd05bdddb83dbf85e64bcc5e3dd22e7b677af1 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Thu, 4 Jun 2026 16:52:05 +0200 Subject: [PATCH 369/635] examples/natmod/deflate: Fix building with Clang toolchains. This commit fixes building the `deflate` module using Clang rather than using GCC, on x86, x64, and ArmV7 targets. The Clang standard library (libc) implementation of `memset` for x86 and x64 depends on functions that have a non-empty data section, which is not currently supported. Therefore we provide our own `memset` implementation that is good enough to let linking succeed for `x86` and `x64` targets. On Arm targets, `memset` is not a builtin of the compiler toolchain, so it has to be fetched from the runtime support library. Signed-off-by: Alessandro Gatti --- examples/natmod/deflate/Makefile | 9 ++++++++- examples/natmod/deflate/deflate.c | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/examples/natmod/deflate/Makefile b/examples/natmod/deflate/Makefile index a76f8c843bd..aa0951e88ef 100644 --- a/examples/natmod/deflate/Makefile +++ b/examples/natmod/deflate/Makefile @@ -11,8 +11,15 @@ SRC = deflate.c # Architecture to build for (x86, x64, armv7m, xtensa, xtensawin, rv32imc, rv64imc) ARCH ?= x64 +ifeq ($(ARCH),armv7m) +ifeq ($(findstring clang,$(shell $(CC) --version)),clang) +# Link with libclang_rt.a for memset +LINK_RUNTIME = 1 +endif +endif + ifeq ($(ARCH),armv6m) -# Link with libgcc.a for division helper functions +# Link with libgcc.a or libclang_rt.a for division helper functions LINK_RUNTIME = 1 endif diff --git a/examples/natmod/deflate/deflate.c b/examples/natmod/deflate/deflate.c index add58ed1a9d..dc948c3d1d1 100644 --- a/examples/natmod/deflate/deflate.c +++ b/examples/natmod/deflate/deflate.c @@ -3,7 +3,7 @@ #include "py/dynruntime.h" -#if !defined(__linux__) +#if !defined(__linux__) || (defined(__clang__) && (defined(__x86_64__) || defined(__i386__) || __ARM_ARCH == 7)) void *memcpy(void *dst, const void *src, size_t n) { return mp_fun_table.memmove_(dst, src, n); } From b343d2ecf72c2b5f471ba525a6b3d3530fbe626b Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 5 Jun 2026 06:59:53 +0200 Subject: [PATCH 370/635] examples/natmod/features2: Fix building with Clang toolchains. This commit fixes building the `features2` module using Clang rather than using GCC. Parts of the floating point support code for Clang may end up in libc.a rather than its builtins support library. This is the case for the armv7m target, so we have to force linking symbols from libc.a in that case. Depending on the toolchain, this may or may not build successfully, but the location of the `roundf` symbol should not move across toolchains. This makes it work on armv6m, rv32imc, and possibly on armv7m too. The latter depends on whether Clang's builtins support library not relying on features that are unsupported by `tools/mpy_ld.py`. Signed-off-by: Alessandro Gatti --- examples/natmod/features2/Makefile | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/examples/natmod/features2/Makefile b/examples/natmod/features2/Makefile index efd096c4ede..69909f0689a 100644 --- a/examples/natmod/features2/Makefile +++ b/examples/natmod/features2/Makefile @@ -10,6 +10,13 @@ SRC = main.c prod.c test.py # Architecture to build for (x86, x64, armv7m, xtensa, xtensawin, rv32imc, rv64imc) ARCH = x64 +ifeq ($(findstring clang,$(shell $(CC) --version)),clang) +ifeq ($(ARCH),$(filter $(ARCH),armv6m armv7m rv32imc)) +# Link with both libc.a and libclang_rt.builtins.a +LINK_CLANG_LIBC = 1 +endif +endif + # Link with libm.a and libgcc.a from the toolchain LINK_RUNTIME = 1 From 1428e58de2d5baf2a0a406d333727bd0ef15e3fd Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Thu, 4 Jun 2026 16:54:26 +0200 Subject: [PATCH 371/635] examples/natmod/framebuf: Fix building with Clang toolchains. This commit fixes building the `framebuf` module using Clang rather than using GCC, on x86, x64, and ArmV7 targets. The Clang standard library (libc) implementation of `memset` for x86 and x64 depends on functions that have a non-empty data section, which is not currently supported. Therefore we provide our own `memset` implementation that is good enough to let linking succeed for `x86` and `x64` targets. On Arm targets, `memset` is not a builtin of the compiler toolchain, so it has to be fetched from the runtime support library. Signed-off-by: Alessandro Gatti --- examples/natmod/framebuf/Makefile | 7 +++++++ examples/natmod/framebuf/framebuf.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/examples/natmod/framebuf/Makefile b/examples/natmod/framebuf/Makefile index ed0a795dc00..86a201d23bd 100644 --- a/examples/natmod/framebuf/Makefile +++ b/examples/natmod/framebuf/Makefile @@ -11,6 +11,13 @@ SRC = framebuf.c # Architecture to build for (x86, x64, armv7m, xtensa, xtensawin, rv32imc, rv64imc) ARCH ?= x64 +ifeq ($(ARCH),armv7m) +ifeq ($(findstring clang,$(shell $(CC) --version)),clang) +# Link with libclang_rt.a for memset +LINK_RUNTIME = 1 +endif +endif + ifeq ($(ARCH),armv6m) # Link with libgcc.a for division helper functions LINK_RUNTIME = 1 diff --git a/examples/natmod/framebuf/framebuf.c b/examples/natmod/framebuf/framebuf.c index 4e03810ce4f..3a981772745 100644 --- a/examples/natmod/framebuf/framebuf.c +++ b/examples/natmod/framebuf/framebuf.c @@ -3,7 +3,7 @@ #include "py/dynruntime.h" -#if !defined(__linux__) +#if !defined(__linux__) || (defined(__clang__) && (defined(__x86_64__) || defined(__i386__) || __ARM_ARCH == 7)) void *memcpy(void *dst, const void *src, size_t n) { return mp_fun_table.memmove_(dst, src, n); } From 1454c3e2012f15dcccb2b3a6356d8ee28fe03136 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Thu, 4 Jun 2026 16:55:00 +0200 Subject: [PATCH 372/635] examples/natmod/re: Fix building with Clang toolchains. This commit fixes building the `re` module using Clang rather than using GCC, on x86, x64, and ArmV7 targets. The Clang standard library (libc) implementation of `memset` for x86 and x64 depends on functions that have a non-empty data section, which is not currently supported. Therefore we provide our own `memset` implementation that is good enough to let linking succeed for `x86` and `x64` targets. On Arm targets, `memset` is not a builtin of the compiler toolchain, so it has to be fetched from the runtime support library. Signed-off-by: Alessandro Gatti --- examples/natmod/re/Makefile | 7 +++++++ examples/natmod/re/re.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/examples/natmod/re/Makefile b/examples/natmod/re/Makefile index a82847d98f8..e53fed80321 100644 --- a/examples/natmod/re/Makefile +++ b/examples/natmod/re/Makefile @@ -11,6 +11,13 @@ SRC = re.c # Architecture to build for (x86, x64, armv7m, xtensa, xtensawin, rv32imc, rv64imc) ARCH = x64 +ifeq ($(ARCH),armv7m) +ifeq ($(findstring clang,$(shell $(CC) --version)),clang) +# Link with libclang_rt.a for memmove +LINK_RUNTIME = 1 +endif +endif + ifeq ($(ARCH),armv6m) # Link with libgcc.a for division helper functions LINK_RUNTIME = 1 diff --git a/examples/natmod/re/re.c b/examples/natmod/re/re.c index f20e6062a3c..db2b6754d18 100644 --- a/examples/natmod/re/re.c +++ b/examples/natmod/re/re.c @@ -32,7 +32,7 @@ void mp_cstack_check(void) { } } -#if !defined(__linux__) +#if !defined(__linux__) || (defined(__clang__) && (defined(__x86_64__) || defined(__i386__) || __ARM_ARCH == 7)) void *memcpy(void *dst, const void *src, size_t n) { return mp_fun_table.memmove_(dst, src, n); } From 3fff03367a6b32ff860ab1eb4d084da49583739f Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 9 Jan 2026 12:28:39 +0100 Subject: [PATCH 373/635] tools/ci.sh: Use an i686 cross-compiler for Unix/x86 bit builds. This commit forces usage of an i686 cross-compiler for 32-bits x86 Unix port builds, instead of relying on the "-m32" flag passed to the currently installed GCC version. Before this change it was not possible to build an x86 native module on anything but an x86/x64 machine, since the scripts used the generic "gcc" compiler installed on the system the code was built on. Recent Ubuntu versions (at least five years old now) provide a 32-bits x86 cross-compiler on all supported machines ("gcc-i686-linux-gnu" and "g++-i686-linux-gnu"), and since the CI uses Ubuntu as its base OS, that compiler is now used for x86 builds. Installing said cross-compiler, though, conflicts with the "gcc-multilib" and "g++-multilib" packages that are installed on the CI image as part of the 32-bits jobs setup procedure. This means that all 32-bits x86 builds have to be migrated to the new cross-compiler as well. Signed-off-by: Alessandro Gatti --- ports/unix/Makefile | 2 ++ py/dynruntime.mk | 4 ++-- tools/ci.sh | 27 ++++++++++++++++----------- 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/ports/unix/Makefile b/ports/unix/Makefile index 7d71fc3f955..8746d0b5efe 100644 --- a/ports/unix/Makefile +++ b/ports/unix/Makefile @@ -240,8 +240,10 @@ CFLAGS += -DMPZ_DIG_SIZE=16 # force 16 bits to work on both 32 and 64 bit archs endif ifeq ($(MICROPY_FORCE_32BIT),1) +ifeq ($(RUN_TESTS_MPY_CROSS_FLAGS),) RUN_TESTS_MPY_CROSS_FLAGS = --mpy-cross-flags='-march=x86' endif +endif ifeq ($(CROSS_COMPILE),arm-linux-gnueabi-) # Force disable error text compression when compiling for ARM as the compiler diff --git a/py/dynruntime.mk b/py/dynruntime.mk index e3c9ee4cbd5..966df204184 100644 --- a/py/dynruntime.mk +++ b/py/dynruntime.mk @@ -48,8 +48,8 @@ CLEAN_EXTRA += $(MOD).mpy .mpy_ld_cache-$(ARCH) ifeq ($(ARCH),x86) # x86 -CROSS = -CFLAGS_ARCH += -m32 -fno-stack-protector +CROSS = i686-linux-gnu- +CFLAGS_ARCH += -fno-stack-protector MICROPY_FLOAT_IMPL ?= double else ifeq ($(ARCH),x64) diff --git a/tools/ci.sh b/tools/ci.sh index 8081b113087..de671d3b527 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -630,7 +630,11 @@ CI_UNIX_OPTS_REPR_B=( CFLAGS_EXTRA="-DMICROPY_OBJ_REPR=MICROPY_OBJ_REPR_B -DMICROPY_PY_UCTYPES=0 -Dmp_int_t=int32_t -Dmp_uint_t=uint32_t" MICROPY_FORCE_32BIT=1 RUN_TESTS_MPY_CROSS_FLAGS="--mpy-cross-flags=\"-march=x86 -msmall-int-bits=30\"" +) +CI_UNIX_OPTS_X86=( + CROSS_COMPILE=i686-linux-gnu- + RUN_TESTS_MPY_CROSS_FLAGS=${RUN_TESTS_MPY_CROSS_FLAGS:-"--mpy-cross-flags=\"-march=x86\""} ) function ci_unix_build_helper { @@ -793,20 +797,20 @@ function ci_unix_coverage_run_native_mpy_tests { function ci_unix_32bit_setup { sudo dpkg --add-architecture i386 sudo apt-get update - sudo apt-get install gcc-multilib g++-multilib libffi-dev:i386 + sudo apt-get install gcc-i686-linux-gnu g++-i686-linux-gnu patchelf libffi-dev:i386 python -m pip install pyelftools python -m pip install ar - gcc --version + i686-linux-gnu-gcc --version python3 --version } function ci_unix_coverage_32bit_build { - ci_unix_build_helper VARIANT=coverage MICROPY_FORCE_32BIT=1 - ci_unix_build_ffi_lib_helper gcc -m32 + ci_unix_build_helper VARIANT=coverage MICROPY_FORCE_32BIT=1 "${CI_UNIX_OPTS_X86[@]}" + ci_unix_build_ffi_lib_helper i686-linux-gnu-gcc } function ci_unix_coverage_32bit_run_tests { - ci_unix_run_tests_full_helper coverage MICROPY_FORCE_32BIT=1 + ci_unix_run_tests_full_helper coverage MICROPY_FORCE_32BIT=1 "${CI_UNIX_OPTS_X86[@]}" } function ci_unix_coverage_32bit_run_native_mpy_tests { @@ -814,8 +818,8 @@ function ci_unix_coverage_32bit_run_native_mpy_tests { } function ci_unix_nanbox_build { - ci_unix_build_helper VARIANT=nanbox CFLAGS_EXTRA="-DMICROPY_PY_MATH_CONSTANTS=1" - ci_unix_build_ffi_lib_helper gcc -m32 + ci_unix_build_helper VARIANT=nanbox CFLAGS_EXTRA="-DMICROPY_PY_MATH_CONSTANTS=1" "${CI_UNIX_OPTS_X86[@]}" + ci_unix_build_ffi_lib_helper i686-linux-gnu-gcc } function ci_unix_nanbox_run_tests { @@ -823,7 +827,8 @@ function ci_unix_nanbox_run_tests { } function ci_unix_longlong_build { - ci_unix_build_helper VARIANT=longlong "${CI_UNIX_OPTS_SANITIZE_UNDEFINED[@]}" + ci_unix_build_helper VARIANT=longlong "${CI_UNIX_OPTS_SANITIZE_UNDEFINED[@]}" "${CI_UNIX_OPTS_X86[@]}" + patchelf --add-rpath "/usr/i686-linux-gnu/lib" ports/unix/build-longlong/micropython } function ci_unix_longlong_run_tests { @@ -1026,14 +1031,14 @@ EOF } function ci_unix_repr_b_build { - ci_unix_build_helper "${CI_UNIX_OPTS_REPR_B[@]}" - ci_unix_build_ffi_lib_helper gcc -m32 + ci_unix_build_helper "${CI_UNIX_OPTS_REPR_B[@]}" "${CI_UNIX_OPTS_X86[@]}" + ci_unix_build_ffi_lib_helper i686-linux-gnu-gcc } function ci_unix_repr_b_run_tests { # ci_unix_run_tests_full_no_native_helper is not used due to # https://github.com/micropython/micropython/issues/18105 - ci_unix_run_tests_helper "${CI_UNIX_OPTS_REPR_B[@]}" + ci_unix_run_tests_helper "${CI_UNIX_OPTS_REPR_B[@]}" "${CI_UNIX_OPTS_X86[@]}" } ######################################################################################## From 80705342e539014101f4820d447c5195aa8c28b2 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 9 Jan 2026 13:28:36 +0100 Subject: [PATCH 374/635] unix: Remove MICROPY_FORCE_32BIT flag usage. This commit removes support for forced 32-bits builds of the Unix port, as it only worked on x64 machines and x86 usage is low enough these days to allow making changes on how the latter target is built. Passing such flag to the Unix makefile will stop the build, as the flag itself will be removed from MicroPython entirely (right now only the MinGW Windows builds use it) in subsequent commits. CI build scripts had to be updated to manually pass the necessary flags that were once implied by MICROPY_FORCE_32BIT, for all targets that are meant to build 32-bits binaries. Finally, documentation for the Unix port has been updated with a section explaining how to make x86 builds on x64 hosts work again. Given that the 32-bits builds now use a cross-compiler, then other machines for which such a compiler is available can build x86 binaries too (eg. AArch64 or RISC-V 64). Signed-off-by: Alessandro Gatti --- ports/unix/Makefile | 20 +-- ports/unix/README.md | 126 +++++++++++++++++- ports/unix/mpconfigport.mk | 3 - .../unix/variants/longlong/mpconfigvariant.h | 2 +- .../unix/variants/longlong/mpconfigvariant.mk | 4 +- ports/unix/variants/nanbox/mpconfigvariant.mk | 3 +- tools/ci.sh | 5 +- 7 files changed, 136 insertions(+), 27 deletions(-) diff --git a/ports/unix/Makefile b/ports/unix/Makefile index 8746d0b5efe..0eee7b69840 100644 --- a/ports/unix/Makefile +++ b/ports/unix/Makefile @@ -16,6 +16,10 @@ endif # If the build directory is not given, make it reflect the variant name. BUILD ?= build-$(VARIANT) +ifneq ($(MICROPY_FORCE_32BIT),) +$(warning *** The MICROPY_FORCE_32BIT flag is no longer affecting builds, please update your environment ***) +endif + include ../../py/mkenv.mk -include mpconfigport.mk include $(VARIANT_DIR)/mpconfigvariant.mk @@ -107,11 +111,7 @@ endif # while cross-compile ports require gcc, so we test here for OSX and # if necessary override the value of 'CC' set in py/mkenv.mk ifeq ($(UNAME_S),Darwin) -ifeq ($(MICROPY_FORCE_32BIT),1) -CC = clang -m32 -else CC = clang -endif # Use clang syntax for map file LDFLAGS_ARCH = -Wl,-map,$@.map -Wl,-dead_strip else @@ -174,11 +174,7 @@ ifeq ($(MICROPY_STANDALONE),1) GIT_SUBMODULES += lib/libffi DEPLIBS += libffi LIBFFI_CFLAGS := -I$(shell ls -1d $(BUILD)/lib/libffi/include) - ifeq ($(MICROPY_FORCE_32BIT),1) - LIBFFI_LDFLAGS = $(BUILD)/lib/libffi/out/lib32/libffi.a - else - LIBFFI_LDFLAGS = $(BUILD)/lib/libffi/out/lib/libffi.a - endif +LIBFFI_LDFLAGS = $(BUILD)/lib/libffi/out/lib/libffi.a else # Use system version of libffi. LIBFFI_CFLAGS := $(shell pkg-config --cflags libffi) @@ -239,12 +235,6 @@ ifneq ($(FROZEN_MANIFEST),) CFLAGS += -DMPZ_DIG_SIZE=16 # force 16 bits to work on both 32 and 64 bit archs endif -ifeq ($(MICROPY_FORCE_32BIT),1) -ifeq ($(RUN_TESTS_MPY_CROSS_FLAGS),) -RUN_TESTS_MPY_CROSS_FLAGS = --mpy-cross-flags='-march=x86' -endif -endif - ifeq ($(CROSS_COMPILE),arm-linux-gnueabi-) # Force disable error text compression when compiling for ARM as the compiler # cannot optimise out the giant strcmp list generated for MP_MATCH_COMPRESSED. diff --git a/ports/unix/README.md b/ports/unix/README.md index 2276b2a381d..720be8a047c 100644 --- a/ports/unix/README.md +++ b/ports/unix/README.md @@ -19,7 +19,7 @@ To build the unix port locally then you will need: * git command line executable, unless you downloaded a source .tar.xz file from https://micropython.org/download/ -* gcc (or clang for macOS) toolchain +* an appropriate GCC or Clang toolchain for your target (macOS only supports Clang) * GNU Make * Python 3.x @@ -167,7 +167,7 @@ optimisations, assertions enabled, and debug symbols. ### Sanitizers -Sanitizers are extra runtime checks supported by gcc and clang. The CI process +Sanitizers are extra runtime checks supported by GCC and Clang. The CI process supports building with the "undefined behavior" (UBSan) or "address" (ASan) sanitizers. The script `tools/ci.sh` is the source of truth about how to build and run in these modes. @@ -182,3 +182,125 @@ Several classes of checks are disabled via compiler flags: check is intended to make sure locals in a "returned from" stack frame are not used. However, this mode interferes with various assumptions that MicroPython's stack checking, NLR, and GC rely on. + +### Notes about x86 (i686) support + +It used to be possible to create an x86 (32-bits) build on a x64 (64-bits) host +by passing `MICROPY_FORCE_32BIT=1` to `make`. That option was retired: x86 +usage has declined quite a bit in the past few years, and MicroPython now +supports at least one more mixed 32/64-bits target architecture for which +enabling `MICROPY_FORCE_32BIT` would make builds fail. + +x86 will be treated as a cross-compilation target from now on. This means you +will need to install a suitable compiler (on Ubuntu you can install either the +`gcc-i686-linux-gnu` and `g++-i686-linux-gnu` packages for GCC, or the `clang` +package for Clang, for example) and pass the appropriate command arguments to +`make` depending on which compiler you chose. + +### Building x86 (i686) code with GCC + +For GCC, you will need to pass the toolchain's command prefix to the +`CROSS_COMPILE` command line variable. + +This change is also extended to native modules, for which you may need to pass +the toolchain's command prefix to the `CROSS` command line variable if your +x86 compiler cannot be invoked with `i686-linux-gnu-gcc`. + +Or, as an example: + +```bash +$ printf "%s %s %s %s\n" $(lsb_release -d | cut -f 2) $(uname -m) +Ubuntu 24.04.4 LTS x86_64 + +$ i686-linux-gnu-gcc --version | head -n 1 +i686-linux-gnu-gcc (Ubuntu 13.3.0-6ubuntu2~24.04.1) 13.3.0 + +$ CROSS_COMPILE=i686-linux-gnu- make -C ports/unix +make: Entering directory '/ports/unix' +Use make V=1 or set BUILD_VERBOSE in your environment to increase build verbosity. +... +LINK build-standard/micropython + text data bss dec hex filename + 723115 36104 2124 761343 b9dff build-standard/micropython +make: Leaving directory '/ports/unix' + +$ file -b ports/unix/build-standard/micropython | cut -d, -f-2 +ELF 32-bit LSB pie executable, Intel 80386 + +# `i686-linux-gnu-` is the default prefix for x86 native modules now, it has +# been explicitly mentioned here in case you want to see how to set it. + +$ make -C examples/natmod/features0 ARCH=x86 CROSS=i686-linux-gnu- +make: Entering directory '/examples/natmod/features0' +GEN build/features0.config.h +CC features0.c +LINK build/features0.o +arch: EM_386 +text size: 192 +bss size: 0 +GOT entries: 4 +GEN features0.mpy +make: Leaving directory '/examples/natmod/features0' + +$ cd examples/natmod/features0 && ../../../ports/unix/build-standard/micropython +MicroPython v1.29.0-preview.490.gb4c58f7ba5.dirty on 2026-07-04; linux [GCC 13.3.0] version +Type "help()" for more information. +>>> import features0 +>>> features0.factorial(10) +3628800 +``` + +### Building x86 (i686) code with Clang + +For Clang, you will need need to pass both the name of the compiler to invoke +as the `CC` command line variable and the extra command line arguments needed +to let Clang know you are building an i686 binary as the `CFLAGS_EXTRA` and +`LDFLAGS_EXTRA` command line variables (usually +`--target=i686-unknown-linux-gnu`). + +For native modules, since linking is not done by the compiler, only the `CC` +and `CFLAGS_EXTRA` arguments are needed. + +Or, as an example: + +```bash +$ printf "%s %s %s %s\n" $(lsb_release -d | cut -f 2) $(uname -m) +Ubuntu 24.04.4 LTS x86_64 + +$ clang --version | head -1 +Ubuntu clang version 18.1.3 (1ubuntu1) + +$ clang -print-targets | grep -i 32-bit.x86 + x86 - 32-bit X86: Pentium-Pro and above + +$ make -C ports/unix CC=clang CFLAGS_EXTRA="--target=i686-unknown-linux-gnu" LDFLAGS_EXTRA='--target=i686-unknown-linux-gnu' +make: Entering directory '/ports/unix' +Use make V=1 or set BUILD_VERBOSE in your environment to increase build verbosity. +... +LINK build-standard/micropython + text data bss dec hex filename + 836241 34748 2052 873041 d5251 build-standard/micropython +make: Leaving directory '/ports/unix' + +$ file -b ports/unix/build-standard/micropython | cut -d, -f-2 +ELF 32-bit LSB pie executable, Intel 80386 + +$ make -C examples/natmod/features0 ARCH=x86 CC=clang CFLAGS_EXTRA="--target=i686-unknown-linux-gnu" +make: Entering directory '/examples/natmod/features0' +GEN build-x86/features0.config.h +CC features0.c +LINK build-x86/features0.o +arch: EM_386 +text size: 180 +bss size: 0 +GOT entries: 2 +GEN features0.mpy +make: Leaving directory '/examples/natmod/features0' + +$ cd examples/natmod/features0 && ../../../ports/unix/build-standard/micropython +MicroPython v1.29.0-preview.490.gb4c58f7ba5.dirty on 2026-07-04; linux [Clang 18.1.3] version +Type "help()" for more information. +>>> import features0 +>>> features0.factorial(10) +3628800 +``` diff --git a/ports/unix/mpconfigport.mk b/ports/unix/mpconfigport.mk index f5ad0a14365..57a402bfc8f 100644 --- a/ports/unix/mpconfigport.mk +++ b/ports/unix/mpconfigport.mk @@ -1,8 +1,5 @@ # Enable/disable modules and 3rd-party libs to be included in interpreter -# Build 32-bit binaries on a 64-bit host -MICROPY_FORCE_32BIT = 0 - # This variable can take the following values: # 0 - no readline, just simple stdin input # 1 - use MicroPython version of readline diff --git a/ports/unix/variants/longlong/mpconfigvariant.h b/ports/unix/variants/longlong/mpconfigvariant.h index d50d360b1fe..1554d537c04 100644 --- a/ports/unix/variants/longlong/mpconfigvariant.h +++ b/ports/unix/variants/longlong/mpconfigvariant.h @@ -32,7 +32,7 @@ // We build it on top of REPR C, which uses memory-efficient floating point // objects encoded directly mp_obj_t (30 bits only). -// Therefore this variant should be built using MICROPY_FORCE_32BIT=1 +// Therefore this variant should be built for a 32-bits target. #define MICROPY_OBJ_REPR (MICROPY_OBJ_REPR_C) #define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT) diff --git a/ports/unix/variants/longlong/mpconfigvariant.mk b/ports/unix/variants/longlong/mpconfigvariant.mk index 2d2c3706469..9fe20cd584d 100644 --- a/ports/unix/variants/longlong/mpconfigvariant.mk +++ b/ports/unix/variants/longlong/mpconfigvariant.mk @@ -1,7 +1,7 @@ # build interpreter with "bigints" implemented as "longlong" -# otherwise, small int is essentially 64-bit -MICROPY_FORCE_32BIT := 1 +# This needs to be built for a 32-bits target, otherwise small ints will +# essentially be 64-bit wide. MICROPY_PY_FFI := 0 diff --git a/ports/unix/variants/nanbox/mpconfigvariant.mk b/ports/unix/variants/nanbox/mpconfigvariant.mk index e588e657efc..6d63a86e9b0 100644 --- a/ports/unix/variants/nanbox/mpconfigvariant.mk +++ b/ports/unix/variants/nanbox/mpconfigvariant.mk @@ -1,3 +1,4 @@ # build interpreter with nan-boxing as object model (object repr D) -MICROPY_FORCE_32BIT = 1 +# This needs to be built for a 32-bits target, as object representation D is +# only meant to work on 32-bits machines. diff --git a/tools/ci.sh b/tools/ci.sh index de671d3b527..68b5f3d9177 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -628,7 +628,6 @@ CI_UNIX_OPTS_SANITIZE_UNDEFINED=( CI_UNIX_OPTS_REPR_B=( VARIANT=standard CFLAGS_EXTRA="-DMICROPY_OBJ_REPR=MICROPY_OBJ_REPR_B -DMICROPY_PY_UCTYPES=0 -Dmp_int_t=int32_t -Dmp_uint_t=uint32_t" - MICROPY_FORCE_32BIT=1 RUN_TESTS_MPY_CROSS_FLAGS="--mpy-cross-flags=\"-march=x86 -msmall-int-bits=30\"" ) @@ -805,12 +804,12 @@ function ci_unix_32bit_setup { } function ci_unix_coverage_32bit_build { - ci_unix_build_helper VARIANT=coverage MICROPY_FORCE_32BIT=1 "${CI_UNIX_OPTS_X86[@]}" + ci_unix_build_helper VARIANT=coverage "${CI_UNIX_OPTS_X86[@]}" ci_unix_build_ffi_lib_helper i686-linux-gnu-gcc } function ci_unix_coverage_32bit_run_tests { - ci_unix_run_tests_full_helper coverage MICROPY_FORCE_32BIT=1 "${CI_UNIX_OPTS_X86[@]}" + ci_unix_run_tests_full_helper coverage "${CI_UNIX_OPTS_X86[@]}" } function ci_unix_coverage_32bit_run_native_mpy_tests { From 13303f8d293f7bc33b865feb7ef4974fb307cabd Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 9 Jan 2026 13:44:21 +0100 Subject: [PATCH 375/635] py/py.mk: Move MICROPY_FORCE_32BIT to the Windows port's Makefile. This commit moves the definition of the "MICROPY_FORCE_32BIT" build flag away from the core's Makefile definition, migrating it to the Windows port's Makefile instead. Both Windows and Unix ports used this flag, which was intrinsically x64 specific. Since the Unix port is no longer using it and the Windows port is currently limited to x86/x64 builds it makes more sense to move that flag's support away from MicroPython's core. This assures that MinGW builds will still operate as usual without any changes. Support for this flag will probably be removed from the Windows port (and therefore from MicroPython) when Windows/Arm builds will show up. Signed-off-by: Alessandro Gatti --- ports/windows/Makefile | 7 +++++++ py/py.mk | 7 ------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/ports/windows/Makefile b/ports/windows/Makefile index 6e206e7f23c..82fa25f21a4 100644 --- a/ports/windows/Makefile +++ b/ports/windows/Makefile @@ -29,6 +29,13 @@ PROG ?= micropython QSTR_DEFS += ../unix/qstrdefsport.h QSTR_GLOBAL_DEPENDENCIES += $(VARIANT_DIR)/mpconfigvariant.h +# Enable building 32-bit code on 64-bit hosts. +ifeq ($(MICROPY_FORCE_32BIT),1) +CC += -m32 +CXX += -m32 +LD += -m32 +endif + # include py core make definitions include $(TOP)/py/py.mk include $(TOP)/extmod/extmod.mk diff --git a/py/py.mk b/py/py.mk index 9f9e900b97a..5dadb7db81c 100644 --- a/py/py.mk +++ b/py/py.mk @@ -21,13 +21,6 @@ QSTR_GLOBAL_REQUIREMENTS += $(HEADER_BUILD)/mpversion.h # some code is performance bottleneck and compiled with other optimization options CSUPEROPT = -O3 -# Enable building 32-bit code on 64-bit host. -ifeq ($(MICROPY_FORCE_32BIT),1) -CC += -m32 -CXX += -m32 -LD += -m32 -endif - # External modules written in C. ifneq ($(USER_C_MODULES),) # pre-define USERMOD variables as expanded so that variables are immediate From c8e440ea33a79a4f83132d81b3ab9e3fb11da8fa Mon Sep 17 00:00:00 2001 From: Rafal Date: Thu, 4 Jun 2026 22:45:00 +1000 Subject: [PATCH 376/635] esp32: Add support for ESP32-H2 along with two board definitions. This commit adds support for the ESP32-H2 processor from Espressif in the form of two board definitions - ESP32_GENERIC_H2 and M5STACK_NANOH2. Completed testing on the M5StackH2: - tested GPIO via on board LED - tested ADC channels can be read - I2C & SPI instantiation - BLE packet scanner - run_tests.py Signed-off-by: Rafal Wadowski --- ports/esp32/README.md | 2 +- .../esp32/boards/ESP32_GENERIC_H2/board.json | 20 +++++++++++ .../ESP32_GENERIC_H2/mpconfigboard.cmake | 1 + .../boards/ESP32_GENERIC_H2/mpconfigboard.h | 11 +++++++ ports/esp32/boards/M5STACK_NANOH2/board.json | 23 +++++++++++++ .../boards/M5STACK_NANOH2/mpconfigboard.cmake | 1 + .../boards/M5STACK_NANOH2/mpconfigboard.h | 9 +++++ ports/esp32/boards/M5STACK_NANOH2/pins.csv | 7 ++++ .../boards/mpconfigboard_esp32h2_common.cmake | 8 +++++ ports/esp32/boards/sdkconfig.h2 | 7 ++++ ports/esp32/machine_adc.c | 6 ++++ ports/esp32/machine_hw_spi.c | 8 ++--- ports/esp32/machine_pin.c | 7 +++- ports/esp32/machine_pin.h | 33 +++++++++++++++++++ ports/esp32/modmachine.c | 9 +++-- ports/esp32/mpconfigport.h | 2 ++ 16 files changed, 146 insertions(+), 8 deletions(-) create mode 100644 ports/esp32/boards/ESP32_GENERIC_H2/board.json create mode 100644 ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.cmake create mode 100644 ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h create mode 100644 ports/esp32/boards/M5STACK_NANOH2/board.json create mode 100644 ports/esp32/boards/M5STACK_NANOH2/mpconfigboard.cmake create mode 100644 ports/esp32/boards/M5STACK_NANOH2/mpconfigboard.h create mode 100644 ports/esp32/boards/M5STACK_NANOH2/pins.csv create mode 100644 ports/esp32/boards/mpconfigboard_esp32h2_common.cmake create mode 100644 ports/esp32/boards/sdkconfig.h2 mode change 100755 => 100644 ports/esp32/machine_pin.c diff --git a/ports/esp32/README.md b/ports/esp32/README.md index c097ca7e76d..54dd192e9e8 100644 --- a/ports/esp32/README.md +++ b/ports/esp32/README.md @@ -5,7 +5,7 @@ This is a port of MicroPython to the Espressif ESP32 series of microcontrollers. It uses the ESP-IDF framework and MicroPython runs as a task under FreeRTOS. -Currently supports ESP32, ESP32-C2 (aka ESP8684), ESP32-C3, ESP32-C5, ESP32-C6, +Currently supports ESP32, ESP32-C2 (aka ESP8684), ESP32-C3, ESP32-C5, ESP32-C6, ESP32-H2, ESP32-P4, ESP32-S2 and ESP32-S3. ESP8266 is supported by a separate MicroPython port. Supported features include: diff --git a/ports/esp32/boards/ESP32_GENERIC_H2/board.json b/ports/esp32/boards/ESP32_GENERIC_H2/board.json new file mode 100644 index 00000000000..5e19282f71e --- /dev/null +++ b/ports/esp32/boards/ESP32_GENERIC_H2/board.json @@ -0,0 +1,20 @@ +{ + "deploy": [ + "../deploy.md" + ], + "deploy_options": { + "flash_offset": "0" + }, + "docs": "", + "features": [ + "BLE" + ], + "images": [ + "esp32h2_devkitmini.jpg" + ], + "mcu": "esp32h2", + "product": "ESP32-H2", + "thumbnail": "", + "url": "https://www.espressif.com/en/products/modules", + "vendor": "Espressif" +} diff --git a/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.cmake b/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.cmake new file mode 100644 index 00000000000..fb84642735e --- /dev/null +++ b/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.cmake @@ -0,0 +1 @@ +include(boards/mpconfigboard_esp32h2_common.cmake) diff --git a/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h new file mode 100644 index 00000000000..9c83a8f3650 --- /dev/null +++ b/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h @@ -0,0 +1,11 @@ +// This configuration is for a generic ESP32H2 board with 4MiB (or more) of flash. + +#define MICROPY_HW_BOARD_NAME "ESP32H2 module" +#define MICROPY_HW_MCU_NAME "ESP32-H2" + +// Disable WiFi/WLAN (ESP32-H2 does not have WiFi) +#define MICROPY_PY_NETWORK_WLAN (0) +#define MICROPY_PY_ESPNOW (0) + +// Enable UART REPL for modules that have an external USB-UART and don't use native USB. +#define MICROPY_HW_ENABLE_UART_REPL (1) diff --git a/ports/esp32/boards/M5STACK_NANOH2/board.json b/ports/esp32/boards/M5STACK_NANOH2/board.json new file mode 100644 index 00000000000..0259b6c5de8 --- /dev/null +++ b/ports/esp32/boards/M5STACK_NANOH2/board.json @@ -0,0 +1,23 @@ +{ + "deploy": [ + "../deploy_nativeusb.md" + ], + "deploy_options": { + "flash_offset": "0" + }, + "docs": "", + "features": [ + "BLE", + "RGB LED", + "USB", + "USB-C", + "JST-PH" + ], + "images": [ + "m5stack_nanoh2.jpg" + ], + "mcu": "esp32h2", + "product": "NanoH2", + "url": "https://shop.m5stack.com/products/m5stack-nanoh2-dev-kit-esp32-h2", + "vendor": "M5Stack" +} diff --git a/ports/esp32/boards/M5STACK_NANOH2/mpconfigboard.cmake b/ports/esp32/boards/M5STACK_NANOH2/mpconfigboard.cmake new file mode 100644 index 00000000000..fb84642735e --- /dev/null +++ b/ports/esp32/boards/M5STACK_NANOH2/mpconfigboard.cmake @@ -0,0 +1 @@ +include(boards/mpconfigboard_esp32h2_common.cmake) diff --git a/ports/esp32/boards/M5STACK_NANOH2/mpconfigboard.h b/ports/esp32/boards/M5STACK_NANOH2/mpconfigboard.h new file mode 100644 index 00000000000..2e7964ca05b --- /dev/null +++ b/ports/esp32/boards/M5STACK_NANOH2/mpconfigboard.h @@ -0,0 +1,9 @@ +#define MICROPY_HW_BOARD_NAME "M5Stack NanoH2" +#define MICROPY_HW_MCU_NAME "ESP32-H2" + +// Disable WiFi/WLAN (ESP32-H2 does not have WiFi) +#define MICROPY_PY_NETWORK_WLAN (0) +#define MICROPY_PY_ESPNOW (0) + +#define MICROPY_HW_I2C0_SCL (1) +#define MICROPY_HW_I2C0_SDA (2) diff --git a/ports/esp32/boards/M5STACK_NANOH2/pins.csv b/ports/esp32/boards/M5STACK_NANOH2/pins.csv new file mode 100644 index 00000000000..89967b07b31 --- /dev/null +++ b/ports/esp32/boards/M5STACK_NANOH2/pins.csv @@ -0,0 +1,7 @@ +G1,GPIO1 +G2,GPIO2 +IR_LED,GPIO3 +LED_BLUE,GPIO4 +BUTTON,GPIO9 +NEOPIXEL_POWER,GPIO10 +NEOPIXEL,GPIO11 diff --git a/ports/esp32/boards/mpconfigboard_esp32h2_common.cmake b/ports/esp32/boards/mpconfigboard_esp32h2_common.cmake new file mode 100644 index 00000000000..d84cb0280c6 --- /dev/null +++ b/ports/esp32/boards/mpconfigboard_esp32h2_common.cmake @@ -0,0 +1,8 @@ +set(IDF_TARGET esp32h2) + +set(SDKCONFIG_DEFAULTS + boards/sdkconfig.base + boards/sdkconfig.riscv + boards/sdkconfig.h2 + boards/sdkconfig.ble +) diff --git a/ports/esp32/boards/sdkconfig.h2 b/ports/esp32/boards/sdkconfig.h2 new file mode 100644 index 00000000000..92eb97bb065 --- /dev/null +++ b/ports/esp32/boards/sdkconfig.h2 @@ -0,0 +1,7 @@ +# 802.15.4 not currently supported in MicroPython, disabling saves +# a little compile time (no difference in binary) +CONFIG_IEEE802154_ENABLED=n + +# Using the SPI flash implementation in ROM saves about 10KB of binary size +# (and some static RAM) +CONFIG_SPI_FLASH_ROM_IMPL=y diff --git a/ports/esp32/machine_adc.c b/ports/esp32/machine_adc.c index ff80762ebd7..a14adef3ddf 100644 --- a/ports/esp32/machine_adc.c +++ b/ports/esp32/machine_adc.c @@ -115,6 +115,12 @@ static const machine_adc_obj_t madc_obj[] = { {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_4, GPIO_NUM_4}, {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_5, GPIO_NUM_5}, {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_6, GPIO_NUM_6}, + #elif CONFIG_IDF_TARGET_ESP32H2 + {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_0, GPIO_NUM_1}, + {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_1, GPIO_NUM_2}, + {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_2, GPIO_NUM_3}, + {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_3, GPIO_NUM_4}, + {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_4, GPIO_NUM_5}, #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_0, GPIO_NUM_1}, {{&machine_adc_type}, ADCBLOCK1, ADC_CHANNEL_1, GPIO_NUM_2}, diff --git a/ports/esp32/machine_hw_spi.c b/ports/esp32/machine_hw_spi.c index 7153084b1b6..f2b47a0f13e 100644 --- a/ports/esp32/machine_hw_spi.c +++ b/ports/esp32/machine_hw_spi.c @@ -38,10 +38,10 @@ #include "soc/spi_pins.h" // SPI mappings by device, naming used by IDF old/new -// MicroPython | ESP32 | ESP32S2 | ESP32S3 | ESP32C3 | ESP32C6 -// ------------+-----------+-----------+---------+---------+--------- -// SPI(id=1) | HSPI/SPI2 | FSPI/SPI2 | SPI2 | SPI2 | SPI2 -// SPI(id=2) | VSPI/SPI3 | HSPI/SPI3 | SPI3 | err | err +// MicroPython | ESP32 | ESP32S2 | ESP32S3 | ESP32C3 | ESP32C6 | ESP32H2 +// ------------+-----------+-----------+---------+---------+---------+--------- +// SPI(id=1) | HSPI/SPI2 | FSPI/SPI2 | SPI2 | SPI2 | SPI2 | SPI2 +// SPI(id=2) | VSPI/SPI3 | HSPI/SPI3 | SPI3 | err | err | err // Number of available hardware SPI peripherals. #if SOC_SPI_PERIPH_NUM > 2 diff --git a/ports/esp32/machine_pin.c b/ports/esp32/machine_pin.c old mode 100755 new mode 100644 index 5eb13a48ce5..f3996924149 --- a/ports/esp32/machine_pin.c +++ b/ports/esp32/machine_pin.c @@ -180,7 +180,7 @@ static mp_obj_t machine_pin_obj_init_helper(const machine_pin_obj_t *self, size_ // reset the pin to digital if this is a mode-setting init (grab it back from ADC) if (args[ARG_mode].u_obj != mp_const_none) { if (rtc_gpio_is_valid_gpio(index)) { - #if !(CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C6) + #if !(CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2) rtc_gpio_deinit(index); #endif } @@ -201,6 +201,11 @@ static mp_obj_t machine_pin_obj_init_helper(const machine_pin_obj_t *self, size_ CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } #endif + #if CONFIG_IDF_TARGET_ESP32H2 && !MICROPY_HW_ESP_USB_SERIAL_JTAG + if (index == 26 || index == 27) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + } + #endif // configure the pin for gpio esp_rom_gpio_pad_select_gpio(index); diff --git a/ports/esp32/machine_pin.h b/ports/esp32/machine_pin.h index c63630eb85d..3801000606b 100644 --- a/ports/esp32/machine_pin.h +++ b/ports/esp32/machine_pin.h @@ -167,6 +167,39 @@ #define MICROPY_HW_ENABLE_GPIO23 (1) // GPIO 24-30 are used for spi/sip flash. +#elif CONFIG_IDF_TARGET_ESP32H2 + +#define MICROPY_HW_ENABLE_GPIO0 (1) +#define MICROPY_HW_ENABLE_GPIO1 (1) +#define MICROPY_HW_ENABLE_GPIO2 (1) +#define MICROPY_HW_ENABLE_GPIO3 (1) +#define MICROPY_HW_ENABLE_GPIO4 (1) +#define MICROPY_HW_ENABLE_GPIO5 (1) +#define MICROPY_HW_ENABLE_GPIO6 (0) +#define MICROPY_HW_ENABLE_GPIO7 (0) +#define MICROPY_HW_ENABLE_GPIO8 (1) +#define MICROPY_HW_ENABLE_GPIO9 (1) +#define MICROPY_HW_ENABLE_GPIO10 (1) +#define MICROPY_HW_ENABLE_GPIO11 (1) +#define MICROPY_HW_ENABLE_GPIO12 (1) +#define MICROPY_HW_ENABLE_GPIO13 (1) +#define MICROPY_HW_ENABLE_GPIO14 (1) +#define MICROPY_HW_ENABLE_GPIO15 (0) +#define MICROPY_HW_ENABLE_GPIO16 (0) +#define MICROPY_HW_ENABLE_GPIO17 (0) +#define MICROPY_HW_ENABLE_GPIO18 (0) +#define MICROPY_HW_ENABLE_GPIO19 (0) +#define MICROPY_HW_ENABLE_GPIO20 (0) +#define MICROPY_HW_ENABLE_GPIO21 (0) +#define MICROPY_HW_ENABLE_GPIO22 (1) +#define MICROPY_HW_ENABLE_GPIO23 (1) +#define MICROPY_HW_ENABLE_GPIO24 (1) +#define MICROPY_HW_ENABLE_GPIO25 (1) +#if !MICROPY_HW_ESP_USB_SERIAL_JTAG +#define MICROPY_HW_ENABLE_GPIO26 (1) +#define MICROPY_HW_ENABLE_GPIO27 (1) +#endif + #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #define MICROPY_HW_ENABLE_GPIO0 (1) diff --git a/ports/esp32/modmachine.c b/ports/esp32/modmachine.c index b0335520417..968e64123c0 100644 --- a/ports/esp32/modmachine.c +++ b/ports/esp32/modmachine.c @@ -99,13 +99,18 @@ static void mp_machine_set_freq(size_t n_args, const mp_obj_t *args) { mp_raise_ValueError(MP_ERROR_TEXT("frequency must be 80MHz or 120MHz")); } #else - if (freq != 20 && freq != 40 && freq != 80 && freq != 160 - #if !(CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6) + if (freq != 20 && freq != 40 && freq != 80 + #if !(CONFIG_IDF_TARGET_ESP32H2) + && freq != 160 + #endif + #if !(CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2) && freq != 240 #endif ) { #if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 mp_raise_ValueError(MP_ERROR_TEXT("frequency must be 20MHz, 40MHz, 80Mhz or 160MHz")); + #elif CONFIG_IDF_TARGET_ESP32H2 + mp_raise_ValueError(MP_ERROR_TEXT("frequency must be 20MHz, 40MHz or 80Mhz")); #else mp_raise_ValueError(MP_ERROR_TEXT("frequency must be 20MHz, 40MHz, 80Mhz, 160MHz or 240MHz")); #endif diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index 20827cf81e7..632c2f31774 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -186,6 +186,8 @@ #define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-esp32c5" #elif CONFIG_IDF_TARGET_ESP32C6 #define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-esp32c6" +#elif CONFIG_IDF_TARGET_ESP32H2 +#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-esp32h2" #elif CONFIG_IDF_TARGET_ESP32P4 #define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-esp32p4" #endif From b9116c39fd1bf9655110127b9f64a142db17ef39 Mon Sep 17 00:00:00 2001 From: Rafal Wadowski Date: Sun, 14 Jun 2026 08:28:12 +1000 Subject: [PATCH 377/635] tests: Update tests for compatibility with ESP32-H2. Added pins for I2S. Added ESP32-H2 check to reduce number of SPI peripherals. Signed-off-by: Rafal Wadowski --- tests/extmod/machine_i2s_rate.py | 9 +++++---- tests/target_wiring/esp32.py | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/extmod/machine_i2s_rate.py b/tests/extmod/machine_i2s_rate.py index f6de3d8f13c..9262a42f491 100644 --- a/tests/extmod/machine_i2s_rate.py +++ b/tests/extmod/machine_i2s_rate.py @@ -26,11 +26,12 @@ (2, Pin("D4"), Pin("D3"), Pin("D2"), None), ) elif "esp32" in sys.platform: - try: - i2s_instances = ((0, Pin(18), Pin(19), Pin(21), Pin(14)),) - except ValueError: - # fallback to lower pin number for ESP32-C3 + if "ESP32-C3" in sys.implementation._machine: i2s_instances = ((0, Pin(6), Pin(7), Pin(10), Pin(11)),) + elif "ESP32-H2" in sys.implementation._machine: + i2s_instances = ((0, Pin(3), Pin(4), Pin(10), Pin(12)),) + else: + i2s_instances = ((0, Pin(18), Pin(19), Pin(21), Pin(14)),) # Allow for small additional RTOS overhead MAX_DELTA_MS = 8 diff --git a/tests/target_wiring/esp32.py b/tests/target_wiring/esp32.py index 068f14ae77e..a707a171c8b 100644 --- a/tests/target_wiring/esp32.py +++ b/tests/target_wiring/esp32.py @@ -9,7 +9,7 @@ uart_loopback_args = (1,) uart_loopback_kwargs = {"tx": 4, "rx": 5} -if "ESP32-C" in sys.implementation._machine: +if "ESP32-C" in sys.implementation._machine or "ESP32-H2" in sys.implementation._machine: spi_standalone_args_list = [(1,)] else: spi_standalone_args_list = [(1,), (2,)] From b1125d750fe7bc53412e02050d6b2d149eed412e Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 6 Jul 2026 22:57:25 +1000 Subject: [PATCH 378/635] tools/ci.sh: Build ESP32_GENERIC_H2 as part of esp32 CI. Signed-off-by: Damien George --- .github/workflows/ports_esp32.yml | 4 ++-- tools/ci.sh | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/.github/workflows/ports_esp32.yml b/.github/workflows/ports_esp32.yml index d8c1f40e2b0..ac18b82fc5d 100644 --- a/.github/workflows/ports_esp32.yml +++ b/.github/workflows/ports_esp32.yml @@ -34,13 +34,13 @@ jobs: - esp32_build_cmod_spiram_s2 - esp32_build_s3_c3 - esp32_build_c2_c5_c6 - - esp32_build_p4 + - esp32_build_h2_p4 exclude: # Exclude some jobs on the oldest IDF version, to save resources - idf_ver: *oldest ci_func: esp32_build_c2_c5_c6 - idf_ver: *oldest - ci_func: esp32_build_p4 + ci_func: esp32_build_h2_p4 runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 diff --git a/tools/ci.sh b/tools/ci.sh index 68b5f3d9177..91cd1aa6328 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -274,9 +274,10 @@ function ci_esp32_build_c2_c5_c6 { make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_C6 } -function ci_esp32_build_p4 { +function ci_esp32_build_h2_p4 { ci_esp32_build_common + make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_H2 make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_P4 make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_P4 BOARD_VARIANT=C6_WIFI } From 6d1c47bc55496bb31923cc401ba34c2a0849b0a9 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 6 Jul 2026 23:31:56 +1000 Subject: [PATCH 379/635] esp32/lockfiles: Add lockfile for ESP32-H2. Signed-off-by: Damien George --- .../esp32/lockfiles/dependencies.lock.esp32h2 | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 ports/esp32/lockfiles/dependencies.lock.esp32h2 diff --git a/ports/esp32/lockfiles/dependencies.lock.esp32h2 b/ports/esp32/lockfiles/dependencies.lock.esp32h2 new file mode 100644 index 00000000000..a79f823bdea --- /dev/null +++ b/ports/esp32/lockfiles/dependencies.lock.esp32h2 @@ -0,0 +1,21 @@ +dependencies: + espressif/mdns: + component_hash: 46ee81d32fbf850462d8af1e83303389602f6a6a9eddd2a55104cb4c063858ed + dependencies: + - name: idf + require: private + version: '>=5.0' + source: + registry_url: https://components.espressif.com/ + type: service + version: 1.1.0 + idf: + source: + type: idf + version: 5.5.2 +direct_dependencies: +- espressif/mdns +- idf +manifest_hash: 40b684ab14058130e675aab422296e4ad9d87ee39c5aa46d7b3df55c245e14f5 +target: esp32h2 +version: 2.0.0 From 5e19abdbc7cf566e6d04e5af43a867b52435c827 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 380/635] py/mpconfig: Add MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS. Signed-off-by: Jos Verlinde --- py/mpconfig.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/py/mpconfig.h b/py/mpconfig.h index 6bd179e3b83..7d9a98fd92e 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -1375,6 +1375,11 @@ typedef time_t mp_timestamp_t; #define MICROPY_PY_BUILTINS_STR_UNICODE_CHECK (MICROPY_PY_BUILTINS_STR_UNICODE) #endif +// Whether bytes.decode() supports the 'ignore' and 'replace' error handlers +#ifndef MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS +#define MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_EXTRA_FEATURES) +#endif + // Whether str.center() method provided #ifndef MICROPY_PY_BUILTINS_STR_CENTER #define MICROPY_PY_BUILTINS_STR_CENTER (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_EXTRA_FEATURES) From bcde6f518407dea51e4f7738769f7540ad0c0b05 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 381/635] py/objstr: Implement bytes.decode() 'ignore' and 'replace' modes. Raises LookupError for not implemented error handlers. Improves repr() rendering for unicode. Signed-off-by: Jos Verlinde --- py/objstr.c | 92 ++++++++++++++++++++++++++++++++++++++++++++-- py/objstrunicode.c | 12 +++++- 2 files changed, 100 insertions(+), 4 deletions(-) diff --git a/py/objstr.c b/py/objstr.c index 06afb91fc7f..5973dd8b4df 100644 --- a/py/objstr.c +++ b/py/objstr.c @@ -209,19 +209,104 @@ mp_obj_t mp_obj_str_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ } default: // 2 or 3 args - // TODO: validate 2nd/3rd args + #if MICROPY_PY_BUILTINS_BYTEARRAY + if (mp_obj_is_type(args[0], &mp_type_bytes) || mp_obj_is_type(args[0], &mp_type_bytearray)) { + #else if (mp_obj_is_type(args[0], &mp_type_bytes)) { + #endif GET_STR_DATA_LEN(args[0], str_data, str_len); GET_STR_HASH(args[0], str_hash); if (str_hash == 0) { str_hash = qstr_compute_hash(str_data, str_len); } + #if MICROPY_PY_BUILTINS_STR_UNICODE_CHECK - if (!utf8_check(str_data, str_len)) { - mp_raise_msg(&mp_type_UnicodeError, NULL); + #if MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS + // Check if error handler is specified (3rd argument) + const char *errors = "strict"; + if (n_args >= 3 && args[2] != mp_const_none) { + errors = mp_obj_str_get_str(args[2]); } #endif + // Fast path: if data is valid UTF-8, return directly + if (utf8_check(str_data, str_len)) { + // Check if a qstr with this data already exists + qstr q = qstr_find_strn((const char *)str_data, str_len); + if (q != MP_QSTRnull) { + return MP_OBJ_NEW_QSTR(q); + } + + mp_obj_str_t *o = MP_OBJ_TO_PTR(mp_obj_new_str_copy(type, NULL, str_len)); + o->data = str_data; + o->hash = str_hash; + return MP_OBJ_FROM_PTR(o); + } + + // Data has invalid UTF-8, handle based on error mode + #if MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS + // Error handlers are enabled + bool do_ignore = strcmp(errors, "ignore") == 0; + bool do_replace = strcmp(errors, "replace") == 0; + + if (do_ignore || do_replace) { + // Build new string skipping/replacing invalid bytes + vstr_t vstr; + vstr_init(&vstr, str_len); + const byte *p = str_data; + const byte *end = str_data + str_len; + + while (p < end) { + byte c = *p; + if (c < 0x80) { + // Valid ASCII + vstr_add_byte(&vstr, c); + p++; + } else if (c >= 0xc0 && c < 0xf8) { + // Potential multi-byte sequence + uint8_t need = (0xe5 >> ((c >> 3) & 0x6)) & 3; + const byte *seq_start = p; + p++; + + // Check continuation bytes + uint8_t got = 0; + while (got < need && p < end && UTF8_IS_CONT(*p)) { + got++; + p++; + } + + if (got == need) { + // Valid complete sequence, decode and add the character + unichar ch = *seq_start & (0x7f >> need); + for (uint8_t i = 0; i < need; i++) { + ch = (ch << 6) | (seq_start[i + 1] & 0x3f); + } + vstr_add_char(&vstr, ch); + } else if (do_replace) { + // Invalid or incomplete sequence - replace with U+FFFD + vstr_add_char(&vstr, 0xFFFD); + } + // For 'ignore' mode, do nothing (skip invalid bytes) + } else if (do_replace) { + // Invalid start byte - replace with U+FFFD + vstr_add_char(&vstr, 0xFFFD); + p++; + } else { + // Invalid start byte - skip for 'ignore' mode + p++; + } + } + + return mp_obj_new_str_type_from_vstr(type, &vstr); + } else { + // Strict mode (or unrecognized error handler) + mp_raise_msg(&mp_type_UnicodeError, NULL); + } + #else + // Error handlers are not enabled - just raise UnicodeError on invalid UTF-8 + mp_raise_msg(&mp_type_UnicodeError, NULL); + #endif + #else // Check if a qstr with this data already exists qstr q = qstr_find_strn((const char *)str_data, str_len); if (q != MP_QSTRnull) { @@ -232,6 +317,7 @@ mp_obj_t mp_obj_str_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ o->data = str_data; o->hash = str_hash; return MP_OBJ_FROM_PTR(o); + #endif } else { mp_buffer_info_t bufinfo; mp_get_buffer_raise(args[0], &bufinfo, MP_BUFFER_READ); diff --git a/py/objstrunicode.c b/py/objstrunicode.c index d7ce4fca0e5..fc511667a36 100644 --- a/py/objstrunicode.c +++ b/py/objstrunicode.c @@ -57,9 +57,11 @@ static void uni_print_quoted(const mp_print_t *print, const byte *str_data, uint mp_printf(print, "%c", quote_char); const byte *s = str_data, *top = str_data + str_len; while (s < top) { + const byte *seq_start = s; unichar ch; ch = utf8_get_char(s); s = utf8_next_char(s); + size_t seq_len = s - seq_start; if (ch == quote_char) { mp_printf(print, "\\%c", quote_char); } else if (ch == '\\') { @@ -72,11 +74,19 @@ static void uni_print_quoted(const mp_print_t *print, const byte *str_data, uint mp_print_str(print, "\\r"); } else if (ch == '\t') { mp_print_str(print, "\\t"); - } else if (ch < 0x100) { + } else if (ch <= 127) { mp_printf(print, "\\x%02x", ch); + } else if (ch < 0xD800) { + // Printable Unicode character (excluding surrogates) - output UTF-8 bytes directly + print->print_strn(print->data, (const char *)seq_start, seq_len); + } else if (ch >= 0xE000 && ch < 0x110000) { + // Printable Unicode character (after surrogates) - output UTF-8 bytes directly + print->print_strn(print->data, (const char *)seq_start, seq_len); } else if (ch < 0x10000) { + // Surrogate (0xD800-0xDFFF) - output as \uXXXX escape. mp_printf(print, "\\u%04x", ch); } else { + // Invalid (>=0x110000) - output as \UXXXXXXXX escape. mp_printf(print, "\\U%08x", ch); } } From 770bb3b79b0df0b23f93ac9ccc0474f31a6ad650 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 382/635] py/objstr: Validate encoding for decode and encode. Only accepts `utf-8`, `utf8` or `ascii` Fixes https://github.com/micropython/micropython/issues/15849 Signed-off-by: Jos Verlinde --- py/objstr.c | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/py/objstr.c b/py/objstr.c index 5973dd8b4df..f51ae92c4a9 100644 --- a/py/objstr.c +++ b/py/objstr.c @@ -246,11 +246,24 @@ mp_obj_t mp_obj_str_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ // Data has invalid UTF-8, handle based on error mode #if MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS // Error handlers are enabled - bool do_ignore = strcmp(errors, "ignore") == 0; - bool do_replace = strcmp(errors, "replace") == 0; + #if !MICROPY_PY_BUILTINS_BYTES_DECODE_REPLACE + // Raise NotImplementedError if 'replace' is used but not enabled + if (strcmp(errors, "replace") == 0) { + mp_raise_NotImplementedError(NULL); + } + #endif - if (do_ignore || do_replace) { + if (strcmp(errors, "ignore") == 0 + #if MICROPY_PY_BUILTINS_BYTES_DECODE_REPLACE + || strcmp(errors, "replace") == 0 + #endif + ) { // Build new string skipping/replacing invalid bytes + #if MICROPY_PY_BUILTINS_BYTES_DECODE_REPLACE + bool do_replace = strcmp(errors, "replace") == 0; + #else + const bool do_replace = false; + #endif vstr_t vstr; vstr_init(&vstr, str_len); const byte *p = str_data; @@ -2069,6 +2082,17 @@ static mp_obj_t bytes_decode(size_t n_args, const mp_obj_t *args) { new_args[1] = MP_OBJ_NEW_QSTR(MP_QSTR_utf_hyphen_8); args = new_args; n_args++; + } else if (n_args >= 2) { + // Validate encoding parameter + // MicroPython only supports UTF-8 encoding + const char *encoding = mp_obj_str_get_str(args[1]); + + // Accept utf-8 and ascii (ascii is a subset of utf-8) + if (!(strcmp(encoding, "utf-8") == 0 || strcmp(encoding, "utf8") == 0 || + strcmp(encoding, "ascii") == 0)) { + mp_raise_msg_varg(&mp_type_LookupError, + MP_ERROR_TEXT("encoding not supported: %s"), encoding); + } } return mp_obj_str_make_new(&mp_type_str, n_args, 0, args); } @@ -2082,6 +2106,17 @@ static mp_obj_t str_encode(size_t n_args, const mp_obj_t *args) { new_args[1] = MP_OBJ_NEW_QSTR(MP_QSTR_utf_hyphen_8); args = new_args; n_args++; + } else if (n_args >= 2) { + // Validate encoding parameter + // MicroPython only supports UTF-8 encoding + const char *encoding = mp_obj_str_get_str(args[1]); + + // Accept utf-8 and ascii (ascii is a subset of utf-8) + if (!(strcmp(encoding, "utf-8") == 0 || strcmp(encoding, "utf8") == 0 || + strcmp(encoding, "ascii") == 0)) { + mp_raise_msg_varg(&mp_type_LookupError, + MP_ERROR_TEXT("encoding not supported: %s"), encoding); + } } return bytes_make_new(NULL, n_args, 0, args); } From ed9071015a3259edea6737f669810764b3625061 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 383/635] py/objstr: Enhance utf-8 character handling in string formatting. Fixes: issue 3364 Fixes: issue 13084 Signed-off-by: Jos Verlinde --- py/objstr.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/py/objstr.c b/py/objstr.c index f51ae92c4a9..5da177db979 100644 --- a/py/objstr.c +++ b/py/objstr.c @@ -1418,8 +1418,19 @@ static vstr_t mp_obj_str_format_helper(const char *str, const char *top, int *ar continue; case 'c': { + #if MICROPY_PY_BUILTINS_STR_UNICODE + mp_uint_t c = mp_obj_get_int(arg); + if (c >= 0x110000) { + mp_raise_msg(&mp_type_OverflowError, MP_ERROR_TEXT("chr() arg not in range(0x110000)")); + } + VSTR_FIXED(ch_vstr, 4); + vstr_add_char(&ch_vstr, c); + mp_print_strn(&print, ch_vstr.buf, ch_vstr.len, flags, fill, width); + vstr_clear(&ch_vstr); + #else char ch = mp_obj_get_int(arg); mp_print_strn(&print, &ch, 1, flags, fill, width); + #endif continue; } @@ -1712,8 +1723,21 @@ static mp_obj_t str_modulo_format(mp_obj_t pattern, size_t n_args, const mp_obj_ } mp_print_strn(&print, s, 1, flags, ' ', width); } else if (arg_looks_integer(arg)) { + #if MICROPY_PY_BUILTINS_STR_UNICODE + mp_uint_t c = mp_obj_get_int(arg); + if (c >= 0x110000) { + mp_raise_msg(&mp_type_OverflowError, MP_ERROR_TEXT("%c arg not in range(0x110000)")); + } + vstr_t ch_vstr; + vstr_init_len(&ch_vstr, 4); + ch_vstr.len = 0; + vstr_add_char(&ch_vstr, c); + mp_print_strn(&print, ch_vstr.buf, ch_vstr.len, flags, ' ', width); + vstr_clear(&ch_vstr); + #else char ch = mp_obj_get_int(arg); mp_print_strn(&print, &ch, 1, flags, ' ', width); + #endif } else { mp_raise_TypeError(MP_ERROR_TEXT("integer needed")); } From 70666e75cd0f5d03d2144dea8052467f75868de7 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 384/635] py/objstr: Fix str_center for Unicode strings. Fixes Issue 17827 Signed-off-by: Jos Verlinde --- py/objstr.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/py/objstr.c b/py/objstr.c index 5da177db979..42f27bbbf97 100644 --- a/py/objstr.c +++ b/py/objstr.c @@ -1061,14 +1061,33 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(str_rstrip_obj, 1, 2, str_rstrip); static mp_obj_t str_center(mp_obj_t str_in, mp_obj_t width_in) { GET_STR_DATA_LEN(str_in, str, str_len); mp_uint_t width = mp_obj_get_int(width_in); + + #if MICROPY_PY_BUILTINS_STR_UNICODE + // Get character count (not byte count) for proper Unicode handling + size_t char_len = utf8_charlen(str, str_len); + if (char_len >= width) { + return str_in; + } + // Calculate padding: width is in characters, need to convert to bytes for allocation + mp_uint_t padding_chars = width - char_len; + // Padding is always spaces (1 byte each), plus the original string bytes + mp_uint_t total_bytes = padding_chars + str_len; + #else + // Non-Unicode build: byte length equals character length if (str_len >= width) { return str_in; } + mp_uint_t total_bytes = width; + #endif // MICROPY_PY_BUILTINS_STR_UNICODE vstr_t vstr; - vstr_init_len(&vstr, width); - memset(vstr.buf, ' ', width); + vstr_init_len(&vstr, total_bytes); + memset(vstr.buf, ' ', total_bytes); + #if MICROPY_PY_BUILTINS_STR_UNICODE + int left = padding_chars / 2; + #else int left = (width - str_len) / 2; + #endif // MICROPY_PY_BUILTINS_STR_UNICODE memcpy(vstr.buf + left, str, str_len); return mp_obj_new_str_type_from_vstr(mp_obj_get_type(str_in), &vstr); } From b2b86db880c135dc13280035539f6a6f3c562636 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 385/635] py/objstr: Optimize character handling and encoding validation. Signed-off-by: Jos Verlinde --- py/modbuiltins.c | 2 +- py/objstr.c | 295 +++++++++++++++++++++-------------------------- 2 files changed, 130 insertions(+), 167 deletions(-) diff --git a/py/modbuiltins.c b/py/modbuiltins.c index eabc562f19d..caa8c28dcb9 100644 --- a/py/modbuiltins.c +++ b/py/modbuiltins.c @@ -138,7 +138,7 @@ static mp_obj_t mp_builtin_chr(mp_obj_t o_in) { #if MICROPY_PY_BUILTINS_STR_UNICODE mp_uint_t c = mp_obj_get_int(o_in); if (c >= 0x110000) { - mp_raise_ValueError(MP_ERROR_TEXT("chr() arg not in range(0x110000)")); + mp_raise_ValueError(MP_ERROR_TEXT("char not in range(0x110000)")); } VSTR_FIXED(buf, 4); vstr_add_char(&buf, c); diff --git a/py/objstr.c b/py/objstr.c index 42f27bbbf97..90e24f1ab81 100644 --- a/py/objstr.c +++ b/py/objstr.c @@ -187,6 +187,62 @@ static void str_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t } } +#if MICROPY_PY_BUILTINS_STR_UNICODE_CHECK && MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS +// Build a new string from data containing invalid UTF-8, either skipping the +// invalid bytes (errors=="ignore") or replacing them with U+FFFD +// (errors=="replace"). +static mp_obj_t str_from_invalid_utf8(const mp_obj_type_t *type, const byte *str_data, size_t str_len, qstr errors) { + bool do_replace = (errors == MP_QSTR_replace); + vstr_t vstr; + vstr_init(&vstr, str_len); + const byte *p = str_data; + const byte *end = str_data + str_len; + + while (p < end) { + byte c = *p; + if (c < 0x80) { + // Valid ASCII + vstr_add_byte(&vstr, c); + p++; + } else if (c >= 0xc0 && c < 0xf8) { + // Potential multi-byte sequence + uint8_t need = (0xe5 >> ((c >> 3) & 0x6)) & 3; + const byte *seq_start = p; + p++; + + // Check continuation bytes + uint8_t got = 0; + while (got < need && p < end && UTF8_IS_CONT(*p)) { + got++; + p++; + } + + if (got == need) { + // Valid complete sequence, decode and add the character + unichar ch = *seq_start & (0x7f >> need); + for (uint8_t i = 0; i < need; i++) { + ch = (ch << 6) | (seq_start[i + 1] & 0x3f); + } + vstr_add_char(&vstr, ch); + } else if (do_replace) { + // Invalid or incomplete sequence - replace with U+FFFD + vstr_add_char(&vstr, 0xFFFD); + } + // For 'ignore' mode, do nothing (skip invalid bytes) + } else if (do_replace) { + // Invalid start byte - replace with U+FFFD + vstr_add_char(&vstr, 0xFFFD); + p++; + } else { + // Invalid start byte - skip for 'ignore' mode + p++; + } + } + + return mp_obj_new_str_type_from_vstr(type, &vstr); +} +#endif // MICROPY_PY_BUILTINS_STR_UNICODE_CHECK && MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS + mp_obj_t mp_obj_str_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { #if MICROPY_CPYTHON_COMPAT if (n_kw != 0) { @@ -208,135 +264,60 @@ mp_obj_t mp_obj_str_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_ return mp_obj_new_str_type_from_vstr(type, &vstr); } - default: // 2 or 3 args - #if MICROPY_PY_BUILTINS_BYTEARRAY - if (mp_obj_is_type(args[0], &mp_type_bytes) || mp_obj_is_type(args[0], &mp_type_bytearray)) { - #else + default: { // 2 or 3 args + // Extract the source data. + const byte *str_data; + size_t str_len; if (mp_obj_is_type(args[0], &mp_type_bytes)) { - #endif - GET_STR_DATA_LEN(args[0], str_data, str_len); - GET_STR_HASH(args[0], str_hash); - if (str_hash == 0) { - str_hash = qstr_compute_hash(str_data, str_len); - } + // Immutable bytes can be referenced directly (zero-copy); + GET_STR_DATA_LEN(args[0], bytes_data, bytes_len); + str_data = bytes_data; + str_len = bytes_len; + } else { + // any other buffer object is mutable sob its data must be copied. + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[0], &bufinfo, MP_BUFFER_READ); + str_data = bufinfo.buf; + str_len = bufinfo.len; + } - #if MICROPY_PY_BUILTINS_STR_UNICODE_CHECK + #if MICROPY_PY_BUILTINS_STR_UNICODE_CHECK + if (!utf8_check(str_data, str_len)) { #if MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS // Check if error handler is specified (3rd argument) - const char *errors = "strict"; + qstr errors = MP_QSTR_; // default to "" if (n_args >= 3 && args[2] != mp_const_none) { - errors = mp_obj_str_get_str(args[2]); - } - #endif - - // Fast path: if data is valid UTF-8, return directly - if (utf8_check(str_data, str_len)) { - // Check if a qstr with this data already exists - qstr q = qstr_find_strn((const char *)str_data, str_len); - if (q != MP_QSTRnull) { - return MP_OBJ_NEW_QSTR(q); - } - - mp_obj_str_t *o = MP_OBJ_TO_PTR(mp_obj_new_str_copy(type, NULL, str_len)); - o->data = str_data; - o->hash = str_hash; - return MP_OBJ_FROM_PTR(o); + errors = mp_obj_str_get_qstr(args[2]); } - - // Data has invalid UTF-8, handle based on error mode - #if MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS - // Error handlers are enabled - #if !MICROPY_PY_BUILTINS_BYTES_DECODE_REPLACE - // Raise NotImplementedError if 'replace' is used but not enabled - if (strcmp(errors, "replace") == 0) { - mp_raise_NotImplementedError(NULL); + if (errors == MP_QSTR_ignore || errors == MP_QSTR_replace) { + return str_from_invalid_utf8(type, str_data, str_len, errors); } - #endif + #endif // MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS + mp_raise_msg(&mp_type_UnicodeError, NULL); + } + #endif // MICROPY_PY_BUILTINS_STR_UNICODE_CHECK - if (strcmp(errors, "ignore") == 0 - #if MICROPY_PY_BUILTINS_BYTES_DECODE_REPLACE - || strcmp(errors, "replace") == 0 - #endif - ) { - // Build new string skipping/replacing invalid bytes - #if MICROPY_PY_BUILTINS_BYTES_DECODE_REPLACE - bool do_replace = strcmp(errors, "replace") == 0; - #else - const bool do_replace = false; - #endif - vstr_t vstr; - vstr_init(&vstr, str_len); - const byte *p = str_data; - const byte *end = str_data + str_len; - - while (p < end) { - byte c = *p; - if (c < 0x80) { - // Valid ASCII - vstr_add_byte(&vstr, c); - p++; - } else if (c >= 0xc0 && c < 0xf8) { - // Potential multi-byte sequence - uint8_t need = (0xe5 >> ((c >> 3) & 0x6)) & 3; - const byte *seq_start = p; - p++; - - // Check continuation bytes - uint8_t got = 0; - while (got < need && p < end && UTF8_IS_CONT(*p)) { - got++; - p++; - } - - if (got == need) { - // Valid complete sequence, decode and add the character - unichar ch = *seq_start & (0x7f >> need); - for (uint8_t i = 0; i < need; i++) { - ch = (ch << 6) | (seq_start[i + 1] & 0x3f); - } - vstr_add_char(&vstr, ch); - } else if (do_replace) { - // Invalid or incomplete sequence - replace with U+FFFD - vstr_add_char(&vstr, 0xFFFD); - } - // For 'ignore' mode, do nothing (skip invalid bytes) - } else if (do_replace) { - // Invalid start byte - replace with U+FFFD - vstr_add_char(&vstr, 0xFFFD); - p++; - } else { - // Invalid start byte - skip for 'ignore' mode - p++; - } - } + // Check if a qstr with this data already exists + qstr q = qstr_find_strn((const char *)str_data, str_len); + if (q != MP_QSTRnull) { + return MP_OBJ_NEW_QSTR(q); + } - return mp_obj_new_str_type_from_vstr(type, &vstr); - } else { - // Strict mode (or unrecognized error handler) - mp_raise_msg(&mp_type_UnicodeError, NULL); - } - #else - // Error handlers are not enabled - just raise UnicodeError on invalid UTF-8 - mp_raise_msg(&mp_type_UnicodeError, NULL); - #endif - #else - // Check if a qstr with this data already exists - qstr q = qstr_find_strn((const char *)str_data, str_len); - if (q != MP_QSTRnull) { - return MP_OBJ_NEW_QSTR(q); - } + if (!mp_obj_is_type(args[0], &mp_type_bytes)) { + // Source is a mutable buffer: copy the data. + return mp_obj_new_str_copy(type, str_data, str_len); + } - mp_obj_str_t *o = MP_OBJ_TO_PTR(mp_obj_new_str_copy(type, NULL, str_len)); - o->data = str_data; - o->hash = str_hash; - return MP_OBJ_FROM_PTR(o); - #endif - } else { - mp_buffer_info_t bufinfo; - mp_get_buffer_raise(args[0], &bufinfo, MP_BUFFER_READ); - // This will utf-8 check the input. - return mp_obj_new_str(bufinfo.buf, bufinfo.len); + // Source is immutable bytes: reference its data without copying. + GET_STR_HASH(args[0], str_hash); + if (str_hash == 0) { + str_hash = qstr_compute_hash(str_data, str_len); } + mp_obj_str_t *o = MP_OBJ_TO_PTR(mp_obj_new_str_copy(type, NULL, str_len)); + o->data = str_data; + o->hash = str_hash; + return MP_OBJ_FROM_PTR(o); + } } } @@ -1148,6 +1129,23 @@ static MP_NORETURN void terse_str_format_value_error(void) { #define terse_str_format_value_error() #endif +// Print the character with the code point given by the integer object arg. +// Used by both the str.format and the modulo (%c) formatters. +static void mp_print_char(const mp_print_t *print, mp_obj_t arg, unsigned int flags, char fill, int width) { + #if MICROPY_FULL_CHECKS + mp_uint_t c = mp_obj_get_int(arg); + if (c >= 0x110000) { + mp_raise_msg(&mp_type_OverflowError, MP_ERROR_TEXT("char not in range(0x110000)")); + } + VSTR_FIXED(ch_vstr, 4); + vstr_add_char(&ch_vstr, c); + mp_print_strn(print, ch_vstr.buf, ch_vstr.len, flags, fill, width); + #else + char ch = mp_obj_get_int(arg); + mp_print_strn(print, &ch, 1, flags, fill, width); + #endif +} + static vstr_t mp_obj_str_format_helper(const char *str, const char *top, int *arg_i, size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) { vstr_t vstr; mp_print_t print; @@ -1437,19 +1435,7 @@ static vstr_t mp_obj_str_format_helper(const char *str, const char *top, int *ar continue; case 'c': { - #if MICROPY_PY_BUILTINS_STR_UNICODE - mp_uint_t c = mp_obj_get_int(arg); - if (c >= 0x110000) { - mp_raise_msg(&mp_type_OverflowError, MP_ERROR_TEXT("chr() arg not in range(0x110000)")); - } - VSTR_FIXED(ch_vstr, 4); - vstr_add_char(&ch_vstr, c); - mp_print_strn(&print, ch_vstr.buf, ch_vstr.len, flags, fill, width); - vstr_clear(&ch_vstr); - #else - char ch = mp_obj_get_int(arg); - mp_print_strn(&print, &ch, 1, flags, fill, width); - #endif + mp_print_char(&print, arg, flags, fill, width); continue; } @@ -1742,21 +1728,7 @@ static mp_obj_t str_modulo_format(mp_obj_t pattern, size_t n_args, const mp_obj_ } mp_print_strn(&print, s, 1, flags, ' ', width); } else if (arg_looks_integer(arg)) { - #if MICROPY_PY_BUILTINS_STR_UNICODE - mp_uint_t c = mp_obj_get_int(arg); - if (c >= 0x110000) { - mp_raise_msg(&mp_type_OverflowError, MP_ERROR_TEXT("%c arg not in range(0x110000)")); - } - vstr_t ch_vstr; - vstr_init_len(&ch_vstr, 4); - ch_vstr.len = 0; - vstr_add_char(&ch_vstr, c); - mp_print_strn(&print, ch_vstr.buf, ch_vstr.len, flags, ' ', width); - vstr_clear(&ch_vstr); - #else - char ch = mp_obj_get_int(arg); - mp_print_strn(&print, &ch, 1, flags, ' ', width); - #endif + mp_print_char(&print, arg, flags, ' ', width); } else { mp_raise_TypeError(MP_ERROR_TEXT("integer needed")); } @@ -2117,6 +2089,15 @@ MP_DEFINE_CONST_FUN_OBJ_1(str_islower_obj, str_islower); #if MICROPY_CPYTHON_COMPAT // These methods are superfluous in the presence of str() and bytes() // constructors. + +static void check_utf8_encoding(qstr encoding) { + if (!(encoding == MP_QSTR_utf_hyphen_8 || encoding == MP_QSTR_utf8 || + encoding == MP_QSTR_ascii)) { + mp_raise_msg_varg(&mp_type_LookupError, + MP_ERROR_TEXT("encoding not supported: %q"), encoding); + } +} + // TODO: should accept kwargs too static mp_obj_t bytes_decode(size_t n_args, const mp_obj_t *args) { mp_obj_t new_args[2]; @@ -2126,16 +2107,7 @@ static mp_obj_t bytes_decode(size_t n_args, const mp_obj_t *args) { args = new_args; n_args++; } else if (n_args >= 2) { - // Validate encoding parameter - // MicroPython only supports UTF-8 encoding - const char *encoding = mp_obj_str_get_str(args[1]); - - // Accept utf-8 and ascii (ascii is a subset of utf-8) - if (!(strcmp(encoding, "utf-8") == 0 || strcmp(encoding, "utf8") == 0 || - strcmp(encoding, "ascii") == 0)) { - mp_raise_msg_varg(&mp_type_LookupError, - MP_ERROR_TEXT("encoding not supported: %s"), encoding); - } + check_utf8_encoding(mp_obj_str_get_qstr(args[1])); } return mp_obj_str_make_new(&mp_type_str, n_args, 0, args); } @@ -2150,16 +2122,7 @@ static mp_obj_t str_encode(size_t n_args, const mp_obj_t *args) { args = new_args; n_args++; } else if (n_args >= 2) { - // Validate encoding parameter - // MicroPython only supports UTF-8 encoding - const char *encoding = mp_obj_str_get_str(args[1]); - - // Accept utf-8 and ascii (ascii is a subset of utf-8) - if (!(strcmp(encoding, "utf-8") == 0 || strcmp(encoding, "utf8") == 0 || - strcmp(encoding, "ascii") == 0)) { - mp_raise_msg_varg(&mp_type_LookupError, - MP_ERROR_TEXT("encoding not supported: %s"), encoding); - } + check_utf8_encoding(mp_obj_str_get_qstr(args[1])); } return bytes_make_new(NULL, n_args, 0, args); } From 641fa01c0bd7fd6b492f62a4b175b4d30ad42040 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 386/635] docs: Document Unicode support and limitations. Signed-off-by: Jos Verlinde --- docs/develop/writingtests.rst | 5 + docs/library/builtins.rst | 58 +++++++++ docs/reference/constrained.rst | 21 ++- docs/reference/index.rst | 1 + docs/reference/unicode_support.rst | 201 +++++++++++++++++++++++++++++ 5 files changed, 285 insertions(+), 1 deletion(-) create mode 100644 docs/reference/unicode_support.rst diff --git a/docs/develop/writingtests.rst b/docs/develop/writingtests.rst index fd3daf91c1e..7ac7e038ca8 100644 --- a/docs/develop/writingtests.rst +++ b/docs/develop/writingtests.rst @@ -46,6 +46,11 @@ If you run your tests, this test should appear in the test output: Tests are run by comparing the output from the test target against the output from CPython. So any test should use print statements to indicate test results. +When writing tests for name or string-related functionality, please add both English/ASCII +as well as non-English/non-ASCII text and include Unicode examples. +Please do add comments in English explaining the meaning and intent of the Unicode text. +This help ensure Unicode support is tested and verified across different platforms. + For tests that can't be compared to CPython (i.e. micropython-specific functionality), you can provide a ``.py.exp`` file which will be used as the truth for comparison. diff --git a/docs/library/builtins.rst b/docs/library/builtins.rst index 8fb8f03080c..92c0b8dcf7f 100644 --- a/docs/library/builtins.rst +++ b/docs/library/builtins.rst @@ -25,6 +25,35 @@ Functions and types |see_cpython| `python:bytes`. + .. method:: bytes.decode(encoding='utf-8', errors='strict') + + Decode the bytes object to a string using the specified *encoding*. + + MicroPython supports the following encodings: + + - ``'utf-8'`` or ``'utf8'`` - UTF-8 encoding (default) + - ``'ascii'`` - ASCII encoding (subset of UTF-8) + + The *errors* parameter controls how decoding errors are handled: + + - ``'strict'`` - Raise a ``UnicodeError`` on invalid UTF-8 (default) + - ``'ignore'`` - Skip invalid bytes (requires ``MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS``) + - ``'replace'`` - Replace invalid bytes with U+FFFD '�' (requires ``MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS``) + + .. note:: + Error handler support depends on build configuration. On constrained + systems, only ``'strict'`` mode may be available. + + Example:: + + >>> b'\xc2\xa9 2024'.decode('utf-8') # © symbol + '© 2024' + >>> b'hello\xffworld'.decode('utf-8', 'ignore') # Skip invalid bytes + 'helloworld' + + Raises ``LookupError`` if the encoding is not supported, or + ``UnicodeError`` if the data contains invalid UTF-8 and ``errors='strict'``. + .. function:: callable() .. function:: chr() @@ -144,6 +173,35 @@ Functions and types .. class:: str() + .. method:: str.encode(encoding='utf-8') + + Encode the string to bytes using the specified *encoding*. + + MicroPython supports the following encodings: + + - ``'utf-8'`` or ``'utf8'`` - UTF-8 encoding (default) + - ``'ascii'`` - ASCII encoding (subset of UTF-8) + + Example:: + + >>> '© 2024'.encode('utf-8') # Copyright symbol + b'\xc2\xa9 2024' + + Raises ``LookupError`` if the encoding is not supported. + + .. method:: str.center(width) + + Return a centered string of length *width*. Padding is done using spaces. + + When Unicode support is enabled (``MICROPY_PY_BUILTINS_STR_UNICODE``), this + method counts Unicode characters rather than bytes, ensuring proper alignment + for multi-byte UTF-8 characters. + + Example:: + + >>> 'café'.center(10) # é is 2 bytes in UTF-8 + ' café ' + .. function:: sum() .. function:: super() diff --git a/docs/reference/constrained.rst b/docs/reference/constrained.rst index 616dc8833fd..60f76b9c783 100644 --- a/docs/reference/constrained.rst +++ b/docs/reference/constrained.rst @@ -251,7 +251,26 @@ instances so the process of eliminating Unicode can be painless. b = b'the quick brown fox' # A bytes instance Where it is necessary to convert between strings and bytes the :meth:`str.encode` -and the :meth:`bytes.decode` methods can be used. Note that both strings and bytes +and the :meth:`bytes.decode` methods can be used. MicroPython validates the +encoding parameter and only supports UTF-8 and ASCII. The :meth:`bytes.decode` +method also supports error handlers (``'ignore'`` and ``'replace'``) for handling +invalid UTF-8, when enabled in the build configuration. + +For memory-conscious applications processing untrusted data, using the ``'ignore'`` +error handler can be more efficient than ``'strict'`` mode (the default), as it +avoids raising exceptions while still recovering valid text:: + + # Strict mode (default) raises an error on invalid UTF-8 + try: + s = data.decode('utf-8') + except UnicodeError: + # Handle error + pass + + # Ignore mode skips invalid bytes (more memory-efficient) + s = data.decode('utf-8', 'ignore') + +Note that both strings and bytes are immutable. Any operation which takes as input such an object and produces another implies at least one RAM allocation to produce the result. In the second line below a new bytes object is allocated. This would also occur if ``foo`` diff --git a/docs/reference/index.rst b/docs/reference/index.rst index 1558c0fdfa9..24fe5746eb0 100644 --- a/docs/reference/index.rst +++ b/docs/reference/index.rst @@ -31,5 +31,6 @@ implementation and the best practices to use them. packages.rst asm_thumb2_index.rst filesystem.rst + unicode_support.rst pyboard.py.rst micropython2_migration.rst diff --git a/docs/reference/unicode_support.rst b/docs/reference/unicode_support.rst new file mode 100644 index 00000000000..ac8b52995ac --- /dev/null +++ b/docs/reference/unicode_support.rst @@ -0,0 +1,201 @@ +.. _unicode_support: + +Unicode Support +=============== + +MicroPython provides Unicode support for strings, with the level of support +depending on the build configuration. + +Terminology +----------- + +This document uses the following Unicode terms: + +- **Code point**: a single Unicode value in the range U+0000 to U+10FFFF, for + example U+0041 ``A`` or U+1F600 😀. MicroPython strings are sequences of + code points. +- **Character**: informally used to mean a code point. Be aware that a + user-perceived character (a *grapheme*) may consist of several code points, + such as a base letter followed by combining marks. +- **Byte**: a single 8-bit value. In UTF-8 each code point is stored as one to + four bytes (see below). + +Operations such as ``len()``, indexing and slicing act on code points, not on +graphemes or display width, so a base letter followed by a combining mark counts +as two code points. + +Character Encoding +------------------ + +MicroPython uses UTF-8 encoding for all strings. When Unicode support is enabled +(``MICROPY_PY_BUILTINS_STR_UNICODE``), strings can contain any valid Unicode code +point from U+0000 to U+10FFFF. + +ASCII characters (0-127) are stored in a single byte, making them as memory-efficient +as on systems without Unicode support. Multi-byte UTF-8 code points use 2-4 bytes +depending on the code point: + +- U+0000 to U+007F: 1 byte (ASCII) +- U+0080 to U+07FF: 2 bytes +- U+0800 to U+FFFF: 3 bytes +- U+10000 to U+10FFFF: 4 bytes + +Encoding and Decoding +---------------------- + +The :meth:`bytes.decode` and :meth:`str.encode` methods support the following encodings: + +- UTF-8 (``'utf-8'`` or ``'utf8'``) +- ASCII (``'ascii'``) + +Other encodings (such as ``'latin-1'``, ``'utf-16'``, etc.) are not supported and +will raise ``LookupError``. + +Example:: + + >>> '日本語'.encode('utf-8') + b'\xe6\x97\xa5\xe6\x9c\xac\xe8\xaa\x9e' + >>> b'\xe6\x97\xa5\xe6\x9c\xac\xe8\xaa\x9e'.decode('utf-8') + '日本語' + +Error Handling +~~~~~~~~~~~~~~ + +When decoding bytes that contain invalid UTF-8 sequences, the ``errors`` parameter +of :meth:`bytes.decode` controls the behavior: + +- ``'strict'`` (default): Raise ``UnicodeError`` +- ``'ignore'``: Skip invalid bytes (requires ``MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS``) +- ``'replace'``: Replace invalid bytes with U+FFFD � (requires ``MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS``) + +Example:: + + >>> # Strict mode (default) raises an error + >>> b'hello\xffworld'.decode('utf-8') + UnicodeError: invalid UTF-8 + + >>> # Ignore mode skips invalid bytes + >>> b'hello\xffworld'.decode('utf-8', 'ignore') + 'helloworld' + + >>> # Replace mode substitutes replacement character + >>> b'hello\xffworld'.decode('utf-8', 'replace') + 'hello�world' + +For memory-conscious applications, consider using ``'ignore'`` mode when processing +untrusted or partially corrupted data, as it avoids raising exceptions while still +recovering valid text. + +The same ``errors`` handling applies when decoding any bytes-like object, including +via the ``str()`` constructor (for example ``str(buf, 'utf-8', 'replace')`` where +``buf`` is a ``bytes``, ``bytearray``, ``memoryview`` or ``array`` object). + + +String Methods +-------------- + +When Unicode support is enabled, string methods operate on code points rather than bytes: + +- :meth:`str.center` - Counts code points for width calculation +- ``len(s)`` - Returns number of code points (not bytes) +- String indexing and slicing work on code-point boundaries +- No support for display width calculations (East Asian width, combining characters, etc.) + +Example:: + + >>> s = 'Hello 世界' + >>> len(s) # 8 code points + 8 + >>> len(s.encode()) # 12 bytes + 12 + >>> s.center(12) # Centered by code-point count + ' Hello 世界 ' + +String Formatting +----------------- + +The ``%c`` format specifier and ``{:c}`` format code support full Unicode: + +- Accepts code points from 0 to 0x10FFFF +- Properly encodes multi-byte UTF-8 code points +- Raises ``ValueError`` for invalid code points + +Example:: + + >>> '%c' % 65 # ASCII + 'A' + >>> '%c' % 0x03B1 # Greek α + 'α' + >>> '%c' % 0x1F600 # Emoji 😀 + '😀' + >>> '{:c}'.format(0x4E2D) # Chinese 中 + '中' + + >>> # Invalid code point + >>> '%c' % 0x110000 + ValueError: %c arg not in range(0x110000) + +F-strings also support the ``:c`` format code:: + + >>> code_point = 0x2665 # Heart suit ♥ + >>> f'I {code_point:c} Python' + 'I ♥ Python' + +Build Configuration +------------------- + +Unicode features are controlled by several build-time flags in ``mpconfigport.h``: + +``MICROPY_PY_BUILTINS_STR_UNICODE`` + Enable Unicode string support. When enabled, strings can contain any valid + Unicode character and string operations work on character boundaries rather + than byte boundaries. + + Default: Enabled at ``MICROPY_CONFIG_ROM_LEVEL_EXTRA_FEATURES`` and above. + +``MICROPY_PY_BUILTINS_STR_UNICODE_CHECK`` + Enable UTF-8 validation during string operations. When disabled, string + operations may produce incorrect results with invalid UTF-8 sequences. + + Default: Follows ``MICROPY_PY_BUILTINS_STR_UNICODE`` setting. + +``MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS`` + Enable the ``'ignore'`` and ``'replace'`` error handlers for + :meth:`bytes.decode`. When enabled, invalid UTF-8 bytes can be either + skipped (``'ignore'``) or replaced with U+FFFD (``'replace'``). + + Default: Enabled at ``MICROPY_CONFIG_ROM_LEVEL_EXTRA_FEATURES`` and above. + +Example Configuration +~~~~~~~~~~~~~~~~~~~~~ + +For a constrained port with limited flash, disable error handlers:: + + #define MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS (0) + +For a port with more resources, enable all Unicode features:: + + #define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_EXTRA_FEATURES) + // This automatically enables: + // - MICROPY_PY_BUILTINS_STR_UNICODE + // - MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS + +Limitations +----------- + +MicroPython's Unicode support has some limitations compared to CPython: + +- Only UTF-8 and ASCII encodings are supported +- No support for Unicode normalization +- No locale-aware string operations +- The ``errors`` parameter accepts only positional arguments (not keyword arguments) +- String methods like ``upper()``, ``lower()``, etc. work correctly only for ASCII +- The MicroPython interactive REPL and ``input()`` function currently have limited + Unicode support. The line editor is unaware of the displayed width of characters: + wide characters (for example many CJK characters) take two terminal columns, while a + grapheme cluster (a base code point plus combining marks, or an emoji sequence) can + span several code points yet occupy a single column. Because editing tracks code + points rather than displayed columns, line-editing keys such as backspace and the + left/right arrows may leave the cursor misaligned with the text shown on screen. + A workaround is to place the Unicode text in a UTF-8 encoded MicroPython script and + run it using ``mpremote run ``. From a6f1149e940aea367a1bdfacedc7e2b6fb8c564f Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 387/635] tests/cpydiff: Document unicode differences. Signed-off-by: Jos Verlinde --- tests/cpydiff/types_bytes_decode_encoding.py | 19 +++++++++++++++++++ tests/cpydiff/types_bytes_decode_kwargs.py | 19 +++++++++++++++++++ tests/cpydiff/types_str_repr_nonprintable.py | 11 +++++++++++ 3 files changed, 49 insertions(+) create mode 100644 tests/cpydiff/types_bytes_decode_encoding.py create mode 100644 tests/cpydiff/types_bytes_decode_kwargs.py create mode 100644 tests/cpydiff/types_str_repr_nonprintable.py diff --git a/tests/cpydiff/types_bytes_decode_encoding.py b/tests/cpydiff/types_bytes_decode_encoding.py new file mode 100644 index 00000000000..e4564d20ee0 --- /dev/null +++ b/tests/cpydiff/types_bytes_decode_encoding.py @@ -0,0 +1,19 @@ +""" +categories: Types,bytes +description: bytes.decode() only supports 'utf-8' and 'ascii' encodings, not other encodings like 'latin-1' +cause: MicroPython is optimized for embedded systems and only includes UTF-8 and ASCII codec support to save memory. Other encodings would require additional codec tables. +workaround: Convert data to UTF-8 before processing, or implement custom encoding/decoding if needed. +""" + +# CPython supports many encodings, MicroPython only utf-8 and ascii +try: + b"\xe9".decode("latin-1") # 'é' in latin-1 + print("latin-1 supported") +except (ValueError, NotImplementedError, LookupError) as e: + print("latin-1 not supported:", type(e).__name__) + +try: + b"\x80".decode("cp1252") # Euro sign in cp1252 + print("cp1252 supported") +except (ValueError, NotImplementedError, LookupError) as e: + print("cp1252 not supported:", type(e).__name__) diff --git a/tests/cpydiff/types_bytes_decode_kwargs.py b/tests/cpydiff/types_bytes_decode_kwargs.py new file mode 100644 index 00000000000..a1ca2b74c5c --- /dev/null +++ b/tests/cpydiff/types_bytes_decode_kwargs.py @@ -0,0 +1,19 @@ +""" +categories: Types,bytes +description: bytes.decode() does not accept keyword arguments, only positional arguments +cause: MicroPython optimizes for code size and does not implement keyword argument handling for bytes.decode() +workaround: Use positional arguments instead of keyword arguments +""" + +# CPython accepts keyword arguments, MicroPython only accepts positional +b = b"hello\xffworld" + +try: + # Using keyword arguments + result = b.decode(encoding="utf-8", errors="ignore") + print("kwargs supported:", repr(result)) +except TypeError as e: + print("kwargs not supported: TypeError") + # Workaround: use positional arguments + result = b.decode("utf-8", "ignore") + print("positional args work:", repr(result)) diff --git a/tests/cpydiff/types_str_repr_nonprintable.py b/tests/cpydiff/types_str_repr_nonprintable.py new file mode 100644 index 00000000000..6f9af65d8e1 --- /dev/null +++ b/tests/cpydiff/types_str_repr_nonprintable.py @@ -0,0 +1,11 @@ +""" +categories: Types,str +description: repr() may print some non-printable Unicode characters literally instead of as escape sequences +cause: MicroPython uses a simplified heuristic to determine printable characters, avoiding the need for a full Unicode character database (saves memory). It prints characters >= U+0080 (excluding surrogates) as UTF-8. CPython uses the Unicode database to identify non-printable characters like noncharacters (U+FFFx in each plane). +workaround: Accept the difference for embedded use cases, or use ascii() or manual escaping if exact control is needed. +""" + +# These are noncharacters that CPython escapes but MicroPython prints +# showing as hex to avoid display issues in documentation tables +print("U+FFFF:", repr("\uffff").encode("utf-8").hex()) +print("U+1FFFF:", repr("\U0001ffff").encode("utf-8").hex()) From f5283f2456179d5ddef24aebbeec5f175f638f4c Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:46 +0200 Subject: [PATCH 388/635] tests/run-tests.py: Specify UTF-8 encoding when opening test files. Signed-off-by: Jos Verlinde --- tests/run-tests.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/run-tests.py b/tests/run-tests.py index d5a0fbd9a9a..459ef693f20 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -1137,7 +1137,7 @@ def run_one_test(test_file): # Print a note if this looks like it might have been a misfired unittest if not uses_unittest and not test_passed: - with open(test_file, "r") as f: + with open(test_file, "r", encoding="utf-8") as f: if any(re.match("^import.+unittest", l) for l in f.readlines()): print( "NOTE: {} may be a unittest that doesn't run unittest.main()".format( From afc31ce3495ef78c67852cf3702494eb2e5c8d3a Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:47 +0200 Subject: [PATCH 389/635] tests/unicode: Remove known differences from test. Prevent the test from failing by not testing known unsupported characters. These will be documented in a cpydiff test. Signed-off-by: Jos Verlinde --- tests/unicode/unicode.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tests/unicode/unicode.py b/tests/unicode/unicode.py index 58d406e63eb..fbf4039a9e5 100644 --- a/tests/unicode/unicode.py +++ b/tests/unicode/unicode.py @@ -17,11 +17,6 @@ enc = s.encode() print(enc, enc.decode() == s) -# printing of unicode chars using repr -# NOTE: for some characters (eg \u10ff) we differ to CPython -print(repr("a\uffff")) -print(repr("a\U0001ffff")) - # test invalid escape code try: eval('"\\U00110000"') From 79d0896ac55c0b416d19a1e1cd8ac5dd96f23f3a Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:47 +0200 Subject: [PATCH 390/635] tests/unicode: Add tests for unicode character formatting. Signed-off-by: Jos Verlinde --- tests/unicode/unicode_char_format.py | 58 ++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 tests/unicode/unicode_char_format.py diff --git a/tests/unicode/unicode_char_format.py b/tests/unicode/unicode_char_format.py new file mode 100644 index 00000000000..937806a6ae6 --- /dev/null +++ b/tests/unicode/unicode_char_format.py @@ -0,0 +1,58 @@ +# test %c formatting with unicode characters (issue #3364) +# tests that character codes >= 128 are properly encoded as UTF-8 + +print("%c%c" % (0x3BC, 0x1F40D)) # Greek letter mu and snake emoji + +# ASCII character +print("%c" % 65) + +# 2-byte UTF-8 characters +print("%c" % 128) +print("%c" % 169) # copyright symbol © +print("%c" % 255) + +# 3-byte UTF-8 character +print("%c" % 0x4E00) # CJK ideograph 一 + +# 4-byte UTF-8 character +print("%c" % 0x1F600) # emoji 😀 + +# test with .format() method +print("{:c}".format(169)) +print("{:c}".format(0x4E00)) +print("{:c}{:c}".format(0x3BC, 0x1F40D)) + +# test with f-strings +c = 169 +print(f"{c:c}") +c = 0x1F600 +print(f"{c:c}") + +# Test boundary values - valid maximum unicode codepoint +print("%c" % 0x10FFFF) # Last valid unicode codepoint + +# Test invalid codepoint - >= 0x110000 should raise OverflowError +try: + print("%c" % 0x110000) + print("UNEXPECTED: should have raised OverflowError") +except OverflowError: + print("OverflowError") + +try: + print("%c" % 0x110001) + print("UNEXPECTED: should have raised OverflowError") +except OverflowError: + print("OverflowError") + +# Test format() method with invalid codepoint +try: + print("{:c}".format(0x110000)) + print("UNEXPECTED: should have raised OverflowError") +except OverflowError: + print("OverflowError") + +try: + print("{:c}".format(0x200000)) + print("UNEXPECTED: should have raised OverflowError") +except OverflowError: + print("OverflowError") From f95cec3854b20e38d56671e66111800396e3af8d Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:47 +0200 Subject: [PATCH 391/635] tests/unicode: Test str.center() with Unicode characters. Signed-off-by: Jos Verlinde --- tests/unicode/str_center.py | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 tests/unicode/str_center.py diff --git a/tests/unicode/str_center.py b/tests/unicode/str_center.py new file mode 100644 index 00000000000..226074df4b7 --- /dev/null +++ b/tests/unicode/str_center.py @@ -0,0 +1,36 @@ +# Test str.center() with Unicode characters +# Issue #17827 + +try: + str.center +except AttributeError: + print("SKIP") + raise SystemExit + +# ASCII baseline +print("hello".center(10)) + +# Latin with accent (é is 2 bytes in UTF-8) +print("héllo".center(10)) + +# Chinese (each char is 3 bytes in UTF-8) +print("你好".center(10)) + +# Emoji (4 bytes in UTF-8) +print("🎉".center(5)) + +# German with umlaut +print("München".center(15)) + +# Cyrillic +print("Москва".center(12)) + +# Edge cases +print("test".center(4)) # Exact fit +print("test".center(3)) # String longer than width +print("x".center(1)) # Single char, exact fit +print("".center(5)) # Empty string + +# Mixed ASCII and Unicode +print("café".center(10)) +print("hello世界".center(12)) From 6a03bd92daec30cd0782530bb2a2c5b539f18b82 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:47 +0200 Subject: [PATCH 392/635] tests/unicode: Test bytes.decode() and str.encode(). Signed-off-by: Jos Verlinde --- tests/unicode/bytes_decode_encoding.py | 60 ++++++++++ tests/unicode/bytes_decode_encoding.py.exp | 27 +++++ tests/unicode/bytes_decode_ignore.py | 105 +++++++++++++++++ tests/unicode/bytes_decode_replace.py | 126 +++++++++++++++++++++ 4 files changed, 318 insertions(+) create mode 100644 tests/unicode/bytes_decode_encoding.py create mode 100644 tests/unicode/bytes_decode_encoding.py.exp create mode 100644 tests/unicode/bytes_decode_ignore.py create mode 100644 tests/unicode/bytes_decode_replace.py diff --git a/tests/unicode/bytes_decode_encoding.py b/tests/unicode/bytes_decode_encoding.py new file mode 100644 index 00000000000..5235c46fa0a --- /dev/null +++ b/tests/unicode/bytes_decode_encoding.py @@ -0,0 +1,60 @@ +# Test bytes.decode() and str.encode() with encoding parameter validation + +# Check if decode method is available (requires MICROPY_CPYTHON_COMPAT) +try: + b"".decode() +except AttributeError: + print("SKIP") + raise SystemExit + +# Test valid encodings for bytes.decode() +# utf-8 (default) +print(b"hello".decode("utf-8")) +print(b"hello".decode("utf8")) + +# ascii (subset of utf-8) +print(b"hello".decode("ascii")) + +# Test valid encoding for str.encode() +print("hello".encode("utf-8")) +print("hello".encode("utf8")) +print("hello".encode("ascii")) + +# Test with bytearray +print(bytearray(b"test").decode("utf-8")) + +# Test that UTF-8 still works correctly with non-ASCII characters +# © symbol (U+00A9) +print(b"\xc2\xa9".decode("utf-8")) +print("©".encode("utf-8")) + +# Test emoji 👍 (U+1F44D) +print(b"\xf0\x9f\x91\x8d".decode("utf-8")) +print("👍".encode("utf-8")) + +# Test invalid decoded code points in repr fallback path. +print(repr(b"\xf4\x90\x80\x80".decode("utf-8"))) +print(repr(b"\xf5\x80\x80\x80".decode("utf-8"))) + +# Test invalid encodings for bytes.decode() +# These should raise LookupError +invalid_encodings = ["latin-1", "latin1", "utf-16", "utf-32", "iso-8859-1", "cp1252"] + +for encoding in invalid_encodings: + try: + b"hello".decode(encoding) + print("UNEXPECTED:", encoding, "should raise LookupError") + except LookupError as e: + print("LookupError:", encoding) + +# Test bytes method accepting bytearray as argument (arg type normalization) +print(b"hello world".find(bytearray(b"world"))) +print(bytearray(b"hello world").find(bytearray(b"world"))) + +# Test invalid encodings for str.encode() +for encoding in invalid_encodings: + try: + "hello".encode(encoding) + print("UNEXPECTED:", encoding, "should raise LookupError") + except LookupError as e: + print("LookupError:", encoding) diff --git a/tests/unicode/bytes_decode_encoding.py.exp b/tests/unicode/bytes_decode_encoding.py.exp new file mode 100644 index 00000000000..aa2e487a62e --- /dev/null +++ b/tests/unicode/bytes_decode_encoding.py.exp @@ -0,0 +1,27 @@ +hello +hello +hello +b'hello' +b'hello' +b'hello' +test +© +b'\xc2\xa9' +👍 +b'\xf0\x9f\x91\x8d' +'\U00110000' +'\U00140000' +LookupError: latin-1 +LookupError: latin1 +LookupError: utf-16 +LookupError: utf-32 +LookupError: iso-8859-1 +LookupError: cp1252 +6 +6 +LookupError: latin-1 +LookupError: latin1 +LookupError: utf-16 +LookupError: utf-32 +LookupError: iso-8859-1 +LookupError: cp1252 diff --git a/tests/unicode/bytes_decode_ignore.py b/tests/unicode/bytes_decode_ignore.py new file mode 100644 index 00000000000..33fbc5dbe63 --- /dev/null +++ b/tests/unicode/bytes_decode_ignore.py @@ -0,0 +1,105 @@ +# Test bytes.decode() with error handler 'ignore' + +# Check if decode method is available (requires MICROPY_CPYTHON_COMPAT) +try: + b"".decode() +except AttributeError: + print("SKIP") + raise SystemExit + +# Check if error handlers are available (requires MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS) +# When feature is disabled, invalid UTF-8 raises LookupError even with 'ignore' +# When feature is enabled, invalid UTF-8 with 'ignore' returns a string +try: + result = b"\xff".decode("utf-8", "ignore") + # If we get here, feature is available +except (UnicodeError, LookupError): + # Feature not available - 'ignore' was ignored, strict mode was used + print("SKIP") + raise SystemExit + +# Test ignore mode with invalid UTF-8 +print(repr(b"\xff\xfe".decode("utf-8", "ignore"))) + +# Test strict mode (default) with invalid UTF-8 +try: + b"\xff\xfe".decode("utf-8") + print("UNEXPECTED") +except UnicodeError: + print("UnicodeError") + +# Test strict mode (explicit) with invalid UTF-8 +try: + b"\xff\xfe".decode("utf-8", "strict") + print("UNEXPECTED") +except UnicodeError: + print("UnicodeError") + +# Test with valid UTF-8 +print(repr(b"hello".decode("utf-8", "ignore"))) + +# Test valid UTF-8 with default mode +print(repr(b"hello".decode("utf-8"))) + +# Test mixed valid and invalid UTF-8 +print(repr(b"hello\xffworld".decode("utf-8", "ignore"))) + +# Test multiple invalid bytes +print(repr(b"\x80\x81\x82".decode("utf-8", "ignore"))) + +# Test invalid continuation byte +print(repr(b"\xc0\x20".decode("utf-8", "ignore"))) + +# Test incomplete sequence at end +print(repr(b"hello\xc0".decode("utf-8", "ignore"))) + +# Test valid multi-byte UTF-8 (© symbol) +print(repr(b"\xc2\xa9".decode("utf-8", "ignore"))) + +# Test bytearray support +print(repr(bytearray(b"\xff\xfe").decode("utf-8", "ignore"))) + +# Additional tests for continuation byte validation and incomplete sequences + +# Test 3-byte UTF-8 sequence - valid (e.g., U+4E00 - 一) +print(repr(b"\xe4\xb8\x80".decode("utf-8", "ignore"))) + +# Test 4-byte UTF-8 sequence - valid (e.g., U+1F600 - 😀) +print(repr(b"\xf0\x9f\x98\x80".decode("utf-8", "ignore"))) + +# Test incomplete 3-byte sequence (missing 2 continuation bytes) +print(repr(b"\xe4".decode("utf-8", "ignore"))) + +# Test incomplete 3-byte sequence (missing 1 continuation byte) +print(repr(b"\xe4\xb8".decode("utf-8", "ignore"))) + +# Test incomplete 4-byte sequence (missing 3 continuation bytes) +print(repr(b"\xf0".decode("utf-8", "ignore"))) + +# Test incomplete 4-byte sequence (missing 2 continuation bytes) +print(repr(b"\xf0\x9f".decode("utf-8", "ignore"))) + +# Test incomplete 4-byte sequence (missing 1 continuation byte) +print(repr(b"\xf0\x9f\x98".decode("utf-8", "ignore"))) + +# Test 3-byte sequence with invalid continuation byte (first byte invalid) +print(repr(b"\xe4\x20\x80".decode("utf-8", "ignore"))) + +# Test 3-byte sequence with invalid continuation byte (second byte invalid) +print(repr(b"\xe4\xb8\x20".decode("utf-8", "ignore"))) + +# Test 4-byte sequence with invalid continuation bytes +print(repr(b"\xf0\x20\x98\x80".decode("utf-8", "ignore"))) +print(repr(b"\xf0\x9f\x20\x80".decode("utf-8", "ignore"))) +print(repr(b"\xf0\x9f\x98\x20".decode("utf-8", "ignore"))) + +# Test mixed valid and incomplete sequences +print(repr(b"hello\xe4world".decode("utf-8", "ignore"))) +print(repr(b"hello\xf0world".decode("utf-8", "ignore"))) + +# Test valid multi-byte sequence mixed with invalid bytes (exercises got==need path) +print(repr(b"\xff\xc2\xa9".decode("utf-8", "ignore"))) # © preserved after invalid \xff +print(repr(b"\xff\xe4\xb8\x80".decode("utf-8", "ignore"))) # 一 preserved after invalid \xff + +# Test multiple incomplete sequences in a row +print(repr(b"\xe4\xf0\xe4".decode("utf-8", "ignore"))) diff --git a/tests/unicode/bytes_decode_replace.py b/tests/unicode/bytes_decode_replace.py new file mode 100644 index 00000000000..29ba139153b --- /dev/null +++ b/tests/unicode/bytes_decode_replace.py @@ -0,0 +1,126 @@ +# Test bytes.decode() with error handler 'replace' + +# Check if decode method is available (requires MICROPY_CPYTHON_COMPAT) +try: + b"".decode() +except AttributeError: + print("SKIP") + raise SystemExit + +# Check if error handlers are available (requires MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS) +# When feature is disabled, invalid UTF-8 raises UnicodeError even with 'replace' +# When feature is enabled, invalid UTF-8 with 'replace' returns a string +try: + result = b"\xff".decode("utf-8", "replace") + # If we get here, feature is available +except (UnicodeError, LookupError): + # Feature not available - 'replace' was ignored, strict mode was used + print("SKIP") + raise SystemExit + +# Test replace mode with invalid UTF-8 +print(repr(b"\xff\xfe".decode("utf-8", "replace"))) + +# Test strict mode (default) with invalid UTF-8 +try: + b"\xff\xfe".decode("utf-8") + print("UNEXPECTED") +except UnicodeError: + print("UnicodeError") + +# Test strict mode (explicit) with invalid UTF-8 +try: + b"\xff\xfe".decode("utf-8", "strict") + print("UNEXPECTED") +except UnicodeError: + print("UnicodeError") + +# Test with valid UTF-8 +print(repr(b"hello".decode("utf-8", "replace"))) + +# Test valid UTF-8 with default mode +print(repr(b"hello".decode("utf-8"))) + +# Test mixed valid and invalid UTF-8 +print(repr(b"hello\xffworld".decode("utf-8", "replace"))) + +# Test multiple invalid bytes +print(repr(b"\x80\x81\x82".decode("utf-8", "replace"))) + +# Test invalid continuation byte +print(repr(b"\xc0\x20".decode("utf-8", "replace"))) + +# Test incomplete sequence at end +print(repr(b"hello\xc0".decode("utf-8", "replace"))) + +# Test valid multi-byte UTF-8 (© symbol) +print(repr(b"\xc2\xa9".decode("utf-8", "replace"))) + +# Test bytearray support +print(repr(bytearray(b"\xff\xfe").decode("utf-8", "replace"))) + +# Test replace mode - should either work or raise NotImplementedError +try: + result = b"\xff\xfe".decode("utf-8", "replace") + print(repr(result)) +except LookupError: + print("LookupError") + +# Test replace with valid UTF-8 +try: + result = b"hello".decode("utf-8", "replace") + print(repr(result)) +except LookupError: + print("LookupError") + +# Test replace with mixed content +try: + result = b"hello\xffworld".decode("utf-8", "replace") + print(repr(result)) +except LookupError: + print("LookupError") + +# Additional tests for continuation byte validation and incomplete sequences + +# Test 3-byte UTF-8 sequence - valid (e.g., U+4E00 - 一) +print(repr(b"\xe4\xb8\x80".decode("utf-8", "replace"))) + +# Test 4-byte UTF-8 sequence - valid (e.g., U+1F600 - 😀) +print(repr(b"\xf0\x9f\x98\x80".decode("utf-8", "replace"))) + +# Test valid multi-byte sequence mixed with invalid bytes (exercises got==need path) +print(repr(b"\xff\xc2\xa9".decode("utf-8", "replace"))) # \ufffd + © after invalid \xff +print(repr(b"\xff\xe4\xb8\x80".decode("utf-8", "replace"))) # \ufffd + 一 after invalid \xff + +# Test incomplete 3-byte sequence (missing 2 continuation bytes) +print(repr(b"\xe4".decode("utf-8", "replace"))) + +# Test incomplete 3-byte sequence (missing 1 continuation byte) +print(repr(b"\xe4\xb8".decode("utf-8", "replace"))) + +# Test incomplete 4-byte sequence (missing 3 continuation bytes) +print(repr(b"\xf0".decode("utf-8", "replace"))) + +# Test incomplete 4-byte sequence (missing 2 continuation bytes) +print(repr(b"\xf0\x9f".decode("utf-8", "replace"))) + +# Test incomplete 4-byte sequence (missing 1 continuation byte) +print(repr(b"\xf0\x9f\x98".decode("utf-8", "replace"))) + +# Test 3-byte sequence with invalid continuation byte (first byte invalid) +print(repr(b"\xe4\x20\x80".decode("utf-8", "replace"))) + +# Test 3-byte sequence with invalid continuation byte (second byte invalid) +print(repr(b"\xe4\xb8\x20".decode("utf-8", "replace"))) + +# Test 4-byte sequence with invalid continuation bytes +print(repr(b"\xf0\x20\x98\x80".decode("utf-8", "replace"))) +print(repr(b"\xf0\x9f\x20\x80".decode("utf-8", "replace"))) +print(repr(b"\xf0\x9f\x98\x20".decode("utf-8", "replace"))) + +# Test mixed valid and incomplete sequences +print(repr(b"hello\xe4world".decode("utf-8", "replace"))) +print(repr(b"hello\xf0world".decode("utf-8", "replace"))) + +# Test multiple incomplete sequences in a row +print(repr(b"\xe4\xf0\xe4".decode("utf-8", "replace"))) From 23f500ad6b26db28b3ad15030e6b6a701ee22d87 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:47 +0200 Subject: [PATCH 393/635] tests/unicode: Test surrogate characters and memoryview encoding. Signed-off-by: Jos Verlinde --- tests/unicode/unicode.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tests/unicode/unicode.py b/tests/unicode/unicode.py index fbf4039a9e5..97f0599ab01 100644 --- a/tests/unicode/unicode.py +++ b/tests/unicode/unicode.py @@ -46,3 +46,13 @@ str(b"\xf0\xe0\xed\xe8", "utf8") except UnicodeError: print("UnicodeError") + +# test surrogate repr uses \uXXXX escape +print(repr(chr(0xD800))) + +# test str() from buffer-protocol object (memoryview) +print(str(memoryview(b"hello"), "utf-8")) +try: + str(memoryview(b"\xff"), "utf-8") +except UnicodeError: + print("UnicodeError") From 754cecee6baa523e6575c8ac590a021c32569e92 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Wed, 1 Jul 2026 21:11:40 +0200 Subject: [PATCH 394/635] tests/unicode: Test unicode str from bytearray and memoryview. Signed-off-by: Jos Verlinde --- tests/unicode/str_from_buffer_errors.py | 39 ++++++++++++++++++ tests/unicode/str_from_buffer_snapshot.py | 30 ++++++++++++++ tests/unicode/str_from_bytearray.py | 50 +++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 tests/unicode/str_from_buffer_errors.py create mode 100644 tests/unicode/str_from_buffer_snapshot.py create mode 100644 tests/unicode/str_from_bytearray.py diff --git a/tests/unicode/str_from_buffer_errors.py b/tests/unicode/str_from_buffer_errors.py new file mode 100644 index 00000000000..64008738a1e --- /dev/null +++ b/tests/unicode/str_from_buffer_errors.py @@ -0,0 +1,39 @@ +# str(buffer, encoding, errors) should apply the 'ignore'/'replace' error +# handlers to any buffer source (array.array, memoryview, ...), the same way it +# does for bytes and bytearray. Companion to str_from_buffer_snapshot.py. + +try: + import array + + memoryview +except (ImportError, NameError): + print("SKIP") + raise SystemExit + +# Requires the decode error handlers (MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS). +# When the feature is disabled, invalid UTF-8 raises even with 'replace'. +try: + str(memoryview(b"\xff"), "utf-8", "replace") +except UnicodeError: + print("SKIP") + raise SystemExit + +# array.array holding invalid UTF-8 bytes (typecode "B" keeps this endian-neutral). +a = array.array("B", b"a\xffb\x80c") +print(repr(str(a, "utf-8", "replace"))) +print(repr(str(a, "utf-8", "ignore"))) + +# A memoryview over invalid UTF-8 (0xc3 0x28 is an invalid 2-byte sequence). +mv = memoryview(b"x\xc3\x28y") +print(repr(str(mv, "utf-8", "replace"))) +print(repr(str(mv, "utf-8", "ignore"))) + +# Strict decoding (the default) must still raise for a buffer source. +try: + str(memoryview(b"a\xffb"), "utf-8") + print("UNEXPECTED") +except UnicodeError: + print("UnicodeError") + +# A valid-UTF-8 buffer passes through an error handler unchanged ("café"). +print(repr(str(array.array("B", b"caf\xc3\xa9"), "utf-8", "replace"))) # codespell:ignore caf diff --git a/tests/unicode/str_from_buffer_snapshot.py b/tests/unicode/str_from_buffer_snapshot.py new file mode 100644 index 00000000000..c4e0a871471 --- /dev/null +++ b/tests/unicode/str_from_buffer_snapshot.py @@ -0,0 +1,30 @@ +# Companion to str_from_bytearray.py: str()/bytes() built from other mutable +# buffer sources (array.array and a writable memoryview) must also be independent +# snapshots, not views onto the source buffer. +try: + import array + + memoryview +except (ImportError, NameError): + print("SKIP") + raise SystemExit + +# Non-interned byte-literal payloads (with raw UTF-8 sequences) avoid relying on +# str.encode() to build the test data. + +# array.array is a mutable buffer source; str()/bytes() must snapshot the data. +# Content decodes to "array ünicode 🐍 target!". +a = array.array("B", b"array \xc3\xbcnicode \xf0\x9f\x90\x8d target!") +s = str(a, "utf-8") +b = bytes(a) +a[0] = ord("X") +print(s) +print(b) + +# A writable memoryview (here over an array) is also a mutable source. +# Content decodes to "memoryview över 🐍 python!". +a = array.array("B", b"memoryview \xc3\xb6ver \xf0\x9f\x90\x8d python!") +mv = memoryview(a) +s = str(mv, "utf-8") +a[0] = ord("X") +print(s) diff --git a/tests/unicode/str_from_bytearray.py b/tests/unicode/str_from_bytearray.py new file mode 100644 index 00000000000..12744da5c47 --- /dev/null +++ b/tests/unicode/str_from_bytearray.py @@ -0,0 +1,50 @@ +# Test that a str/bytes created from a bytearray is an independent snapshot, +# and not a view onto the (mutable) bytearray buffer. Mutating or resizing the +# source bytearray afterwards must not change the previously created object. + +# Skip if needed via `skip_bytearray` logic in run-tests.py + +# Non-interned payloads (byte literals) are used so the result isn't returned as +# an existing qstr. Every scenario is covered with plain-ASCII data so the core +# bytearray paths are exercised directly; a couple of cases embed raw UTF-8 byte +# sequences to also cover multi-byte Unicode decoding, without relying on +# str.encode() to build the test data. + +# str(bytearray, ...) then mutate the source in place. +ba = bytearray(b"the quick brown fox jumped over!") +s = str(ba, "utf-8") +ba[0] = ord("T") +print(s) +print(s[0]) + +# Same, but with multi-byte UTF-8 content: "café naïve 🐍 snapshot!". +ba = bytearray(b"caf\xc3\xa9 na\xc3\xafve \xf0\x9f\x90\x8d snapshot!") # codespell:ignore caf +s = str(ba, "utf-8") +ba[0] = ord("X") +print(s) + +# Overwriting every byte of the source must not change the str. +ba = bytearray(b"snapshot test one two three four!") +s = str(ba, "utf-8") +for i in range(len(ba)): + ba[i] = ord("x") +print(s) + +# Growing the bytearray reallocates its buffer; the str must stay intact. +ba = bytearray(b"grow test alpha bravo charlie delta!") +s = str(ba, "utf-8") +for _ in range(1000): + ba.append(ord("Z")) +print(s) + +# bytes(bytearray) is likewise an independent snapshot. +ba = bytearray(b"bytes snapshot alpha bravo charlie!") +b = bytes(ba) +ba[0] = ord("X") +print(b) + +# Same, but with multi-byte UTF-8 content: "bytes ünicode 🐍 snakes!". +ba = bytearray(b"bytes \xc3\xbcnicode \xf0\x9f\x90\x8d snakes!") +b = bytes(ba) +ba[0] = ord("X") +print(b) From f67ab9efe18246a49aac6a3d0a80a9fc59468caa Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 29 Jun 2026 00:50:47 +0200 Subject: [PATCH 395/635] tests/basics: Update t-string test cases for unicode. These are now printed as characters rather than escaped bytes. Signed-off-by: Jos Verlinde --- tests/basics/string_tstring_basic1.py.exp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/basics/string_tstring_basic1.py.exp b/tests/basics/string_tstring_basic1.py.exp index 52fc6f6c94c..7f2b0d85b60 100644 --- a/tests/basics/string_tstring_basic1.py.exp +++ b/tests/basics/string_tstring_basic1.py.exp @@ -16,14 +16,14 @@ Template(strings=('\\k',), interpolations=()) Invalid \x escape: SyntaxError Invalid \u escape: SyntaxError Invalid \U escape: SyntaxError -Template(strings=('\x00\x01\xff',), interpolations=()) +Template(strings=('\x00\x01ÿ',), interpolations=()) Template(strings=('A',), interpolations=()) -Template(strings=('\u03b1',), interpolations=()) -Template(strings=('\u2764',), interpolations=()) +Template(strings=('α',), interpolations=()) +Template(strings=('❤',), interpolations=()) Template(strings=('A',), interpolations=()) -Template(strings=('\U0001f600',), interpolations=()) +Template(strings=('😀',), interpolations=()) Template(strings=('ABC',), interpolations=()) -Unicode: Template(strings=('Unicode test:\nEmoji: ', '\nSpecial: ', ''), interpolations=(Interpolation('\U0001f40d', "'\\U0001f40d'", None, ''), Interpolation('\u03b1 \u03b2 \u03b3', "'\\u03b1 \\u03b2 \\u03b3'", None, ''))) +Unicode: Template(strings=('Unicode test:\nEmoji: ', '\nSpecial: ', ''), interpolations=(Interpolation('🐍', "'\\U0001f40d'", None, ''), Interpolation('α β γ', "'\\u03b1 \\u03b2 \\u03b3'", None, ''))) === Trailing whitespace preservation (PEP 750) === Expression with trailing spaces: |x| From a7507fb0e397f827dfaa8341fdf7f6cdbf711b6d Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 11 Jun 2026 22:33:35 +1000 Subject: [PATCH 396/635] tests/extmod: Rewrite with unittest select/socket tests that use UDP. Three tests are rewritten using unittest, so that they don't need to be run under CPython to get the expected output. Because running under CPython requires port 8000 to be available, which it may not (at least for tests in the extmod directory having a port available should not be a requirement). Signed-off-by: Damien George --- tests/extmod/select_ipoll.py | 69 +++++++++++++++++------------ tests/extmod/select_ipoll.py.exp | 6 --- tests/extmod/select_poll_udp.py | 42 ++++++++++++------ tests/extmod/socket_udp_nonblock.py | 20 ++++++--- 4 files changed, 83 insertions(+), 54 deletions(-) delete mode 100644 tests/extmod/select_ipoll.py.exp diff --git a/tests/extmod/select_ipoll.py b/tests/extmod/select_ipoll.py index 0b661c11c83..170bb22bcda 100644 --- a/tests/extmod/select_ipoll.py +++ b/tests/extmod/select_ipoll.py @@ -6,14 +6,9 @@ print("SKIP") raise SystemExit - -def print_poll_output(lst): - print([(type(obj), flags) for obj, flags in lst]) - - -poller = select.poll() - # Use a new UDP socket for tests, which should be writable but not readable. +# Some targets (eg PYBV10) have the socket module but are unable to create +# UDP sockets without a registered NIC. try: s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) s.bind(socket.getaddrinfo("127.0.0.1", 8000)[0][-1]) @@ -21,35 +16,51 @@ def print_poll_output(lst): print("SKIP") raise SystemExit -poller.register(s) +import unittest + + +class Test(unittest.TestCase): + def test_ipoll_single_socket(self): + poller = select.poll() + + # Register socket. + poller.register(s) + + # Basic polling. + self.assertEqual(list(poller.ipoll(0)), [(s, 4)]) + + # Pass in flags=1 for one-shot behaviour. + self.assertEqual(list(poller.ipoll(0, 1)), [(s, 4)]) + + # Socket should be deregistered and poll should return nothing. + self.assertEqual(list(poller.ipoll(0)), []) + + def test_ipoll_multiple_sockets(self): + # Create a second socket. + s2 = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + s2.bind(socket.getaddrinfo("127.0.0.1", 8001)[0][-1]) -# Basic polling. -print_poll_output(poller.ipoll(0)) + poller = select.poll() -# Pass in flags=1 for one-shot behaviour. -print_poll_output(poller.ipoll(0, 1)) + # Register both sockets. + poller.register(s) + poller.register(s2) -# Socket should be deregistered and poll should return nothing. -print_poll_output(poller.ipoll(0)) + # Basic polling with two sockets. + self.assertEqual(list(poller.ipoll(0)), [(s2, 4), (s2, 4)]) -# Create a second socket. -s2 = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) -s2.bind(socket.getaddrinfo("127.0.0.1", 8001)[0][-1]) + # Unregister the first socket, to test polling the remaining one. + poller.unregister(s) + self.assertEqual(list(poller.ipoll(0)), [(s2, 4)]) -# Register both sockets (to reset the first one). -poller.register(s) -poller.register(s2) + # Unregister the second socket, to test polling none. + poller.unregister(s2) + self.assertEqual(list(poller.ipoll(0)), []) -# Basic polling with two sockets. -print_poll_output(poller.ipoll(0)) + s2.close() -# Unregister the first socket, to test polling the remaining one. -poller.unregister(s) -print_poll_output(poller.ipoll(0)) -# Unregister the second socket, to test polling none. -poller.unregister(s2) -print_poll_output(poller.ipoll(0)) +if __name__ == "__main__": + unittest.main() -s2.close() s.close() diff --git a/tests/extmod/select_ipoll.py.exp b/tests/extmod/select_ipoll.py.exp deleted file mode 100644 index cbeabdce902..00000000000 --- a/tests/extmod/select_ipoll.py.exp +++ /dev/null @@ -1,6 +0,0 @@ -[(, 4)] -[(, 4)] -[] -[(, 4), (, 4)] -[(, 4)] -[] diff --git a/tests/extmod/select_poll_udp.py b/tests/extmod/select_poll_udp.py index 887176a4f65..44ea965efab 100644 --- a/tests/extmod/select_poll_udp.py +++ b/tests/extmod/select_poll_udp.py @@ -2,12 +2,12 @@ try: import socket, select - - select.poll # Raises AttributeError for CPython implementations without poll() -except (ImportError, AttributeError): +except ImportError: print("SKIP") raise SystemExit +# Some targets (eg PYBV10) have the socket module but are unable to create +# UDP sockets without a registered NIC. try: s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) s.bind(socket.getaddrinfo("127.0.0.1", 8000)[0][-1]) @@ -15,19 +15,33 @@ print("SKIP") raise SystemExit -poll = select.poll() +import unittest + + +class Test(unittest.TestCase): + def test_poll(self): + poll = select.poll() + + # UDP socket should not be readable. + poll.register(s, select.POLLIN) + res = poll.poll(0) + self.assertEqual(len(res), 0) + + # UDP socket should be writable. + poll.modify(s, select.POLLOUT) + res = poll.poll(0) + self.assertEqual(res[0][1], select.POLLOUT) -# UDP socket should not be readable -poll.register(s, select.POLLIN) -print(len(poll.poll(0))) + @unittest.skipUnless(hasattr(select, "select"), "no select") + def test_select(self): + # UDP socket should only be writable. + r, w, e = select.select([s], [s], [s], 0) + self.assertEqual(r, []) + self.assertEqual(w, [s]) + self.assertEqual(e, []) -# UDP socket should be writable -poll.modify(s, select.POLLOUT) -print(poll.poll(0)[0][1] == select.POLLOUT) -# same test for select.select, but just skip it if the function isn't available -if hasattr(select, "select"): - r, w, e = select.select([s], [], [], 0) - assert not r and not w and not e +if __name__ == "__main__": + unittest.main() s.close() diff --git a/tests/extmod/socket_udp_nonblock.py b/tests/extmod/socket_udp_nonblock.py index 394115e4b88..7a4aac4647e 100644 --- a/tests/extmod/socket_udp_nonblock.py +++ b/tests/extmod/socket_udp_nonblock.py @@ -6,6 +6,8 @@ print("SKIP") raise SystemExit +# Some targets (eg PYBV10) have the socket module but are unable to create +# UDP sockets without a registered NIC. try: s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) s.bind(socket.getaddrinfo("127.0.0.1", 8000)[0][-1]) @@ -13,11 +15,19 @@ print("SKIP") raise SystemExit -s.settimeout(0) +import unittest -try: - s.recv(1) -except OSError as er: - print("EAGAIN:", er.errno == errno.EAGAIN) + +class Test(unittest.TestCase): + def test_nonblocking(self): + s.settimeout(0) + + with self.assertRaises(OSError) as ctx: + s.recv(1) + self.assertEqual(ctx.exception.errno, errno.EAGAIN) + + +if __name__ == "__main__": + unittest.main() s.close() From 8f2ed62ba0d85e2a06c21523320a0dd16fd6a5e3 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 11 Jun 2026 22:37:52 +1000 Subject: [PATCH 397/635] tests/extmod: Add .py.exp file for select_poll_eintr test. Similar to the parent commit, this means CPython doesn't need to run to get the expected output, and means port 8000 doesn't need to be available. Signed-off-by: Damien George --- tests/extmod/select_poll_eintr.py | 3 +++ tests/extmod/select_poll_eintr.py.exp | 5 +++++ 2 files changed, 8 insertions(+) create mode 100644 tests/extmod/select_poll_eintr.py.exp diff --git a/tests/extmod/select_poll_eintr.py b/tests/extmod/select_poll_eintr.py index fdc5ee5074a..5dfa5d4395f 100644 --- a/tests/extmod/select_poll_eintr.py +++ b/tests/extmod/select_poll_eintr.py @@ -1,5 +1,8 @@ # Test interruption of select.poll by EINTR signal, when # MICROPY_PY_SELECT_POSIX_OPTIMISATIONS is enabled. +# +# Note: this test should run and pass under CPython, but it has a .py.exp file +# so that port 8000 does not need to be available to get the expected output. try: import time, gc, select, socket, _thread diff --git a/tests/extmod/select_poll_eintr.py.exp b/tests/extmod/select_poll_eintr.py.exp new file mode 100644 index 00000000000..2b15f86649c --- /dev/null +++ b/tests/extmod/select_poll_eintr.py.exp @@ -0,0 +1,5 @@ +poll +thread gc start +thread gc end +result: [] +dt in range From 9f7a6df4d69f51082b277b6dfe686ae8ecd51168 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 30 Apr 2026 13:56:16 +1000 Subject: [PATCH 398/635] py/mpconfig: Enable unicode support at the basic feature level. MicroPython allows unicode to be disabled to reduce firmware size, in which case str objects are essentially the same as bytes objects when it comes to code points between 128 and 255. But that behaviour has subtle differences to when unicode is enabled, eg string lengths can be different. Since unicode strings are arguably an important feature of Python, and users would likely be tripped up with it disabled, this commit changes the default level at which unicode is enabled from "extra" down to "basic". Costs about +1600 bytes on ARM Cortex-M targets. Signed-off-by: Damien George --- py/mpconfig.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py/mpconfig.h b/py/mpconfig.h index 7d9a98fd92e..ce1b6ba4ad4 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -1367,7 +1367,7 @@ typedef time_t mp_timestamp_t; // Whether str object is proper unicode #ifndef MICROPY_PY_BUILTINS_STR_UNICODE -#define MICROPY_PY_BUILTINS_STR_UNICODE (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_EXTRA_FEATURES) +#define MICROPY_PY_BUILTINS_STR_UNICODE (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_BASIC_FEATURES) #endif // Whether to check for valid UTF-8 when converting bytes to str From 6145cc71ed52c9f4c8a976b53fe2efcad1414a76 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 9 Jul 2026 00:20:34 +1000 Subject: [PATCH 399/635] docs/reference/unicode_support: Update where unicode is enabled. The following ports use the extra or full ROM feature level, and so implicitly enable unicode as well as bytes decode errors: alif, esp32, esp8266, mimxrt, qemu, renesas-ra, rp2, samd (SAMD51 only), stm32, unix and webassembly. (Note that the stm32 board B_L072Z_LRWAN1 explicitly uses the core feature level and so disables unicode.) The following ports use the basic ROM feature level, and so implicitly enable unicode (but now bytes decode errors): samd (SAMD21) and zephyr. The following ports use the core ROM feature level, and explicitly enable unicode: cc3200, nrf and windows. The bare-arm and minimal ports use the minimum ROM feature level and do not enable unicode (similarly for minimal unix and zephyr variants). Signed-off-by: Damien George --- docs/reference/unicode_support.rst | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/docs/reference/unicode_support.rst b/docs/reference/unicode_support.rst index ac8b52995ac..d3d4c1eef61 100644 --- a/docs/reference/unicode_support.rst +++ b/docs/reference/unicode_support.rst @@ -3,8 +3,9 @@ Unicode Support =============== -MicroPython provides Unicode support for strings, with the level of support -depending on the build configuration. +MicroPython provides Unicode support for strings. All Tier 1, 2 and 3 ports +have Unicode support enabled by default, but it is possible to change that with +a different build configuration. Terminology ----------- @@ -151,7 +152,9 @@ Unicode features are controlled by several build-time flags in ``mpconfigport.h` Unicode character and string operations work on character boundaries rather than byte boundaries. - Default: Enabled at ``MICROPY_CONFIG_ROM_LEVEL_EXTRA_FEATURES`` and above. + Default: Enabled at ``MICROPY_CONFIG_ROM_LEVEL_BASIC_FEATURES`` and above. + + Enabled on all Tier 1, 2 and 3 ports. ``MICROPY_PY_BUILTINS_STR_UNICODE_CHECK`` Enable UTF-8 validation during string operations. When disabled, string @@ -159,6 +162,8 @@ Unicode features are controlled by several build-time flags in ``mpconfigport.h` Default: Follows ``MICROPY_PY_BUILTINS_STR_UNICODE`` setting. + Enabled on all Tier 1, 2 and 3 ports. + ``MICROPY_PY_BUILTINS_BYTES_DECODE_ERRORS`` Enable the ``'ignore'`` and ``'replace'`` error handlers for :meth:`bytes.decode`. When enabled, invalid UTF-8 bytes can be either @@ -166,6 +171,9 @@ Unicode features are controlled by several build-time flags in ``mpconfigport.h` Default: Enabled at ``MICROPY_CONFIG_ROM_LEVEL_EXTRA_FEATURES`` and above. + Enabled on alif, esp32, esp8266, mimxrt, renesas-ra, rp2, samd (SAMD51 only), + stm32, unix and webassembly ports. + Example Configuration ~~~~~~~~~~~~~~~~~~~~~ From ff2ed4936732de9697adafa4d296c99b842b369a Mon Sep 17 00:00:00 2001 From: Matt Trentini Date: Tue, 30 Jun 2026 23:40:15 +1000 Subject: [PATCH 400/635] docs/library/machine: Add port availability notes. Signed-off-by: Matt Trentini --- docs/library/machine.I2CTarget.rst | 2 ++ docs/library/machine.I2S.rst | 2 ++ docs/library/machine.RTC.rst | 1 + docs/library/machine.USBDevice.rst | 6 +++--- docs/library/machine.WDT.rst | 2 +- 5 files changed, 9 insertions(+), 4 deletions(-) diff --git a/docs/library/machine.I2CTarget.rst b/docs/library/machine.I2CTarget.rst index 2765b98143a..1d54cf795e9 100644 --- a/docs/library/machine.I2CTarget.rst +++ b/docs/library/machine.I2CTarget.rst @@ -74,6 +74,8 @@ example, to see the raw events as they are triggered:: ) i2c.irq(irq_handler, trigger=all_triggers, hard=True) +Availability: **Alif, ESP32, MIMXRT, RP2, SAMD, STM32, Zephyr** + Constructors ------------ diff --git a/docs/library/machine.I2S.rst b/docs/library/machine.I2S.rst index 84edb94e78d..f2704e9a33d 100644 --- a/docs/library/machine.I2S.rst +++ b/docs/library/machine.I2S.rst @@ -79,6 +79,8 @@ other things. For these drivers see: - :ref:`wm8960` +Availability: **ESP32, MIMXRT, RP2, STM32** + Constructor ----------- diff --git a/docs/library/machine.RTC.rst b/docs/library/machine.RTC.rst index e2ddd728bde..281274ed19d 100644 --- a/docs/library/machine.RTC.rst +++ b/docs/library/machine.RTC.rst @@ -13,6 +13,7 @@ Example usage:: rtc.datetime((2020, 1, 21, 2, 10, 32, 36, 0)) print(rtc.datetime()) +Availability: **Alif, ESP32, ESP8266, MIMXRT, Renesas-RA, RP2, SAMD, STM32** Constructors ------------ diff --git a/docs/library/machine.USBDevice.rst b/docs/library/machine.USBDevice.rst index 45f9e9cef38..15bf49a4d31 100644 --- a/docs/library/machine.USBDevice.rst +++ b/docs/library/machine.USBDevice.rst @@ -4,9 +4,9 @@ class USBDevice -- USB Device driver ==================================== -.. note:: ``machine.USBDevice`` is currently only supported for esp32, rp2 and - samd ports. Native USB support is also required, and not every board - supports native USB. +Availability: **ESP32, RP2, SAMD** + +.. note:: Native USB support is required, and not every board supports native USB. USBDevice provides a low-level Python API for implementing USB device functions using Python code. diff --git a/docs/library/machine.WDT.rst b/docs/library/machine.WDT.rst index 8ab249678fb..09a4f05fe90 100644 --- a/docs/library/machine.WDT.rst +++ b/docs/library/machine.WDT.rst @@ -15,7 +15,7 @@ Example usage:: wdt = WDT(timeout=2000) # enable it with a timeout of 2s wdt.feed() -Availability of this class: pyboard, WiPy, esp8266, esp32, rp2040, mimxrt. +Availability: **ESP32, ESP8266, MIMXRT, RP2, SAMD, STM32, Zephyr** Constructors ------------ From a5bac1b75ad4ba69d30f73ee3ce7bc358665069c Mon Sep 17 00:00:00 2001 From: o-murphy Date: Fri, 26 Jun 2026 11:53:41 +0300 Subject: [PATCH 401/635] webassembly/library: Fix ccall ABI for mp_hal_get_interrupt_char. Signed-off-by: o-murphy --- ports/webassembly/README.md | 4 ++++ ports/webassembly/library.js | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/ports/webassembly/README.md b/ports/webassembly/README.md index 8a3029aa076..52858e4100e 100644 --- a/ports/webassembly/README.md +++ b/ports/webassembly/README.md @@ -123,6 +123,10 @@ MicroPython code execution will suspend the browser so be sure to atomize usage within this environment. Unfortunately interrupts have not been implemented for the browser. +In Node.js, pressing Ctrl+C during Python execution sends a keyboard interrupt +(``KeyboardInterrupt``) to the running MicroPython instance via ``mp_js_hook``, +which periodically polls stdin for the interrupt character. + Testing ------- diff --git a/ports/webassembly/library.js b/ports/webassembly/library.js index 3f6c9cb61f1..6fcd9f2e254 100644 --- a/ports/webassembly/library.js +++ b/ports/webassembly/library.js @@ -35,8 +35,8 @@ mergeInto(LibraryManager.library, { const mp_interrupt_char = Module.ccall( "mp_hal_get_interrupt_char", "number", - ["number"], - ["null"], + [], + [], ); const fs = require("fs"); From b8a9782a2bb2f5cd78e8b062ebef87bb16deec0e Mon Sep 17 00:00:00 2001 From: Mikhail Zakharov Date: Fri, 13 Dec 2024 08:30:05 -0500 Subject: [PATCH 402/635] esp32/network_lan: Add support for OPENETH LAN PHY. Can be used with QEMU. Signed-off-by: Mikhail Zakharov --- ports/esp32/modnetwork.h | 1 + ports/esp32/modnetwork_globals.h | 4 ++++ ports/esp32/network_lan.c | 10 ++++++++++ 3 files changed, 15 insertions(+) diff --git a/ports/esp32/modnetwork.h b/ports/esp32/modnetwork.h index 47fd733c086..a7be34cd8dd 100644 --- a/ports/esp32/modnetwork.h +++ b/ports/esp32/modnetwork.h @@ -52,6 +52,7 @@ enum { #if PHY_GENERIC_ENABLED PHY_GENERIC, #endif + PHY_OPENETH, // PHYs which are actually SPI Ethernet MAC+PHY chips: PHY_KSZ8851SNL = 100, PHY_DM9051, PHY_W5500 }; diff --git a/ports/esp32/modnetwork_globals.h b/ports/esp32/modnetwork_globals.h index 12252ddbc5d..77eb95ba320 100644 --- a/ports/esp32/modnetwork_globals.h +++ b/ports/esp32/modnetwork_globals.h @@ -54,6 +54,10 @@ { MP_ROM_QSTR(MP_QSTR_PHY_GENERIC), MP_ROM_INT(PHY_GENERIC) }, #endif +#if CONFIG_ETH_USE_OPENETH +{ MP_ROM_QSTR(MP_QSTR_PHY_OPENETH), MP_ROM_INT(PHY_OPENETH) }, +#endif + #if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL { MP_ROM_QSTR(MP_QSTR_PHY_KSZ8851SNL), MP_ROM_INT(PHY_KSZ8851SNL) }, #endif diff --git a/ports/esp32/network_lan.c b/ports/esp32/network_lan.c index e5fcdd8a121..b66270cb198 100644 --- a/ports/esp32/network_lan.c +++ b/ports/esp32/network_lan.c @@ -208,6 +208,9 @@ static mp_obj_t get_lan(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar #if PHY_GENERIC_ENABLED args[ARG_phy_type].u_int != PHY_GENERIC && #endif + #if CONFIG_ETH_USE_OPENETH + args[ARG_phy_type].u_int != PHY_OPENETH && + #endif #if CONFIG_ETH_USE_SPI_ETHERNET #if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL args[ARG_phy_type].u_int != PHY_KSZ8851SNL && @@ -294,6 +297,13 @@ static mp_obj_t get_lan(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar break; #endif #endif // CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32P4 + #if CONFIG_ETH_USE_OPENETH + case PHY_OPENETH: + phy_config.autonego_timeout_ms = 100; + mac = esp_eth_mac_new_openeth(&mac_config); + self->phy = esp_eth_phy_new_dp83848(&phy_config); + break; + #endif #if CONFIG_ETH_USE_SPI_ETHERNET #if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL case PHY_KSZ8851SNL: { From f71a2316eebaeaf95724672f3f56540ecf73c014 Mon Sep 17 00:00:00 2001 From: Mikhail Zakharov Date: Tue, 17 Dec 2024 19:54:01 -0500 Subject: [PATCH 403/635] esp32: Add QEMU support for ESP32_GENERIC_C3 board. Add support for C3 target to run on QEMU emulator with LAN networking support. Build and run via: make BOARD=ESP32_GENERIC_C3 BOARD_VARIANT=QEMU qemu Signed-off-by: Mikhail Zakharov --- ports/esp32/Makefile | 3 +++ ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h | 2 ++ .../ESP32_GENERIC_C3/mpconfigvariant_QEMU.cmake | 7 +++++++ ports/esp32/boards/ESP32_GENERIC_C3/sdkconfig.qemu | 1 + ports/esp32/esp32_common.cmake | 1 + ports/esp32/main.c | 11 +++++++++++ 6 files changed, 25 insertions(+) create mode 100644 ports/esp32/boards/ESP32_GENERIC_C3/mpconfigvariant_QEMU.cmake create mode 100644 ports/esp32/boards/ESP32_GENERIC_C3/sdkconfig.qemu diff --git a/ports/esp32/Makefile b/ports/esp32/Makefile index e767f96c290..6a36b4da93c 100644 --- a/ports/esp32/Makefile +++ b/ports/esp32/Makefile @@ -106,6 +106,9 @@ size-components: size-files: $(call RUN_IDF_PY,size-files) +qemu: + $(call RUN_IDF_PY,qemu monitor) + # Run idf.py with the UPDATE_SUBMODULES flag to update # necessary submodules for this board. # diff --git a/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h index c3d798b6e5e..7a1905ca643 100644 --- a/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigboard.h @@ -1,6 +1,8 @@ // This configuration is for a generic ESP32C3 board with 4MiB (or more) of flash. +#ifndef MICROPY_HW_BOARD_NAME #define MICROPY_HW_BOARD_NAME "ESP32C3 module" +#endif #define MICROPY_HW_MCU_NAME "ESP32-C3" // Enable UART REPL for modules that have an external USB-UART and don't use native USB. diff --git a/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigvariant_QEMU.cmake b/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigvariant_QEMU.cmake new file mode 100644 index 00000000000..06c7c4dcae6 --- /dev/null +++ b/ports/esp32/boards/ESP32_GENERIC_C3/mpconfigvariant_QEMU.cmake @@ -0,0 +1,7 @@ +list(APPEND SDKCONFIG_DEFAULTS + boards/ESP32_GENERIC_C3/sdkconfig.qemu +) + +list(APPEND MICROPY_DEF_BOARD + MICROPY_HW_BOARD_NAME="Generic ESP32C3 module with QEMU" +) diff --git a/ports/esp32/boards/ESP32_GENERIC_C3/sdkconfig.qemu b/ports/esp32/boards/ESP32_GENERIC_C3/sdkconfig.qemu new file mode 100644 index 00000000000..7905b5bd95b --- /dev/null +++ b/ports/esp32/boards/ESP32_GENERIC_C3/sdkconfig.qemu @@ -0,0 +1 @@ +CONFIG_ETH_USE_OPENETH=y diff --git a/ports/esp32/esp32_common.cmake b/ports/esp32/esp32_common.cmake index 62726a0b6a5..da762e50459 100644 --- a/ports/esp32/esp32_common.cmake +++ b/ports/esp32/esp32_common.cmake @@ -307,6 +307,7 @@ target_link_options(${MICROPY_TARGET} PUBLIC # Enable the panic handler wrapper -Wl,--undefined=esp_panic_handler -Wl,--wrap=esp_panic_handler + -Wl,--wrap=esp_efuse_rtc_calib_get_ver ) # Collect all of the include directories and compile definitions for the IDF components, diff --git a/ports/esp32/main.c b/ports/esp32/main.c index 8c3c79008ef..4627c06ee94 100644 --- a/ports/esp32/main.c +++ b/ports/esp32/main.c @@ -324,3 +324,14 @@ void *esp_native_code_commit(void *buf, size_t len, void *reloc) { memcpy(p, buf, len); return p; } + + +// Workaround for https://github.com/espressif/esp-insights/issues/38 +extern int __real_esp_efuse_rtc_calib_get_ver(void); +int __wrap_esp_efuse_rtc_calib_get_ver(void) { + #if CONFIG_ETH_USE_OPENETH // detect QEMU build + return 1; + #else + return __real_esp_efuse_rtc_calib_get_ver(); + #endif +} From 8f9f5c599e49382a3f70412b861f39bad6c55165 Mon Sep 17 00:00:00 2001 From: jetpax Date: Fri, 8 May 2026 08:33:08 -0700 Subject: [PATCH 404/635] esp32/network_lan: Add mDNS support for Ethernet interface. Initialise mDNS on IP_EVENT_ETH_GOT_IP, inside the existing eth_event_handler(). This fixes mDNS hostname resolution when WiFi is disabled and only Ethernet is used. The mdns_initialised flag is shared with network_wlan.c (made non-static there), so a single mdns_init() runs even when both interfaces are present. Signed-off-by: jetpax --- ports/esp32/network_lan.c | 22 ++++++++++++++++++++++ ports/esp32/network_wlan.c | 4 ++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/ports/esp32/network_lan.c b/ports/esp32/network_lan.c index b66270cb198..336802cb9dd 100644 --- a/ports/esp32/network_lan.c +++ b/ports/esp32/network_lan.c @@ -45,6 +45,18 @@ #include "modnetwork.h" #include "extmod/modnetwork.h" +#ifndef NO_QSTR +#include "mdns.h" +#endif + +#if MICROPY_HW_ENABLE_MDNS_QUERIES || MICROPY_HW_ENABLE_MDNS_RESPONDER +#if MICROPY_PY_NETWORK_WLAN +extern bool mdns_initialised; // Defined in network_wlan.c +#else +static bool mdns_initialised = false; +#endif +#endif + #if PHY_LAN867X_ENABLED #include "esp_eth_phy_lan867x.h" #endif @@ -106,6 +118,16 @@ static void eth_event_handler(void *arg, esp_event_base_t event_base, case IP_EVENT_ETH_GOT_IP: eth_status = ETH_GOT_IP; ESP_LOGI("ethernet", "Ethernet Got IP"); + #if MICROPY_HW_ENABLE_MDNS_QUERIES || MICROPY_HW_ENABLE_MDNS_RESPONDER + if (!mdns_initialised) { + mdns_init(); + #if MICROPY_HW_ENABLE_MDNS_RESPONDER + mdns_hostname_set(mod_network_hostname_data); + mdns_instance_name_set(mod_network_hostname_data); + #endif + mdns_initialised = true; + } + #endif break; default: break; diff --git a/ports/esp32/network_wlan.c b/ports/esp32/network_wlan.c index 85493dff570..a8a6f9bc509 100644 --- a/ports/esp32/network_wlan.c +++ b/ports/esp32/network_wlan.c @@ -80,8 +80,8 @@ static bool wifi_sta_connected = false; static uint8_t wifi_sta_disconn_reason = 0; #if MICROPY_HW_ENABLE_MDNS_QUERIES || MICROPY_HW_ENABLE_MDNS_RESPONDER -// Whether mDNS has been initialised or not -static bool mdns_initialised = false; +// Whether mDNS has been initialised or not (shared with network_lan.c) +bool mdns_initialised = false; #endif static uint8_t conf_wifi_sta_reconnects = 0; From 67f7fdd37b28617756b7856d087a4ec32b1859bc Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 13 Jul 2026 13:25:41 +1000 Subject: [PATCH 405/635] esp32/boards/ESP32_GENERIC_H2: Disable mDNS. It does not build due to dependencies on the `WIFI_EVENT` symbol. Signed-off-by: Damien George --- ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h index 9c83a8f3650..002524d384a 100644 --- a/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_H2/mpconfigboard.h @@ -7,5 +7,9 @@ #define MICROPY_PY_NETWORK_WLAN (0) #define MICROPY_PY_ESPNOW (0) +// Disable mDNS (doesn't build due to WiFi dependencies) +#define MICROPY_HW_ENABLE_MDNS_QUERIES (0) +#define MICROPY_HW_ENABLE_MDNS_RESPONDER (0) + // Enable UART REPL for modules that have an external USB-UART and don't use native USB. #define MICROPY_HW_ENABLE_UART_REPL (1) From 5cd48135644c8dbd7598dc64b9152fc3967defe4 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 9 Jul 2026 22:39:58 +1000 Subject: [PATCH 406/635] stm32/boards/PYBD_SF2: Free up more space in internal flash. Some recent additions -- such as `pulse_width_us`, `pulse_width_ns`, WWDG support and improved Unicode -- have increased stm32 firmware by about 1.5k. All up, that made that the internal flash of PYBD_SF3 overflow by about 80 bytes. Following on from 702f15ab9800769c76539d760fe7b365d8654595, this commit moves all machine-code-based emitter functions from internal to external QSPI flash. That frees up about 13k internal flash, and shouldn't affect performance. Signed-off-by: Damien George --- ports/stm32/boards/PYBD_SF2/f722_qspi.ld | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ports/stm32/boards/PYBD_SF2/f722_qspi.ld b/ports/stm32/boards/PYBD_SF2/f722_qspi.ld index 8ada037d6e0..6d51d47b4fd 100644 --- a/ports/stm32/boards/PYBD_SF2/f722_qspi.ld +++ b/ports/stm32/boards/PYBD_SF2/f722_qspi.ld @@ -50,7 +50,9 @@ SECTIONS .text_ext : { . = ALIGN(4); - *py/emit*(.text.emit_inline_thumb_* .rodata.emit_inline_thumb_*) + *py/asmthumb.o(.text* .rodata*) + *py/emitinlinethumb.o(.text* .rodata*) + *py/emitnthumb.o(.text* .rodata*) *lib/btstack/*(.text* .rodata*) *lib/mbedtls/*(.text* .rodata*) *lib/mynewt-nimble/*(.text* .rodata*) From 42a89113826d7589b9b8c6df343414f782e0acb2 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Thu, 9 Jul 2026 14:37:36 +0200 Subject: [PATCH 407/635] tools/mpy_ld.py: Fix aligned jump target in natmod trampolines. This commit fixes a regression introduced in dd476ce1f63a5a744efd2909407d7b39ba64b304, that was meant to fix native modules' entry trampolines for x86/x64 when built with Clang. Unfortunately it broke things for almost every other platform, and this was not caught by the QEMU-based CI infrastructure. These changes aim to fix that situation by rearranging the way offset are calculated for all architecture. These changes also address a potential issue that may arise if there's a mismatch in trampoline length due to different opcode sequences being emitted. Signed-off-by: Alessandro Gatti --- tools/mpy_ld.py | 83 ++++++++++++++++++++++++++++++++++++------------- 1 file changed, 62 insertions(+), 21 deletions(-) diff --git a/tools/mpy_ld.py b/tools/mpy_ld.py index 4f161abbe10..4fd85484c7d 100755 --- a/tools/mpy_ld.py +++ b/tools/mpy_ld.py @@ -143,15 +143,16 @@ def fit_signed(bits, value): def asm_jump_x86(entry): - if fit_signed(7, entry): - return struct.pack("Bb", 0xEB, entry) - elif fit_signed(31, entry): - return struct.pack("> 1) & 0x07FF) @@ -161,7 +162,7 @@ def asm_jump_thumb(entry): # push {r0, lr} # bl # pop {r0, pc} - entry += 2 # skip "push {r0, lr}" + entry -= 2 # skip "push {r0, lr}" b0 = 0xB400 | 0x0100 | 0x0001 # push, lr, r0 b1 = 0xF000 | ((entry >> 12) & 0x07FF) b2 = 0xF800 | ((entry >> 1) & 0x07FF) @@ -170,6 +171,7 @@ def asm_jump_thumb(entry): def asm_jump_thumb2(entry): + entry -= 4 if fit_signed(11, entry): # Signed value fits in 12 bits b0 = 0xE000 | ((entry >> 1) & 0x07FF) @@ -182,36 +184,37 @@ def asm_jump_thumb2(entry): def asm_jump_xtensa(entry): - if fit_signed(17, entry): - jump_op = (entry - 4) << 6 | 6 + if fit_signed(17, entry - 8): + jump_op = ((entry - 8) << 6) | 6 return struct.pack("> 8) else: - raise LinkError("Large jumps are not yet supported on Xtensa") + raise LinkError("jumps larger than 128KiB are not supported") def asm_jump_riscv(entry): if fit_signed(11, entry): - entry += 2 # c.j entry return struct.pack( "> 2) + | ((entry & 0x300) << 1) | ((entry & 0x80) >> 1) | ((entry & 0x40) << 1) | ((entry & 0x20) >> 3) - | ((entry & 0x10) << 7), + | ((entry & 0x10) << 7) + | ((entry & 0x0E) << 2), ) - else: + elif fit_signed(31, entry - 8): # auipc t6, HI(entry) # jalr zero, t6, LO(entry) - upper, lower = split_riscv_address(entry + 8) + upper, lower = split_riscv_address(entry) return struct.pack( " Date: Thu, 9 Jul 2026 10:37:25 +0200 Subject: [PATCH 408/635] samd/mcu/samd21/mpconfigmcu: Drop features of the SAMD21 minimal build. Allowing it to fit into the flash. The dropped features are available for SAMD21 boards with external flash. Affected feature: - MICROPY_PY_BUILTINS_HELP_MODULES - MICROPY_PY_HEAPQ - MICROPY_PY_GENERATOR_PEND_THROW - MICROPY_ENABLE_SOURCE_LINE Signed-off-by: robert-hh --- ports/samd/mcu/samd21/mpconfigmcu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ports/samd/mcu/samd21/mpconfigmcu.h b/ports/samd/mcu/samd21/mpconfigmcu.h index ff5b2d5e4a3..884e0e8b4e5 100644 --- a/ports/samd/mcu/samd21/mpconfigmcu.h +++ b/ports/samd/mcu/samd21/mpconfigmcu.h @@ -14,10 +14,8 @@ #define MICROPY_KBD_EXCEPTION (1) #define MICROPY_HELPER_REPL (1) #define MICROPY_REPL_AUTO_INDENT (1) -#define MICROPY_ENABLE_SOURCE_LINE (1) #define MICROPY_STREAMS_NON_BLOCK (1) #define MICROPY_PY_BUILTINS_HELP (1) -#define MICROPY_PY_BUILTINS_HELP_MODULES (1) #define MICROPY_ENABLE_SCHEDULER (1) #define MICROPY_PY_BUILTINS_BYTES_HEX (1) #define MICROPY_PY_BUILTINS_MEMORYVIEW (1) @@ -29,10 +27,10 @@ #define MICROPY_PY_IO_IOBASE (1) #define MICROPY_PY_OS (1) #define MICROPY_PY_JSON (1) +#define MICROPY_PY_GENERATOR_PEND_THROW (0) #define MICROPY_PY_RE (1) #define MICROPY_PY_BINASCII (1) #define MICROPY_PY_UCTYPES (1) -#define MICROPY_PY_HEAPQ (1) #define MICROPY_PY_RANDOM (1) #define MICROPY_PY_PLATFORM (1) @@ -49,6 +47,8 @@ unsigned long trng_random_u32(int delay); // selected extensions of the extra features set #define MICROPY_PY_OS_URANDOM (1) +#define MICROPY_ENABLE_SOURCE_LINE (SAMD21_EXTRA_FEATURES) +#define MICROPY_PY_BUILTINS_HELP_MODULES (SAMD21_EXTRA_FEATURES) #define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (SAMD21_EXTRA_FEATURES) #define MICROPY_COMP_RETURN_IF_EXPR (SAMD21_EXTRA_FEATURES) #define MICROPY_OPT_MPZ_BITWISE (SAMD21_EXTRA_FEATURES) From 43229cee3d05c615620861efc148f41ae25bb1c1 Mon Sep 17 00:00:00 2001 From: robert-hh Date: Fri, 10 Jul 2026 10:05:49 +0200 Subject: [PATCH 409/635] tools/ci.sh: Build SPARKFUN_SAMD21_DEV_BREAKOUT firmware in samd CI. It is the tightest on flash. Signed-off-by: robert-hh --- tools/ci.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/ci.sh b/tools/ci.sh index 91cd1aa6328..9cf00887b35 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -503,6 +503,7 @@ function ci_samd_build { make ${MAKEOPTS} -C ports/samd submodules make ${MAKEOPTS} -C ports/samd BOARD=ADAFRUIT_ITSYBITSY_M0_EXPRESS make ${MAKEOPTS} -C ports/samd BOARD=ADAFRUIT_ITSYBITSY_M4_EXPRESS + make ${MAKEOPTS} -C ports/samd BOARD=SPARKFUN_SAMD21_DEV_BREAKOUT } ######################################################################################## From e686426f837a59aa3e01665c2e3e01c65784b918 Mon Sep 17 00:00:00 2001 From: massimosala Date: Thu, 20 Jun 2024 23:13:04 +0200 Subject: [PATCH 410/635] docs/library/os: Add addendum to sync regarding different ports. Signed-off-by: massimosala --- docs/library/os.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/library/os.rst b/docs/library/os.rst index 483ef1c0a1e..598891a330b 100644 --- a/docs/library/os.rst +++ b/docs/library/os.rst @@ -107,6 +107,7 @@ Filesystem access .. function:: sync() Sync all filesystems. + On some ports this function isn't present because it isn't necessary to sync after writes to the file-system. Terminal redirection and duplication ------------------------------------ From 5598814764e83aa883f82c8fffe34e5fb78cd20a Mon Sep 17 00:00:00 2001 From: massimosala Date: Thu, 20 Jun 2024 23:17:49 +0200 Subject: [PATCH 411/635] docs/library/machine: Add note about memory reads being signed integers. Signed-off-by: massimosala --- docs/library/machine.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/docs/library/machine.rst b/docs/library/machine.rst index dad6128feec..b92602d4fc2 100644 --- a/docs/library/machine.rst +++ b/docs/library/machine.rst @@ -49,6 +49,23 @@ Example use (registers are specific to an stm32 microcontroller): # read PA3 value = (machine.mem32[GPIOA + GPIO_IDR] >> 3) & 1 + +Note: the returned values are signed integers. +Example: reading the cpuid register on esp8266 + +.. code-block:: python3 + + value = mem32[0x40001000] + +will return a negative value, that could be counter-intuitive. + +To always read a positive integer + +.. code-block:: python3 + + value = mem32[0x40001000] & 0xffffffff + + Reset related functions ----------------------- From e1f8f204b668666eeb3ac48d61292c4a4bf62e37 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Fri, 27 Mar 2026 23:31:37 +1100 Subject: [PATCH 412/635] tools/{mpremote,pyboard.py}: Add PTY device detection for QEMU. On PTY devices (e.g. QEMU serial), ioctl(FIONREAD) can race with write() causing inWaiting() to return 0 when data is available. This adds automatic PTY detection on Linux (/dev/pts/* with major number 136) and skips the inWaiting() check for PTY devices, falling through to the blocking serial.read() instead. Signed-off-by: Andrew Leech --- tools/mpremote/mpremote/transport_serial.py | 20 +++++++++++++++++-- tools/pyboard.py | 22 ++++++++++++++++++++- 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/tools/mpremote/mpremote/transport_serial.py b/tools/mpremote/mpremote/transport_serial.py index dbd47cffd18..ab70982b646 100644 --- a/tools/mpremote/mpremote/transport_serial.py +++ b/tools/mpremote/mpremote/transport_serial.py @@ -35,7 +35,7 @@ # Once the API is stabilised, the idea is that mpremote can be used both # as a command line tool and a library for interacting with devices. -import ast, io, os, re, struct, sys, time +import ast, io, os, re, stat, struct, sys, time import serial import serial.tools.list_ports from errno import EPERM, ENOTTY @@ -105,6 +105,20 @@ def __init__(self, device, baudrate=115200, wait=0, exclusive=True, timeout=None if delayed: print("") + self.is_pty = self._is_pty_device(device) + + @staticmethod + def _is_pty_device(device): + """Detect if device is a PTY (pseudo-terminal), e.g. used by QEMU.""" + if device.startswith("/dev/pts/"): + try: + st = os.stat(device) + if stat.S_ISCHR(st.st_mode) and os.major(st.st_rdev) == 136: + return True + except (OSError, AttributeError): + pass + return False + def close(self): # ESP Windows quirk: Prevent target from resetting when Windows clears DTR before RTS try: @@ -140,8 +154,10 @@ def read_until( while True: if data.endswith(ending): break - elif self.serial.inWaiting() > 0: + new_data = None + if self.is_pty or self.serial.inWaiting() > 0: new_data = self.serial.read(1) + if new_data: if data_consumer: data_consumer(new_data) data = new_data diff --git a/tools/pyboard.py b/tools/pyboard.py index 4099de299b2..6f146473837 100755 --- a/tools/pyboard.py +++ b/tools/pyboard.py @@ -70,6 +70,7 @@ import ast import errno import os +import stat import struct import sys import time @@ -333,6 +334,23 @@ def __init__( if delayed: print("") + if device.startswith("execpty:"): + self.is_pty = True + else: + self.is_pty = self._is_pty_device(device) + + @staticmethod + def _is_pty_device(device): + """Detect if device is a PTY (pseudo-terminal), e.g. used by QEMU.""" + if device.startswith("/dev/pts/"): + try: + st = os.stat(device) + if stat.S_ISCHR(st.st_mode) and os.major(st.st_rdev) == 136: + return True + except (OSError, AttributeError): + pass + return False + def close(self): self.serial.close() @@ -358,8 +376,10 @@ def read_until( while True: if data.endswith(ending): break - elif self.serial.inWaiting() > 0: + new_data = None + if self.is_pty or self.serial.inWaiting() > 0: new_data = self.serial.read(1) + if new_data: if data_consumer: data_consumer(new_data) data = new_data From 17f304110d92971488306ff116efec3808e14a1c Mon Sep 17 00:00:00 2001 From: Cristian Dinca Date: Mon, 13 Oct 2025 19:56:57 +0300 Subject: [PATCH 413/635] cc3200/ftp: Fix ftp_pop_param buffer overflows. This commit fixes some potential buffer overflow issues identified in the CC3200 FTP code. Signed-off-by: Cristian Dinca --- ports/cc3200/ftp/ftp.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/ports/cc3200/ftp/ftp.c b/ports/cc3200/ftp/ftp.c index 3f1099518fe..57ece7ba05f 100644 --- a/ports/cc3200/ftp/ftp.c +++ b/ports/cc3200/ftp/ftp.c @@ -281,7 +281,7 @@ static void ftp_close_files (void); static void ftp_close_filesystem_on_error (void); static void ftp_close_cmd_data (void); static ftp_cmd_index_t ftp_pop_command (char **str); -static void ftp_pop_param (char **str, char *param); +static void ftp_pop_param (char **str, char *param, size_t maxlen); static int ftp_print_eplf_item (char *dest, uint32_t destsize, FILINFO *fno); static int ftp_print_eplf_drive (char *dest, uint32_t destsize, const char *name); static bool ftp_open_file (const char *path, int mode); @@ -576,10 +576,7 @@ static void ftp_send_reply (_u16 status, char *message) { if (!message) { message = ""; } - snprintf((char *)ftp_cmd_buffer, 4, "%u", status); - strcat ((char *)ftp_cmd_buffer, " "); - strcat ((char *)ftp_cmd_buffer, message); - strcat ((char *)ftp_cmd_buffer, "\r\n"); + snprintf((char *)ftp_cmd_buffer, FTP_MAX_PARAM_SIZE + FTP_CMD_SIZE_MAX, "%u %s\r\n", status, message); fifoelement.sd = &ftp_data.c_sd; fifoelement.datasize = strlen((char *)ftp_cmd_buffer); fifoelement.data = mem_Malloc(fifoelement.datasize); @@ -666,7 +663,7 @@ static ftp_result_t ftp_recv_non_blocking (_i16 sd, void *buff, _i16 Maxlen, _i3 } static void ftp_get_param_and_open_child (char **bufptr) { - ftp_pop_param (bufptr, ftp_scratch_buffer); + ftp_pop_param (bufptr, ftp_scratch_buffer, FTP_MAX_PARAM_SIZE); ftp_open_child (ftp_path, ftp_scratch_buffer); ftp_data.closechild = true; } @@ -701,7 +698,7 @@ static void ftp_process_cmd (void) { case E_FTP_CMD_CWD: { fres = FR_NO_PATH; - ftp_pop_param (&bufptr, ftp_scratch_buffer); + ftp_pop_param (&bufptr, ftp_scratch_buffer, FTP_MAX_PARAM_SIZE); ftp_open_child (ftp_path, ftp_scratch_buffer); if ((ftp_path[0] == '/' && ftp_path[1] == '\0') || ((fres = f_opendir_helper (&ftp_data.dp, ftp_path)) == FR_OK)) { if (fres == FR_OK) { @@ -751,14 +748,14 @@ static void ftp_process_cmd (void) { ftp_send_reply(200, NULL); break; case E_FTP_CMD_USER: - ftp_pop_param (&bufptr, ftp_scratch_buffer); + ftp_pop_param (&bufptr, ftp_scratch_buffer, FTP_MAX_PARAM_SIZE); if (!memcmp(ftp_scratch_buffer, servers_user, MAX(strlen(ftp_scratch_buffer), strlen(servers_user)))) { ftp_data.login.uservalid = true && (strlen(servers_user) == strlen(ftp_scratch_buffer)); } ftp_send_reply(331, NULL); break; case E_FTP_CMD_PASS: - ftp_pop_param (&bufptr, ftp_scratch_buffer); + ftp_pop_param (&bufptr, ftp_scratch_buffer, FTP_MAX_PARAM_SIZE); if (!memcmp(ftp_scratch_buffer, servers_pass, MAX(strlen(ftp_scratch_buffer), strlen(servers_pass))) && ftp_data.login.uservalid) { ftp_data.login.passvalid = true && (strlen(servers_pass) == strlen(ftp_scratch_buffer)); @@ -938,8 +935,8 @@ static void stoupper (char *str) { } static ftp_cmd_index_t ftp_pop_command (char **str) { - char _cmd[FTP_CMD_SIZE_MAX]; - ftp_pop_param (str, _cmd); + char _cmd[FTP_CMD_SIZE_MAX + 1]; + ftp_pop_param (str, _cmd, sizeof(_cmd)); stoupper (_cmd); for (ftp_cmd_index_t i = 0; i < E_FTP_NUM_FTP_CMDS; i++) { if (!strcmp (_cmd, ftp_cmd_table[i].cmd)) { @@ -951,11 +948,18 @@ static ftp_cmd_index_t ftp_pop_command (char **str) { return E_FTP_CMD_NOT_SUPPORTED; } -static void ftp_pop_param (char **str, char *param) { +static void ftp_pop_param (char **str, char *param, size_t maxlen) { + size_t copied = 0; + + // copy at most maxlen - 1 bytes and NUL terminate while (**str != ' ' && **str != '\r' && **str != '\n' && **str != '\0') { - *param++ = **str; + if (copied + 1 < maxlen) { + *param++ = **str; + copied++; + } (*str)++; } + *param = '\0'; } From 1557d83598829bc484131be9c79be6aa11759943 Mon Sep 17 00:00:00 2001 From: npt-1707 Date: Mon, 14 Jul 2025 03:00:30 +0800 Subject: [PATCH 414/635] cc3200/FreeRTOS/Source/queue: Add assert for potential integer overflow. This issue was originally reported in CVE-2021-31571. It was resolved upstream in commit https://github.com/FreeRTOS/FreeRTOS-Kernel/commit/47338393f1f79558f6144213409f09f81d7c4837 Signed-off-by: npt-1707 --- ports/cc3200/FreeRTOS/Source/queue.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ports/cc3200/FreeRTOS/Source/queue.c b/ports/cc3200/FreeRTOS/Source/queue.c index ce623bec262..8c5787e164b 100644 --- a/ports/cc3200/FreeRTOS/Source/queue.c +++ b/ports/cc3200/FreeRTOS/Source/queue.c @@ -403,6 +403,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ } + /* Check for addition overflow. */ + configASSERT( ( sizeof( Queue_t ) + xQueueSizeInBytes ) > xQueueSizeInBytes ); + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); if( pxNewQueue != NULL ) From fe96314e9cb1163cc73d043d0dc3e74253e03426 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 3 Jun 2025 13:00:00 +1000 Subject: [PATCH 415/635] pyproject.toml: Enforce trailing newline on python files. Signed-off-by: Andrew Leech --- pyproject.toml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index f528961b2c8..00f2faf260f 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -61,8 +61,8 @@ exclude = [ # Ruff finds Python SyntaxError in these files "tests/micropython/heapalloc_fail_tstring.py", "tests/micropython/viper_args.py", ] -extend-select = ["C9", "PLC"] -extend-ignore = [ +extend-select = ["C9", "PLC", "W292"] +ignore = [ "E401", "E402", "E722", From 99c5fe85401202d573b310aa62d6c19b2d531c03 Mon Sep 17 00:00:00 2001 From: Hugo Frisk Date: Fri, 13 Jun 2025 11:55:30 +0200 Subject: [PATCH 416/635] rp2/machine_i2c: Allow disabling hardware I2C. Allows rp2 board definitions to disable i2c. This already exists in other ports such as esp32 and Zephyr. Signed-off-by: Hugo Frisk --- ports/rp2/machine_i2c.c | 4 ++++ ports/rp2/mpconfigport.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/ports/rp2/machine_i2c.c b/ports/rp2/machine_i2c.c index 99a94ec2f1a..51e5961a2d5 100644 --- a/ports/rp2/machine_i2c.c +++ b/ports/rp2/machine_i2c.c @@ -32,6 +32,8 @@ #include "hardware/i2c.h" +#if MICROPY_PY_MACHINE_I2C + #define DEFAULT_I2C_FREQ (400000) #define DEFAULT_I2C_TIMEOUT (50000) @@ -170,3 +172,5 @@ MP_DEFINE_CONST_OBJ_TYPE( protocol, &machine_i2c_p, locals_dict, &mp_machine_i2c_locals_dict ); + +#endif // MICROPY_PY_MACHINE_I2C diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index ae40d1e8090..54278ad4fd9 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -168,7 +168,9 @@ #define MICROPY_PY_MACHINE_PULSE (1) #define MICROPY_PY_MACHINE_PWM (1) #define MICROPY_PY_MACHINE_PWM_INCLUDEFILE "ports/rp2/machine_pwm.c" +#ifndef MICROPY_PY_MACHINE_I2C #define MICROPY_PY_MACHINE_I2C (1) +#endif #ifndef MICROPY_PY_MACHINE_I2C_TARGET #define MICROPY_PY_MACHINE_I2C_TARGET (1) #define MICROPY_PY_MACHINE_I2C_TARGET_INCLUDEFILE "ports/rp2/machine_i2c_target.c" From 37f9ecfd8177ce56063343c83d86fc5c82f575b5 Mon Sep 17 00:00:00 2001 From: Hugo Frisk Date: Fri, 13 Jun 2025 13:08:45 +0200 Subject: [PATCH 417/635] rp2/machine_spi: Allow disabling hardware SPI. Allow rp2 board definitions to disable SPI. This exists in other ports such as NRF and SAMD. Signed-off-by: Hugo Frisk --- ports/rp2/machine_spi.c | 4 ++++ ports/rp2/mpconfigport.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/ports/rp2/machine_spi.c b/ports/rp2/machine_spi.c index 9a3bf3a708b..124f45b61ef 100644 --- a/ports/rp2/machine_spi.c +++ b/ports/rp2/machine_spi.c @@ -32,6 +32,8 @@ #include "hardware/spi.h" #include "hardware/dma.h" +#if MICROPY_PY_MACHINE_SPI + #define DEFAULT_SPI_BAUDRATE (1000000) #define DEFAULT_SPI_POLARITY (0) #define DEFAULT_SPI_PHASE (0) @@ -381,3 +383,5 @@ mp_obj_base_t *mp_hal_get_spi_obj(mp_obj_t o) { mp_raise_TypeError(MP_ERROR_TEXT("expecting an SPI object")); } } + +#endif // MICROPY_PY_MACHINE_SPI diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index 54278ad4fd9..b74021b4726 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -183,9 +183,11 @@ #define MICROPY_PY_MACHINE_I2S_CONSTANT_RX (RX) #define MICROPY_PY_MACHINE_I2S_CONSTANT_TX (TX) #define MICROPY_PY_MACHINE_I2S_RING_BUF (1) +#ifndef MICROPY_PY_MACHINE_SPI #define MICROPY_PY_MACHINE_SPI (1) #define MICROPY_PY_MACHINE_SPI_MSB (SPI_MSB_FIRST) #define MICROPY_PY_MACHINE_SPI_LSB (SPI_LSB_FIRST) +#endif #define MICROPY_PY_MACHINE_SOFTSPI (1) #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_UART_INCLUDEFILE "ports/rp2/machine_uart.c" From f309e0119a8d7b708c4be0a0a090ab43a5266f2c Mon Sep 17 00:00:00 2001 From: Hugo Frisk Date: Fri, 13 Jun 2025 13:35:06 +0200 Subject: [PATCH 418/635] rp2/mpconfigport: Allow board definition of float implementation. Allow rp2 boards to define MICROPY_FLOAT_IMPL to desired custom type. Signed-off-by: Hugo Frisk --- ports/rp2/mpconfigport.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index b74021b4726..5f1c5c60cf8 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -120,7 +120,9 @@ #define MICROPY_STACK_CHECK_MARGIN (256) #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) #define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ) +#ifndef MICROPY_FLOAT_IMPL #define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT) +#endif #define MICROPY_SCHEDULER_DEPTH (8) #define MICROPY_SCHEDULER_STATIC_NODES (1) #ifndef MICROPY_USE_INTERNAL_ERRNO From 89e2c006d078b9c20f9bd8a2fe31cab3a779dd23 Mon Sep 17 00:00:00 2001 From: Hugo Frisk Date: Fri, 13 Jun 2025 14:26:34 +0200 Subject: [PATCH 419/635] rp2/mpconfigport: Allow board definition of GC stack entry type. Allows rp2 boards to define MICROPY_GC_STACK_ENTRY_TYPE to desired type other than the standard uint16_t for no psram or uint32_t with psram enabled. Signed-off-by: Hugo Frisk --- ports/rp2/mpconfigport.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index 5f1c5c60cf8..e9a4e44771d 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -87,11 +87,16 @@ // Memory allocation policies #if MICROPY_HW_ENABLE_PSRAM +#ifdef MICROPY_GC_STACK_ENTRY_TYPE +#error MICROPY_GC_STACK_ENTRY_TYPE can not be configured when MICROPY_HW_ENABLE_PSRAM is set. +#endif #define MICROPY_GC_STACK_ENTRY_TYPE uint32_t #define MICROPY_ALLOC_GC_STACK_SIZE (1024) // Avoid slowdown when GC stack overflow causes a full sweep of PSRAM-backed heap #else +#ifndef MICROPY_GC_STACK_ENTRY_TYPE #define MICROPY_GC_STACK_ENTRY_TYPE uint16_t #endif +#endif #ifndef MICROPY_GC_SPLIT_HEAP #define MICROPY_GC_SPLIT_HEAP MICROPY_HW_ENABLE_PSRAM // whether PSRAM is added to or replaces the heap #endif From fc6402faf45117a574e31aa81a96c5a6a90a202e Mon Sep 17 00:00:00 2001 From: Hugo Frisk Date: Fri, 13 Jun 2025 14:29:06 +0200 Subject: [PATCH 420/635] rp2/mpconfigport: Allow disabling software I2C. Allow rp2 board definitions to disable soft i2c. Signed-off-by: Hugo Frisk --- ports/rp2/mpconfigport.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index e9a4e44771d..b65fc2e9fc7 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -184,7 +184,9 @@ #define MICROPY_PY_MACHINE_I2C_TARGET_MAX (2) #define MICROPY_PY_MACHINE_I2C_TARGET_HARD_IRQ (1) #endif +#ifndef MICROPY_PY_MACHINE_SOFTI2C #define MICROPY_PY_MACHINE_SOFTI2C (1) +#endif #define MICROPY_PY_MACHINE_I2S (1) #define MICROPY_PY_MACHINE_I2S_INCLUDEFILE "ports/rp2/machine_i2s.c" #define MICROPY_PY_MACHINE_I2S_CONSTANT_RX (RX) From 532428cc6d85b1183a43bf82ca789e3f3f99fd1f Mon Sep 17 00:00:00 2001 From: Hugo Frisk Date: Fri, 13 Jun 2025 14:32:18 +0200 Subject: [PATCH 421/635] rp2/mpconfigport: Allow disabling I2S. Allow rp2 board definitions to disable I2S. Signed-off-by: Hugo Frisk --- ports/rp2/mpconfigport.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index b65fc2e9fc7..cbe2540ebbd 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -187,7 +187,9 @@ #ifndef MICROPY_PY_MACHINE_SOFTI2C #define MICROPY_PY_MACHINE_SOFTI2C (1) #endif +#ifndef MICROPY_PY_MACHINE_I2S #define MICROPY_PY_MACHINE_I2S (1) +#endif #define MICROPY_PY_MACHINE_I2S_INCLUDEFILE "ports/rp2/machine_i2s.c" #define MICROPY_PY_MACHINE_I2S_CONSTANT_RX (RX) #define MICROPY_PY_MACHINE_I2S_CONSTANT_TX (TX) From 67524d6473d6b270b53a7e448efb7f82ccf229a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Tue, 28 Apr 2026 18:33:00 +0200 Subject: [PATCH 422/635] esp32/machine_timer: Use GPTimer and ESP Timer, support virtual timers. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-Authored-By: Lucien Murray-Pitts Signed-off-by: Daniël van de Giessen --- ports/esp32/esp32_common.cmake | 1 + ports/esp32/machine_timer.c | 413 +++++++++++++++++++-------------- ports/esp32/machine_timer.h | 44 ++-- ports/esp32/machine_uart.c | 54 +++-- 4 files changed, 302 insertions(+), 210 deletions(-) diff --git a/ports/esp32/esp32_common.cmake b/ports/esp32/esp32_common.cmake index da762e50459..fee776fa661 100644 --- a/ports/esp32/esp32_common.cmake +++ b/ports/esp32/esp32_common.cmake @@ -170,6 +170,7 @@ list(APPEND IDF_COMPONENTS esp_app_format esp_mm esp_common + esp_driver_gptimer esp_eth esp_event esp_hw_support diff --git a/ports/esp32/machine_timer.c b/ports/esp32/machine_timer.c index d953f324b9c..4fc9fc7839a 100644 --- a/ports/esp32/machine_timer.c +++ b/ports/esp32/machine_timer.c @@ -35,200 +35,222 @@ #include "py/runtime.h" #include "modmachine.h" -#include "hal/timer_hal.h" -#include "hal/timer_ll.h" -#include "soc/timer_periph.h" -#include "esp_private/esp_clk_tree_common.h" -#include "esp_private/periph_ctrl.h" #include "machine_timer.h" +#include "esp_clk_tree.h" + +#if !MICROPY_ENABLE_FINALISER +#error "machine.Timer requires MICROPY_ENABLE_FINALISER." +#endif #define TIMER_CLK_SRC GPTIMER_CLK_SRC_DEFAULT #define TIMER_DIVIDER 8 -#define TIMER_FLAGS 0 - -#if CONFIG_IDF_TARGET_ESP32P4 -static uint8_t __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); -#endif const mp_obj_type_t machine_timer_type; -static mp_obj_t machine_timer_init_helper(machine_timer_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args); -static mp_obj_t machine_timer_deinit(mp_obj_t self_in); +uint32_t machine_timer_freq_hz(machine_timer_obj_t *self) { + if (self->id >= 0) { + // The timer source clock is APB or a fixed PLL (depending on chip), both constant frequency. + uint32_t freq; + check_esp_err(esp_clk_tree_src_get_freq_hz(TIMER_CLK_SRC, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &freq)); + assert(freq % TIMER_DIVIDER == 0); // Source clock should divide evenly into TIMER_DIVIDER + return freq / TIMER_DIVIDER; + } -uint32_t machine_timer_freq_hz(void) { - // The timer source clock is APB or a fixed PLL (depending on chip), both constant frequency. - uint32_t freq; - check_esp_err(esp_clk_tree_src_get_freq_hz(TIMER_CLK_SRC, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &freq)); - assert(freq % TIMER_DIVIDER == 0); // Source clock should divide evenly into TIMER_DIVIDER - return freq / TIMER_DIVIDER; + // Virtual timers always use microsecond resolution + return 1000000; } -void machine_timer_deinit_all(void) { - // Disable, deallocate and remove all timers from list - machine_timer_obj_t **t = &MP_STATE_PORT(machine_timer_obj_head); - while (*t != NULL) { - machine_timer_deinit(*t); - machine_timer_obj_t *next = (*t)->next; - m_del_obj(machine_timer_obj_t, *t); - *t = next; - } +static bool machine_timer_isr_hardware(gptimer_handle_t timer, const gptimer_alarm_event_data_t *event_data, void *self_in) { + machine_timer_obj_t *self = self_in; + return self->handler(self); } -static void machine_timer_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { +static void machine_timer_isr_virtual(void *self_in) { machine_timer_obj_t *self = self_in; - qstr mode = self->repeat ? MP_QSTR_PERIODIC : MP_QSTR_ONE_SHOT; - uint64_t period = self->period / (machine_timer_freq_hz() / 1000); // convert to ms - #if SOC_TIMER_GROUP_TIMERS_PER_GROUP == 1 - mp_printf(print, "Timer(%u, mode=%q, period=%lu)", self->group, mode, period); - #else - mp_printf(print, "Timer(%u, mode=%q, period=%lu)", (self->group << 1) | self->index, mode, period); - #endif + if (self->repeat) { + self->virtual_started = esp_timer_get_time(); + } else { + self->virtual_stopped = esp_timer_get_time(); + } + if (self->handler(self)) { + #if CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD + esp_timer_isr_dispatch_need_yield(); + #endif + } } -machine_timer_obj_t *machine_timer_create(mp_uint_t timer) { +static bool machine_timer_handler(machine_timer_obj_t *self) { + mp_sched_schedule(self->handler_ctx, self); + mp_hal_wake_main_task_from_isr(); + // Above function already yields, thus we return false + // so the timer ISR doesn't needlessly yield again + return false; +} - machine_timer_obj_t *self = NULL; - #if SOC_TIMER_GROUP_TIMERS_PER_GROUP == 1 - mp_uint_t group = timer & 1; - mp_uint_t index = 0; - #else - mp_uint_t group = (timer >> 1) & 1; - mp_uint_t index = timer & 1; - #endif +machine_timer_obj_t *machine_timer_create(mp_int_t id) { + // Check hardware timer ID is valid + if (id >= SOC_TIMER_GROUP_TOTAL_TIMERS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Timer(%d) doesn't exist, there are only %d hardware timers"), id, SOC_TIMER_GROUP_TOTAL_TIMERS); + } - // Check whether the timer is already initialized, if so use it - for (machine_timer_obj_t *t = MP_STATE_PORT(machine_timer_obj_head); t; t = t->next) { - if (t->group == group && t->index == index) { - self = t; - break; + // Check whether this hardware timer is already initialized, if so reuse it + if (id >= 0) { + for (machine_timer_obj_t *t = MP_STATE_PORT(machine_timer_obj_head); t; t = t->next) { + if (t->id == id) { + return t; + } } } - // The timer does not exist, create it. - if (self == NULL) { - self = mp_obj_malloc(machine_timer_obj_t, &machine_timer_type); - self->group = group; - self->index = index; - self->handle = NULL; - - // Add the timer to the linked-list of timers - self->next = MP_STATE_PORT(machine_timer_obj_head); - MP_STATE_PORT(machine_timer_obj_head) = self; - } - return self; -} -static mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { - mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true); - - // Create the new timer. - uint32_t timer_number = mp_obj_get_int(args[0]); - if (timer_number >= SOC_TIMER_GROUP_TOTAL_TIMERS) { - mp_raise_ValueError(MP_ERROR_TEXT("invalid Timer number")); + // We want hardware timer IDs to be deterministic, meaning a specific ID always + // maps the the same hardware peripheral. gptimer_new_timer() returns the first + // available timer, starting from ID 0. Thus we ensure we initialize all timers + // in order (or to be more precise, we always initialize timers with a lower ID + // first) so that the first available timer ID is always the timer ID requested + // regardless of the order in which timer IDs are created and deleted in Python. + if (id > 0) { + machine_timer_create(id - 1); } - machine_timer_obj_t *self = machine_timer_create(timer_number); - if (n_args > 1 || n_kw > 0) { - mp_map_t kw_args; - mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); - machine_timer_init_helper(self, n_args - 1, args + 1, &kw_args); + machine_timer_obj_t *self = mp_obj_malloc_with_finaliser(machine_timer_obj_t, &machine_timer_type); + self->id = id; + self->period = 0; + self->repeat = false; + self->virtual_started = 0; + self->virtual_stopped = 0; + self->handler = NULL; + self->handler_ctx = NULL; + + if (id >= 0) { + const gptimer_config_t hardware_config = { + .clk_src = TIMER_CLK_SRC, + .direction = GPTIMER_COUNT_UP, + .resolution_hz = machine_timer_freq_hz(self), + }; + check_esp_err(gptimer_new_timer(&hardware_config, &self->handle.hardware)); + gptimer_event_callbacks_t hardware_event_callbacks = { + .on_alarm = machine_timer_isr_hardware + }; + esp_err_t result = gptimer_register_event_callbacks(self->handle.hardware, &hardware_event_callbacks, (void *)self); + if (result != ESP_OK) { + gptimer_del_timer(self->handle.hardware); + check_esp_err(result); + } + + // Hardware timers are immediately added to the + // linked-list of timers so they can be reused + self->next = MP_STATE_PORT(machine_timer_obj_head); + MP_STATE_PORT(machine_timer_obj_head) = self; + } else { + const esp_timer_create_args_t virtual_args = { + .callback = machine_timer_isr_virtual, + .arg = (void *)self, + .dispatch_method = ESP_TIMER_TASK, + .name = "mpy_machine_timer", + .skip_unhandled_events = true, + }; + check_esp_err(esp_timer_create(&virtual_args, &self->handle.virtual)); } return self; } -void machine_timer_disable(machine_timer_obj_t *self) { - if (self->hal_context.dev != NULL) { - // Disable the counter and alarm. - timer_ll_enable_counter(self->hal_context.dev, self->index, false); - timer_ll_enable_alarm(self->hal_context.dev, self->index, false); +void machine_timer_configure(machine_timer_obj_t *self) { + // Period must be non-zero + if (self->period == 0) { + mp_raise_ValueError(MP_ERROR_TEXT("Timer period is too short for this timer")); } - if (self->handle) { - // Disable the interrupt - ESP_ERROR_CHECK(esp_intr_disable(self->handle)); + if (self->id >= 0) { + gptimer_alarm_config_t alarm_config = { + .reload_count = 0, + .alarm_count = self->period, + .flags.auto_reload_on_alarm = self->repeat, + }; + check_esp_err(gptimer_set_alarm_action(self->handle.hardware, &alarm_config)); + esp_err_t result = gptimer_enable(self->handle.hardware); + if (result != ESP_ERR_INVALID_STATE) { + check_esp_err(result); + } + } else { + // Virtual timers need no configuration but should be + // be added to the linked-list of timers so they are + // not automatically garbage collected while running + for (machine_timer_obj_t *t = MP_STATE_PORT(machine_timer_obj_head); t; t = t->next) { + if (t == self) { + return; + } + } + self->next = MP_STATE_PORT(machine_timer_obj_head); + MP_STATE_PORT(machine_timer_obj_head) = self; } - - // We let the disabled timer stay in the list, as it might be - // referenced elsewhere } -static void machine_timer_isr(void *self_in) { - machine_timer_obj_t *self = self_in; - - uint32_t intr_status = timer_ll_get_intr_status(self->hal_context.dev); - - if (intr_status & TIMER_LL_EVENT_ALARM(self->index)) { - timer_ll_clear_intr_status(self->hal_context.dev, TIMER_LL_EVENT_ALARM(self->index)); +void machine_timer_start(machine_timer_obj_t *self) { + if (self->id >= 0) { + check_esp_err(gptimer_set_raw_count(self->handle.hardware, 0)); + check_esp_err(gptimer_start(self->handle.hardware)); + } else { + self->virtual_started = esp_timer_get_time(); if (self->repeat) { - timer_ll_enable_alarm(self->hal_context.dev, self->index, true); + check_esp_err(esp_timer_start_periodic(self->handle.virtual, self->period)); + } else { + check_esp_err(esp_timer_start_once(self->handle.virtual, self->period)); } - self->handler(self); } } -static void machine_timer_isr_handler(machine_timer_obj_t *self) { - mp_sched_schedule(self->callback, self); - mp_hal_wake_main_task_from_isr(); -} - -void machine_timer_enable(machine_timer_obj_t *self) { - // Initialise the timer. - timer_hal_init(&self->hal_context, self->group, self->index); - - PERIPH_RCC_ACQUIRE_ATOMIC(timer_group_periph_signals.groups[self->index].module, ref_count) { - if (ref_count == 0) { - timer_ll_enable_bus_clock(self->index, true); - timer_ll_reset_register(self->index); +void machine_timer_stop(machine_timer_obj_t *self) { + esp_err_t result; + if (self->id >= 0) { + result = gptimer_stop(self->handle.hardware); + } else { + result = esp_timer_stop(self->handle.virtual); + if (result == ESP_OK) { + self->virtual_stopped = esp_timer_get_time(); } } + if (result != ESP_ERR_INVALID_STATE) { + check_esp_err(result); + } +} - timer_ll_enable_counter(self->hal_context.dev, self->index, false); - - #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) - esp_clk_tree_enable_src(TIMER_CLK_SRC, true); - #elif TIMER_CLK_SRC != SOC_MOD_CLK_APB - // esp_clk_tree_enable_src() is only required on some newer chips where timer - // source clock may not be enabled by default - #error "This chip requires ESP-IDF v5.4 or newer for working Timer." - #endif - - #if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) - timer_ll_set_clock_source(self->hal_context.dev, self->index, TIMER_CLK_SRC); - timer_ll_enable_clock(self->hal_context.dev, self->index, true); - #else - timer_ll_set_clock_source(self->group, self->index, TIMER_CLK_SRC); - timer_ll_enable_clock(self->group, self->index, true); - #endif - timer_ll_set_clock_prescale(self->hal_context.dev, self->index, TIMER_DIVIDER); - timer_hal_set_counter_value(&self->hal_context, 0); - timer_ll_set_count_direction(self->hal_context.dev, self->index, GPTIMER_COUNT_UP); - - // Allocate and enable the alarm interrupt. - timer_ll_enable_intr(self->hal_context.dev, TIMER_LL_EVENT_ALARM(self->index), false); - timer_ll_clear_intr_status(self->hal_context.dev, TIMER_LL_EVENT_ALARM(self->index)); - if (self->handle) { - ESP_ERROR_CHECK(esp_intr_enable(self->handle)); +mp_obj_t machine_timer_deinit(mp_obj_t self_in) { + machine_timer_obj_t *self = self_in; + machine_timer_stop(self); + if (self->id >= 0) { + esp_err_t result = gptimer_disable(self->handle.hardware); + if (result != ESP_ERR_INVALID_STATE) { + check_esp_err(result); + } } else { - ESP_ERROR_CHECK(esp_intr_alloc( - timer_group_periph_signals.groups[self->group].timer_irq_id[self->index], - TIMER_FLAGS, - machine_timer_isr, - self, - &self->handle - )); + // Virtual timers may be immediately garbage collected + // (hardware timers must stay in the list to be reused) + for (machine_timer_obj_t **t = &MP_STATE_PORT(machine_timer_obj_head); *t != NULL; t = &(*t)->next) { + if (*t == self) { + *t = self->next; + break; + } + } } - timer_ll_enable_intr(self->hal_context.dev, TIMER_LL_EVENT_ALARM(self->index), true); - - // Enable the alarm to trigger at the given period. - timer_ll_set_alarm_value(self->hal_context.dev, self->index, self->period); - timer_ll_enable_alarm(self->hal_context.dev, self->index, true); - - // Set the counter to reload at 0 if it's in repeat mode. - timer_ll_set_reload_value(self->hal_context.dev, self->index, 0); - timer_ll_enable_auto_reload(self->hal_context.dev, self->index, self->repeat); + self->period = 0; + self->repeat = false; + self->virtual_started = 0; + self->virtual_stopped = 0; + self->handler = NULL; + self->handler_ctx = NULL; + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_deinit_obj, machine_timer_deinit); - // Enable the counter. - timer_ll_enable_counter(self->hal_context.dev, self->index, true); +// Called by board port soft reset routine to deactivate all timers before reboot. +void machine_timer_deinit_all(void) { + machine_timer_obj_t **t = &MP_STATE_PORT(machine_timer_obj_head); + while (*t != NULL) { + machine_timer_obj_t *next = (*t)->next; + machine_timer_deinit(*t); + *t = next; + } } static mp_obj_t machine_timer_init_helper(machine_timer_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { @@ -253,7 +275,11 @@ static mp_obj_t machine_timer_init_helper(machine_timer_obj_t *self, mp_uint_t n { MP_QSTR_hard, MP_ARG_KW_ONLY | MP_ARG_BOOL, {.u_bool = false} }, }; - machine_timer_disable(self); + // If previously initialized, indicated by a handler being set, first deinitialize + // (Deiniting is always safe, but needlessly prints an error if already deinited) + if (self->handler != NULL) { + machine_timer_deinit(self); + } mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); @@ -264,56 +290,101 @@ static mp_obj_t machine_timer_init_helper(machine_timer_obj_t *self, mp_uint_t n #if MICROPY_PY_BUILTINS_FLOAT if (args[ARG_freq].u_obj != mp_const_none) { - self->period = (uint64_t)(machine_timer_freq_hz() / mp_obj_get_float(args[ARG_freq].u_obj)); + self->period = (uint64_t)(machine_timer_freq_hz(self) / mp_obj_get_float(args[ARG_freq].u_obj)); } #else if (args[ARG_freq].u_int != 0xffffffff) { - self->period = TIMER_SCALE / ((uint64_t)args[ARG_freq].u_int); + self->period = machine_timer_freq_hz(self) / ((uint64_t)args[ARG_freq].u_int); } #endif else { - self->period = (((uint64_t)args[ARG_period].u_int) * machine_timer_freq_hz()) / args[ARG_tick_hz].u_int; + self->period = (((uint64_t)args[ARG_period].u_int) * machine_timer_freq_hz(self)) / args[ARG_tick_hz].u_int; } self->repeat = args[ARG_mode].u_int; - self->handler = machine_timer_isr_handler; - self->callback = args[ARG_callback].u_obj; - machine_timer_enable(self); + self->handler = machine_timer_handler; + self->handler_ctx = args[ARG_callback].u_obj; + + machine_timer_configure(self); + machine_timer_start(self); return mp_const_none; } -static mp_obj_t machine_timer_deinit(mp_obj_t self_in) { - machine_timer_obj_t *self = self_in; +static mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // Get timer ID, or default to -1 (virtual) + mp_int_t id = -1; + if (n_args > 0) { + id = mp_obj_get_int(args[0]); + --n_args; + ++args; + } - machine_timer_disable(self); - if (self->handle) { - ESP_ERROR_CHECK(esp_intr_free(self->handle)); - self->handle = NULL; + machine_timer_obj_t *self = machine_timer_create(id); + + if (n_args > 0 || n_kw > 0) { + // Start the timer + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + machine_timer_init_helper(self, n_args, args, &kw_args); } - return mp_const_none; + return self; } -static MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_deinit_obj, machine_timer_deinit); static mp_obj_t machine_timer_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { return machine_timer_init_helper(args[0], n_args - 1, args + 1, kw_args); } static MP_DEFINE_CONST_FUN_OBJ_KW(machine_timer_init_obj, 1, machine_timer_init); +static mp_obj_t machine_timer_del(mp_obj_t self_in) { + machine_timer_obj_t *self = self_in; + + machine_timer_deinit(self); + if (self->id >= 0) { + // Hardware timers must first be removed from the linked-list of timers, + // virtual timers will already have been removed during deinitialization + for (machine_timer_obj_t **t = &MP_STATE_PORT(machine_timer_obj_head); *t != NULL; t = &(*t)->next) { + if (*t == self) { + *t = self->next; + break; + } + } + check_esp_err(gptimer_del_timer(self->handle.hardware)); + } else { + check_esp_err(esp_timer_delete(self->handle.virtual)); + } + + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_del_obj, machine_timer_del); + static mp_obj_t machine_timer_value(mp_obj_t self_in) { machine_timer_obj_t *self = self_in; - if (self->handle == NULL) { - mp_raise_ValueError(MP_ERROR_TEXT("timer not set")); + uint64_t result; + if (self->id >= 0) { + check_esp_err(gptimer_get_raw_count(self->handle.hardware, &result)); + } else { + if (esp_timer_is_active(self->handle.virtual)) { + result = esp_timer_get_time() - self->virtual_started; + } else { + result = self->virtual_stopped - self->virtual_started; + } } - uint64_t result = timer_ll_get_counter_value(self->hal_context.dev, self->index); - return MP_OBJ_NEW_SMALL_INT((mp_uint_t)(result / (machine_timer_freq_hz() / 1000))); // value in ms + return MP_OBJ_NEW_SMALL_INT((mp_uint_t)(result / (machine_timer_freq_hz(self) / 1000))); // value in ms } static MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_value_obj, machine_timer_value); +static void machine_timer_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_timer_obj_t *self = self_in; + qstr mode = self->repeat ? MP_QSTR_ONE_SHOT : MP_QSTR_PERIODIC; + uint64_t period = self->period / (machine_timer_freq_hz(self) / 1000); // convert to ms + mp_printf(print, "Timer(%d, mode=%q, period=%lu)", self->id, mode, period); +} + static const mp_rom_map_elem_t machine_timer_locals_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&machine_timer_deinit_obj) }, + { MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&machine_timer_del_obj) }, { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_timer_deinit_obj) }, { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_timer_init_obj) }, { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&machine_timer_value_obj) }, diff --git a/ports/esp32/machine_timer.h b/ports/esp32/machine_timer.h index 5dd0ce95ac8..d8afe38a661 100644 --- a/ports/esp32/machine_timer.h +++ b/ports/esp32/machine_timer.h @@ -30,33 +30,45 @@ #ifndef MICROPY_INCLUDED_ESP32_MACHINE_TIMER_H #define MICROPY_INCLUDED_ESP32_MACHINE_TIMER_H -#include "hal/timer_hal.h" -#include "hal/timer_ll.h" -#include "soc/timer_periph.h" +#include "driver/gptimer.h" +#include "esp_timer.h" typedef struct _machine_timer_obj_t { mp_obj_base_t base; - timer_hal_context_t hal_context; - mp_uint_t group; - mp_uint_t index; + // Positive means hardware, -1 means virtual + mp_int_t id; + union { + gptimer_handle_t hardware; + esp_timer_handle_t virtual; + } handle; - mp_uint_t repeat; - // ESP32 timers are 64-bit + // Period is in units of the timers' frequency, + // as returned by machine_timer_freq_hz() uint64_t period; + bool repeat; - mp_obj_t callback; + // Virtual timers don't have counters, thus we + // emulate it by calculating based on the time + int64_t virtual_started; + int64_t virtual_stopped; - intr_handle_t handle; - void (*handler)(struct _machine_timer_obj_t *timer); + // Default handler simply schedules execution of the context + // (which usually is a callable Python object). Other C code + // may set different handlers; see for example UART's RXIDLE. + bool (*handler)(struct _machine_timer_obj_t *timer); + mp_obj_t handler_ctx; + // Pointer to next timer in linked list of active timers struct _machine_timer_obj_t *next; } machine_timer_obj_t; -machine_timer_obj_t *machine_timer_create(mp_uint_t timer); -void machine_timer_enable(machine_timer_obj_t *self); -void machine_timer_disable(machine_timer_obj_t *self); - -uint32_t machine_timer_freq_hz(void); +// Externalize machine timer for use elsewhere in board support +machine_timer_obj_t *machine_timer_create(mp_int_t id); +uint32_t machine_timer_freq_hz(machine_timer_obj_t *self); +void machine_timer_configure(machine_timer_obj_t *self); +void machine_timer_start(machine_timer_obj_t *self); +void machine_timer_stop(machine_timer_obj_t *self); +mp_obj_t machine_timer_deinit(mp_obj_t self_in); #endif // MICROPY_INCLUDED_ESP32_MACHINE_TIMER_H diff --git a/ports/esp32/machine_uart.c b/ports/esp32/machine_uart.c index 1bcdae4e8a0..3f69b079093 100644 --- a/ports/esp32/machine_uart.c +++ b/ports/esp32/machine_uart.c @@ -59,7 +59,7 @@ #define UART_IRQ_RXIDLE (0x1000) #define UART_IRQ_BREAK (1 << UART_BREAK) #define MP_UART_ALLOWED_FLAGS (UART_IRQ_RX | UART_IRQ_RXIDLE | UART_IRQ_BREAK) -#define RXIDLE_TIMER_MIN (machine_timer_freq_hz() * 5 / 10000) // 500us minimum rxidle time +#define RXIDLE_TIMER_MIN (500) // 500us minimum rxidle time #define UART_QUEUE_SIZE (3) typedef struct _machine_uart_default_pins_t { @@ -119,7 +119,6 @@ typedef struct _machine_uart_obj_t { mp_irq_obj_t *mp_irq_obj; // user IRQ object machine_timer_obj_t *rxidle_timer; uint8_t rxidle_state; - uint16_t rxidle_period; } machine_uart_obj_t; static const char *_parity_name[] = {"None", "1", "0"}; @@ -146,20 +145,22 @@ static bool uart_is_repl(uart_port_t uart_num) { { MP_ROM_QSTR(MP_QSTR_IRQ_RXIDLE), MP_ROM_INT(UART_IRQ_RXIDLE) }, \ { MP_ROM_QSTR(MP_QSTR_IRQ_BREAK), MP_ROM_INT(UART_IRQ_BREAK) }, \ -static void uart_timer_callback(machine_timer_obj_t *timer) { - // The UART object is referred here by the callback field. - machine_uart_obj_t *self = (machine_uart_obj_t *)timer->callback; +static bool uart_timer_callback(machine_timer_obj_t *timer) { + machine_uart_obj_t *self = (machine_uart_obj_t *)timer->handler_ctx; if (self->rxidle_state == RXIDLE_ALERT) { // At the first call, just switch the state self->rxidle_state = RXIDLE_ARMED; } else if (self->rxidle_state == RXIDLE_ARMED) { - // At the second call, run the irq callback and stop the timer + // At the second call, stop the timer and run the irq callback + machine_timer_stop(self->rxidle_timer); self->rxidle_state = RXIDLE_STANDBY; self->mp_irq_flags = UART_IRQ_RXIDLE; mp_irq_handler(self->mp_irq_obj); mp_hal_wake_main_task_from_isr(); - machine_timer_disable(self->rxidle_timer); } + // Above function already yields, thus we return false + // so the timer ISR doesn't needlessly yield again + return false; } static void uart_event_task(void *self_in) { @@ -173,10 +174,8 @@ static void uart_event_task(void *self_in) { // Event of UART receiving data case UART_DATA: if (self->mp_irq_trigger & UART_IRQ_RXIDLE) { - if (self->rxidle_state != RXIDLE_INACTIVE) { - if (self->rxidle_state == RXIDLE_STANDBY) { - machine_timer_enable(self->rxidle_timer); - } + if (self->rxidle_state == RXIDLE_STANDBY) { + machine_timer_start(self->rxidle_timer); } self->rxidle_state = RXIDLE_ALERT; } @@ -509,7 +508,7 @@ static void mp_machine_uart_deinit(machine_uart_obj_t *self) { self->uart_event_task = NULL; } if (self->rxidle_timer != NULL) { - machine_timer_disable(self->rxidle_timer); + machine_timer_stop(self->rxidle_timer); if (self->rxidle_state > RXIDLE_STANDBY) { // Currently deinit(),init() sequence resumes any previously // configured irqs, and we currently also rely on this when changing @@ -573,17 +572,17 @@ static void uart_irq_configure_timer(machine_uart_obj_t *self, mp_uint_t trigger self->mp_irq_obj->ishard = false; uint32_t baudrate; uart_get_baudrate(self->uart_num, &baudrate); - mp_int_t period = machine_timer_freq_hz() * 20 / baudrate + 1; - if (period < RXIDLE_TIMER_MIN) { - period = RXIDLE_TIMER_MIN; + // Wait for 2 characters worth of time before triggering the RXIDLE event + uint8_t bits_per_character = 1 + self->bits + self->parity + self->stop; + uint64_t period_us = ((2 * bits_per_character) * 1000000) / baudrate; + if (period_us < RXIDLE_TIMER_MIN) { + period_us = RXIDLE_TIMER_MIN; } - self->rxidle_period = period; - self->rxidle_timer->period = period; - self->rxidle_timer->handler = uart_timer_callback; - // The Python callback is not used. So use this - // data field to hold a reference to the UART object. - self->rxidle_timer->callback = self; + self->rxidle_timer->period = (period_us * machine_timer_freq_hz(self->rxidle_timer)) / 1000000 + 1; self->rxidle_timer->repeat = true; + self->rxidle_timer->handler = uart_timer_callback; + self->rxidle_timer->handler_ctx = self; + machine_timer_configure(self->rxidle_timer); self->rxidle_state = RXIDLE_STANDBY; } } @@ -641,8 +640,17 @@ static mp_irq_obj_t *mp_machine_uart_irq(machine_uart_obj_t *self, bool any_args } self->mp_irq_obj->ishard = false; self->mp_irq_trigger = trigger; - self->rxidle_timer = machine_timer_create(RXIDLE_TIMER_IDX); - uart_irq_configure_timer(self, trigger); + + // Set up the RXIDLE timer + if (handler != mp_const_none) { + if (self->rxidle_timer == NULL) { + self->rxidle_timer = machine_timer_create(RXIDLE_TIMER_IDX); + } + uart_irq_configure_timer(self, trigger); + } else if (self->rxidle_timer != NULL) { + machine_timer_deinit(self->rxidle_timer); + self->rxidle_timer = NULL; + } // Start a task for handling events if (handler != mp_const_none && self->uart_event_task == NULL && self->uart_queue != NULL) { From 96de72daeeeecdeb0181dbfeefc941c3949b966d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Wed, 29 Apr 2026 12:41:10 +0200 Subject: [PATCH 423/635] esp32/machine_timer: Remove deinit_all because timers have finalisers. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Daniël van de Giessen --- ports/esp32/machine_timer.c | 10 ---------- ports/esp32/main.c | 3 --- ports/esp32/modmachine.h | 1 - 3 files changed, 14 deletions(-) diff --git a/ports/esp32/machine_timer.c b/ports/esp32/machine_timer.c index 4fc9fc7839a..26d9cd03855 100644 --- a/ports/esp32/machine_timer.c +++ b/ports/esp32/machine_timer.c @@ -243,16 +243,6 @@ mp_obj_t machine_timer_deinit(mp_obj_t self_in) { } static MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_deinit_obj, machine_timer_deinit); -// Called by board port soft reset routine to deactivate all timers before reboot. -void machine_timer_deinit_all(void) { - machine_timer_obj_t **t = &MP_STATE_PORT(machine_timer_obj_head); - while (*t != NULL) { - machine_timer_obj_t *next = (*t)->next; - machine_timer_deinit(*t); - *t = next; - } -} - static mp_obj_t machine_timer_init_helper(machine_timer_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { enum { ARG_mode, diff --git a/ports/esp32/main.c b/ports/esp32/main.c index 4627c06ee94..697f4efde63 100644 --- a/ports/esp32/main.c +++ b/ports/esp32/main.c @@ -197,12 +197,9 @@ void mp_task(void *pvParameter) { wifi_csi_deinit(); #endif - // Deinit uart before timers, as esp32 uart - // depends on a timer instance #if MICROPY_PY_MACHINE_UART machine_uart_deinit_all(); #endif - machine_timer_deinit_all(); #if MICROPY_PY_ESP32_PCNT esp32_pcnt_deinit_all(); diff --git a/ports/esp32/modmachine.h b/ports/esp32/modmachine.h index 60005323c3e..af58f5f1052 100644 --- a/ports/esp32/modmachine.h +++ b/ports/esp32/modmachine.h @@ -18,7 +18,6 @@ void machine_pins_init(void); void machine_pins_deinit(void); void machine_pwm_deinit_all(void); // TODO: void machine_rmt_deinit_all(void); -void machine_timer_deinit_all(void); void machine_uart_deinit_all(void); void machine_i2s_init0(); From 4d68c1638142bb4ba97da04c305fbc4a06c58a64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Fri, 3 Jul 2026 11:12:12 +0200 Subject: [PATCH 424/635] tests/extmod/machine_timer: Enable virtual timer tests for all ports. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 35779273dc now virtual timers were added to the ESP32 port. All ports that support machine.Timer now support virtual timers. Signed-off-by: Daniël van de Giessen --- docs/library/machine.Timer.rst | 3 +-- tests/extmod/machine_timer.py | 6 ------ 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/docs/library/machine.Timer.rst b/docs/library/machine.Timer.rst index 69eea9d8d1f..2767bff6043 100644 --- a/docs/library/machine.Timer.rst +++ b/docs/library/machine.Timer.rst @@ -20,8 +20,7 @@ There are two types of Timer in MicroPython, but not all ports support both: - Virtual timers. These are managed in software, and are generally more flexible. Multiple virtual timers can be constructed and active at once. The - ``id`` of a virtual timer is ``-1``. Not all ports support virtual timers, but - it's recommended to use them when available. + ``id`` of a virtual timer is ``-1``. - Hardware timers. Hardware timers have integer ``id`` values starting at ``0``. The number of available ``id`` values is determined by the hardware. Hardware timers may be more accurate for very fine sub-millisecond timing (especially diff --git a/tests/extmod/machine_timer.py b/tests/extmod/machine_timer.py index c34741f7345..a8f33bfa030 100644 --- a/tests/extmod/machine_timer.py +++ b/tests/extmod/machine_timer.py @@ -19,15 +19,11 @@ # Hardware timers are only supported on the esp32 port SUPPORTS_HARDWARE_TIMERS = sys.platform == "esp32" -# Virtual timers are not supported on the esp32 port -SUPPORTS_VIRTUAL_TIMERS = sys.platform != "esp32" - # Hard IRQs are not supported on the esp32 port SUPPORTS_HARD_IRQ = sys.platform != "esp32" class Test(unittest.TestCase): - @unittest.skipUnless(SUPPORTS_VIRTUAL_TIMERS, "no virtual timers") def test_virtual_create(self): self._test_create(-1) self._test_create_multiple(-1, -1) @@ -37,12 +33,10 @@ def test_hardware_create(self): self._test_create(0) self._test_create_multiple(0, 1) - @unittest.skipUnless(SUPPORTS_VIRTUAL_TIMERS, "no virtual timers") def test_virtual_softirq(self): self._test_all_freq_period(-1, Timer.ONE_SHOT, False) self._test_all_freq_period(-1, Timer.PERIODIC, False) - @unittest.skipUnless(SUPPORTS_VIRTUAL_TIMERS, "no virtual timers") @unittest.skipUnless(SUPPORTS_HARD_IRQ, "no hard-irq support") def test_virtual_hardirq(self): self._test_all_freq_period(-1, Timer.ONE_SHOT, True) From c891536b5accf938211d19859af68ec587c88102 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Wed, 29 Apr 2026 13:31:24 +0200 Subject: [PATCH 425/635] esp32/machine_uart: Default to virtual timer for RXIDLE. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Daniël van de Giessen --- docs/esp32/quickref.rst | 3 +-- docs/library/machine.UART.rst | 3 +-- ports/esp32/machine_uart.c | 5 +++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/docs/esp32/quickref.rst b/docs/esp32/quickref.rst index b4961fd4ed4..d0662ea8763 100644 --- a/docs/esp32/quickref.rst +++ b/docs/esp32/quickref.rst @@ -284,8 +284,7 @@ with a timer ID of 0, 0 and 1, or from 0 to 3 (inclusive):: tim1 = Timer(1) tim1.init(period=2000, mode=Timer.PERIODIC, callback=lambda t:print(1)) -The period is in milliseconds. When using UART.IRQ_RXIDLE, timer 0 is needed for -the IRQ_RXIDLE mechanism and must not be used otherwise. +The period is in milliseconds. Timer callbacks are scheduled as soft interrupts on this port; hard callbacks are not implemented. Specifying ``hard=True`` will raise diff --git a/docs/library/machine.UART.rst b/docs/library/machine.UART.rst index fbad3fc5922..5be79cccce8 100644 --- a/docs/library/machine.UART.rst +++ b/docs/library/machine.UART.rst @@ -224,8 +224,7 @@ Methods .. note:: - - The ESP32 port does not support the option hard=True. It uses Timer(0) - for UART.IRQ_RXIDLE, so this timer cannot be used for other means. + - The ESP32 port does not support the option hard=True. - The rp2 port's UART.IRQ_TXIDLE is only triggered when the message is longer than 5 characters and the trigger happens when still 5 characters diff --git a/ports/esp32/machine_uart.c b/ports/esp32/machine_uart.c index 3f69b079093..cebbccc8de0 100644 --- a/ports/esp32/machine_uart.c +++ b/ports/esp32/machine_uart.c @@ -93,8 +93,9 @@ enum { RXIDLE_ALERT, }; -// RXIDLE irq feature uses this machine.Timer id -#define RXIDLE_TIMER_IDX 0 +// machine.Timer id used for RXIDLE IRQ. If a hardware timer it should not be +// used elsewhere (and thus also no more than one RXIDLE IRQ should be used). +#define RXIDLE_TIMER_IDX (-1) typedef struct _machine_uart_obj_t { mp_obj_base_t base; From ca8bcebded23adfd343dc5a4c67318d54842db79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Tue, 5 May 2026 14:20:36 +0200 Subject: [PATCH 426/635] esp32/build: Support building against IDFv5.4.3. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Daniël van de Giessen --- ports/esp32/network_wlan.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/esp32/network_wlan.c b/ports/esp32/network_wlan.c index a8a6f9bc509..a16b07ea0e7 100644 --- a/ports/esp32/network_wlan.c +++ b/ports/esp32/network_wlan.c @@ -817,7 +817,7 @@ static const mp_rom_map_elem_t wlan_if_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_SEC_WPA3_ENT), MP_ROM_INT(WIFI_AUTH_WPA3_ENTERPRISE) }, { MP_ROM_QSTR(MP_QSTR_SEC_WPA2_WPA3_ENT), MP_ROM_INT(WIFI_AUTH_WPA2_WPA3_ENTERPRISE) }, #endif - #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) + #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 3) { MP_ROM_QSTR(MP_QSTR_SEC_WPA_ENT), MP_ROM_INT(WIFI_AUTH_WPA_ENTERPRISE) }, #endif @@ -838,7 +838,7 @@ static const mp_rom_map_elem_t wlan_if_locals_dict_table[] = { }; static MP_DEFINE_CONST_DICT(wlan_if_locals_dict, wlan_if_locals_dict_table); -#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 3) _Static_assert(WIFI_AUTH_MAX == 17, "Synchronize WIFI_AUTH_XXX constants with the ESP-IDF. Look at esp-idf/components/esp_wifi/include/esp_wifi_types_generic.h"); #elif ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) _Static_assert(WIFI_AUTH_MAX == 16, "Synchronize WIFI_AUTH_XXX constants with the ESP-IDF. Look at esp-idf/components/esp_wifi/include/esp_wifi_types_generic.h"); From 833ad9f9c44f37b95f276eb593dcbd0fc2e14f4b Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Wed, 1 Jul 2026 09:58:51 +0200 Subject: [PATCH 427/635] esp32/machine_sdcard: Make default SPI pins board-configurable. The default pins for the primary SPI-mode SD card bus (slot 2) were hard-coded per chip, and the ESP32-S3 defaults (GPIO 35/36/37) clash with the octal SPIRAM bus, so they are unusable on many S3 boards. Add a machine_sdcard.h header defining MICROPY_HW_SDCARD_SPI_SCK, _MOSI, _MISO and _CS, following the existing per-peripheral pin-define convention (machine_i2c.h, machine_hw_spi.c). A board can override these in its mpconfigboard.h so that machine.SDCard(slot=2) works without passing pins. The defaults match the previous per-chip values, so behaviour is unchanged unless a board overrides them. SDMMC-mode pins (slots 0 and 1) are not affected. Signed-off-by: Pavel Revak --- ports/esp32/machine_sdcard.c | 37 +++++++++++++------------ ports/esp32/machine_sdcard.h | 53 ++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+), 18 deletions(-) create mode 100644 ports/esp32/machine_sdcard.h diff --git a/ports/esp32/machine_sdcard.c b/ports/esp32/machine_sdcard.c index 68e8a2b145a..1b1582a0913 100644 --- a/ports/esp32/machine_sdcard.c +++ b/ports/esp32/machine_sdcard.c @@ -44,6 +44,8 @@ #include "sdmmc_cmd.h" #include "esp_log.h" +#include "machine_sdcard.h" + #define DEBUG 0 #if DEBUG #define DEBUG_printf(...) ESP_LOGI("modsdcard", __VA_ARGS__) @@ -88,19 +90,10 @@ typedef struct _sdcard_obj_t { static const spi_bus_config_t spi_bus_defaults[NUM_SD_SPI_BUS] = { { - #if CONFIG_IDF_TARGET_ESP32 - .miso_io_num = GPIO_NUM_19, - .mosi_io_num = GPIO_NUM_23, - .sclk_io_num = GPIO_NUM_18, - #elif CONFIG_IDF_TARGET_ESP32S3 - .miso_io_num = GPIO_NUM_36, - .mosi_io_num = GPIO_NUM_35, - .sclk_io_num = GPIO_NUM_37, - #else - .miso_io_num = GPIO_NUM_NC, - .mosi_io_num = GPIO_NUM_NC, - .sclk_io_num = GPIO_NUM_NC, - #endif + // Primary SPI SD bus (slot 2): board-configurable via machine_sdcard.h. + .miso_io_num = MICROPY_HW_SDCARD_SPI_MISO, + .mosi_io_num = MICROPY_HW_SDCARD_SPI_MOSI, + .sclk_io_num = MICROPY_HW_SDCARD_SPI_SCK, .data2_io_num = GPIO_NUM_NC, .data3_io_num = GPIO_NUM_NC, .data4_io_num = GPIO_NUM_NC, @@ -139,16 +132,14 @@ static const uint8_t spi_dma_channel_defaults[NUM_SD_SPI_BUS] = { static const sdspi_device_config_t spi_dev_defaults[NUM_SD_SPI_BUS] = { #if NUM_SD_SPI_BUS > 1 { + // Primary SPI SD bus (slot 2): CS is board-configurable via + // machine_sdcard.h; host_id stays chip-specific. #if CONFIG_IDF_TARGET_ESP32 .host_id = VSPI_HOST, - .gpio_cs = GPIO_NUM_5, - #elif CONFIG_IDF_TARGET_ESP32S3 - .host_id = SPI3_HOST, - .gpio_cs = GPIO_NUM_34, #else .host_id = SPI3_HOST, - .gpio_cs = GPIO_NUM_NC, #endif + .gpio_cs = MICROPY_HW_SDCARD_SPI_CS, .gpio_cd = SDSPI_SLOT_NO_CD, .gpio_wp = SDSPI_SLOT_NO_WP, .gpio_int = SDSPI_SLOT_NO_INT, @@ -352,6 +343,16 @@ static mp_obj_t machine_sdcard_make_new(const mp_obj_type_t *type, size_t n_args #endif sdspi_device_config_t dev_config = spi_dev_defaults[slot_num]; + #if NUM_SD_SPI_BUS == 1 + // Single-bus chips use SDSPI_DEVICE_CONFIG_DEFAULT() for the only SPI SD + // bus (slot 2), which hard-codes its CS pin. If a board provides a + // default CS, apply it instead (keeping the IDF default otherwise). An + // explicit cs= argument still takes precedence below. + if (MICROPY_HW_SDCARD_SPI_CS != GPIO_NUM_NC) { + dev_config.gpio_cs = MICROPY_HW_SDCARD_SPI_CS; + } + #endif + SET_CONFIG_PIN(bus_config, miso_io_num, ARG_miso); SET_CONFIG_PIN(bus_config, mosi_io_num, ARG_mosi); SET_CONFIG_PIN(bus_config, sclk_io_num, ARG_sck); diff --git a/ports/esp32/machine_sdcard.h b/ports/esp32/machine_sdcard.h new file mode 100644 index 00000000000..e417cd04f33 --- /dev/null +++ b/ports/esp32/machine_sdcard.h @@ -0,0 +1,53 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Pavel Revak + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_ESP32_MACHINE_SDCARD_H +#define MICROPY_INCLUDED_ESP32_MACHINE_SDCARD_H + +// Default pins for the primary SPI-mode SD card bus (slot 2). SPI mode is +// available on every ESP32 variant, so a board may override these in its +// mpconfigboard.h to make machine.SDCard(slot=2) work without explicit pins. +// SDMMC-mode pins (slots 0/1) are not affected. +#ifndef MICROPY_HW_SDCARD_SPI_SCK +#if CONFIG_IDF_TARGET_ESP32 +#define MICROPY_HW_SDCARD_SPI_SCK (GPIO_NUM_18) +#define MICROPY_HW_SDCARD_SPI_MOSI (GPIO_NUM_23) +#define MICROPY_HW_SDCARD_SPI_MISO (GPIO_NUM_19) +#define MICROPY_HW_SDCARD_SPI_CS (GPIO_NUM_5) +#elif CONFIG_IDF_TARGET_ESP32S3 +#define MICROPY_HW_SDCARD_SPI_SCK (GPIO_NUM_37) +#define MICROPY_HW_SDCARD_SPI_MOSI (GPIO_NUM_35) +#define MICROPY_HW_SDCARD_SPI_MISO (GPIO_NUM_36) +#define MICROPY_HW_SDCARD_SPI_CS (GPIO_NUM_34) +#else +// Other chips have no historical default; a board or the runtime must assign. +#define MICROPY_HW_SDCARD_SPI_SCK (GPIO_NUM_NC) +#define MICROPY_HW_SDCARD_SPI_MOSI (GPIO_NUM_NC) +#define MICROPY_HW_SDCARD_SPI_MISO (GPIO_NUM_NC) +#define MICROPY_HW_SDCARD_SPI_CS (GPIO_NUM_NC) +#endif +#endif + +#endif // MICROPY_INCLUDED_ESP32_MACHINE_SDCARD_H From c808ad240fd18051243a9821d41de2fa79842d82 Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Wed, 1 Jul 2026 10:00:54 +0200 Subject: [PATCH 428/635] esp32/boards: Add default SD card SPI pins to boards with an SD slot. Define MICROPY_HW_SDCARD_SPI_* so that machine.SDCard(slot=2) works without explicit pins on boards that have an onboard microSD slot wired for SPI mode, where the pins differ from the chip default: - SEEED_XIAO_ESP32S3 (verified on hardware) - LILYGO_T3_S3 - LILYGO_TTGO_LORA32 - SPARKFUN_THINGPLUS_ESP32C5 The pins are taken from each board's definition or official documentation. Signed-off-by: Pavel Revak --- ports/esp32/boards/LILYGO_T3_S3/mpconfigboard.h | 6 ++++++ ports/esp32/boards/LILYGO_TTGO_LORA32/mpconfigboard.h | 6 ++++++ ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h | 6 ++++++ .../esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/ports/esp32/boards/LILYGO_T3_S3/mpconfigboard.h b/ports/esp32/boards/LILYGO_T3_S3/mpconfigboard.h index 73bbe8f5677..c6492215cf9 100644 --- a/ports/esp32/boards/LILYGO_T3_S3/mpconfigboard.h +++ b/ports/esp32/boards/LILYGO_T3_S3/mpconfigboard.h @@ -12,3 +12,9 @@ #define MICROPY_HW_SPI1_MOSI (6) #define MICROPY_HW_SPI1_MISO (3) #define MICROPY_HW_SPI1_SCK (5) + +// microSD card in SPI mode: machine.SDCard(slot=2). +#define MICROPY_HW_SDCARD_SPI_MOSI (11) +#define MICROPY_HW_SDCARD_SPI_MISO (2) +#define MICROPY_HW_SDCARD_SPI_SCK (14) +#define MICROPY_HW_SDCARD_SPI_CS (13) diff --git a/ports/esp32/boards/LILYGO_TTGO_LORA32/mpconfigboard.h b/ports/esp32/boards/LILYGO_TTGO_LORA32/mpconfigboard.h index 6be22dd0ffc..0c50edd9107 100644 --- a/ports/esp32/boards/LILYGO_TTGO_LORA32/mpconfigboard.h +++ b/ports/esp32/boards/LILYGO_TTGO_LORA32/mpconfigboard.h @@ -1,3 +1,9 @@ #define MICROPY_HW_BOARD_NAME "LILYGO TTGO LoRa32" #define MICROPY_HW_MCU_NAME "ESP32" #define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-ttgo-lora32" + +// microSD card in SPI mode: machine.SDCard(slot=2). +#define MICROPY_HW_SDCARD_SPI_MOSI (15) +#define MICROPY_HW_SDCARD_SPI_MISO (2) +#define MICROPY_HW_SDCARD_SPI_SCK (14) +#define MICROPY_HW_SDCARD_SPI_CS (13) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h b/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h index 94c8b534162..5376b6d840a 100644 --- a/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h +++ b/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h @@ -10,3 +10,9 @@ #define MICROPY_HW_SPI1_MOSI (9) #define MICROPY_HW_SPI1_MISO (8) #define MICROPY_HW_SPI1_SCK (7) + +// microSD (Sense expansion board) in SPI mode: machine.SDCard(slot=2). +#define MICROPY_HW_SDCARD_SPI_MOSI (9) +#define MICROPY_HW_SDCARD_SPI_MISO (8) +#define MICROPY_HW_SDCARD_SPI_SCK (7) +#define MICROPY_HW_SDCARD_SPI_CS (21) diff --git a/ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h b/ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h index 0da84f9920b..fb42d5a62c8 100644 --- a/ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h +++ b/ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.h @@ -9,3 +9,9 @@ #define MICROPY_HW_SPI1_SCK (10) #define MICROPY_HW_SPI1_MOSI (8) #define MICROPY_HW_SPI1_MISO (9) + +// microSD card in SPI mode (shares the SPI1 bus): machine.SDCard(slot=2). +#define MICROPY_HW_SDCARD_SPI_MOSI (8) +#define MICROPY_HW_SDCARD_SPI_MISO (9) +#define MICROPY_HW_SDCARD_SPI_SCK (10) +#define MICROPY_HW_SDCARD_SPI_CS (25) From 8c8623296fc66d6a0e2c42a4cdd01234457a7385 Mon Sep 17 00:00:00 2001 From: Jim Lipsey Date: Mon, 1 Apr 2024 11:58:58 -0500 Subject: [PATCH 429/635] stm32/boards/ARDUINO_PORTENTA_H7: Add high-density pin names. Changes made to pins.csv: - Added board designations for the high-density connectors. Signed-off-by: Jim Lipsey Signed-off-by: Damien George --- .../stm32/boards/ARDUINO_PORTENTA_H7/pins.csv | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/ports/stm32/boards/ARDUINO_PORTENTA_H7/pins.csv b/ports/stm32/boards/ARDUINO_PORTENTA_H7/pins.csv index da2bed78c69..38bd47e05ab 100644 --- a/ports/stm32/boards/ARDUINO_PORTENTA_H7/pins.csv +++ b/ports/stm32/boards/ARDUINO_PORTENTA_H7/pins.csv @@ -167,6 +167,89 @@ PK5,PK5 PK6,PK6 PK7,PK7 +# High Density Connectors +J1_26,PA12 +J1_28,PA11 +J1_33,PA9 +J1_34,PA0 +J1_35,PA10 +J1_36,PI9 +J1_37,PI14 +J1_38,PI10 +J1_39,PI15 +J1_40,PI13 +J1_43,PB7 +J1_44,PH8 +J1_45,PB6 +J1_46,PH7 +J1_49,PH13 +J1_51,PB8 +J1_55,PD6 +J1_56,PD3 +J1_57,PD7 +J1_58,PB9 +J1_59,PB14 +J1_60,PI2 +J1_61,PB15 +J1_62,PI3 +J1_63,PB3 +J1_65,PB4 +J1_66,PE2 +J1_68,PB2 +J1_75,PA13 +J1_77,PA14 +J1_79,PB3 +J2_2,PI7 +J2_3,PI8 +J2_4,PI6 +J2_6,PI4 +J2_8,PH14 +J2_10,PH12 +J2_12,PH11 +J2_14,PH10 +J2_16,PH9 +J2_18,PI5 +J2_20,PA6 +J2_22,PA4 +J2_25,PJ8 +J2_26,PG14 +J2_27,PH9 +J2_28,PG9 +J2_36,PI0 +J2_38,PI1 +J2_40,PC2 +J2_42,PC3 +J2_45,PH12 +J2_46,PC13 +J2_47,PH11 +J2_48,PC15 +J2_49,PI5 +J2_50,PD4 +J2_51,PI7 +J2_52,PD5 +J2_53,PI6 +J2_54,PE3 +J2_56,PG3 +J2_58,PG10 +J2_59,PA8 +J2_60,PK1 +J2_61,PC6 +J2_62,PH15 +J2_63,PC7 +J2_64,PJ7 +J2_65,PG7 +J2_66,PJ10 +J2_67,PJ11 +J2_68,PH6 +J2_73,PA0 +J2_74,PC2 +J2_75,PA1 +J2_76,PC3 +J2_77,PC2 +J2_78,PA4 +J2_79,PC3 +J2_80,PA6 + # Arduino Digital Pins D0,PH15 D1,PK1 From 501fb912cb9c92b898fbf4d9fb6e6a4bb9a58687 Mon Sep 17 00:00:00 2001 From: Yuuki NAGAO Date: Sat, 2 Aug 2025 22:09:55 +0900 Subject: [PATCH 430/635] stm32/octospi: Add memory-mapped feature to OCTOSPI. To be able to use OCTOSPI as memory-mapped, it is possible to implement in the same as QUADSPI. Signed-off-by: Yuuki NAGAO --- ports/stm32/mpu.h | 3 + ports/stm32/octospi.c | 142 ++++++++++++++++++++++++++++++++++-- ports/stm32/octospi.h | 11 +++ ports/stm32/vfs_rom_ioctl.c | 24 ++++++ 4 files changed, 174 insertions(+), 6 deletions(-) diff --git a/ports/stm32/mpu.h b/ports/stm32/mpu.h index 1d43e87f8d7..a268d3a364d 100644 --- a/ports/stm32/mpu.h +++ b/ports/stm32/mpu.h @@ -34,6 +34,9 @@ #define MPU_REGION_QSPI1 (MPU_REGION_NUMBER1) #define MPU_REGION_QSPI2 (MPU_REGION_NUMBER2) #define MPU_REGION_QSPI3 (MPU_REGION_NUMBER3) +#define MPU_REGION_OSPI1 (MPU_REGION_NUMBER1) +#define MPU_REGION_OSPI2 (MPU_REGION_NUMBER2) +#define MPU_REGION_OSPI3 (MPU_REGION_NUMBER3) #define MPU_REGION_SDRAM1 (MPU_REGION_NUMBER4) #define MPU_REGION_SDRAM2 (MPU_REGION_NUMBER5) diff --git a/ports/stm32/octospi.c b/ports/stm32/octospi.c index 861941325c6..ea400089de1 100644 --- a/ports/stm32/octospi.c +++ b/ports/stm32/octospi.c @@ -30,8 +30,10 @@ #include "py/mperrno.h" #include "py/mphal.h" +#include "mpu.h" #include "octospi.h" #include "pin_static_af.h" +#include "storage.h" #if defined(MICROPY_HW_OSPIFLASH_SIZE_BITS_LOG2) @@ -43,7 +45,70 @@ #define MICROPY_HW_OSPI_CS_HIGH_CYCLES (2) // nCS stays high for 2 cycles #endif +// Region size in units of 1024*1024 bytes. +#ifndef MICROPY_HW_SPI_MPU_REGION_SIZE +#define MICROPY_HW_OSPI_MPU_REGION_SIZE ((1 << (MICROPY_HW_OSPIFLASH_SIZE_BITS_LOG2 - 3)) >> 20) +#endif + +static inline void octospi_mpu_disable_all(void) { + #if defined(STM32H5) + // TODO: for STM32H5 implementation. + #else + // Configure MPU to disable access to entire QSPI region, to prevent CPU + // speculative execution from accessing this region and modifying QSPI registers. + uint32_t irq_state = mpu_config_start(); + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x00, MPU_REGION_SIZE_256MB)); + mpu_config_end(irq_state); + #endif +} + +static inline void octospi_mpu_enable_mapped(void) { + #if defined(STM32H5) + // TODO: for STM32H5 implementation. + #else + // Configure MPU to allow access to only the valid part of external SPI flash. + // The memory accesses to the mapped OctoSPI are faster if the MPU is not used + // for the memory-mapped region, so 3 MPU regions are used to disable access + // to everything except the valid address space, using holes in the bottom + // of the regions and nesting them. + // Note: Disabling a subregion (by setting its corresponding SRD bit to 1) + // means another region overlapping the disabled range matches instead. If no + // other enabled region overlaps the disabled subregion, and the access is + // unprivileged or the background region is disabled, the MPU issues a fault. + uint32_t irq_state = mpu_config_start(); + if (MICROPY_HW_OSPI_MPU_REGION_SIZE > 128) { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0xFF, MPU_REGION_SIZE_256MB)); + } else if (MICROPY_HW_OSPI_MPU_REGION_SIZE > 64) { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_256MB)); + } else if (MICROPY_HW_OSPI_MPU_REGION_SIZE > 32) { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_256MB)); + } else if (MICROPY_HW_OSPI_MPU_REGION_SIZE > 16) { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + } else if (MICROPY_HW_OSPI_MPU_REGION_SIZE > 8) { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_OSPI2, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_32MB)); + } else if (MICROPY_HW_OSPI_MPU_REGION_SIZE > 4) { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_OSPI2, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_32MB)); + } else if (MICROPY_HW_OSPI_MPU_REGION_SIZE > 2) { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_OSPI2, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_32MB)); + } else if (MICROPY_HW_OSPI_MPU_REGION_SIZE > 1) { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_OSPI2, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_32MB)); + mpu_config_region(MPU_REGION_OSPI3, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_16MB)); + } else { + mpu_config_region(MPU_REGION_OSPI1, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_OSPI2, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_32MB)); + mpu_config_region(MPU_REGION_OSPI3, OCTOSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_4MB)); + } + mpu_config_end(irq_state); + #endif +} + void octospi_init(void) { + octospi_mpu_disable_all(); + // Configure OCTOSPI pins (allows 1, 2, 4 or 8 line configuration). #if defined(STM32H7) #define STATIC_AF_OCTOSPI(signal) STATIC_AF_OCTOSPIM_P1_##signal @@ -105,6 +170,63 @@ void octospi_init(void) { OCTOSPI1->CR |= OCTOSPI_CR_EN; } +void octospi_memory_map(void) { + // Enable memory-mapped mode + + // Work out command to use for reads, based on size of the memory. + uint8_t cmd; + uint8_t adsize; + if ((MICROPY_HW_OSPIFLASH_SIZE_BITS_LOG2 - 3 - 1) >= 24) { + cmd = 0xec; + adsize = 3; + } else { + cmd = 0xeb; + adsize = 2; + } + + OCTOSPI1->ABR = 0; // disable continuous read mode + + OCTOSPI1->CCR = + 0 << OCTOSPI_CCR_DQSE_Pos + | 0 << OCTOSPI_CCR_SIOO_Pos // send instruction every transaction + | 3 << OCTOSPI_CCR_DMODE_Pos // data on 4 lines + | 0 << OCTOSPI_CCR_ABSIZE_Pos // 8-bit alternate byte + | 3 << OCTOSPI_CCR_ABMODE_Pos // alternate byte on 4 lines + | adsize << OCTOSPI_CCR_ADSIZE_Pos + | 3 << OCTOSPI_CCR_ADMODE_Pos // address on 4 lines + | 1 << OCTOSPI_CCR_IMODE_Pos // instruction on 1 line + ; + + OCTOSPI1->TCR = + 4 << OCTOSPI_TCR_DCYC_Pos + | 1 << OCTOSPI_TCR_SSHIFT_Pos + | 0 << OCTOSPI_TCR_DHQC_Pos + ; + + OCTOSPI1->IR = cmd; + + // Enter memory map mode. + OCTOSPI1->CR |= OCTOSPI_CR_FMODE; + octospi_mpu_enable_mapped(); +} + +void octospi_memory_map_exit(void) { + // Prevent access to QSPI memory-mapped region. + octospi_mpu_disable_all(); + + // Abort any ongoing transfer if peripheral is busy. + if (OCTOSPI1->SR & OCTOSPI_SR_BUSY) { + OCTOSPI1->CR |= OCTOSPI_CR_ABORT; + while (OCTOSPI1->CR & OCTOSPI_CR_ABORT) { + } + } +} + +void octospi_memory_map_restart(void) { + octospi_memory_map_exit(); + octospi_memory_map(); +} + static int octospi_ioctl(void *self_in, uint32_t cmd, uintptr_t arg) { (void)self_in; (void)arg; @@ -113,15 +235,23 @@ static int octospi_ioctl(void *self_in, uint32_t cmd, uintptr_t arg) { octospi_init(); break; case MP_QSPI_IOCTL_BUS_ACQUIRE: - // Abort any ongoing transfer if peripheral is busy. - if (OCTOSPI1->SR & OCTOSPI_SR_BUSY) { - OCTOSPI1->CR |= OCTOSPI_CR_ABORT; - while (OCTOSPI1->CR & OCTOSPI_CR_ABORT) { - } - } + // Disable memory-mapped region during bus access + octospi_memory_map_exit(); break; case MP_QSPI_IOCTL_BUS_RELEASE: + // Switch to memory-map mode when bus is idle + octospi_memory_map(); break; + case MP_QSPI_IOCTL_MEMORY_MODIFIED: { + #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + uintptr_t *addr_len = (uintptr_t *)arg; + volatile void *addr = (volatile void *)(OCTOSPI_MAP_ADDR + addr_len[0]); + size_t len = addr_len[1]; + SCB_InvalidateICache_by_Addr(addr, len); + SCB_InvalidateDCache_by_Addr(addr, len); + #endif + break; + } } return 0; // success } diff --git a/ports/stm32/octospi.h b/ports/stm32/octospi.h index 3ef4b8206fa..22c91854b47 100644 --- a/ports/stm32/octospi.h +++ b/ports/stm32/octospi.h @@ -28,6 +28,17 @@ #include "drivers/bus/qspi.h" +#define OCTOSPI_MAP_ADDR (0x90000000) +#define OCTOSPI_MAP_ADDR_MAX (0xa0000000) + extern const mp_qspi_proto_t octospi_proto; +void octospi_memory_map(void); +void octospi_memory_map_exit(void); +void octospi_memory_map_restart(void); + +static inline bool octospi_is_valid_addr(uint32_t addr) { + return OCTOSPI_MAP_ADDR <= addr && addr < OCTOSPI_MAP_ADDR_MAX; +} + #endif // MICROPY_INCLUDED_STM32_OCTOSPI_H diff --git a/ports/stm32/vfs_rom_ioctl.c b/ports/stm32/vfs_rom_ioctl.c index 5dbc855861d..480924b0105 100644 --- a/ports/stm32/vfs_rom_ioctl.c +++ b/ports/stm32/vfs_rom_ioctl.c @@ -32,6 +32,7 @@ #include "flash.h" #include "qspi.h" +#include "octospi.h" #include "storage.h" #include "xspi.h" @@ -144,6 +145,21 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { } #endif + #if MICROPY_HW_ROMFS_ENABLE_EXTERNAL_OSPI + if (octospi_is_valid_addr(dest)) { + dest -= OCTOSPI_MAP_ADDR; + dest_max -= OCTOSPI_MAP_ADDR; + while (dest < dest_max) { + int ret = mp_spiflash_erase_block(MICROPY_HW_ROMFS_OSPI_SPIFLASH_OBJ, dest); + if (ret < 0) { + return MP_OBJ_NEW_SMALL_INT(ret); + } + dest += MP_SPIFLASH_ERASE_BLOCK_SIZE; + } + return MP_OBJ_NEW_SMALL_INT(4); + } + #endif + #if MICROPY_HW_ROMFS_ENABLE_EXTERNAL_XSPI if (xspi_is_valid_addr(&xspi_flash2, dest)) { dest -= xspi_get_xip_base(&xspi_flash2); @@ -184,6 +200,14 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { } #endif + #if MICROPY_HW_ROMFS_ENABLE_EXTERNAL_OSPI + if (octospi_is_valid_addr(dest)) { + dest -= OCTOSPI_MAP_ADDR; + int ret = mp_spiflash_write(MICROPY_HW_ROMFS_OSPI_SPIFLASH_OBJ, dest, bufinfo.len, bufinfo.buf); + return MP_OBJ_NEW_SMALL_INT(ret); + } + #endif + #if MICROPY_HW_ROMFS_ENABLE_EXTERNAL_XSPI if (xspi_is_valid_addr(&xspi_flash2, dest)) { dest -= xspi_get_xip_base(&xspi_flash2); From af2c47965b4b385d007f1c4ec7cc091c23408099 Mon Sep 17 00:00:00 2001 From: Yuuki NAGAO Date: Sun, 3 Aug 2025 00:55:02 +0900 Subject: [PATCH 431/635] stm32/rng: Add retry process for RNG. In some case, getting random number from RNG fails. This can recover by issuing soft reset RNG. Signed-off-by: Yuuki NAGAO --- ports/stm32/rng.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/ports/stm32/rng.c b/ports/stm32/rng.c index 400e1bd16da..5f9bf1448df 100644 --- a/ports/stm32/rng.c +++ b/ports/stm32/rng.c @@ -31,6 +31,7 @@ #if MICROPY_HW_ENABLE_RNG #define RNG_TIMEOUT_MS (10) +#define RNG_RETRY_MAX_COUNT (10) uint32_t rng_get(void) { // Enable the RNG peripheral if it's not already enabled @@ -46,9 +47,23 @@ uint32_t rng_get(void) { // Wait for a new random number to be ready, takes on the order of 10us uint32_t start = HAL_GetTick(); + #if defined(RNG_CR_CONDRST) + uint8_t retry_count = 0; + #endif while (!(RNG->SR & RNG_SR_DRDY)) { if (HAL_GetTick() - start >= RNG_TIMEOUT_MS) { + #if defined(RNG_CR_CONDRST) + if (retry_count > RNG_RETRY_MAX_COUNT) { + return 0; + } + // Reset and retry waiting RNG_SR_DRDY. + RNG->CR |= RNG_CR_CONDRST; + RNG->CR = (RNG->CR & ~RNG_CR_CONDRST); + start = HAL_GetTick(); + retry_count++; + #else return 0; + #endif } } From f6b148acde1a201e2ff61589255fb6f040924b32 Mon Sep 17 00:00:00 2001 From: Yuuki NAGAO Date: Sat, 2 Aug 2025 22:09:48 +0900 Subject: [PATCH 432/635] stm32/boards/WEACTSTUDIO_MINI_STM32H723: Add WeAct H723VG board support. This change adds WeAct STM32H723 Core Board support to the STM32 port. WeAct STM32H723 Core Board: https://github.com/WeActStudio/WeActStudio.MiniSTM32H723 This board uses STM32H723VG: https://www.st.com/en/microcontrollers-microprocessors/stm32h723vg.html Uses OctoSPI and has ROMFS feature. Signed-off-by: Yuuki NAGAO --- .../boards/WEACTSTUDIO_MINI_STM32H723/bdev.c | 47 +++++ .../WEACTSTUDIO_MINI_STM32H723/board.json | 13 ++ .../WEACTSTUDIO_MINI_STM32H723/board_init.c | 16 ++ .../WEACTSTUDIO_MINI_STM32H723/deploy.md | 19 ++ .../WEACTSTUDIO_MINI_STM32H723/manifest.py | 4 + .../mpconfigboard.h | 170 ++++++++++++++++++ .../mpconfigboard.mk | 23 +++ .../WEACTSTUDIO_MINI_STM32H723/pins.csv | 106 +++++++++++ .../stm32h7xx_hal_conf.h | 19 ++ .../weact_stm32h723.ld | 33 ++++ 10 files changed, 450 insertions(+) create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/bdev.c create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/board.json create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/board_init.c create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/deploy.md create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/manifest.py create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/mpconfigboard.h create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/mpconfigboard.mk create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/pins.csv create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/stm32h7xx_hal_conf.h create mode 100644 ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/weact_stm32h723.ld diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/bdev.c b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/bdev.c new file mode 100644 index 00000000000..c9a2c7380f2 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/bdev.c @@ -0,0 +1,47 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2019 Damien P. George + */ + +#include "storage.h" +#include "spi.h" +#include "octospi.h" +#include "py/mpconfig.h" + +static const spi_proto_cfg_t spi_bus = { + .spi = &spi_obj[0], // SPI1 + .baudrate = 25000000, + .polarity = 0, + .phase = 0, + .bits = 8, + .firstbit = SPI_FIRSTBIT_MSB, +}; + +#if MICROPY_HW_SPIFLASH_ENABLE_CACHE +static mp_spiflash_cache_t spi_bdev_cache; +#endif + +const mp_spiflash_config_t spiflash_config = { + .bus_kind = MP_SPIFLASH_BUS_SPI, + .bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS, + + .bus.u_spi.data = (void *)&spi_bus, + .bus.u_spi.proto = &spi_proto, + #if MICROPY_HW_SPIFLASH_ENABLE_CACHE + .cache = &spi_bdev_cache, + #endif +}; + +spi_bdev_t spi_bdev; + +// Second external SPI flash uses hardware QSPI interface +const mp_spiflash_config_t spiflash2_config = { + .bus_kind = MP_SPIFLASH_BUS_QSPI, + .bus.u_qspi.data = NULL, + .bus.u_qspi.proto = &octospi_proto, + #if MICROPY_HW_SPIFLASH_ENABLE_CACHE + .cache = &spi_bdev_cache, + #endif +}; + +spi_bdev_t spi_bdev2; diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/board.json b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/board.json new file mode 100644 index 00000000000..da84931aae8 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/board.json @@ -0,0 +1,13 @@ +{ + "deploy": [ + "deploy.md" + ], + "features": ["External Flash", "DAC", "Display","microSD", "USB", "USB-C"], + "images": [ + "weact_stm32h723.jpg" + ], + "mcu": "stm32h7", + "product": "Mini STM32H723", + "url": "https://github.com/WeActStudio/WeActStudio.MiniSTM32H723", + "vendor": "WeAct Studio" +} diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/board_init.c b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/board_init.c new file mode 100644 index 00000000000..0adf04982c8 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/board_init.c @@ -0,0 +1,16 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2019 Damien P. George + */ + +#include "py/mphal.h" +#include "storage.h" + +void WeAct_Core_early_init(void) { + // Turn off the USB switch. + mp_hal_pin_output(pyb_pin_OTG_FS_POWER); + mp_hal_pin_low(pyb_pin_OTG_FS_POWER); + + // Explicitly init SPI2 because it's not enabled as a block device + spi_bdev_ioctl(&spi_bdev2, BDEV_IOCTL_INIT, (uint32_t)&spiflash2_config); +} diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/deploy.md b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/deploy.md new file mode 100644 index 00000000000..a4572bfe306 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/deploy.md @@ -0,0 +1,19 @@ +### WeAct Studio STM32H7xx + +WeAct Studio make a number of STM32H7xx-based boards, they can all be updated +using +[DFU](https://en.wikipedia.org/wiki/USB?useskin=vector#Device_Firmware_Upgrade_mechanism). + +### DFU update + +Hold the Boot button - the middle of the cluster of three buttons - while the +board is reset (either by connecting USB or by pressing reset). Release the Boot +button shortly after the board has reset. The board ought to now be in DFU mode +and detectable as such from a connected computer. + +Use a tool like [`dfu-util`](https://dfu-util.sourceforge.net/) to update the +firmware: + +```bash +dfu-util --alt 0 -D firmware.dfu +``` diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/manifest.py b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/manifest.py new file mode 100644 index 00000000000..7d163e18479 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/manifest.py @@ -0,0 +1,4 @@ +include("$(PORT_DIR)/boards/manifest.py") + +# Currently this file is a placeholder. +# It would be good to extend to add an LCD driver. diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/mpconfigboard.h b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/mpconfigboard.h new file mode 100644 index 00000000000..db84e3f6ec1 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/mpconfigboard.h @@ -0,0 +1,170 @@ +#define MICROPY_HW_BOARD_NAME "WEACTSTUDIO_MINI_STM32H723" +#define MICROPY_HW_MCU_NAME "STM32H723VGT6" + +#define MICROPY_FATFS_EXFAT (1) +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_ENABLE_RNG (1) +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_ENABLE_DAC (1) +#define MICROPY_HW_ENABLE_USB (1) +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_SERVO (1) +#define MICROPY_HW_ENABLE_TIMER (1) +#define MICROPY_HW_ENABLE_SDCARD (1) +#define MICROPY_HW_ENABLE_MMCARD (0) + +// ROMFS config +#define MICROPY_VFS_ROM (1) +#define MICROPY_VFS_ROM_IOCTL (1) +#define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_OSPI (1) +#define MICROPY_HW_ROMFS_OSPI_SPIFLASH_OBJ (&spi_bdev2.spiflash) +#define MICROPY_HW_ROMFS_ENABLE_PART0 (1) + +// Flash storage config +#define MICROPY_HW_SPIFLASH_ENABLE_CACHE (1) +// Disable internal filesystem to use spiflash. +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0) + +// W25Q64 for storage +#define MICROPY_HW_SPIFLASH_SIZE_BYTES (8 * 1024 * 1024) + +// SPI flash #1, for R/W storage +#define MICROPY_HW_SPIFLASH_CS (pin_D6) +#define MICROPY_HW_SPIFLASH_SCK (pin_B3) +#define MICROPY_HW_SPIFLASH_MOSI (pin_D7) +#define MICROPY_HW_SPIFLASH_MISO (pin_B4) + +// External SPI Flash configuration +#define MICROPY_HW_SPI_IS_RESERVED(id) (id == 1) + +// SPI flash #1, block device config +extern const struct _mp_spiflash_config_t spiflash_config; +extern struct _spi_bdev_t spi_bdev; + +#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev) +#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config) +#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (MICROPY_HW_SPIFLASH_SIZE_BITS / 8) +#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol +#define MICROPY_HW_SPIFLASH_SIZE_BITS (MICROPY_HW_SPIFLASH_SIZE_BYTES * 8) + +// SPI flash #2, to be memory mapped +#define MICROPY_HW_OSPI_PRESCALER (3) // 120 MHz +#define MICROPY_HW_OSPIFLASH_SIZE_BITS_LOG2 (23) // 64Mbit +#define MICROPY_HW_OSPIFLASH_CS (pin_B6) +#define MICROPY_HW_OSPIFLASH_SCK (pin_B2) +#define MICROPY_HW_OSPIFLASH_IO0 (pin_D11) +#define MICROPY_HW_OSPIFLASH_IO1 (pin_D12) +#define MICROPY_HW_OSPIFLASH_IO2 (pin_E2) +#define MICROPY_HW_OSPIFLASH_IO3 (pin_D13) + +// SPI flash #2, block device config +extern const struct _mp_spiflash_config_t spiflash2_config; +extern struct _spi_bdev_t spi_bdev2; + +#define MICROPY_BOARD_EARLY_INIT WeAct_Core_early_init + +// This board has 25MHz HSE. +// The following gives a 550MHz CPU speed. +#define MICROPY_HW_CLK_USE_HSE (1) +#define MICROPY_HW_CLK_PLLM (5) +#define MICROPY_HW_CLK_PLLN (110) +#define MICROPY_HW_CLK_PLLP (1) +#define MICROPY_HW_CLK_PLLQ (5) +#define MICROPY_HW_CLK_PLLR (2) +#define MICROPY_HW_CLK_PLLVCI (RCC_PLL1VCIRANGE_2) +#define MICROPY_HW_CLK_PLLVCO (RCC_PLL1VCOWIDE) +#define MICROPY_HW_CLK_PLLFRAC (0) + +// The USB clock is set using PLL3 +#define MICROPY_HW_CLK_PLL3M (5) +#define MICROPY_HW_CLK_PLL3N (96) +#define MICROPY_HW_CLK_PLL3P (10) +#define MICROPY_HW_CLK_PLL3Q (10) +#define MICROPY_HW_CLK_PLL3R (2) +#define MICROPY_HW_CLK_PLL3VCI (RCC_PLL3VCIRANGE_2) +#define MICROPY_HW_CLK_PLL3VCO (RCC_PLL3VCOWIDE) +#define MICROPY_HW_CLK_PLL3FRAC (0) + +#define MICROPY_HW_RCC_OSPI_CLKSOURCE (RCC_OSPICLKSOURCE_D1HCLK) + +// 3 wait states +#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_3 + +// The board has an external 32kHz crystal attached +#define MICROPY_HW_RTC_USE_LSE (1) + +// UART config +#define MICROPY_HW_UART1_TX (pin_B14) +#define MICROPY_HW_UART1_RX (pin_B15) +#define MICROPY_HW_UART2_TX (pin_D5) +#define MICROPY_HW_UART2_RX (pin_D6) +#define MICROPY_HW_UART2_RTS (pin_D4) +#define MICROPY_HW_UART2_CTS (pin_D3) +#define MICROPY_HW_UART3_TX (pin_D8) +#define MICROPY_HW_UART3_RX (pin_D9) +#define MICROPY_HW_UART5_TX (pin_B6) +#define MICROPY_HW_UART5_RX (pin_B12) +#define MICROPY_HW_UART6_TX (pin_C6) +#define MICROPY_HW_UART6_RX (pin_C7) +#define MICROPY_HW_UART7_TX (pin_E8) +#define MICROPY_HW_UART7_RX (pin_E7) +#define MICROPY_HW_UART8_TX (pin_E1) +#define MICROPY_HW_UART8_RX (pin_E0) + +// I2C buses +#define MICROPY_HW_I2C1_SCL (pin_B8) +#define MICROPY_HW_I2C1_SDA (pin_B9) +#define MICROPY_HW_I2C2_SCL (pin_B10) +#define MICROPY_HW_I2C2_SDA (pin_B11) +#define MICROPY_HW_I2C4_SCL (pin_D12) +#define MICROPY_HW_I2C4_SDA (pin_D13) + +// SPI buses +// NOTE: SPI1 is used for the SPI flash. +#define MICROPY_HW_SPI1_NSS (pin_D6) +#define MICROPY_HW_SPI1_SCK (pin_B3) +#define MICROPY_HW_SPI1_MISO (pin_B4) +#define MICROPY_HW_SPI1_MOSI (pin_D7) + +#define MICROPY_HW_SPI2_NSS (pin_B12) +#define MICROPY_HW_SPI2_SCK (pin_B13) +#define MICROPY_HW_SPI2_MISO (pin_B14) +#define MICROPY_HW_SPI2_MOSI (pin_B15) +// NOTE: SPI3 is used for the QSPI flash. +#define MICROPY_HW_SPI3_NSS (pin_A4) +#define MICROPY_HW_SPI3_SCK (pin_B3) +#define MICROPY_HW_SPI3_MISO (pin_B4) +#define MICROPY_HW_SPI3_MOSI (pin_B5) +// NOTE: SPI4 is used for the ST7735 LCD. +#define MICROPY_HW_SPI4_NSS (pin_E11) +#define MICROPY_HW_SPI4_SCK (pin_E12) +#define MICROPY_HW_SPI4_MISO (pin_E13) +#define MICROPY_HW_SPI4_MOSI (pin_E14) + +// USRSW is pulled low. Pressing the button makes the input go high. +#define MICROPY_HW_USRSW_PIN (pin_C13) +#define MICROPY_HW_USRSW_PULL (GPIO_PULLDOWN) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING) +#define MICROPY_HW_USRSW_PRESSED (1) + +// LEDs +#define MICROPY_HW_LED1 (pin_E3) // blue +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin)) +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin)) + +// FDCAN bus +#define MICROPY_HW_CAN1_NAME "FDCAN1" +#define MICROPY_HW_CAN1_TX (pin_D1) +#define MICROPY_HW_CAN1_RX (pin_D0) + +// SD card detect switch +#define MICROPY_HW_SDCARD_DETECT_PIN (pin_D4) +#define MICROPY_HW_SDCARD_DETECT_PULL (GPIO_PULLUP) +#define MICROPY_HW_SDCARD_DETECT_PRESENT (GPIO_PIN_SET) + +// USB config +#define MICROPY_HW_USB_HS (1) +#define MICROPY_HW_USB_HS_IN_FS (1) + +void WeAct_Core_early_init(void); diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/mpconfigboard.mk b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/mpconfigboard.mk new file mode 100644 index 00000000000..2cdbb378651 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/mpconfigboard.mk @@ -0,0 +1,23 @@ +USE_MBOOT ?= 0 + +# MCU settings +MCU_SERIES = h7 +CMSIS_MCU = STM32H723xx +MICROPY_FLOAT_IMPL = double +AF_FILE = boards/stm32h723_af.csv + +ifeq ($(USE_MBOOT),1) +# When using Mboot everything goes after the bootloader +LD_FILES = boards/stm32h723.ld boards/common_bl.ld +TEXT0_ADDR = 0x08020000 +else +# When not using Mboot everything goes at the start of flash +LD_FILES = boards/WEACTSTUDIO_MINI_STM32H723/weact_stm32h723.ld boards/common_basic.ld +#LD_FILES = boards/stm32h723.ld boards/common_basic.ld +TEXT0_ADDR = 0x08000000 +endif + +# MicroPython settings +MICROPY_VFS_LFS2 = 1 + +FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/pins.csv b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/pins.csv new file mode 100644 index 00000000000..763677c8766 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/pins.csv @@ -0,0 +1,106 @@ +A0,PA0 +A1,PA1 +A2,PA2 +A3,PA3 +A4,PA4 +A5,PA5 +A6,PA6 +A7,PA7 +A8,PA8 +A9,PA9 +A10,PA10 +A11,PA11 +A12,PA12 +A15,PA15 +B0,PB0 +B1,PB1 +B2,PB2 +B3,PB3 +B4,PB4 +B5,PB5 +B6,PB6 +B7,PB7 +B8,PB8 +B9,PB9 +B10,PB10 +B11,PB11 +B12,PB12 +B13,PB13 +B14,PB14 +B15,PB15 +C0,PC0 +C1,PC1 +C2,PC2 +C3,PC3 +C4,PC4 +C5,PC5 +C6,PC6 +C7,PC7 +C8,PC8 +C9,PC9 +C10,PC10 +C11,PC11 +C12,PC12 +C13,PC13 +D0,PD0 +D1,PD1 +D2,PD2 +D3,PD3 +D4,PD4 +D5,PD5 +D6,PD6 +D7,PD7 +D8,PD8 +D9,PD9 +D10,PD10 +D11,PD11 +D12,PD12 +D13,PD13 +D14,PD14 +D15,PD15 +E0,PE0 +E1,PE1 +E2,PE2 +E3,PE3 +E4,PE4 +E5,PE5 +E6,PE6 +E7,PE7 +E8,PE8 +E9,PE9 +E10,PE10 +E11,PE11 +E11,PE11 +E12,PE12 +E13,PE13 +E14,PE14 +E15,PE15 +LED_BLUE,PE3 +KEY_1,PC13 +QSPI_CS,PB6 +QSPI_CLK,PB2 +QSPI_D0,PD11 +QSPI_D1,PD12 +QSPI_D2,PE2 +QSPI_D3,PD13 +USB_DM,PA11 +USB_DP,PA12 +OSC32_IN,PC14 +OSC32_OUT,PC15 +SDIO_D0,PC8 +SDIO_D1,PC9 +SDIO_D2,PC10 +SDIO_D3,PC11 +SDIO_CMD,PD2 +SDIO_CK,PC12 +SD_SW,PD4 +OTG_FS_POWER,PD10 +OTG_FS_OVER_CURRENT,PG7 +USB_VBUS,PA9 +USB_ID,PA10 +-XSPIM_P2_CS,PB6 +-XSPIM_P2_IO0,PD11 +-XSPIM_P2_IO1,PD12 +-XSPIM_P2_IO2,PE2 +-XSPIM_P2_IO3,PD13 +-XSPIM_P2_SCK,PB2 diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/stm32h7xx_hal_conf.h b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/stm32h7xx_hal_conf.h new file mode 100644 index 00000000000..c8f60c56055 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/stm32h7xx_hal_conf.h @@ -0,0 +1,19 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2019 Damien P. George + */ +#ifndef MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H +#define MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H + +// Oscillator values in Hz +#define HSE_VALUE (25000000) +#define LSE_VALUE (32768) +#define EXTERNAL_CLOCK_VALUE (12288000) + +// Oscillator timeouts in ms +#define HSE_STARTUP_TIMEOUT (5000) +#define LSE_STARTUP_TIMEOUT (5000) + +#include "boards/stm32h7xx_hal_conf_base.h" + +#endif // MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H diff --git a/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/weact_stm32h723.ld b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/weact_stm32h723.ld new file mode 100644 index 00000000000..e8708c228a8 --- /dev/null +++ b/ports/stm32/boards/WEACTSTUDIO_MINI_STM32H723/weact_stm32h723.ld @@ -0,0 +1,33 @@ +/* + GNU linker script for WeAct Studio STM32H723 +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* sectors 0-7 */ + FLASH_APP (rx) : ORIGIN = 0x08020000, LENGTH = 896K /* sectors 1-7 */ + FLASH_ROMFS (rx): ORIGIN = 0x90000000, LENGTH = 8192K /* external QSPI */ + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for FS storage cache */ + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 320K /* AXI SRAM (could extend +192K from ITCM) */ + RAM_SRAM1 (xrw) : ORIGIN = 0x30000000, LENGTH = 16K /* SRAM1 */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define the stack. The stack is full descending so begins just above last byte + of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve; +_sstack = _estack - 16K; /* tunable */ + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = _ebss; /* heap starts just after statically allocated memory */ +_heap_end = _sstack; + +/* ROMFS location */ +_micropy_hw_romfs_part0_start = ORIGIN(FLASH_ROMFS); +_micropy_hw_romfs_part0_size = LENGTH(FLASH_ROMFS); From 003ba9b58fb5753cd382ab739b6c5f85467ef34a Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 18 Apr 2026 19:26:49 +1000 Subject: [PATCH 433/635] extmod/machine: Add machine.mem_backup function. Add machine.mem_backup(region=0), which returns a writable memoryview into a battery-backed or persistent hardware memory region. Passing -1 returns a tuple of all regions for discovery. The shared implementation lives in extmod/machine_mem.c; each port provides an enable flag plus a const machine_mem_backup_regions[] table and matching region-count symbol. Automatically enables MICROPY_PY_BUILTINS_MEMORYVIEW_ITEMSIZE so users can discover access granularity at runtime. Signed-off-by: Andrew Leech --- extmod/machine_mem.c | 36 ++++++++++++ extmod/modmachine.c | 3 + extmod/modmachine.h | 4 ++ ports/unix/coverage_backup.c | 34 +++++++++++ .../unix/variants/coverage/mpconfigvariant.h | 4 ++ py/mpconfig.h | 7 ++- tests/extmod/machine_mem_backup.py | 58 +++++++++++++++++++ tests/extmod/machine_mem_backup.py.exp | 17 ++++++ 8 files changed, 162 insertions(+), 1 deletion(-) create mode 100644 ports/unix/coverage_backup.c create mode 100644 tests/extmod/machine_mem_backup.py create mode 100644 tests/extmod/machine_mem_backup.py.exp diff --git a/extmod/machine_mem.c b/extmod/machine_mem.c index c34ece2454c..967d8d77a61 100644 --- a/extmod/machine_mem.c +++ b/extmod/machine_mem.c @@ -25,6 +25,7 @@ */ #include "py/runtime.h" +#include "py/objarray.h" #include "extmod/modmachine.h" #if MICROPY_PY_MACHINE_MEMX @@ -114,3 +115,38 @@ const machine_mem_obj_t machine_mem16_obj = {{&machine_mem_type}, 2}; const machine_mem_obj_t machine_mem32_obj = {{&machine_mem_type}, 4}; #endif // MICROPY_PY_MACHINE_MEMX + +#if MICROPY_PY_MACHINE_MEM_BACKUP + +#if !MICROPY_PY_BUILTINS_MEMORYVIEW +#error "machine.mem_backup requires MICROPY_PY_BUILTINS_MEMORYVIEW" +#endif + +// Convenience initialiser for a read-write memoryview entry in the +// machine_mem_backup_regions[] table provided by each port. typecode is the +// base array typecode char ('B' for uint8, 'I' for uint32). +#define BACKUP_MV(typecode, len, ptr) \ + {{&mp_type_memoryview}, (typecode) | MP_OBJ_ARRAY_TYPECODE_FLAG_RW, 0, (len), (ptr)} + +// The port provides machine_mem_backup_regions[] in this file. +#include MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE + +// region=0 (default) returns region 0, region=-1 returns a tuple of all regions. +static mp_obj_t machine_mem_backup(size_t n_args, const mp_obj_t *args) { + mp_int_t r = n_args ? mp_obj_get_int(args[0]) : 0; + if (r == -1) { + size_t n = MP_ARRAY_SIZE(machine_mem_backup_regions); + mp_obj_tuple_t *tup = MP_OBJ_TO_PTR(mp_obj_new_tuple(n, NULL)); + for (size_t i = 0; i < n; i++) { + tup->items[i] = MP_OBJ_FROM_PTR(&machine_mem_backup_regions[i]); + } + return MP_OBJ_FROM_PTR(tup); + } + if (r < 0 || (size_t)r >= MP_ARRAY_SIZE(machine_mem_backup_regions)) { + mp_raise_ValueError(MP_ERROR_TEXT("invalid region")); + } + return MP_OBJ_FROM_PTR(&machine_mem_backup_regions[r]); +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_mem_backup_fun_obj, 0, 1, machine_mem_backup); + +#endif // MICROPY_PY_MACHINE_MEM_BACKUP diff --git a/extmod/modmachine.c b/extmod/modmachine.c index c4a08918faa..1a01d20c5d3 100644 --- a/extmod/modmachine.c +++ b/extmod/modmachine.c @@ -149,6 +149,9 @@ static const mp_rom_map_elem_t machine_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_mem16), MP_ROM_PTR(&machine_mem16_obj) }, { MP_ROM_QSTR(MP_QSTR_mem32), MP_ROM_PTR(&machine_mem32_obj) }, #endif + #if MICROPY_PY_MACHINE_MEM_BACKUP + { MP_ROM_QSTR(MP_QSTR_mem_backup), MP_ROM_PTR(&machine_mem_backup_fun_obj) }, + #endif // Miscellaneous functions. #if MICROPY_PY_MACHINE_BARE_METAL_FUNCS diff --git a/extmod/modmachine.h b/extmod/modmachine.h index d21c6e6d364..b6d6345a408 100644 --- a/extmod/modmachine.h +++ b/extmod/modmachine.h @@ -203,6 +203,10 @@ extern const machine_mem_obj_t machine_mem8_obj; extern const machine_mem_obj_t machine_mem16_obj; extern const machine_mem_obj_t machine_mem32_obj; +#if MICROPY_PY_MACHINE_MEM_BACKUP +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_mem_backup_fun_obj); +#endif + // These classes correspond to machine.Type entries in the machine module. // Their Python bindings are implemented in extmod, and their implementation // is provided by a port. diff --git a/ports/unix/coverage_backup.c b/ports/unix/coverage_backup.c new file mode 100644 index 00000000000..101a28f8cd1 --- /dev/null +++ b/ports/unix/coverage_backup.c @@ -0,0 +1,34 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. + +// Static backing store for machine.mem_backup coverage testing. +static uint8_t machine_mem_backup_buf[64]; +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('B', sizeof(machine_mem_backup_buf), (void *)machine_mem_backup_buf), +}; diff --git a/ports/unix/variants/coverage/mpconfigvariant.h b/ports/unix/variants/coverage/mpconfigvariant.h index 2f5d9683b3f..1cc2c8cf44a 100644 --- a/ports/unix/variants/coverage/mpconfigvariant.h +++ b/ports/unix/variants/coverage/mpconfigvariant.h @@ -53,3 +53,7 @@ #define MICROPY_HW_MCU_NAME MICROPY_PY_SYS_PLATFORM // Keep the standard banner message #define MICROPY_BANNER_MACHINE MICROPY_PY_SYS_PLATFORM " [" MICROPY_PLATFORM_COMPILER "] version" + +// Enable machine.mem_backup with a static RAM buffer for coverage testing. +#define MICROPY_PY_MACHINE_MEM_BACKUP (1) +#define MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE "ports/unix/coverage_backup.c" diff --git a/py/mpconfig.h b/py/mpconfig.h index ce1b6ba4ad4..c146b76d0e9 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -1431,7 +1431,7 @@ typedef time_t mp_timestamp_t; // Whether to support memoryview.itemsize attribute #ifndef MICROPY_PY_BUILTINS_MEMORYVIEW_ITEMSIZE -#define MICROPY_PY_BUILTINS_MEMORYVIEW_ITEMSIZE (MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_EVERYTHING) +#define MICROPY_PY_BUILTINS_MEMORYVIEW_ITEMSIZE (MICROPY_PY_MACHINE_MEM_BACKUP || MICROPY_CONFIG_ROM_LEVEL_AT_LEAST_BASIC_FEATURES) #endif // Whether to support set object @@ -2099,6 +2099,11 @@ typedef time_t mp_timestamp_t; #define MICROPY_PY_MACHINE_MEMX (MICROPY_PY_MACHINE) #endif +// Whether to provide the "machine.mem_backup" function +#ifndef MICROPY_PY_MACHINE_MEM_BACKUP +#define MICROPY_PY_MACHINE_MEM_BACKUP (0) +#endif + // Whether to provide the "machine.Signal" class #ifndef MICROPY_PY_MACHINE_SIGNAL #define MICROPY_PY_MACHINE_SIGNAL (MICROPY_PY_MACHINE) diff --git a/tests/extmod/machine_mem_backup.py b/tests/extmod/machine_mem_backup.py new file mode 100644 index 00000000000..db2ff910a73 --- /dev/null +++ b/tests/extmod/machine_mem_backup.py @@ -0,0 +1,58 @@ +# Test machine.mem_backup() function. + +try: + import machine + + mem = machine.mem_backup() +except (ImportError, AttributeError): + print("SKIP") + raise SystemExit + +# Discovery: -1 returns a tuple of all regions. +regions = machine.mem_backup(-1) +print("regions is tuple:", isinstance(regions, tuple)) +print("at least one region:", len(regions) >= 1) +print("all memoryviews:", all(isinstance(r, memoryview) for r in regions)) +print("all len > 0:", all(len(r) > 0 for r in regions)) +print("all valid itemsize:", all(r.itemsize in (1, 4) for r in regions)) + +# Default region (index 0). +print("memoryview:", isinstance(mem, memoryview)) +print("len > 0:", len(mem) > 0) +print("itemsize ok:", mem.itemsize in (1, 4)) + +# Small-value write/read. +mem[0] = 42 +print(mem[0] == 42) + +if mem.itemsize == 4: + # Values >= 0x40000000 are big-ints on 32-bit targets; check that + # word-only backup registers receive them as aligned word writes. + for val in (0x40000000, 0x41020304, 0x7FFFFFFF, 0xDEADBEEF): + mem[0] = val + print(mem[0] == val) + mem[0] = -1 + print(mem[0] == 0xFFFFFFFF) +else: + for val in (0x80, 0xA5, 0xFF, 0xC3): + mem[0] = val + print(mem[0] == val) + mem[0] = 0 + print(mem[0] == 0) + +last = len(mem) - 1 +mem[last] = 1 +print(mem[last] == 1) + +# Out-of-range region raises ValueError. +try: + machine.mem_backup(len(regions)) + print("no error") +except ValueError: + print("ValueError") + +try: + machine.mem_backup(-2) + print("no error") +except ValueError: + print("ValueError") diff --git a/tests/extmod/machine_mem_backup.py.exp b/tests/extmod/machine_mem_backup.py.exp new file mode 100644 index 00000000000..c3d858c86d6 --- /dev/null +++ b/tests/extmod/machine_mem_backup.py.exp @@ -0,0 +1,17 @@ +regions is tuple: True +at least one region: True +all memoryviews: True +all len > 0: True +all valid itemsize: True +memoryview: True +len > 0: True +itemsize ok: True +True +True +True +True +True +True +True +ValueError +ValueError From bd789a5fc67cef698e4c462b432fafaecb4a53dd Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 18 Apr 2026 19:26:57 +1000 Subject: [PATCH 434/635] mimxrt: Enable machine.mem_backup via SNVS LPGPR registers. Expose SNVS LP General Purpose Registers as machine.mem_backup with word-level access (itemsize=4). Register count varies by chip (4 on RT1011/RT1176, 8 on RT1015/1021/1052/1062/1064). Signed-off-by: Andrew Leech --- .../boards/SEEED_ARCH_MIX/mpconfigboard.h | 4 ++ ports/mimxrt/machine_mem_backup.c | 40 +++++++++++++++++++ ports/mimxrt/mpconfigport.h | 4 ++ 3 files changed, 48 insertions(+) create mode 100644 ports/mimxrt/machine_mem_backup.c diff --git a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h index cbc6491169b..90c1bdca07f 100644 --- a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h +++ b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h @@ -192,3 +192,7 @@ #define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_28_SEMC_WE #define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_29_SEMC_CS0 + +// LPGPR[3] is used by the TinyUF2 bootloader for double-tap entry detection; +// exclude it from machine.mem_backup() to prevent accidental corruption. +#define MICROPY_HW_SNVS_LPGPR_SAFE_COUNT (3) diff --git a/ports/mimxrt/machine_mem_backup.c b/ports/mimxrt/machine_mem_backup.c new file mode 100644 index 00000000000..c2a6b7ac06a --- /dev/null +++ b/ports/mimxrt/machine_mem_backup.c @@ -0,0 +1,40 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. + +#include "fsl_snvs_lp.h" + +// Boards with a UF2 bootloader use LPGPR[3] for double-tap entry detection +// and should override MICROPY_HW_SNVS_LPGPR_SAFE_COUNT to 3 in mpconfigboard.h. +#ifndef MICROPY_HW_SNVS_LPGPR_SAFE_COUNT +#define MICROPY_HW_SNVS_LPGPR_SAFE_COUNT SNVS_LPGPR_COUNT +#endif + +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('I', MICROPY_HW_SNVS_LPGPR_SAFE_COUNT, (void *)&SNVS->LPGPR[0]), +}; diff --git a/ports/mimxrt/mpconfigport.h b/ports/mimxrt/mpconfigport.h index d0489bc2513..b775c28dcbe 100644 --- a/ports/mimxrt/mpconfigport.h +++ b/ports/mimxrt/mpconfigport.h @@ -144,6 +144,10 @@ uint32_t trng_random_u32(void); #endif #define MICROPY_PY_ONEWIRE (1) #define MICROPY_PY_MACHINE_BOOTLOADER (1) +#ifndef MICROPY_PY_MACHINE_MEM_BACKUP +#define MICROPY_PY_MACHINE_MEM_BACKUP (1) +#endif +#define MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE "ports/mimxrt/machine_mem_backup.c" // fatfs configuration used in ffconf.h #define MICROPY_FATFS_ENABLE_LFN (2) From fb1375b57853202eb55c63741f1e6d927bc7bb64 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 18 Apr 2026 19:27:06 +1000 Subject: [PATCH 435/635] stm32: Enable machine.mem_backup via backup SRAM or BKP registers. On families with dedicated backup SRAM (F4, F7, H5, H7, U5, N6), expose 4-8 KB of byte-addressable battery-backed SRAM as machine.mem_backup with itemsize=1. The BKPSRAM clock and backup regulator are enabled during boot after RTC init. On H7 and N6, an MPU region marks the BKPSRAM non-cacheable since its address falls in the default-cacheable SRAM range. On families without BKPSRAM (L0, L1, L4, G0, G4, WB, WL), fall back to RTC backup registers (BKPxR / TAMP BKPxR) with word-level access (itemsize=4, 20-128 bytes). Gated on MICROPY_HW_ENABLE_RTC. Signed-off-by: Andrew Leech --- ports/stm32/machine_mem_backup.c | 145 +++++++++++++++++++++++++++++++ ports/stm32/main.c | 5 ++ ports/stm32/modmachine.h | 3 + ports/stm32/mpconfigport.h | 7 ++ ports/stm32/mpu.h | 8 +- 5 files changed, 165 insertions(+), 3 deletions(-) create mode 100644 ports/stm32/machine_mem_backup.c diff --git a/ports/stm32/machine_mem_backup.c b/ports/stm32/machine_mem_backup.c new file mode 100644 index 00000000000..54a2e18218f --- /dev/null +++ b/ports/stm32/machine_mem_backup.c @@ -0,0 +1,145 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. + +#include STM32_HAL_H +#include "mpu.h" + +// Detect BKPSRAM availability from CMSIS macros. +#if defined(BKPSRAM_BASE) +// F4, F7, H5, U5 +#define STM32_BKPSRAM_BASE BKPSRAM_BASE +#elif defined(D3_BKPSRAM_BASE) +// H7 (non-7Ax/7Bx) +#define STM32_BKPSRAM_BASE D3_BKPSRAM_BASE +#elif defined(SRD_BKPSRAM_BASE) +// H7A3/H7B3/H7B0 +#define STM32_BKPSRAM_BASE SRD_BKPSRAM_BASE +#elif defined(BKPSRAM_BASE_NS) +// N6 (no unsuffixed alias) +#define STM32_BKPSRAM_BASE BKPSRAM_BASE_NS +#endif + +#if defined(STM32_BKPSRAM_BASE) +#if defined(BKPSRAM_SIZE) +// Families with BKPSRAM_SIZE in CMSIS (H5: 2-4 KB, N6: 8 KB). +#define STM32_BKPSRAM_BYTES BKPSRAM_SIZE +#else +// F4, F7, H7, U5: 4 KB. +#define STM32_BKPSRAM_BYTES (4096) +#endif +#endif + +// Detect RTC/TAMP BKP registers (present on all STM32 families). +#if defined(RTC_BKP_NUMBER) +#define STM32_BKP_REG_COUNT RTC_BKP_NUMBER +#elif defined(TAMP_BKP_NUMBER) +#define STM32_BKP_REG_COUNT TAMP_BKP_NUMBER +#elif defined(RTC_BACKUP_NB) +#define STM32_BKP_REG_COUNT RTC_BACKUP_NB +#elif defined(RTC_BKP_NB) +#define STM32_BKP_REG_COUNT RTC_BKP_NB +#endif + +#if defined(STM32_BKP_REG_COUNT) +#if defined(TAMP) +#define STM32_BKP_REG_ADDR ((void *)&TAMP->BKP0R) +#else +#define STM32_BKP_REG_ADDR ((void *)&RTC->BKP0R) +#endif +#endif + +#if !defined(STM32_BKPSRAM_BASE) && !defined(STM32_BKP_REG_COUNT) +#error "STM32: MICROPY_PY_MACHINE_MEM_BACKUP enabled but no backup storage found" +#endif + +// On BKPSRAM families: region 0 is BKPSRAM, region 1 is BKP registers. +// Otherwise: region 0 is BKP registers only. +#if defined(STM32_BKPSRAM_BASE) +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('B', STM32_BKPSRAM_BYTES, (void *)STM32_BKPSRAM_BASE), + #if defined(STM32_BKP_REG_COUNT) + BACKUP_MV('I', STM32_BKP_REG_COUNT, STM32_BKP_REG_ADDR), + #endif +}; +#else +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('I', STM32_BKP_REG_COUNT, STM32_BKP_REG_ADDR), +}; +#endif + +void machine_mem_backup_init(void) { + #if defined(STM32_BKPSRAM_BASE) + #if defined(RCC_AHB1ENR_BKPSRAMEN) + // F4, F7, U5: BKPSRAM clock on AHB1. + __HAL_RCC_BKPSRAM_CLK_ENABLE(); + #elif defined(RCC_AHB4ENR_BKPRAMEN) + // H7: BKPRAM clock on AHB4. + __HAL_RCC_BKPRAM_CLK_ENABLE(); + #elif defined(RCC_MEMENR_BKPSRAMEN) + // N6: memory enable register. + LL_MEM_EnableClock(LL_MEM_BKPSRAM); + #endif + #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + HAL_PWREx_EnableBkUpReg(); + #elif defined(PWR_BDCR_BREN) + SET_BIT(PWR->BDCR, PWR_BDCR_BREN); + // Wait for backup regulator ready; 1s fail-safe so a stuck bit can't hang boot. + { + uint32_t ticks = HAL_GetTick(); + while (!READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY)) { + if (HAL_GetTick() - ticks > 1000) { + break; + } + } + } + #elif defined(PWR_BDCR1_BREN) + SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); + #elif defined(PWR_BDCR2_BKPRBSEN) + SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); + #endif + // H7/N6 map BKPSRAM into cacheable SRAM and need a non-cacheable MPU region. + #if defined(STM32H7) + // H7 MPU region size is fixed at 4 KB; sync with STM32_BKPSRAM_BYTES if that changes. + MP_STATIC_ASSERT(STM32_BKPSRAM_BYTES == 4096); + { + uint32_t irq_state = mpu_config_start(); + mpu_config_region(MPU_REGION_BKPSRAM, STM32_BKPSRAM_BASE, + MPU_CONFIG_UNCACHED(MPU_REGION_SIZE_4KB)); + mpu_config_end(irq_state); + } + #elif defined(STM32N6) + { + uint32_t irq_state = mpu_config_start(); + mpu_config_region(MPU_REGION_BKPSRAM, STM32_BKPSRAM_BASE, + STM32_BKPSRAM_BYTES); + mpu_config_end(irq_state); + } + #endif + #endif // STM32_BKPSRAM_BASE +} diff --git a/ports/stm32/main.c b/ports/stm32/main.c index fae361af276..e3e7fd014eb 100644 --- a/ports/stm32/main.c +++ b/ports/stm32/main.c @@ -501,6 +501,11 @@ void stm32_main(uint32_t reset_mode) { #if MICROPY_HW_ENABLE_RTC rtc_init_start(false); #endif + + #if MICROPY_PY_MACHINE_MEM_BACKUP + machine_mem_backup_init(); + #endif + uart_init0(); #if defined(MICROPY_HW_UART_REPL) diff --git a/ports/stm32/modmachine.h b/ports/stm32/modmachine.h index 7e5fa42861e..318a70383f0 100644 --- a/ports/stm32/modmachine.h +++ b/ports/stm32/modmachine.h @@ -32,6 +32,9 @@ void machine_init(void); void machine_deinit(void); void machine_i2s_init0(); void machine_pwm_deinit_all(void); +#if MICROPY_PY_MACHINE_MEM_BACKUP +void machine_mem_backup_init(void); +#endif MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_info_obj); diff --git a/ports/stm32/mpconfigport.h b/ports/stm32/mpconfigport.h index ea1b73bece0..d1c480649de 100644 --- a/ports/stm32/mpconfigport.h +++ b/ports/stm32/mpconfigport.h @@ -130,6 +130,13 @@ #endif #define MICROPY_PY_MACHINE_CAN_INCLUDEFILE "ports/stm32/machine_can.c" #define MICROPY_PY_MACHINE_DHT_READINTO (1) +// Backup memory via BKPSRAM or RTC BKP registers. +#if MICROPY_HW_ENABLE_RTC +#ifndef MICROPY_PY_MACHINE_MEM_BACKUP +#define MICROPY_PY_MACHINE_MEM_BACKUP (1) +#endif +#define MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE "ports/stm32/machine_mem_backup.c" +#endif #define MICROPY_PY_MACHINE_PULSE (1) #define MICROPY_PY_MACHINE_PIN_MAKE_NEW mp_pin_make_new #define MICROPY_PY_MACHINE_I2C (MICROPY_HW_ENABLE_HW_I2C) diff --git a/ports/stm32/mpu.h b/ports/stm32/mpu.h index a268d3a364d..de7b35819b7 100644 --- a/ports/stm32/mpu.h +++ b/ports/stm32/mpu.h @@ -46,7 +46,8 @@ #ifdef MPU_REGION_NUMBER8 #define MPU_REGION_OPENAMP (MPU_REGION_NUMBER8) -#define MPU_REGION_LAST_USED (MPU_REGION_NUMBER8) +#define MPU_REGION_BKPSRAM (MPU_REGION_NUMBER9) +#define MPU_REGION_LAST_USED (MPU_REGION_NUMBER9) #else #define MPU_REGION_LAST_USED (MPU_REGION_NUMBER7) #endif @@ -146,7 +147,8 @@ static inline void mpu_config_end(uint32_t irq_state) { #define MPU_REGION_ETH (MPU_REGION_NUMBER1) #define MPU_REGION_DMA_UNCACHED_1 (MPU_REGION_NUMBER2) #define MPU_REGION_DMA_UNCACHED_2 (MPU_REGION_NUMBER3) -#define MPU_REGION_LAST_USED (MPU_REGION_NUMBER3) +#define MPU_REGION_BKPSRAM (MPU_REGION_NUMBER4) +#define MPU_REGION_LAST_USED (MPU_REGION_NUMBER4) #define ST_DEVICE_SIGNATURE_BASE (0x08fff800) #define ST_DEVICE_SIGNATURE_LIMIT (0x08ffffff) @@ -195,7 +197,7 @@ static inline void mpu_config_region(uint32_t region, uint32_t base_addr, uint32 // Disable MPU for this region. MPU->RNR = region; MPU->RLAR &= ~MPU_RLAR_EN_Msk; - } else if (region == MPU_REGION_ETH || region == MPU_REGION_DMA_UNCACHED_1 || region == MPU_REGION_DMA_UNCACHED_2) { + } else if (region == MPU_REGION_ETH || region == MPU_REGION_DMA_UNCACHED_1 || region == MPU_REGION_DMA_UNCACHED_2 || region == MPU_REGION_BKPSRAM) { // Configure region to make DMA memory non-cacheable. __DMB(); From 8d6ce0f56f6694c5e4e6aad77d36ea7bbec9b486 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 18 Apr 2026 19:27:13 +1000 Subject: [PATCH 436/635] rp2: Enable machine.mem_backup via watchdog scratch registers. Expose the watchdog scratch registers (scratch[0..3] and scratch[5..7], skipping scratch[4] which pico-sdk uses for reboot bookkeeping) as machine.mem_backup, with word-level access (itemsize=4, 28 bytes total across two regions). On RP2350 an additional 32-byte powman scratch region is exposed. Data persists across soft resets but not power-off (no battery backing). Signed-off-by: Andrew Leech --- ports/rp2/machine_mem_backup.c | 44 ++++++++++++++++++++++++++++++++++ ports/rp2/mpconfigport.h | 4 ++++ 2 files changed, 48 insertions(+) create mode 100644 ports/rp2/machine_mem_backup.c diff --git a/ports/rp2/machine_mem_backup.c b/ports/rp2/machine_mem_backup.c new file mode 100644 index 00000000000..a7f1368ef17 --- /dev/null +++ b/ports/rp2/machine_mem_backup.c @@ -0,0 +1,44 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. + +#include "hardware/watchdog.h" + +#if PICO_RP2350 +#include "hardware/powman.h" +#endif + +// scratch[4] is reserved by pico-sdk; scratch[5..7] survive watchdog_reboot(pc=0). + +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('I', 4, (void *)&watchdog_hw->scratch[0]), // scratch[0..3], 16 bytes + BACKUP_MV('I', 3, (void *)&watchdog_hw->scratch[5]), // scratch[5..7], 12 bytes + #if PICO_RP2350 + BACKUP_MV('I', 8, (void *)&powman_hw->scratch[0]), // powman scratch, 32 bytes + #endif +}; diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h index cbe2540ebbd..3084531cb40 100644 --- a/ports/rp2/mpconfigport.h +++ b/ports/rp2/mpconfigport.h @@ -206,6 +206,10 @@ #define MICROPY_PY_MACHINE_UART_IRQ (1) #define MICROPY_PY_MACHINE_WDT (1) #define MICROPY_PY_MACHINE_WDT_INCLUDEFILE "ports/rp2/machine_wdt.c" +#ifndef MICROPY_PY_MACHINE_MEM_BACKUP +#define MICROPY_PY_MACHINE_MEM_BACKUP (1) +#endif +#define MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE "ports/rp2/machine_mem_backup.c" #define MICROPY_PY_MACHINE_FREQ_NUM_ARGS_MAX (2) #define MICROPY_PY_ONEWIRE (1) #define MICROPY_VFS (1) From bbd0d481283e221c4ce4af277927e733d876ef4a Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 18 Apr 2026 19:27:21 +1000 Subject: [PATCH 437/635] alif: Enable machine.mem_backup via backup SRAM. Expose the 4KB battery-backed backup SRAM at 0x4902C000 as machine.mem_backup with word-level access (itemsize=4). The region lives in peripheral space and does not support sub-word writes, so the memoryview is exposed as uint32 to enforce word-aligned access from Python. Signed-off-by: Andrew Leech --- ports/alif/machine_mem_backup.c | 36 +++++++++++++++++++++++++++++++++ ports/alif/mpconfigport.h | 4 ++++ 2 files changed, 40 insertions(+) create mode 100644 ports/alif/machine_mem_backup.c diff --git a/ports/alif/machine_mem_backup.c b/ports/alif/machine_mem_backup.c new file mode 100644 index 00000000000..e4cb92bb7c9 --- /dev/null +++ b/ports/alif/machine_mem_backup.c @@ -0,0 +1,36 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. + +// Backup SRAM is in peripheral space; word writes only. No CMSIS macro exists. +#define ALIF_BACKUP_SRAM_BASE (0x4902C000U) +#define ALIF_BACKUP_SRAM_BYTES (4096U) + +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('I', ALIF_BACKUP_SRAM_BYTES / 4, (void *)ALIF_BACKUP_SRAM_BASE), +}; diff --git a/ports/alif/mpconfigport.h b/ports/alif/mpconfigport.h index d0767dfbae1..4baa336aa9f 100644 --- a/ports/alif/mpconfigport.h +++ b/ports/alif/mpconfigport.h @@ -147,6 +147,10 @@ #define MICROPY_PY_MACHINE_UART (1) #define MICROPY_PY_MACHINE_UART_INCLUDEFILE "ports/alif/machine_uart.c" #define MICROPY_PY_MACHINE_UART_IRQ (1) +#ifndef MICROPY_PY_MACHINE_MEM_BACKUP +#define MICROPY_PY_MACHINE_MEM_BACKUP (1) +#endif +#define MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE "ports/alif/machine_mem_backup.c" #define MICROPY_PY_NETWORK (CORE_M55_HP) #ifndef MICROPY_PY_NETWORK_HOSTNAME_DEFAULT #define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-alif" From ff5b9a3085f2b95d6d1af30a840b444645ce3e4c Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 18 Apr 2026 19:27:30 +1000 Subject: [PATCH 438/635] esp32: Enable machine.mem_backup via RTC slow memory. Expose the RTC user memory (2048 bytes default) as machine.mem_backup with byte-level access alongside the existing RTC.memory() method. The two APIs share the same backing buffer but have independent semantics: mem_backup is a raw memoryview while RTC.memory() tracks written length. Signed-off-by: Andrew Leech --- ports/esp32/machine_mem_backup.c | 35 ++++++++++++++++++++++++++++++++ ports/esp32/machine_rtc.c | 4 ---- ports/esp32/machine_rtc.h | 3 +++ ports/esp32/mpconfigport.h | 12 +++++++++++ 4 files changed, 50 insertions(+), 4 deletions(-) create mode 100644 ports/esp32/machine_mem_backup.c diff --git a/ports/esp32/machine_mem_backup.c b/ports/esp32/machine_mem_backup.c new file mode 100644 index 00000000000..01aaeaeca38 --- /dev/null +++ b/ports/esp32/machine_mem_backup.c @@ -0,0 +1,35 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. + +#include "machine_rtc.h" + +// Shares storage with RTC.memory(); don't mix the two APIs on the same data. +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('B', MICROPY_HW_RTC_USER_MEM_MAX, (void *)rtc_user_mem_data), +}; diff --git a/ports/esp32/machine_rtc.c b/ports/esp32/machine_rtc.c index d11ee22b510..f78086cf05b 100644 --- a/ports/esp32/machine_rtc.c +++ b/ports/esp32/machine_rtc.c @@ -56,10 +56,6 @@ typedef struct _machine_rtc_obj_t { If MICROPY_HW_RTC_USER_MEM_MAX is set to 0, the RTC.memory() functionality will be not be compiled which frees some extra flash and RTC memory. */ -#ifndef MICROPY_HW_RTC_USER_MEM_MAX -#define MICROPY_HW_RTC_USER_MEM_MAX 2048 -#endif - // A board can enable MICROPY_HW_RTC_MEM_INIT_ALWAYS to always clear out RTC memory on boot. // Defaults to RTC_NOINIT_ATTR so the user memory survives WDT resets and the like. #if MICROPY_HW_RTC_MEM_INIT_ALWAYS diff --git a/ports/esp32/machine_rtc.h b/ports/esp32/machine_rtc.h index e40a17fb3db..265fecbe060 100644 --- a/ports/esp32/machine_rtc.h +++ b/ports/esp32/machine_rtc.h @@ -56,4 +56,7 @@ typedef struct { extern machine_rtc_config_t machine_rtc_config; +// User backup memory buffer, shared with machine.mem_backup on esp32. +extern uint8_t rtc_user_mem_data[MICROPY_HW_RTC_USER_MEM_MAX]; + #endif diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index 632c2f31774..4074a9f51c9 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -168,6 +168,18 @@ #define MICROPY_PY_MACHINE_UART_IRQ (1) #define MICROPY_PY_MACHINE_WDT (1) #define MICROPY_PY_MACHINE_WDT_INCLUDEFILE "ports/esp32/machine_wdt.c" +#ifndef MICROPY_HW_RTC_USER_MEM_MAX +#define MICROPY_HW_RTC_USER_MEM_MAX 2048 +#endif +// machine.mem_backup exposes the RTC user memory as a byte memoryview. +// RTC.memory() coexists but uses separate length tracking; writes via +// mem_backup won't update RTC.memory()'s length, and vice versa. +#if MICROPY_HW_RTC_USER_MEM_MAX > 0 +#ifndef MICROPY_PY_MACHINE_MEM_BACKUP +#define MICROPY_PY_MACHINE_MEM_BACKUP (1) +#endif +#define MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE "ports/esp32/machine_mem_backup.c" +#endif #ifndef MICROPY_PY_NETWORK #define MICROPY_PY_NETWORK (1) #endif From 994f3620aa892a9bf8cf0155d3e0ceee21915dbb Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 21 Apr 2026 08:43:49 +1000 Subject: [PATCH 439/635] samd: Enable machine.mem_backup via backup RAM on SAMD51. Expose the 8KB backup RAM at 0x47000000 as machine.mem_backup with byte-level access (itemsize=1) on SAMD51 boards. Signed-off-by: Andrew Leech --- ports/samd/machine_mem_backup.c | 34 +++++++++++++++++++++++++++++ ports/samd/mcu/samd51/mpconfigmcu.h | 5 +++++ 2 files changed, 39 insertions(+) create mode 100644 ports/samd/machine_mem_backup.c diff --git a/ports/samd/machine_mem_backup.c b/ports/samd/machine_mem_backup.c new file mode 100644 index 00000000000..2f6bcea3c5d --- /dev/null +++ b/ports/samd/machine_mem_backup.c @@ -0,0 +1,34 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. + +// SAMD51 BKUPRAM lives in the backup power domain; retains across resets and +// power-off with VBAT. SAMD21 has no equivalent (only SAMD51 compiles this file). +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('B', BKUPRAM_SIZE, (void *)BKUPRAM_ADDR), +}; diff --git a/ports/samd/mcu/samd51/mpconfigmcu.h b/ports/samd/mcu/samd51/mpconfigmcu.h index e5709d6cdd6..9810449c471 100644 --- a/ports/samd/mcu/samd51/mpconfigmcu.h +++ b/ports/samd/mcu/samd51/mpconfigmcu.h @@ -28,6 +28,11 @@ unsigned long trng_random_u32(void); #define VFS_BLOCK_SIZE_BYTES (2048) // +#ifndef MICROPY_PY_MACHINE_MEM_BACKUP +#define MICROPY_PY_MACHINE_MEM_BACKUP (1) +#endif +#define MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE "ports/samd/machine_mem_backup.c" + #ifndef MICROPY_HW_UART_TXBUF #define MICROPY_HW_UART_TXBUF (1) #endif From 36870f4f7ee4f30ccc1dbd975eb7bfc99d0ae5c5 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 18 Apr 2026 19:27:37 +1000 Subject: [PATCH 440/635] docs/library: Document machine.mem_backup. Add documentation for the machine.mem_backup function including per-port storage sizes, reserved register table, uctypes integration example, and availability. Signed-off-by: Andrew Leech --- docs/library/machine.RTC.rst | 12 ++++ docs/library/machine.rst | 113 +++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/docs/library/machine.RTC.rst b/docs/library/machine.RTC.rst index 281274ed19d..80570601bbd 100644 --- a/docs/library/machine.RTC.rst +++ b/docs/library/machine.RTC.rst @@ -103,6 +103,18 @@ Methods Availability: esp32, esp8266 ports. + .. note:: + + For cross-port persistent storage, see :func:`machine.mem_backup` + which is available on more ports and provides direct memoryview access. + + .. warning:: + + On esp32, ``RTC.memory()`` and :func:`machine.mem_backup` share the same + backing buffer but track length independently. Writes through one API + are not reflected in the length seen by the other. Avoid mixing the two + in the same application. + Constants --------- diff --git a/docs/library/machine.rst b/docs/library/machine.rst index b92602d4fc2..557224c5078 100644 --- a/docs/library/machine.rst +++ b/docs/library/machine.rst @@ -65,6 +65,119 @@ To always read a positive integer value = mem32[0x40001000] & 0xffffffff +.. function:: mem_backup(region=0) + + Return a writable `memoryview` over a persistent hardware memory region that + survives at least :ref:`soft_reset` on all ports; battery-backed ports also + survive power-off. Per-port persistence guarantees vary, see the table below. + + *region* selects which backup region to access (default 0, the primary region). + Pass ``-1`` to get a tuple of all available regions instead. + + The element type depends on the port's hardware alignment requirements: + ``'B'`` (unsigned byte) on ports with byte-addressable backup memory, + ``'I'`` (unsigned 32-bit) on ports backed by word-sized registers. + Use ``mem.itemsize`` to discover the access granularity at runtime. + + The total size in bytes is ``len(mem) * mem.itemsize``, where ``len(mem)`` + is the number of elements and ``mem.itemsize`` is the size of each element. + For example, on a port with 4 word-sized registers, ``len(mem)`` is 4 and + ``mem.itemsize`` is 4, giving 16 bytes total. On a port with 4096 bytes + of byte-addressable backup SRAM, ``len(mem)`` is 4096 and ``mem.itemsize`` + is 1. + + Cross-port guarantees for portable code: ``mem.itemsize`` is either ``1`` + or ``4``; valid indices are ``0..len(mem)-1``; out-of-range access raises + ``IndexError``; values are stored in host-native byte order. Region index + semantics are not portable, see notes below for ``stm32`` in particular. + + Usage:: + + import machine + + mem = machine.mem_backup() + mem[0] = 0x12345678 # write element 0 + print(hex(mem[0])) # read element 0 + print(len(mem)) # number of elements + print(mem.itemsize) # bytes per element + print(len(mem) * mem.itemsize) # total bytes available + + # Discover all available regions + for i, r in enumerate(machine.mem_backup(-1)): + print(i, len(r), r.itemsize) + + The total byte size and backing hardware vary by port: + + ====== =============================================== =========== ============== + Port Backing storage Total bytes Battery-backed + ====== =============================================== =========== ============== + alif Backup SRAM 4096 yes + esp32 RTC slow memory 2048 no + mimxrt SNVS LPGPR registers (4 per chip) 12-16 yes + nrf POWER GPREGRET registers 1-2 no + rp2 Watchdog scratch registers 28-60 no + samd Backup RAM (SAMD51 only) 8192 yes + stm32 Backup SRAM + BKP registers (F4/F7/H5/H7/U5/N6) 2048-8192 yes + stm32 RTC BKP registers (other families) 20-128 yes + ====== =============================================== =========== ============== + + .. note:: + + On esp32 and rp2, data persists across :ref:`soft_reset`, + `machine.reset()` and `machine.deepsleep()` wake but is lost on + power-off and on poweron-style resets. On esp32 in particular this + includes pressing the EN/RESET button on most dev boards, which the + chip reports as a power-on reset. + + Some ports split backup storage across multiple regions, or exclude + registers reserved by the bootloader or system firmware: + + ====== ==================== ================================================ + Port Register(s) Note + ====== ==================== ================================================ + mimxrt LPGPR[3] Excluded; used by TinyUF2 (when used) + rp2 scratch[4] Excluded; used by pico-sdk on reset + rp2 powman scratch[0..7] Region 2 on RP2350 only + stm32 BKP registers Region 1 on BKPSRAM families (F4/F7/H5/H7/U5/N6) + ====== ==================== ================================================ + + Use ``machine.mem_backup(-1)`` to discover available regions and their sizes. + + On stm32 the region index does not have a uniform meaning across boards: + region 0 is BKPSRAM (``itemsize=1``) on BKPSRAM families and BKP registers + (``itemsize=4``) on others. Portable code should branch on ``mem.itemsize`` + before structuring data. + + Some registers within a region are accessible but reserved by convention + and should not be overwritten. The BKP register file is region 1 on + BKPSRAM families and region 0 on the others: + + ====== ============== ========================================================= + Port Register(s) Used by + ====== ============== ========================================================= + stm32 BKP0R Arduino bootloader (Portenta H7, Giga, Opta, Nicla) + stm32 BKP16R-BKP18R ``rfcore_firmware.py`` on STM32WB + stm32 last BKP reg clock frequency (``MICROPY_HW_CLK_LAST_FREQ``) + stm32 BKP31R (N6) mboot bootloader entry + ====== ============== ========================================================= + + The buffer allows direct register access and can be combined with + ``uctypes`` for structured layouts:: + + import machine, uctypes + + mem = machine.mem_backup() + + # Structured access via uctypes (check len(mem) for your board) + layout = { + "flags": (0 * 4, uctypes.UINT32), # register 0 + "counter": (1 * 4, uctypes.UINT32), # register 1 + } + regs = uctypes.struct(uctypes.addressof(mem), layout) + regs.flags = 0x01 + print(regs.counter) + + Availability: alif, esp32, mimxrt, nrf, rp2, samd, stm32 ports. Reset related functions ----------------------- From b10d1eabe5546d203dffd135e723e1536102951f Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 18 Apr 2026 19:26:33 +1000 Subject: [PATCH 441/635] py/binary: Use typed store for big-int array and struct writes. When writing a big-int value to an array, memoryview, or struct buffer, mp_binary_set_val_array and mp_binary_set_val previously used mp_obj_int_to_bytes_impl which writes individual bytes. On hardware registers and peripheral-backed memory that only supports word-sized stores (e.g. STM32 RTC backup registers, NXP SNVS LPGPR, RP2 watchdog scratch), byte-wise writes silently corrupt the target word. For element sizes that fit in mp_int_t, route big-int values through mp_obj_int_get_truncated and then through the same typed store paths that small-int values already use. This is also slightly faster since it avoids the byte decomposition loop in mpz_as_bytes. The byte-wise path is retained for element sizes exceeding mp_int_t (e.g. int64 on 32-bit targets). The bug only manifests on 32-bit targets where values >= 0x40000000 exceed the small-int range and the destination rejects sub-word stores. On 64-bit hosts all uint32 values are small ints and already take the typed-store path. Signed-off-by: Andrew Leech --- py/binary.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/py/binary.c b/py/binary.c index bd39efa76b4..80eccc577fb 100644 --- a/py/binary.c +++ b/py/binary.c @@ -474,6 +474,11 @@ void mp_binary_set_val(char struct_type, char val_type, mp_obj_t val_in, byte *p #if MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_NONE if (mp_obj_is_exact_type(val_in, &mp_type_int)) { // Note: overflow checks are disabled in this code path but enabled for V2 in mp_binary_set_val_array() + if (size <= sizeof(mp_uint_t)) { + // Aligned store; byte-wise path corrupts word-only registers. + val = mp_obj_int_get_truncated(val_in); + break; + } mp_obj_int_to_bytes(val_in, size, p, struct_type == '>', is_signed(val_type), false); return; } @@ -508,6 +513,14 @@ void mp_binary_set_val_array(char typecode, void *p, size_t index, mp_obj_t val_ #if MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_NONE if (mp_obj_is_exact_type(val_in, &mp_type_int)) { size_t size = mp_binary_get_size('@', typecode, NULL); + #if !OVERFLOW_CHECKS + if (size <= sizeof(mp_int_t)) { + // Aligned store; byte-wise path corrupts word-only registers. + mp_binary_set_val_array_from_int(typecode, p, index, + mp_obj_int_get_truncated(val_in)); + return; + } + #endif p = (uint8_t *)p + index * size; byte *dest; #if OVERFLOW_CHECKS From 4ca325ab196298cff0ed55b6297e3082aa5641ea Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 28 Apr 2026 19:27:31 +1000 Subject: [PATCH 442/635] github/workflows: Upload 32-bit unix coverage to codecov. The coverage_32bit job was building with coverage flags but never running gcov or uploading to codecov, so all reported coverage was from the 64-bit build only. Add the same gcov + codecov-action steps that the 64-bit job has, with distinct flags so codecov can merge the data correctly. This closes coverage gaps in code paths that only execute on 32-bit targets (e.g. py/binary.c byte-write fallbacks for typecodes where size > sizeof(mp_int_t)). Signed-off-by: Andrew Leech --- .github/workflows/ports_unix.yml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/.github/workflows/ports_unix.yml b/.github/workflows/ports_unix.yml index 702e0e67caf..27ac815c7b5 100644 --- a/.github/workflows/ports_unix.yml +++ b/.github/workflows/ports_unix.yml @@ -123,6 +123,8 @@ jobs: # This avoids the annoying situation of the job failing on every push to a fork (if no token is set). fail_ci_if_error: ${{ secrets.CODECOV_TOKEN != '' || github.repository_owner == 'micropython' }} verbose: true + flags: unix-coverage-64bit + name: unix-coverage-64bit # note: when a fork opens a PR into MicroPython repo, the pull_request trigger can't access # secrets so this token value will be empty (codecov will do a 'tokenless' upload). token: ${{ secrets.CODECOV_TOKEN }} @@ -149,6 +151,20 @@ jobs: run: tools/ci.sh native_mpy_modules_32bit_build - name: Test importing .mpy generated by mpy_ld.py run: tools/ci.sh unix_coverage_32bit_run_native_mpy_tests + - name: Run gcov coverage analysis + run: | + (cd ports/unix && gcov -o build-coverage/py ../../py/*.c || true) + (cd ports/unix && gcov -o build-coverage/extmod ../../extmod/*.c || true) + - name: Upload coverage to Codecov + uses: codecov/codecov-action@v7 + with: + # See corresponding comment above. + fail_ci_if_error: ${{ secrets.CODECOV_TOKEN != '' || github.repository_owner == 'micropython' }} + verbose: true + flags: unix-coverage-32bit + name: unix-coverage-32bit + # See corresponding comment above. + token: ${{ secrets.CODECOV_TOKEN }} - name: Print failures if: failure() run: tests/run-tests.py --print-failures From 7b6130a7f30eca494321b3bd3ca27707272005b4 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 2 Jun 2026 22:01:53 +1000 Subject: [PATCH 443/635] nrf: Enable machine.mem_backup via POWER GPREGRET registers. Exposes NRF_POWER->GPREGRET and GPREGRET2 as two separate word-access regions (4 bytes each). Both registers survive soft reset and watchdog reset. On boards with a UF2/Adafruit bootloader, region 0 (GPREGRET) may be overwritten on bootloader entry. Signed-off-by: Andrew Leech --- ports/nrf/machine_mem_backup.c | 39 ++++++++++++++++++++++++++++++++++ ports/nrf/mpconfigport.h | 10 +++++++++ 2 files changed, 49 insertions(+) create mode 100644 ports/nrf/machine_mem_backup.c diff --git a/ports/nrf/machine_mem_backup.c b/ports/nrf/machine_mem_backup.c new file mode 100644 index 00000000000..8e79c15cc7c --- /dev/null +++ b/ports/nrf/machine_mem_backup.c @@ -0,0 +1,39 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. + +#include "nrf.h" + +// GPREGRET/GPREGRET2 retain only bits [7:0] (POWER_GPREGRET_GPREGRET_Msk = 0xFF). +// UF2/Adafruit bootloaders may overwrite region 0 on entry. nRF51 has no GPREGRET2. +static const mp_obj_array_t machine_mem_backup_regions[] = { + BACKUP_MV('B', 1, (void *)&NRF_POWER->GPREGRET), + #if !defined(NRF51) + BACKUP_MV('B', 1, (void *)&NRF_POWER->GPREGRET2), + #endif +}; diff --git a/ports/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h index 62e56fa1ebf..ae440bcc002 100644 --- a/ports/nrf/mpconfigport.h +++ b/ports/nrf/mpconfigport.h @@ -228,6 +228,16 @@ #endif #define MICROPY_PY_MACHINE_PWM (MICROPY_PY_MACHINE_HW_PWM || MICROPY_PY_MACHINE_SOFT_PWM) + +// nrf91 (Cortex-M33 with TrustZone) has POWER->GPREGRET as a 2-element array +// rather than separate GPREGRET/GPREGRET2 fields, and access requires the +// secure/non-secure peripheral split. Not supported here. +#if !defined(NRF91) +#ifndef MICROPY_PY_MACHINE_MEM_BACKUP +#define MICROPY_PY_MACHINE_MEM_BACKUP (1) +#endif +#define MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE "ports/nrf/machine_mem_backup.c" +#endif #define MICROPY_PY_MACHINE_PWM_DUTY (1) #if MICROPY_PY_MACHINE_HW_PWM From fafd20994295c85123d3ecb787be6624d81b421d Mon Sep 17 00:00:00 2001 From: Jim Mussared Date: Tue, 6 Jun 2023 23:09:58 +1000 Subject: [PATCH 444/635] windows/msvc/paths.props: Dont add variant path to PyIncDirs. This file is shared by mpy-cross.vcxproj, where PyVariant will be not set (because common.props explicitly doesn't set it when building mpy-cross). Update common.props to only add the variant path to PyIncDirs if not building mpy-cross. This work was funded through GitHub Sponsors. Signed-off-by: Jim Mussared --- ports/windows/msvc/common.props | 3 +++ ports/windows/msvc/paths.props | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/ports/windows/msvc/common.props b/ports/windows/msvc/common.props index b8d9096d67b..d49d5da72a0 100644 --- a/ports/windows/msvc/common.props +++ b/ports/windows/msvc/common.props @@ -19,6 +19,9 @@ $(PyBuildDir)copycookie$(Configuration)$(Platform) MultiByte + + $(PyIncDirs);$(PyVariantDir) + $(PyIncDirs);%(AdditionalIncludeDirectories) diff --git a/ports/windows/msvc/paths.props b/ports/windows/msvc/paths.props index a88182f4c95..e94e1f12f6a 100644 --- a/ports/windows/msvc/paths.props +++ b/ports/windows/msvc/paths.props @@ -31,8 +31,8 @@ $(PyWinDir)variants\$(PyVariant)\ $(PyBuildDir) - - $(PyIncDirs);$(PyBaseDir);$(PyWinDir);$(PyBuildDir);$(PyWinDir)msvc;$(PyVariantDir) + + $(PyIncDirs);$(PyBaseDir);$(PyWinDir);$(PyBuildDir);$(PyWinDir)msvc cebKaHwD1O6@7{bB9I1J68Rs_>ch_V(s_o`^6tlw@O22Zxmd6sQ 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MicroPython documentation

Quick reference for the ESP32
pinout for ESP32-based boards, snippets of useful code, and a tutorial

+

+ Quick reference for the PSOC™ Edge
+ general information for PSOC™ Edge based boards and snippets of useful code +

Quick reference for the Raspberry Pi RP2xxx
pinout for rp2xxx-based boards, snippets of useful code, and a tutorial From 533cea9d85f9e8254e6273fb498b3b2341631c24 Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Tue, 14 Jul 2026 17:06:56 +0200 Subject: [PATCH 493/635] lib/psoc-edge: Add psoc-edge submodules libs. Signed-off-by: jaenrig-ifx --- lib/psoc-edge/TARGET_KIT_PSE84_AI | 1 + lib/psoc-edge/async-transfer | 1 + lib/psoc-edge/core-lib | 1 + lib/psoc-edge/mtb-dsl-pse8xxgp | 1 + lib/psoc-edge/mtb-ipc | 1 + lib/psoc-edge/mtb-srf | 1 + lib/psoc-edge/se-rt-services-utils | 1 + lib/psoc-edge/serial-memory | 1 + 8 files changed, 8 insertions(+) create mode 160000 lib/psoc-edge/TARGET_KIT_PSE84_AI create mode 160000 lib/psoc-edge/async-transfer create mode 160000 lib/psoc-edge/core-lib create mode 160000 lib/psoc-edge/mtb-dsl-pse8xxgp create mode 160000 lib/psoc-edge/mtb-ipc create mode 160000 lib/psoc-edge/mtb-srf create mode 160000 lib/psoc-edge/se-rt-services-utils create mode 160000 lib/psoc-edge/serial-memory diff --git a/lib/psoc-edge/TARGET_KIT_PSE84_AI b/lib/psoc-edge/TARGET_KIT_PSE84_AI new file mode 160000 index 00000000000..41147b656e8 --- /dev/null +++ b/lib/psoc-edge/TARGET_KIT_PSE84_AI @@ -0,0 +1 @@ +Subproject commit 41147b656e87c9c195f243c39d8f5575909982c8 diff --git a/lib/psoc-edge/async-transfer b/lib/psoc-edge/async-transfer new file mode 160000 index 00000000000..d4d7f347f8b --- /dev/null +++ b/lib/psoc-edge/async-transfer @@ -0,0 +1 @@ +Subproject commit d4d7f347f8b5e3a7c8feb6089fa2ba3b9aba822c diff --git a/lib/psoc-edge/core-lib b/lib/psoc-edge/core-lib new file mode 160000 index 00000000000..b2a7ce7e3a9 --- /dev/null +++ b/lib/psoc-edge/core-lib @@ -0,0 +1 @@ +Subproject commit b2a7ce7e3a96265358cc3512c883befa24d0da06 diff --git a/lib/psoc-edge/mtb-dsl-pse8xxgp b/lib/psoc-edge/mtb-dsl-pse8xxgp new file mode 160000 index 00000000000..15d032bd4cd --- /dev/null +++ b/lib/psoc-edge/mtb-dsl-pse8xxgp @@ -0,0 +1 @@ +Subproject commit 15d032bd4cd1090a10f544a881ae7d0aa4869caf diff --git a/lib/psoc-edge/mtb-ipc b/lib/psoc-edge/mtb-ipc new file mode 160000 index 00000000000..760f4772bd4 --- /dev/null +++ b/lib/psoc-edge/mtb-ipc @@ -0,0 +1 @@ +Subproject commit 760f4772bd4b37abe08062d7229de91e9a23a54f diff --git a/lib/psoc-edge/mtb-srf b/lib/psoc-edge/mtb-srf new file mode 160000 index 00000000000..3c43b49a7e0 --- /dev/null +++ b/lib/psoc-edge/mtb-srf @@ -0,0 +1 @@ +Subproject commit 3c43b49a7e001836d63b60daa19d2616396e014a diff --git a/lib/psoc-edge/se-rt-services-utils b/lib/psoc-edge/se-rt-services-utils new file mode 160000 index 00000000000..5da80102ec1 --- /dev/null +++ b/lib/psoc-edge/se-rt-services-utils @@ -0,0 +1 @@ +Subproject commit 5da80102ec10b8a3e1676aed02073f7f9dcae3f5 diff --git a/lib/psoc-edge/serial-memory b/lib/psoc-edge/serial-memory new file mode 160000 index 00000000000..ae90b884dd1 --- /dev/null +++ b/lib/psoc-edge/serial-memory @@ -0,0 +1 @@ +Subproject commit ae90b884dd16959230c33e5368d18a09bee0df72 From 9120cb74bcf2790603b72968c894b4b7aa581a6a Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Tue, 10 Mar 2026 10:59:51 +0100 Subject: [PATCH 494/635] pyproject.yml: Add psoc-edge bsp generated code to ignore. Signed-off-by: jaenrig-ifx --- pyproject.toml | 1 + 1 file changed, 1 insertion(+) diff --git a/pyproject.toml b/pyproject.toml index 00f2faf260f..ef0a9a31174 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -15,6 +15,7 @@ skip = """ ./ports/cc3200/telnet,\ ./ports/esp32/managed_components,\ ./ports/nrf/drivers/bluetooth/s1*,\ +./ports/psoc-edge/boards/*/bsp-cfg,\ ./ports/stm32/usbhost,\ ./tests,\ ACKNOWLEDGEMENTS,\ From 8e7b3edcce9115371afeae6a09c11b140db13014 Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:04:54 +0200 Subject: [PATCH 495/635] README: Add psoc-edge port to TIER 2. Signed-off-by: jaenrig-ifx --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 46c6deddba7..51bd471e428 100644 --- a/README.md +++ b/README.md @@ -167,6 +167,7 @@ still fully supported: | [alif](ports/alif) | Alif Semiconductor Ensemble MCUs (E3, E7) | | | [embed](ports/embed) | Generates a set of .c/.h files for embedding into a project | | | [nrf](ports/nrf) | Nordic Semiconductor nRF51 and nRF52 | | +| [psoc-edge](ports/psoc-edge) | Infineon PSOC™ Edge | [here](https://docs.micropython.org/en/latest/psoc-edge/quickref.html) | | [renesas-ra](ports/renesas-ra) | Renesas RA family | [here](https://docs.micropython.org/en/latest/renesas-ra/quickref.html) | | [webassembly](ports/webassembly) | Emscripten port targeting browsers and NodeJS | | | [zephyr](ports/zephyr) | Zephyr RTOS | [here](https://docs.micropython.org/en/latest/zephyr/quickref.html) | From 5572640d6b29905bd4fbc6388761815d564b1cb2 Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:10:52 +0200 Subject: [PATCH 496/635] psoc-edge: Add PSOC Edge port basic enablement. The MicroPython application runs on CM33 core in non-secure mode. The core boot sequence requires the secure mode to start the non-secure mode. This minimal application is located in the secboot directory. The board bsp-cfg directory includes the PSOC Edge SDK generated sources for a given board support package. The following modules are already enabled: - time - VFS (LFS2) - machine.Pin - machine.UART - machine.RTC This enablement is a collective work of the following contributors: Co-authored-by: Damien George Co-authored-by: Eder Julian Co-authored-by: IFX-Anusha Co-authored-by: NikhitaR-IFX Co-authored-by: Ramya Subramanyam Co-authored-by: zhanglinjing Signed-off-by: jaenrig-ifx --- ports/psoc-edge/Makefile | 540 ++++++ ports/psoc-edge/README.md | 77 + .../psoc-edge/boards/KIT_PSE84_AI/board.json | 24 + .../KIT_PSE84_AI/bsp-cfg/PSE84_SMIF.FLM | Bin 0 -> 492716 bytes .../boards/KIT_PSE84_AI/bsp-cfg/cycfg.c | 53 + .../boards/KIT_PSE84_AI/bsp-cfg/cycfg.h | 66 + .../KIT_PSE84_AI/bsp-cfg/cycfg.timestamp | 27 + .../KIT_PSE84_AI/bsp-cfg/cycfg_clock_types.h | 27 + .../KIT_PSE84_AI/bsp-cfg/cycfg_clocks.c | 643 +++++++ .../KIT_PSE84_AI/bsp-cfg/cycfg_clocks.h | 123 ++ .../bsp-cfg/cycfg_connectivity_bt.h | 56 + .../bsp-cfg/cycfg_connectivity_wifi.h | 48 + .../boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.c | 193 +++ .../boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.h | 87 + .../KIT_PSE84_AI/bsp-cfg/cycfg_memory.h | 69 + .../KIT_PSE84_AI/bsp-cfg/cycfg_notices.h | 56 + .../bsp-cfg/cycfg_peripheral_clocks.c | 95 ++ .../bsp-cfg/cycfg_peripheral_clocks.h | 256 +++ .../KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.c | 1351 +++++++++++++++ .../KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.h | 367 ++++ .../boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.c | 1472 +++++++++++++++++ .../boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.h | 1213 ++++++++++++++ .../boards/KIT_PSE84_AI/bsp-cfg/cycfg_ppc.h | 489 ++++++ .../KIT_PSE84_AI/bsp-cfg/cycfg_protection.c | 46 + .../KIT_PSE84_AI/bsp-cfg/cycfg_protection.h | 46 + .../KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.c | 550 ++++++ .../KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.h | 76 + .../bsp-cfg/cycfg_qspi_memslot.timestamp | 25 + .../KIT_PSE84_AI/bsp-cfg/cycfg_routing.c | 37 + .../KIT_PSE84_AI/bsp-cfg/cycfg_routing.h | 85 + .../KIT_PSE84_AI/bsp-cfg/cycfg_system.c | 1169 +++++++++++++ .../KIT_PSE84_AI/bsp-cfg/cycfg_system.h | 172 ++ .../KIT_PSE84_AI/bsp-cfg/cymem_CM33_0.h | 92 ++ .../KIT_PSE84_AI/bsp-cfg/cymem_CM33_0_S.h | 134 ++ .../KIT_PSE84_AI/bsp-cfg/cymem_CM55_0.h | 45 + .../bsp-cfg/cymem_armlink_CM33_0.sct | 109 ++ .../bsp-cfg/cymem_armlink_CM33_0_S.sct | 173 ++ .../bsp-cfg/cymem_armlink_CM55_0.sct | 53 + .../KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0.ld | 157 ++ .../bsp-cfg/cymem_gnu_CM33_0_S.ld | 263 +++ .../KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM55_0.ld | 72 + .../bsp-cfg/cymem_ilinkarm_CM33_0.icf | 109 ++ .../bsp-cfg/cymem_ilinkarm_CM33_0_S.icf | 173 ++ .../bsp-cfg/cymem_ilinkarm_CM55_0.icf | 53 + .../bsp-cfg/cymem_ilinkarm_regions_CM33_0.icf | 66 + .../cymem_ilinkarm_regions_CM33_0_S.icf | 130 ++ .../bsp-cfg/cymem_ilinkarm_regions_CM55_0.icf | 28 + .../bsp-cfg/cymem_memory_locations.h | 65 + .../KIT_PSE84_AI/bsp-cfg/cymem_memory_types.h | 17 + .../bsp-cfg/design.cyqspi.memory-export | 13 + .../KIT_PSE84_AI/bsp-cfg/device_mem.json | 43 + .../bsp-cfg/edgeproctectsymbols.json | 273 +++ .../KIT_PSE84_AI/bsp-cfg/qspi_config.cfg | 29 + .../boards/KIT_PSE84_AI/mpconfigboard.h | 61 + .../boards/KIT_PSE84_AI/mpconfigboard.mk | 3 + ports/psoc-edge/boards/KIT_PSE84_AI/pins.csv | 243 +++ ports/psoc-edge/boards/deploy.md | 44 + ports/psoc-edge/boards/make-pins.py | 330 ++++ ports/psoc-edge/boards/manifest.py | 1 + ports/psoc-edge/boards/pse84_prefix.c | 24 + ports/psoc-edge/boards/pse8x_af.csv | 133 ++ ports/psoc-edge/clk.c | 314 ++++ ports/psoc-edge/clk.h | 42 + ports/psoc-edge/config/shift_ns.json | 29 + ports/psoc-edge/config/sign_s.json | 33 + ports/psoc-edge/config/sign_shift_merge.json | 83 + ports/psoc-edge/help.c | 42 + ports/psoc-edge/machine_pin.c | 558 +++++++ ports/psoc-edge/machine_pin.h | 56 + ports/psoc-edge/machine_pin_af.c | 56 + ports/psoc-edge/machine_pin_af.h | 83 + ports/psoc-edge/machine_pin_irq.c | 333 ++++ ports/psoc-edge/machine_rtc.c | 592 +++++++ ports/psoc-edge/machine_scb.c | 108 ++ ports/psoc-edge/machine_scb.h | 49 + ports/psoc-edge/machine_uart.c | 1034 ++++++++++++ ports/psoc-edge/main.c | 189 +++ ports/psoc-edge/modmachine.c | 78 + ports/psoc-edge/modmachine.h | 46 + ports/psoc-edge/modpsocedge.c | 50 + ports/psoc-edge/modpsocedge.h | 36 + ports/psoc-edge/modtime.c | 54 + ports/psoc-edge/modules/_boot.py | 23 + ports/psoc-edge/mpconfigport.h | 85 + ports/psoc-edge/mpconfigport.mk | 1 + ports/psoc-edge/mphalport.c | 183 ++ ports/psoc-edge/mphalport.h | 126 ++ ports/psoc-edge/psoc_edge_qspi_flash.c | 252 +++ ports/psoc-edge/qstrdefsport.h | 5 + ports/psoc-edge/secboot/Makefile | 204 +++ ports/psoc-edge/secboot/main.c | 104 ++ ports/psoc-edge/secboot/nsc_veneer.o | Bin 0 -> 296 bytes ports/psoc-edge/sys_int.c | 65 + ports/psoc-edge/sys_int.h | 56 + ports/psoc-edge/systick.c | 159 ++ ports/psoc-edge/tools/mp-ifx-flash.py | 378 +++++ 96 files changed, 17980 insertions(+) create mode 100644 ports/psoc-edge/Makefile create mode 100644 ports/psoc-edge/README.md create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/board.json create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/PSE84_SMIF.FLM create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg.timestamp create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_clock_types.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_clocks.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_clocks.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_connectivity_bt.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_connectivity_wifi.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_memory.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_notices.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripheral_clocks.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripheral_clocks.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_ppc.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_protection.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_protection.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.timestamp create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_routing.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_routing.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_system.c create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_system.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM33_0.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM33_0_S.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM55_0.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM33_0.sct create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM33_0_S.sct create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM55_0.sct create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0.ld create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0_S.ld create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM55_0.ld create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM33_0.icf create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM33_0_S.icf create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM55_0.icf create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM33_0.icf create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM33_0_S.icf create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM55_0.icf create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_memory_locations.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_memory_types.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/design.cyqspi.memory-export create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/device_mem.json create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/edgeproctectsymbols.json create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/qspi_config.cfg create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/mpconfigboard.h create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/mpconfigboard.mk create mode 100644 ports/psoc-edge/boards/KIT_PSE84_AI/pins.csv create mode 100644 ports/psoc-edge/boards/deploy.md create mode 100644 ports/psoc-edge/boards/make-pins.py create mode 100644 ports/psoc-edge/boards/manifest.py create mode 100644 ports/psoc-edge/boards/pse84_prefix.c create mode 100644 ports/psoc-edge/boards/pse8x_af.csv create mode 100644 ports/psoc-edge/clk.c create mode 100644 ports/psoc-edge/clk.h create mode 100644 ports/psoc-edge/config/shift_ns.json create mode 100644 ports/psoc-edge/config/sign_s.json create mode 100644 ports/psoc-edge/config/sign_shift_merge.json create mode 100644 ports/psoc-edge/help.c create mode 100644 ports/psoc-edge/machine_pin.c create mode 100644 ports/psoc-edge/machine_pin.h create mode 100644 ports/psoc-edge/machine_pin_af.c create mode 100644 ports/psoc-edge/machine_pin_af.h create mode 100644 ports/psoc-edge/machine_pin_irq.c create mode 100644 ports/psoc-edge/machine_rtc.c create mode 100644 ports/psoc-edge/machine_scb.c create mode 100644 ports/psoc-edge/machine_scb.h create mode 100644 ports/psoc-edge/machine_uart.c create mode 100644 ports/psoc-edge/main.c create mode 100644 ports/psoc-edge/modmachine.c create mode 100644 ports/psoc-edge/modmachine.h create mode 100644 ports/psoc-edge/modpsocedge.c create mode 100644 ports/psoc-edge/modpsocedge.h create mode 100644 ports/psoc-edge/modtime.c create mode 100644 ports/psoc-edge/modules/_boot.py create mode 100644 ports/psoc-edge/mpconfigport.h create mode 100644 ports/psoc-edge/mpconfigport.mk create mode 100644 ports/psoc-edge/mphalport.c create mode 100644 ports/psoc-edge/mphalport.h create mode 100644 ports/psoc-edge/psoc_edge_qspi_flash.c create mode 100644 ports/psoc-edge/qstrdefsport.h create mode 100644 ports/psoc-edge/secboot/Makefile create mode 100644 ports/psoc-edge/secboot/main.c create mode 100644 ports/psoc-edge/secboot/nsc_veneer.o create mode 100644 ports/psoc-edge/sys_int.c create mode 100644 ports/psoc-edge/sys_int.h create mode 100644 ports/psoc-edge/systick.c create mode 100644 ports/psoc-edge/tools/mp-ifx-flash.py diff --git a/ports/psoc-edge/Makefile b/ports/psoc-edge/Makefile new file mode 100644 index 00000000000..cf2b11eef01 --- /dev/null +++ b/ports/psoc-edge/Makefile @@ -0,0 +1,540 @@ +################################################################################ +# Initial setup of Makefile environment + +BOARD ?= KIT_PSE84_AI +BOARD_DIR ?= boards/$(BOARD) +BUILD ?= build-$(BOARD) + +ifeq ($(wildcard $(BOARD_DIR)/.),) +$(error Invalid BOARD specified: $(BOARD_DIR)) +endif + +# qstr definitions (must come before including py.mk). +QSTR_DEFS += qstrdefsport.h +QSTR_GLOBAL_DEPENDENCIES += $(BOARD_DIR)/mpconfigboard.h + +# Frozen manifest for VFS support +FROZEN_MANIFEST ?= boards/manifest.py + +ifneq ($(FROZEN_MANIFEST),) + CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool + CFLAGS += -DMICROPY_MODULE_FROZEN_MPY=1 + CFLAGS += -DMICROPY_MODULE_FROZEN_STR=1 +endif + +# Include the core environment definitions; this will set $(TOP). +include ../../py/mkenv.mk + +# Port and board specific make settings. +include mpconfigport.mk +include $(BOARD_DIR)/mpconfigboard.mk + +# Include py core make definitions. +include $(TOP)/py/py.mk +include $(TOP)/extmod/extmod.mk + +################################################################################ +# Project specific settings and compiler/linker flags + +# Required git submodules. +GIT_SUBMODULES += lib/CMSIS_6 +GIT_SUBMODULES += $(addprefix lib/psoc-edge/,\ + async-transfer \ + core-lib \ + mtb-dsl-pse8xxgp \ + mtb-ipc \ + mtb-srf \ + se-rt-services-utils \ + serial-memory \ + TARGET_KIT_PSE84_AI \ +) + +# Define toolchain and other tools. +CROSS_COMPILE ?= arm-none-eabi- +EDGEPROTECTTOOLS ?= edgeprotecttools +OPENOCD ?= openocd + +# SDK locations. +PSE_LIB_TOP_DIR ?= lib/psoc-edge +PSE_LIB_DIR ?= $(TOP)/$(PSE_LIB_TOP_DIR) + +################################################################################ +# Pin generation + +HEADER_BUILD := $(BUILD)/genhdr +MAKE_PINS = boards/make-pins.py +BOARD_PINS = $(BOARD_DIR)/pins.csv +AF_FILE = boards/pse8x_af.csv +PREFIX_FILE = boards/pse84_prefix.c +GEN_PINS_SRC = $(BUILD)/pins_$(BOARD).c +GEN_PINS_HDR = $(HEADER_BUILD)/pins.h +GEN_PINS_AF_HDR= $(HEADER_BUILD)/pins_af.h + +# Making OBJ use an order-only dependency on the generated pins.h file +# has the side effect of making the pins.h file before we actually compile +# any of the objects. The normal dependency generation will deal with the +# case when pins.h is modified. But when it doesn't exist, we don't know +# which source files might need it. +$(OBJ): | $(GEN_PINS_HDR) + +# With conditional pins, we may need to regenerate qstrdefs.h when config +# options change. +$(HEADER_BUILD)/qstrdefs.generated.h: $(BOARD_DIR)/mpconfigboard.h + +# Use a pattern rule here so that make will only call make-pins.py once to make +# both pins_$(BOARD).c and pins.h +$(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h : $(BOARD_DIR)/%.csv $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD) + $(ECHO) "GEN $@" + $(Q)$(PYTHON) $(MAKE_PINS) --board-csv $(BOARD_PINS) --af-csv $(AF_FILE) --prefix $(PREFIX_FILE) \ + --output-source $(GEN_PINS_SRC) --output-header $(GEN_PINS_HDR) --output-af-header $(GEN_PINS_AF_HDR) + +################################################################################# +# libs source files and libraries + +INC += $(addprefix -I$(TOP)/lib/,\ + CMSIS_6/CMSIS/Core/Include \ + CMSIS_6/CMSIS/Core/Include/a-profile \ + CMSIS_6/CMSIS/Core/Include/m-profile \ + CMSIS_6/CMSIS/Core/Include/r-profile \ +) + +################################################################################# +# PSOC Edge source files and libraries + +DEFINES = \ + -DCOMPONENT_CM33 \ + -DCORE_NAME_CM33_0=1 \ + -DCOMPONENT_MTB_HAL \ + -DCOMPONENT_MW_ASYNC_TRANSFER \ + -DCOMPONENT_MW_MTB_IPC \ + -DCOMPONENT_MW_MTB_SRF \ + -DCOMPONENT_NON_SECURE_DEVICE \ + -DCYBSP_MCUBOOT_HEADER_SIZE=0x400 \ + +INC += $(addprefix -I$(PSE_LIB_DIR)/,\ + async-transfer/include \ + \ + core-lib/include \ + \ + mtb-dsl-pse8xxgp/device-utils/syspm/hobto/pdm_pcm/audioss_pdm \ + mtb-dsl-pse8xxgp/device-utils/syspm/hobto/pdm_pcm/mxpdm \ + mtb-dsl-pse8xxgp/device-utils/syspm/include \ + \ + mtb-dsl-pse8xxgp/hal/include \ + \ + mtb-dsl-pse8xxgp/nnkernel/COMPONENT_CM33/include \ + \ + mtb-dsl-pse8xxgp/pdl/devices/include \ + mtb-dsl-pse8xxgp/pdl/devices/include/ip \ + mtb-dsl-pse8xxgp/pdl/drivers/include \ + mtb-dsl-pse8xxgp/pdl/drivers/third_party/ethernet/include \ + \ + mtb-ipc/include \ + \ + mtb-srf/include \ + mtb-srf/include/COMPONENT_NON_SECURE_DEVICE \ + mtb-srf/include/COMPONENT_NON_SECURE_DEVICE/COMPONENT_MW_MTB_IPC \ + \ + serial-memory/include \ + \ + se-rt-services-utils \ + \ + TARGET_$(BOARD) \ + TARGET_$(BOARD)/bluetooth \ + ) + +INC += \ + -I$(BOARD_DIR) \ + -I$(BOARD_DIR)/bsp-cfg \ + -Idualcore/include + +MACHINE_FLAGS = \ + -mcpu=cortex-m33 \ + --specs=nano.specs \ + --specs=nosys.specs \ + -mfloat-abi=hard \ + -mfpu=fpv5-sp-d16 \ + -mthumb + +CFLAGS += -c $(MACHINE_FLAGS) \ + -ffat-lto-objects \ + -g \ + -Wall \ + -pipe \ + $(DEFINES) \ + +# Increase the default stack size from (4 KB) to (16 KB). +APP_MSP_STACK_SIZE ?= 0x4000 + +LDFLAGS += $(MACHINE_FLAGS) \ + -Wl,--gc-sections \ + -Wl,--print-memory-usage \ + -Wl,--defsym=APP_MSP_STACK_SIZE=$(APP_MSP_STACK_SIZE) \ + -Xlinker -L $(PSE_LIB_DIR)/TARGET_$(BOARD)/COMPONENT_CM33/TOOLCHAIN_GCC_ARM \ + -Xlinker -L $(BOARD_DIR)/bsp-cfg \ + -T$(PSE_LIB_DIR)/TARGET_$(BOARD)/COMPONENT_CM33/TOOLCHAIN_GCC_ARM/pse84_ns_cm33.ld \ + -Wl,-Map,$(BUILD)/firmware.map \ + +PSE_BSP_CFG_C += $(addprefix $(BOARD_DIR)/bsp-cfg/,\ + cycfg.c \ + cycfg_clocks.c \ + cycfg_dmas.c \ + cycfg_peripheral_clocks.c \ + cycfg_peripherals.c \ + cycfg_pins.c \ + cycfg_protection.c \ + cycfg_qspi_memslot.c \ + cycfg_routing.c \ + cycfg_system.c \ + ) + +PSE_LIB_SRC_C += $(addprefix $(PSE_LIB_TOP_DIR)/, \ + async-transfer/source/mtb_async_transfer.c \ + \ + mtb-dsl-pse8xxgp/device-utils/syspm/source/mtb_syspm_callbacks_scb_uart.c \ + \ + mtb-dsl-pse8xxgp/hal/source/mtb_hal_clock.c \ + mtb-dsl-pse8xxgp/hal/source/mtb_hal_gpio.c \ + mtb-dsl-pse8xxgp/hal/source/mtb_hal_system.c \ + mtb-dsl-pse8xxgp/hal/source/mtb_hal_timer.c \ + mtb-dsl-pse8xxgp/hal/source/mtb_hal_uart.c \ + mtb-dsl-pse8xxgp/hal/source/mtb_hal_utils_impl.c \ + \ + mtb-dsl-pse8xxgp/pdl/devices/source/cy_device.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_gpio.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_ipc_drv.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_ipc_pipe.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_ipc_sema.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_pdm_pcm_v2.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_rtc.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_scb_common.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_scb_i2c.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_scb_uart.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_smif.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_smif_hb_flash.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_smif_memnum.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_smif_memslot.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_smif_sfdp.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_sysclk_v2.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_sysint_v2.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_syslib.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_syspm_pdcm.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_syspm_ppu.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_syspm_v4.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_systick_v2.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_tcpwm_counter.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/ppu_v1.c \ + \ + mtb-dsl-pse8xxgp/support/source/mtb_stdlib_stubs.c \ + \ + mtb-ipc/source/mtb_ipc.c \ + \ + mtb-srf/source/COMPONENT_NON_SECURE_DEVICE/mtb_srf_pool.c \ + mtb-srf/source/COMPONENT_NON_SECURE_DEVICE/COMPONENT_MW_MTB_IPC/mtb_srf_ipc.c \ + \ + serial-memory/source/mtb_serial_memory.c \ + \ + TARGET_$(BOARD)/cybsp.c \ + TARGET_$(BOARD)/system_edge.c \ + TARGET_$(BOARD)/COMPONENT_CM33/COMPONENT_NON_SECURE_DEVICE/ns_start_pse84.c \ + TARGET_$(BOARD)/COMPONENT_CM33/COMPONENT_NON_SECURE_DEVICE/ns_system_pse84.c \ + ) + +PSE_SRC_ASM = $(PSE_LIB_TOP_DIR)/mtb-dsl-pse8xxgp/pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S \ + +PSE_SRC_O = secboot/nsc_veneer.o + +OBJ += $(PSE_SRC_O) +OBJ += $(addprefix $(BUILD)/, $(PSE_BSP_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(PSE_BSP_CFG_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(PSE_LIB_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(PSE_SRC_ASM:.S=.o)) + +################################################################################ +# MicroPython source files and libraries + +INC += -I. +INC += -I$(TOP) +INC += -I$(BUILD) + +CFLAGS += $(INC) + +# Select debugging or optimisation build. +ifeq ($(DEBUG), 1) +CFLAGS += -Og +else +CFLAGS += -Os -DNDEBUG +CFLAGS += -fdata-sections -ffunction-sections +endif + +AFLAGS = -mthumb -march=armv8.1-m.main+fp+mve.fp + +LDFLAGS += + +LIBS += -lm + +# PSOC Edge uses Cortex-M33 and Cortex-M55 (ARMv8-M architecture) +# However, since ARMv8-M is not directly supported by mpy-cross, +# we use armv7emsp as the closest compatible architecture +MPY_CROSS_FLAGS += -march=armv7emsp + +SRC_O += \ + shared/runtime/gchelper_thumb2.o \ + +SHARED_SRC_C += $(addprefix shared/,\ + readline/readline.c \ + \ + runtime/gchelper_native.c \ + runtime/interrupt_char.c \ + runtime/mpirq.c \ + runtime/pyexec.c \ + runtime/stdout_helpers.c \ + runtime/sys_stdio_mphal.c \ + \ + timeutils/timeutils.c \ + ) + +MOD_SRC_C += \ + machine_pin.c \ + machine_pin_af.c \ + machine_pin_irq.c \ + machine_rtc.c \ + modpsocedge.c \ + machine_scb.c \ + +ifeq ($(MICROPY_PY_EXT_FLASH),1) + CFLAGS += -DMICROPY_ENABLE_EXT_QSPI_FLASH=1 + MOD_SRC_C += psoc_edge_qspi_flash.c +endif + +SRC_C += \ + clk.c \ + help.c \ + main.c \ + mphalport.c \ + systick.c \ + sys_int.c \ + +# List of sources for qstr extraction +SRC_QSTR += $(SRC_C) $(SHARED_SRC_C) $(MOD_SRC_C) $(GEN_PINS_SRC) + +# Define the required object files. +OBJ += $(PY_O) +OBJ += $(addprefix $(BUILD)/, $(SRC_O)) +OBJ += $(addprefix $(BUILD)/, $(LIBM_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(SHARED_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(MOD_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) +OBJ += $(GEN_PINS_SRC:.c=.o) + +################################################################################ +# Secondary targets + +## Secure targets +## +## Build, sign and flash separately +## the secure boot hex. + +build_s: $(BUILD)/secboot/secboot.hex + +$(BUILD)/secboot/secboot.hex: + $(Q)$(MAKE) -C secboot BOARD=$(BOARD) BUILD=$(abspath $(BUILD)/secboot) + +deploy_s: $(BUILD)/secboot/secboot.signed.hex + $(call flash_target,$<) + +sign_s: $(BUILD)/secboot/secboot.signed.hex +$(BUILD)/secboot/secboot.signed.hex: $(BUILD)/secboot/secboot.hex + @echo "Reallocating hex file..." + @$(EDGEPROTECTTOOLS) run-config -i config/sign_s.json \ + --set s_hex $^ \ + --set s_signed_hex $@ \ + --symbol-search $(BOARD_DIR)/bsp-cfg + +clean_s: + $(Q)$(MAKE) -C secboot BOARD=$(BOARD) BUILD=$(abspath $(BUILD)/secboot) clean + +.PHONY: build_s sign_s deploy_s clean_s + +## Non-secure targets +## +## Build, shift and deploy separately +## the non-secure hex file when the secure hex +## is already build, signed and flashed in the +## device + +build_ns: $(BUILD)/firmware.unshifted.hex + +shift_ns: $(BUILD)/firmware.shifted.hex +$(BUILD)/firmware.shifted.hex: $(BUILD)/firmware.unshifted.hex + @echo "Reallocating hex file..." + @$(EDGEPROTECTTOOLS) run-config -i config/shift_ns.json \ + --set ns_hex $^ \ + --set ns_shifted_hex $@ \ + --symbol-search $(BOARD_DIR)/bsp-cfg + +deploy_ns: $(BUILD)/firmware.shifted.hex + $(call flash_target,$<) + +.PHONY: build_ns shift_ns deploy_ns + +## Openocd reusable flashing target + +# Deploy on an specific serial device if passed +ifndef DEV_SERIAL_NUMBER +SERIAL_ADAPTER_CMD = +else +SERIAL_ADAPTER_CMD = -c "adapter serial $(DEV_SERIAL_NUMBER)" +endif + +FLM_FILE = $(BOARD_DIR)/bsp-cfg/PSE84_SMIF.FLM +QSPI_CFG_FILE = $(BOARD_DIR)/bsp-cfg/qspi_config.cfg + +OPENOCD_OPEN_CMDS = \ + -s $(BOARD_DIR)/bsp-cfg \ + -c "set QSPI_FLASHLOADER $(FLM_FILE)" \ + -c "source [find interface/kitprog3.cfg]" \ + $(SERIAL_ADAPTER_CMD) \ + -c "transport select swd" \ + -c "source [find target/infineon/pse84xgxs2.cfg]" \ + -c "init" \ + -c "reset init" \ + -c "adapter speed 12000" \ + +OPENOCD_CLOSE_CMDS = \ + -c "reset run; shutdown" \ + + +define flash_target + $(Q)$(OPENOCD) \ + $(OPENOCD_OPEN_CMDS) \ + -c "flash write_image erase $(1)" \ + -c "verify_image $(1)" \ + $(OPENOCD_CLOSE_CMDS) +endef + +## Multiple devices deploy targets +## +## Supports test and CI HIL operations. + +ifndef EXT_HEX_FILE +HEX_FILE = $(BUILD)/firmware.hex +else +HEX_FILE = $(EXT_HEX_FILE) +endif + +qdeploy: + $(call flash_target,$(HEX_FILE)) + +# When multiple types of boards are connected, a devs file needs to be provided. +# When working locally, if a "local-devs.yml" file is placed in "tools/psoc-edge" +# it will be used +ifneq ($(DEVS_FILE),) +MULTI_BOARD_DEVS_OPTS = -f name=$(BOARD) --devs-yml $(DEVS_FILE) +else +DFLT_LOCAL_DEVS_FILE_NAME = local-devs.yml +LOCAL_DEVS_FILE=$(TOP)/tools/psoc-edge/$(DFLT_LOCAL_DEVS_FILE_NAME) +ifneq (,$(wildcard $(LOCAL_DEVS_FILE))) +MULTI_BOARD_DEVS_OPTS = -f name=$(BOARD) --devs-yml $(LOCAL_DEVS_FILE) +endif +endif + +attached_devs: + @: + $(eval ATTACHED_TARGET_LIST = $(shell etdevs-query serial_number $(MULTI_BOARD_DEVS_OPTS))) + $(eval ATTACHED_TARGETS_NUMBER = $(words $(ATTACHED_TARGET_LIST))) + $(info Number of attached targets : $(ATTACHED_TARGETS_NUMBER)) + $(info List of attached targets : $(ATTACHED_TARGET_LIST)) + +qdeploy_multi: attached_devs + $(foreach ATTACHED_TARGET, $(ATTACHED_TARGET_LIST), $(MAKE) qdeploy DEV_SERIAL_NUMBER=$(ATTACHED_TARGET);) + +deploy_multi: all qdeploy_multi + +.PHONY: qdeploy qdeploy_multi deploy_multi attached_devs + +################################################################################ +# Main targets + +all: $(BUILD)/firmware.hex $(BUILD)/firmware.zip + +$(BUILD)/firmware.unshifted.elf: $(OBJ) + $(ECHO) "Link $@" + @$(Q)$(CC) $(LDFLAGS) -o $@ $(OBJ) $(LIBS) + @$(Q)$(SIZE) $@ + +$(BUILD)/firmware.unshifted.hex: $(BUILD)/firmware.unshifted.elf + $(ECHO) "Create $@" + @$(Q)$(OBJCOPY) -O ihex $^ $@ + +sign_merge: $(BUILD)/firmware.hex +$(BUILD)/firmware.hex: $(BUILD)/secboot/secboot.hex $(BUILD)/firmware.unshifted.hex + @echo "Signing and combining hex files..." + @$(EDGEPROTECTTOOLS) run-config -i config/sign_shift_merge.json \ + --set s_hex $(word 1,$^) \ + --set s_signed_hex $(BUILD)/secboot/secboot.signed.hex \ + --set ns_hex $(word 2,$^) \ + --set ns_shifted_hex $(BUILD)/firmware.shifted.hex \ + --set signed_merged_hex $@ \ + --symbol-search $(BOARD_DIR)/bsp-cfg + +deploy: $(BUILD)/firmware.hex + $(call flash_target,$<) + +zip: $(BUILD)/firmware.zip +$(BUILD)/firmware.zip: $(BUILD)/firmware.hex $(FLM_FILE) $(QSPI_CFG_FILE) + $(ECHO) "Create $@" + $(Q)$(ZIP) -q -j $@ $^ + +.PHONY: all sign_merge deploy zip + +############################################################################### +# Help target + +help: + @: + $(info ) + $(info Main targets:) + $(info ) + $(info all Build the MicroPython firmware) + $(info submodules Initialize port required port submodules) + $(info deploy Deploy the MicroPython firmware on the board) + $(info clean Remove the board build directory) + $(info help Show this help message) + $(info ) + $(info Secondary targets:) + $(info ) + $(info build_s Build separately the secure boot signed firmware) + $(info deploy_s Deploy separately the secure boot signed firmware) + $(info clean_s Remove the secure boot build directory) + $(info build_ns Build separately the non secure firmware.) + $(info deploy_ns Deploy separately the non secure shifted firmware) + $(info sign_s Sign the secure boot firmware) + $(info shift_ns Reallocate the non secure firmware ) + $(info sign_merge Sign the secure boot firmware, reallocate the non) + $(info .. secure firmware, and merge them into a single file) + $(info ) + $(info Test and CI support targets:) + $(info ) + $(info qdeploy Deploy the MicroPython firmware without rebuilding) + $(info qdeploy_multi Deploy the MicroPython firmware on multiple devices) + $(info .. without rebuilding) + $(info deploy_multi Deploy the MicroPython firmware on multiple devices) + $(info ) + $(info Options for build targets:) + $(info - BOARD Target PSOC Edge MicroPython board) + $(info ) + $(info Options for deploy targets:) + $(info - DEV_SERIAL_NUMBER Serial number of the target to program) + $(info .. when multiple devices are connected) + $(info - EXT_HEX_FILE An external .hex file can be provided to the deploy) + $(info .. targets, instead of building from the sources) + $(info ) + +.PHONY: help + +################################################################################ +# Remaining make rules + +# Include remaining core make rules. +include $(TOP)/py/mkrules.mk diff --git a/ports/psoc-edge/README.md b/ports/psoc-edge/README.md new file mode 100644 index 00000000000..e10d784755e --- /dev/null +++ b/ports/psoc-edge/README.md @@ -0,0 +1,77 @@ +# PSOC™ Edge port + +This port is intended to run on PSOC™ Edge microcontrollers. + +## Build environment + +Install the following tools on your Linux host machine: + + - An ARM cross compiler such as `arm-none-eabi-gcc` and associated binary utilities and libc. The minimum required version is 14.2.1. + + Download the [Infineon MTB GCC package](https://softwaretools.infineon.com/tools/com.ifx.tb.tool.mtbgccpackage) and install it with the command: + + sudo apt install ./mtbgccpackage_14.2.1.265_Linux_x64.deb + + Alternatively, you can also install the `gcc-arm-none-eabi` official package: + + sudo apt-get install gcc-arm-none-eabi libnewlib-arm-none-eabi + +- [edgeprotecttools](https://github.com/Infineon/edgeprotecttools/). The minimum required version is 1.6.0. + + It can be installed from PyPi via `pip`: + + sudo pip install edgeprotecttools + +- [Infineon OpenOCD](https://github.com/Infineon/openocd). Download the latest [release](https://github.com/Infineon/openocd/releases) manually or via `wget`. The minimum required version is v5.8.0. For example: + + wget -O openocd.tar.gz https://github.com/Infineon/openocd/releases/download/release-v5.16.1/openocd-5.16.1.4486-linux.tar.gz + + And unarchive it in the desired location. For example, in the `/opt/openocd` dir: + + mkdir -p /opt/openocd + tar -xzf openocd.tar.gz -C /opt/openocd --strip-components=1 + +### Setting up the environment + +Make sure that `arm-none-eabi-gcc`, `edgeprotecttools` and `openocd` are added to the system `PATH`. + +## Building and running on Linux + +Before building the firmware for a given board the MicroPython cross-compiler +must be built; it will be used to pre-compile some of the built-in scripts to +bytecode. The cross-compiler is built and run on the host machine, using: + + make -C mpy-cross + +The following build commands should be run from the `ports/psoc-edge` directory: + +Retrieve submodules: + + make submodules + +Build the firmware: + + make BOARD=KIT_PSE84_AI + +And flash it to the board: + + make deploy + +> [!NOTE] +> This will also build the firmware if it has not been built yet. +> Use `qdeploy` target to avoid rebuilding the firmware. + +If you have multiple boards connected, you can specify the serial number of the board to be programmed: + + make deploy DEV_SERIAL_NUMBER=123456 + +Find more information about all the available makefile targets: + + make help +----------------------------------------------------- + +# Run micropython + +Use any serial terminal (e.g. putty, minicom..) and establish a session with your device with +115200 bauds and 8-N-1 configuration. + diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/board.json b/ports/psoc-edge/boards/KIT_PSE84_AI/board.json new file mode 100644 index 00000000000..7071b44c51f --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/board.json @@ -0,0 +1,24 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [ + "BLE", + "Dual-core", + "External Flash", + "WiFi", + "Microphone", + "IMU", + "RGB LED", + "USB-C" + ], + "images": [ + "kit_pse84_ai.jpg" + ], + "mcu": "PSE846GPS2DBZC4", + "product": "KIT_PSE84_AI", + "thumbnail": "", + "url": "https://www.infineon.com/evaluation-board/kit-pse84-ai", + "vendor": "Infineon Technologies" +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/PSE84_SMIF.FLM b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/PSE84_SMIF.FLM new file mode 100644 index 0000000000000000000000000000000000000000..0b2a0915db09bdda180e39f36496a5ba825e044a GIT binary patch literal 492716 zcmeFZdwf*Y)jz!VIcH{0W+utx1_=Z>lM75BN&=_>Q71E#lL-WfTr5_s6F{6G)#0WA zQBJtnh|neo8ZPlkTib$SO@g#U#RTv!^qpwz6D^i``q+jfw$B*?&LOw?efLc8(&zTR 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z9GQjI_CnO?Wpb=oP^;JBw(1bC?GDhY=#H_hx8mb296n8LIBH#N!Tr!6Tskv3TnhWO zIzIb7{@m)~mE#Au2LHSRf2kazV=&*T zA%+m*;JBY#?ZF-Rq;j|5mttzX>vv3C4NLQ0gO2aQFO_pYFFu>e{Nz0jdG5Us$#O4z z8{s*Wax@fK?)yJPjHma|D9n%JJ_P8Fi8=W52Qt6>SvoR5jw=JYV`Ap69moW)n=iXt*Vm&E9CSi_p1*RC<0Lzgvm3(U42`c( 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + + /* Enable all source clocks */ + Cy_SysClk_PiloInit(); + Cy_SysClk_WcoInit(); + Cy_SysClk_EcoInit(); + Cy_SysClk_ClkLfInit(); + Cy_SysClk_ExtClkInit(); + + /* Configure the path clocks, except for the fail-safe bypass for the IHO/IMO */ + for (uint32_t i = 0; i < CY_SRSS_NUM_CLKPATH; i++) + { + if (i != CY_CFG_SYSCLK_FIRST_CLKPATH_DIRECT) { + Cy_SysClk_ClkPathSetSource(i, cycfg_clkpath_configs[i]); + } + } + + /* Configure PLL clocks */ + + /* Configure the HF clocks, excluding the HF clock of the active core */ + for (uint32_t i = 0U; i < CY_SRSS_NUM_HFROOT; i++) + { + if (i != CY_CFG_SYSCLK_ACTIVE_CORE_HF) { + const cycfg_clkhf_config_t *hfConfig = cycfg_clkhf_configs[i]; + if (hfConfig != NULL) { + cycfg_SysClk_ClkHfInit(i, hfConfig->source, hfConfig->divider); + } + } + } + /* Configure miscellaneous clocks */ + Cy_SysClk_ClkBakInit(); + Cy_SysClk_Dpll_Hp0_Init(); + #ifdef UPDATE_DPLL_LP_TRIM_VALUES + /* Workaround: update DPLL_LP trim values */ + CY_SET_REG32(0x52403218, 0x921F190A); /* DPLL_LP0_TEST3 */ + CY_SET_REG32(0x5240321C, 0x08100000); /* DPLL_LP0_TEST4 */ + #endif + Cy_SysClk_Dpll_Lp0_Init(); + #ifdef UPDATE_DPLL_LP_TRIM_VALUES + /* Workaround: update DPLL_LP trim values */ + CY_SET_REG32(0x52403238, 0x921F190A); /* DPLL_LP1_TEST3 */ + CY_SET_REG32(0x5240323C, 0x08100000); /* DPLL_LP1_TEST4 */ + #endif + Cy_SysClk_Dpll_Lp1_Init(); + /* Configure HF0 clock and disable any unused HF clocks */ + for (uint32_t i = 0U; i < CY_SRSS_NUM_HFROOT; i++) + { + const cycfg_clkhf_config_t *hfConfig = cycfg_clkhf_configs[i]; + if (hfConfig != NULL) { + if (i == CY_CFG_SYSCLK_ACTIVE_CORE_HF) { + cycfg_SysClk_ClkHfInit(i, hfConfig->source, hfConfig->divider); + } + } else { + (void)Cy_SysClk_ClkHfDisable(i); + } + } + /* Configure the path clocks used for the fail-safe bypass for the IHO/IMO */ + Cy_SysClk_ClkPathSetSource(CY_CFG_SYSCLK_FIRST_CLKPATH_DIRECT, cycfg_clkpath_configs[CY_CFG_SYSCLK_FIRST_CLKPATH_DIRECT]); + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + /* Configure default enabled clocks */ + /* Disable unused clock sources */ + /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */ + Cy_SysLib_DelayUs(200U); + + /* Update System configuration based on clock configuration */ + SystemCoreClockUpdate(); + + /* Configure clock supervisors */ + for (uint32_t i = 0U; i < CY_SRSS_NUM_HFROOT; i++) + { + const cycfg_clkhf_csv_config_t *hfCsvConfig = cycfg_clkhf_csv_configs[i]; + if (hfCsvConfig != NULL) { + cycfg_SysClk_ClkHfCsvInit(i, hfCsvConfig->refClk, hfCsvConfig->accuracy, hfCsvConfig->action); + } else { + Cy_SysClk_ClkHfCsvDisable(i); + } + } + + +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_clocks.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_clocks.h new file mode 100644 index 00000000000..18855bfc7cc --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_clocks.h @@ -0,0 +1,123 @@ +/******************************************************************************* + * File Name: cycfg_clocks.h + * + * Description: + * Clock configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" +#include "cycfg_clock_types.h" +#include "cy_rtc.h" +#include "cy_gpio.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define CYBSP_RTC_ENABLED 1U +#define CYBSP_RTC_10_MONTH_OFFSET (28U) +#define CYBSP_RTC_MONTH_OFFSET (24U) +#define CYBSP_RTC_10_DAY_OFFSET (20U) +#define CYBSP_RTC_DAY_OFFSET (16U) +#define CYBSP_RTC_1000_YEAR_OFFSET (12U) +#define CYBSP_RTC_100_YEAR_OFFSET (8U) +#define CYBSP_RTC_10_YEAR_OFFSET (4U) +#define CYBSP_RTC_YEAR_OFFSET (0U) +#define srss_0_clock_0_eco_0_ENABLED 1U +#define srss_0_clock_0_ext_0_ENABLED 1U +#define srss_0_clock_0_iho_0_ENABLED 1U +#define srss_0_clock_0_wco_0_ENABLED 1U +#define srss_0_clock_0_timerclk_0_ENABLED 1U +#define srss_0_clock_0_pilo_0_ENABLED 1U +#define srss_0_clock_0_lfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_PILO +#define srss_0_clock_0_pathmux_0_ENABLED 1U +#define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_pathmux_2_ENABLED 1U +#define srss_0_clock_0_pathmux_3_ENABLED 1U +#define srss_0_clock_0_pathmux_4_ENABLED 1U +#define srss_0_clock_0_pathmux_5_ENABLED 1U +#define srss_0_clock_0_bakclk_0_ENABLED 1U +#define srss_0_clock_0_pll250m_0_ENABLED 1U +#define srss_0_clock_0_pll250m_1_ENABLED 1U +#define srss_0_clock_0_pll500m_0_ENABLED 1U +#define srss_0_clock_0_hfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF0 0UL +#define srss_0_clock_0_hfclk_1_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF1 1UL +#define srss_0_clock_0_hfclk_2_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF2 2UL +#define srss_0_clock_0_hfclk_3_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF3 3UL +#define srss_0_clock_0_hfclk_4_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF4 4UL +#define srss_0_clock_0_hfclk_5_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF5 5UL +#define srss_0_clock_0_hfclk_6_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF6 6UL +#define srss_0_clock_0_hfclk_7_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF7 7UL +#define srss_0_clock_0_hfclk_8_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF8 8UL +#define srss_0_clock_0_hfclk_9_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF9 9UL +#define srss_0_clock_0_hfclk_10_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF10 10UL +#define srss_0_clock_0_hfclk_11_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF11 11UL +#define srss_0_clock_0_hfclk_12_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF12 12UL +#define srss_0_clock_0_hfclk_13_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF13 13UL + +extern const cy_stc_rtc_config_t CYBSP_RTC_config; +extern const cycfg_clkhf_config_t cycfg_hf0Config; +extern const cycfg_clkhf_config_t cycfg_hf1Config; +extern const cycfg_clkhf_config_t cycfg_hf2Config; +extern const cycfg_clkhf_config_t cycfg_hf3Config; +extern const cycfg_clkhf_config_t cycfg_hf4Config; +extern const cycfg_clkhf_config_t cycfg_hf5Config; +extern const cycfg_clkhf_config_t cycfg_hf6Config; +extern const cycfg_clkhf_config_t cycfg_hf7Config; +extern const cycfg_clkhf_config_t cycfg_hf8Config; +extern const cycfg_clkhf_config_t cycfg_hf9Config; +extern const cycfg_clkhf_config_t cycfg_hf10Config; +extern const cycfg_clkhf_config_t cycfg_hf11Config; +extern const cycfg_clkhf_config_t cycfg_hf12Config; +extern const cycfg_clkhf_config_t cycfg_hf13Config; + +void init_cycfg_ns_clocks(void); +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_CLOCKS_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_connectivity_bt.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_connectivity_bt.h new file mode 100644 index 00000000000..b61fbba9c03 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_connectivity_bt.h @@ -0,0 +1,56 @@ +/******************************************************************************* + * File Name: cycfg_connectivity_bt.h + * + * Description: + * Connectivity BT configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_BT_H) +#define CYCFG_CONNECTIVITY_BT_H + +#include "cycfg_notices.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define bt_0_power_0_ENABLED 1U +#define CYCFG_BT_LP_ENABLED (1u) +#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0) +#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1) +#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE_HAL_PORT_PIN +#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH +#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN +#define CYCFG_BT_DEV_WAKE_POLARITY CYCFG_BT_WAKE_EVENT_ACTIVE_LOW +#define CYCFG_BT_HOST_WAKE_PORT_NUM CYBSP_BT_HOST_WAKE_HAL_PORT_PIN +#define CYCFG_BT_HOST_WAKE_PIN CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH +#define CYCFG_BT_DEVICE_WAKE_PORT_NUM CYBSP_BT_HOST_WAKE_HAL_PORT_PIN +#define CYCFG_BT_DEVICE_WAKE_PIN CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_CONNECTIVITY_BT_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_connectivity_wifi.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_connectivity_wifi.h new file mode 100644 index 00000000000..2de04102a17 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_connectivity_wifi.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * File Name: cycfg_connectivity_wifi.h + * + * Description: + * Connectivity Wi-Fi configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_WIFI_H) +#define CYCFG_CONNECTIVITY_WIFI_H + +#include "cycfg_notices.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define wifi_0_power_0_ENABLED 1U +#define CYCFG_WIFI_HOST_WAKE_ENABLED (1u) +#define CYCFG_WIFI_HOST_WAKE_GPIO CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN +#define CYCFG_WIFI_HOST_WAKE_IRQ_EVENT CYBSP_WIFI_HOST_WAKE_HAL_IRQ + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_CONNECTIVITY_WIFI_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.c b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.c new file mode 100644 index 00000000000..da8e659eca3 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.c @@ -0,0 +1,193 @@ +/******************************************************************************* + * File Name: cycfg_dmas.c + * + * Description: + * DMA configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_dmas.h" + +const cy_stc_dma_descriptor_config_t CYBSP_DMA_DVP_CAM_CONTROLLER_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_DESCR, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0, + .dstXincrement = 1, + .xCount = 160, + .srcYincrement = 0, + .dstYincrement = 160, + .yCount = 4, + .nextDescriptor = &CYBSP_DMA_DVP_CAM_CONTROLLER_Descriptor_0, +}; +CY_SECTION(".cy_socmem_data") CY_ALIGN(8) cy_stc_dma_descriptor_t CYBSP_DMA_DVP_CAM_CONTROLLER_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t CYBSP_DMA_DVP_CAM_CONTROLLER_channelConfig = +{ + .descriptor = &CYBSP_DMA_DVP_CAM_CONTROLLER_Descriptor_0, + .preemptable = false, + .priority = 3, + .enable = false, + .bufferable = true, +}; +const cy_stc_dma_crc_config_t CYBSP_DMA_DVP_CAM_CONTROLLER_crcConfig = +{ + .dataReverse = false, + .dataXor = 0, + .reminderReverse = false, + .reminderXor = 0, + .polynomial = 79764919, +}; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) +const mtb_hal_dma_configurator_t CYBSP_DMA_DVP_CAM_CONTROLLER_hal_config = +{ + .dma_type = MTB_HAL_DMA_DW, + .channel = CYBSP_DMA_DVP_CAM_CONTROLLER_CHANNEL, + .dw_base = CYBSP_DMA_DVP_CAM_CONTROLLER_HW, + .dw_descriptor = &CYBSP_DMA_DVP_CAM_CONTROLLER_Descriptor_0, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) */ + +const cy_stc_dma_descriptor_config_t CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1, + .dstXincrement = 0, + .xCount = 12, + .srcYincrement = 0, + .dstYincrement = 0, + .yCount = 1, + .nextDescriptor = &CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0, +}; +CY_SECTION(".cy_socmem_data") CY_ALIGN(8) cy_stc_dma_descriptor_t CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t CYBSP_DMA_TX_SPI_CONTROLLER_channelConfig = +{ + .descriptor = &CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0, + .preemptable = false, + .priority = 3, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_crc_config_t CYBSP_DMA_TX_SPI_CONTROLLER_crcConfig = +{ + .dataReverse = false, + .dataXor = 0, + .reminderReverse = false, + .reminderXor = 0, + .polynomial = 79764919, +}; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) +const mtb_hal_dma_configurator_t CYBSP_DMA_TX_SPI_CONTROLLER_hal_config = +{ + .dma_type = MTB_HAL_DMA_DW, + .channel = CYBSP_DMA_TX_SPI_CONTROLLER_CHANNEL, + .dw_base = CYBSP_DMA_TX_SPI_CONTROLLER_HW, + .dw_descriptor = &CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) */ + +const cy_stc_axidmac_descriptor_config_t CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_Descriptor_0_config = +{ + .retrigger = CY_AXIDMAC_WAIT_FOR_REACT, + .interruptType = CY_AXIDMAC_DESCR, + .triggerOutType = CY_AXIDMAC_DESCR, + .channelState = CY_AXIDMAC_CHANNEL_DISABLED, + .triggerInType = CY_AXIDMAC_M_LOOP, + .dataPrefetch = false, + .descriptorType = CY_AXIDMAC_3D_MEMORY_COPY, + .srcAddress = NULL, + .dstAddress = NULL, + .mCount = 640, + .srcXincrement = 640, + .dstXincrement = 640, + .xCount = 2, + .srcYincrement = 0, + .dstYincrement = 1280, + .yCount = 120, + .nextDescriptor = &CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_Descriptor_0, +}; +CY_SECTION(".cy_socmem_data") CY_ALIGN(8) cy_stc_axidmac_descriptor_t CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .mSize = 0UL, + .xSize = 0UL, + .xIncr = 0UL, + .ySize = 0UL, + .yIncr = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_axidmac_channel_config_t CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_channelConfig = +{ + .descriptor = &CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_Descriptor_0, + .priority = 3, + .enable = false, + .bufferable = false, +}; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) +const mtb_hal_dma_configurator_t CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_hal_config = +{ + .dma_type = MTB_HAL_DMA_DMAC, + .channel = CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_CHANNEL, + .dmac_base = CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_HW, + .dmac_descriptor = &CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_Descriptor_0, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.h new file mode 100644 index 00000000000..6f56ab3208e --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_dmas.h @@ -0,0 +1,87 @@ +/******************************************************************************* + * File Name: cycfg_dmas.h + * + * Description: + * DMA configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_DMAS_H) +#define CYCFG_DMAS_H + +#include "cycfg_notices.h" +#include "cy_dma.h" +#include "cy_axidmac.h" + +#if defined(COMPONENT_MTB_HAL) +#include "mtb_hal.h" +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define CYBSP_DMA_DVP_CAM_CONTROLLER_ENABLED 1U +#define CYBSP_DMA_DVP_CAM_CONTROLLER_HW DW0 +#define CYBSP_DMA_DVP_CAM_CONTROLLER_CHANNEL 0U +#define CYBSP_DMA_DVP_CAM_CONTROLLER_IRQ cpuss_interrupts_dw0_0_IRQn +#define CYBSP_DMA_TX_SPI_CONTROLLER_ENABLED 1U +#define CYBSP_DMA_TX_SPI_CONTROLLER_HW DW0 +#define CYBSP_DMA_TX_SPI_CONTROLLER_CHANNEL 1U +#define CYBSP_DMA_TX_SPI_CONTROLLER_IRQ cpuss_interrupts_dw0_1_IRQn +#define CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_ENABLED 1U +#define CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_HW SAXI_DMAC +#define CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_CHANNEL 0U +#define CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_IRQ m55appcpuss_interrupts_axidmac_0_IRQn + +extern const cy_stc_dma_descriptor_config_t CYBSP_DMA_DVP_CAM_CONTROLLER_Descriptor_0_config; +extern CY_SECTION(".cy_socmem_data") CY_ALIGN(8) cy_stc_dma_descriptor_t CYBSP_DMA_DVP_CAM_CONTROLLER_Descriptor_0; +extern const cy_stc_dma_channel_config_t CYBSP_DMA_DVP_CAM_CONTROLLER_channelConfig; +extern const cy_stc_dma_crc_config_t CYBSP_DMA_DVP_CAM_CONTROLLER_crcConfig; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) +extern const mtb_hal_dma_configurator_t CYBSP_DMA_DVP_CAM_CONTROLLER_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) */ + +extern const cy_stc_dma_descriptor_config_t CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0_config; +extern CY_SECTION(".cy_socmem_data") CY_ALIGN(8) cy_stc_dma_descriptor_t CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0; +extern const cy_stc_dma_channel_config_t CYBSP_DMA_TX_SPI_CONTROLLER_channelConfig; +extern const cy_stc_dma_crc_config_t CYBSP_DMA_TX_SPI_CONTROLLER_crcConfig; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) +extern const mtb_hal_dma_configurator_t CYBSP_DMA_TX_SPI_CONTROLLER_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) */ + +extern const cy_stc_axidmac_descriptor_config_t CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_Descriptor_0_config; +extern CY_SECTION(".cy_socmem_data") CY_ALIGN(8) cy_stc_axidmac_descriptor_t CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_Descriptor_0; +extern const cy_stc_axidmac_channel_config_t CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_channelConfig; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) +extern const mtb_hal_dma_configurator_t CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) */ + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_DMAS_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_memory.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_memory.h new file mode 100644 index 00000000000..8cb98f418df --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_memory.h @@ -0,0 +1,69 @@ +/******************************************************************************* + * File Name: cycfg_memory.h + * + * Description: + * Memory configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_MEMORY_H) +#define CYCFG_MEMORY_H + +#include "cycfg_notices.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define vres_0_memory_region_data_0_ENABLED 1U +#define vres_0_memory_region_data_1_ENABLED 1U +#define vres_0_memory_region_data_2_ENABLED 1U +#define vres_0_memory_region_data_3_ENABLED 1U +#define vres_0_memory_region_data_4_ENABLED 1U +#define vres_0_memory_region_data_5_ENABLED 1U +#define vres_0_memory_region_data_6_ENABLED 1U +#define vres_0_memory_region_data_7_ENABLED 1U +#define vres_0_memory_region_data_8_ENABLED 1U +#define vres_0_memory_region_data_9_ENABLED 1U +#define vres_0_memory_region_data_10_ENABLED 1U +#define vres_0_memory_region_data_11_ENABLED 1U +#define vres_0_memory_region_data_12_ENABLED 1U +#define vres_0_memory_region_data_13_ENABLED 1U +#define vres_0_memory_region_data_14_ENABLED 1U +#define vres_0_memory_region_data_15_ENABLED 1U +#define vres_0_memory_region_data_16_ENABLED 1U +#define vres_0_memory_region_data_17_ENABLED 1U +#define vres_0_memory_region_data_18_ENABLED 1U +#define vres_0_memory_region_data_19_ENABLED 1U +#define vres_0_memory_region_data_20_ENABLED 1U +#define vres_0_memory_region_data_21_ENABLED 1U +#define vres_0_memory_region_data_22_ENABLED 1U +#define vres_0_memory_region_data_23_ENABLED 1U +#define vres_0_memory_region_data_24_ENABLED 1U +#define vres_0_memory_0_ENABLED 1U + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_MEMORY_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_notices.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_notices.h new file mode 100644 index 00000000000..5faea957171 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_notices.h @@ -0,0 +1,56 @@ +/******************************************************************************* + * File Name: cycfg_notices.h + * + * Description: + * Contains warnings and errors that occurred while generating code for the + * design. + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#if defined(CY_SUPPORTS_DEVICE_VALIDATION) +#if !defined(PSE846GPS2DBZC4A) +#error "Unexpected MPN; expected DEVICE:=PSE846GPS2DBZC4A. There may be an inconsistency between the *.modus file and the makefile target configuration device sets." +#endif /* !defined(PSE846GPS2DBZC4A) */ +#endif /* defined(CY_SUPPORTS_DEVICE_VALIDATION) */ + +#if defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION) +#if !defined(PSE846GPS2DBZC4A) +#error "Unexpected MPN; expected DEVICE:=PSE846GPS2DBZC4A, ADDITIONAL_DEVICES:=CYW55513IUBG. There may be an inconsistency between the *.modus file and the makefile target configuration device sets." +#endif /* !defined(PSE846GPS2DBZC4A) */ +#if !defined(CYW55513IUBG) +#error "Unexpected MPN; expected DEVICE:=PSE846GPS2DBZC4A, ADDITIONAL_DEVICES:=CYW55513IUBG. There may be an inconsistency between the *.modus file and the makefile target configuration device sets." +#endif /* !defined(CYW55513IUBG) */ +#endif /* defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION) */ + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_NOTICES_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripheral_clocks.c b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripheral_clocks.c new file mode 100644 index 00000000000..82e10fe332a --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripheral_clocks.c @@ -0,0 +1,95 @@ +/******************************************************************************* + * File Name: cycfg_peripheral_clocks.c + * + * Description: + * Peripheral clock divider configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_peripheral_clocks.h" + +void init_cycfg_peripheral_clocks(void) { + Cy_SysClk_PeriGroupSetDivider((0 << 8) | 2, 1U); + Cy_SysClk_PeriGroupSetDivider((1 << 8) | 1, 1U); + Cy_SysClk_PeriGroupSetDivider((1 << 8) | 3, 3U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 31U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_USB_OS_TIMER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_USB_OS_TIMER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_USB_OS_TIMER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_PWM_DT_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_PWM_DT_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U, 249U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_PWM_DT_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U, 9U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 1U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 1U, 86U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 1U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 2U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 2U, 9999U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 2U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_PWM_LED_CTRL_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 3U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_PWM_LED_CTRL_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 3U, 49999U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_PWM_LED_CTRL_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 3U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U); + Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U, 107U, 16U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U); + Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U, 3U, 5U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_SMART_IO_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U); + Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_SMART_IO_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U, 505049U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_SMART_IO_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U); + Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U, 0U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 7U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_TDM_CONTROLLER_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U); + Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_TDM_CONTROLLER_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U, 23U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_TDM_CONTROLLER_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_PDM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U); + Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_PDM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U, 3U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_PDM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 1U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); +} + + +/** + * This function is not part of the generated sources. + * It is added by MicroPython to avoid unused peripheral default allocations. + */ + +void init_cycfg_peripheral_clocks_s_minimal(void) { + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 1U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripheral_clocks.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripheral_clocks.h new file mode 100644 index 00000000000..c1a1576346c --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripheral_clocks.h @@ -0,0 +1,256 @@ +/******************************************************************************* + * File Name: cycfg_peripheral_clocks.h + * + * Description: + * Peripheral clock divider configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_PERIPHERAL_CLOCKS_H) +#define CYCFG_PERIPHERAL_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define peri_0_mmio_0_ENABLED 1U +#define peri_1_mmio_0_ENABLED 1U +#define CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_NUM 0U +#define CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM) +#define CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM) */ + +#define CYBSP_SPI_CONTROLLER_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_SPI_CONTROLLER_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_SPI_CONTROLLER_CLK_DIV_NUM 1U +#define CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM) +#define CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM) */ + +#define CYBSP_USB_OS_TIMER_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_USB_OS_TIMER_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_USB_OS_TIMER_CLK_DIV_NUM 2U +#define CYBSP_USB_OS_TIMER_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_USB_OS_TIMER_CLK_DIV_GRP_NUM) +#define CYBSP_USB_OS_TIMER_CLK_DIV_GRP_NUM CYBSP_USB_OS_TIMER_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_USB_OS_TIMER_CLK_DIV_GRP_NUM) */ + +#define CYBSP_PWM_DT_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_PWM_DT_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_PWM_DT_CLK_DIV_NUM 3U +#define CYBSP_PWM_DT_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_PWM_DT_CLK_DIV_GRP_NUM) +#define CYBSP_PWM_DT_CLK_DIV_GRP_NUM CYBSP_PWM_DT_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_PWM_DT_CLK_DIV_GRP_NUM) */ + +#define CYBSP_I2C_CONTROLLER_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_I2C_CONTROLLER_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_I2C_CONTROLLER_CLK_DIV_NUM 0U +#define CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM) +#define CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM) */ + +#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_DEBUG_UART_CLK_DIV_NUM 1U +#define CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM) +#define CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM) */ + +#define CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_NUM 2U +#define CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_GRP_NUM) +#define CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_GRP_NUM CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_GENERAL_PURPOSE_TIMER_CLK_DIV_GRP_NUM) */ + +#define CYBSP_PWM_LED_CTRL_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_PWM_LED_CTRL_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_PWM_LED_CTRL_CLK_DIV_NUM 3U +#define CYBSP_PWM_LED_CTRL_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_PWM_LED_CTRL_CLK_DIV_GRP_NUM) +#define CYBSP_PWM_LED_CTRL_CLK_DIV_GRP_NUM CYBSP_PWM_LED_CTRL_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_PWM_LED_CTRL_CLK_DIV_GRP_NUM) */ + +#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_5_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_BT_UART_CLK_DIV_NUM 0U +#define CYBSP_BT_UART_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_BT_UART_CLK_DIV_GRP_NUM) +#define CYBSP_BT_UART_CLK_DIV_GRP_NUM CYBSP_BT_UART_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_BT_UART_CLK_DIV_GRP_NUM) */ + +#define CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_HW CY_SYSCLK_DIV_16_5_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_NUM 1U +#define CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_GRP_NUM) +#define CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_GRP_NUM CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_PWM_DVP_CAM_CTRL_CLK_DIV_GRP_NUM) */ + +#define CYBSP_SMART_IO_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_SMART_IO_CLK_DIV_HW CY_SYSCLK_DIV_24_5_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_SMART_IO_CLK_DIV_NUM 0U +#define CYBSP_SMART_IO_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_SMART_IO_CLK_DIV_GRP_NUM) +#define CYBSP_SMART_IO_CLK_DIV_GRP_NUM CYBSP_SMART_IO_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_SMART_IO_CLK_DIV_GRP_NUM) */ + +#define CYBSP_TRACE_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_TRACE_CLK_DIV_HW CY_SYSCLK_DIV_16_5_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_TRACE_CLK_DIV_NUM 0U +#define CYBSP_TRACE_CLK_DIV_GRP_NUM ((7U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_TRACE_CLK_DIV_GRP_NUM) +#define CYBSP_TRACE_CLK_DIV_GRP_NUM CYBSP_TRACE_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_TRACE_CLK_DIV_GRP_NUM) */ + +#define CYBSP_I3C_CONTROLLER_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_I3C_CONTROLLER_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_I3C_CONTROLLER_CLK_DIV_NUM 0U +#define CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM ((9U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM) +#define CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM) */ + +#define CYBSP_TDM_CONTROLLER_0_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_TDM_CONTROLLER_0_CLK_DIV_HW CY_SYSCLK_DIV_16_5_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_TDM_CONTROLLER_0_CLK_DIV_NUM 0U +#define CYBSP_TDM_CONTROLLER_0_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (1U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_TDM_CONTROLLER_0_CLK_DIV_GRP_NUM) +#define CYBSP_TDM_CONTROLLER_0_CLK_DIV_GRP_NUM CYBSP_TDM_CONTROLLER_0_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_TDM_CONTROLLER_0_CLK_DIV_GRP_NUM) */ + +#define CYBSP_PDM_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_PDM_CLK_DIV_HW CY_SYSCLK_DIV_16_5_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_PDM_CLK_DIV_NUM 1U +#define CYBSP_PDM_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (1U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_PDM_CLK_DIV_GRP_NUM) +#define CYBSP_PDM_CLK_DIV_GRP_NUM CYBSP_PDM_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_PDM_CLK_DIV_GRP_NUM) */ + +#define CYBSP_SDHC_0_CLK_DIV_ENABLED 1U + +#if !defined(CY_USING_HAL) && !defined(CY_USING_HAL_LITE) +#define CYBSP_SDHC_0_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_SDHC_0_CLK_DIV_NUM 0U +#define CYBSP_SDHC_0_CLK_DIV_GRP_NUM ((2U << PERI_PCLK_GR_NUM_Pos) | (1U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined(CYBSP_SDHC_0_CLK_DIV_GRP_NUM) +#define CYBSP_SDHC_0_CLK_DIV_GRP_NUM CYBSP_SDHC_0_CLK_DIV_GRP_NUM +#endif /* !defined (CYBSP_SDHC_0_CLK_DIV_GRP_NUM) */ + +void init_cycfg_peripheral_clocks(void); +void init_cycfg_peripheral_clocks_s_minimal(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_PERIPHERAL_CLOCKS_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.c b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.c new file mode 100644 index 00000000000..c3e7482d377 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.c @@ -0,0 +1,1351 @@ +/******************************************************************************* + * File Name: cycfg_peripherals.c + * + * Description: + * Analog configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_peripherals.h" + +#define CYBSP_PWM_LED_CTRL_INPUT_DISABLED 0x7U +#define emUSB_OS_Timer_INPUT_DISABLED 0x7U +#define CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED 0x7U +#define CYBSP_PWM_DVP_CAM_CTRL_INPUT_DISABLED 0x7U +#define CYBSP_DEAD_TIME_PWM_INPUT_DISABLED 0x7U + +cy_stc_autanalog_cfg_t autonomous_analog_cfg = +{ + .prb = NULL, + .ac = &CYBSP_AUTONOMOUS_CONTROLLER_cfg, + .ctb = + { + NULL, + NULL, + }, + .ptcomp = + { + NULL, + }, + .dac = + { + NULL, + NULL, + }, + .sar = + { + &CYBSP_SAR_ADC_cfg, + }, +}; +cy_stc_autanalog_stt_t autonomous_analog_stt[] = +{ + { + .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[0U], + .prb = NULL, + .ctb = + { + NULL, + NULL, + }, + .ptcomp = + { + NULL, + }, + .dac = + { + NULL, + NULL, + }, + .sar = + { + &CYBSP_SAR_ADC_stt[0U], + }, + }, + { + .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[1U], + .prb = NULL, + .ctb = + { + NULL, + NULL, + }, + .ptcomp = + { + NULL, + }, + .dac = + { + NULL, + NULL, + }, + .sar = + { + &CYBSP_SAR_ADC_stt[1U], + }, + }, + { + .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[2U], + .prb = NULL, + .ctb = + { + NULL, + NULL, + }, + .ptcomp = + { + NULL, + }, + .dac = + { + NULL, + NULL, + }, + .sar = + { + &CYBSP_SAR_ADC_stt[2U], + }, + }, +}; +cy_stc_autanalog_t autonomous_analog_init = +{ + .configuration = &autonomous_analog_cfg, + .numSttEntries = sizeof(autonomous_analog_stt) / sizeof(autonomous_analog_stt[0U]), + .stateTransitionTable = &autonomous_analog_stt[0U], +}; +cy_en_autanalog_ac_out_trigger_mask_t CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[] = +{ + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, +}; +cy_stc_autanalog_ac_t CYBSP_AUTONOMOUS_CONTROLLER_cfg = +{ + .gpioOutEn = + CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, + .mask = + { + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[0U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[1U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[2U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[3U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[4U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[5U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[6U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[7U], + }, + .timer = + { + .enable = false, + .clkSrc = CY_AUTANALOG_TIMER_CLK_LP, + .period = 0U, + }, +}; +cy_stc_autanalog_stt_ac_t CYBSP_AUTONOMOUS_CONTROLLER_stt[] = +{ + { + .unlock = true, + .lpMode = false, + .condition = CY_AUTANALOG_STT_AC_CONDITION_BLOCK_READY, + .action = CY_AUTANALOG_STT_AC_ACTION_WAIT_FOR, + .branchState = 1U, + .trigInt = false, + .count = 0U, + .unlockGpioOut = false, + .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, + }, + { + .unlock = false, + .lpMode = false, + .condition = CY_AUTANALOG_STT_AC_CONDITION_SAR_DONE, + .action = CY_AUTANALOG_STT_AC_ACTION_WAIT_FOR, + .branchState = 0U, + .trigInt = false, + .count = 0U, + .unlockGpioOut = false, + .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, + }, + { + .unlock = false, + .lpMode = false, + .condition = CY_AUTANALOG_STT_AC_CONDITION_FALSE, + .action = CY_AUTANALOG_STT_AC_ACTION_STOP, + .branchState = 0U, + .trigInt = false, + .count = 0U, + .unlockGpioOut = false, + .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, + }, +}; +cy_stc_autanalog_sar_hs_chan_t CYBSP_SAR_ADC_gpio_ch_cfg[] = +{ + { + .posPin = CY_AUTANALOG_SAR_PIN_GPIO1, + .hsDiffEn = false, + .sign = false, + .posCoeff = CY_AUTANALOG_SAR_CH_COEFF_DISABLED, + .negPin = CY_AUTANALOG_SAR_PIN_GPIO0, + .accShift = false, + .negCoeff = CY_AUTANALOG_SAR_CH_COEFF_DISABLED, + .hsLimit = CY_AUTANALOG_SAR_LIMIT_STATUS_DISABLED, + .fifoSel = CY_AUTANALOG_FIFO_DISABLED, + }, +}; +cy_stc_autanalog_sar_sta_hs_t CYBSP_SAR_ADC_sta_hs_cfg = +{ + .hsVref = CY_AUTANALOG_SAR_VREF_VDDA, + .hsSampleTime = + { + 31U, + 31U, + 31U, + 31U, + }, + .hsGpioChan = + { + &CYBSP_SAR_ADC_gpio_ch_cfg[0U], + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + }, + .hsGpioResultMask = + CY_AUTANALOG_SAR_CHAN_MASK_GPIO0, +}; +cy_stc_autanalog_sar_sta_t CYBSP_SAR_ADC_sta_cfg = +{ + .lpStaCfg = NULL, + .hsStaCfg = &CYBSP_SAR_ADC_sta_hs_cfg, + .posBufPwr = CY_AUTANALOG_SAR_BUF_PWR_OFF, + .negBufPwr = CY_AUTANALOG_SAR_BUF_PWR_OFF, + .accMode = CY_AUTANALOG_SAR_ACC_DISABLED, + .startupCal = CY_AUTANALOG_SAR_CAL_DISABLED, + .chanID = false, + .shiftMode = false, + .intMuxChan = + { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + }, + .limitCond = + { + NULL, + NULL, + NULL, + NULL, + }, + .muxResultMask = + CY_AUTANALOG_SAR_CHAN_MASK_MUX_DISABLED, + .firResultMask = + CY_AUTANALOG_SAR_MASK_FIR_DISABLED, +}; +cy_stc_autanalog_sar_seq_tab_hs_t CYBSP_SAR_ADC_seq_hs_cfg[] = +{ + { + .chanEn = CY_AUTANALOG_SAR_CHAN_MASK_GPIO0, + .muxMode = CY_AUTANALOG_SAR_CHAN_CFG_MUX_DISABLED, + .mux0Sel = CY_AUTANALOG_SAR_CHAN_CFG_MUX0, + .mux1Sel = CY_AUTANALOG_SAR_CHAN_CFG_MUX0, + .sampleTimeEn = true, + .sampleTime = CY_AUTANALOG_SAR_SAMPLE_TIME0, + .accEn = false, + .accCount = CY_AUTANALOG_SAR_ACC_CNT2, + .calReq = CY_AUTANALOG_SAR_CAL_DISABLED, + .nextAction = CY_AUTANALOG_SAR_NEXT_ACTION_GO_TO_ENTRY_ADDR, + }, +}; +cy_stc_autanalog_sar_t CYBSP_SAR_ADC_cfg = +{ + .sarStaCfg = &CYBSP_SAR_ADC_sta_cfg, + .hsSeqTabNum = sizeof(CYBSP_SAR_ADC_seq_hs_cfg) / sizeof(CYBSP_SAR_ADC_seq_hs_cfg[0U]), + .hsSeqTabArr = &CYBSP_SAR_ADC_seq_hs_cfg[0U], + .lpSeqTabNum = 0U, + .lpSeqTabArr = NULL, + .firNum = 0U, + .firCfg = NULL, + .fifoCfg = NULL, +}; +cy_stc_autanalog_stt_sar_t CYBSP_SAR_ADC_stt[] = +{ + { + .unlock = true, + .enable = true, + .trigger = false, + .entryState = 0U, + }, + { + .unlock = true, + .enable = true, + .trigger = true, + .entryState = 0U, + }, + { + .unlock = true, + .enable = true, + .trigger = false, + .entryState = 0U, + }, +}; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_ADC) +mtb_hal_adc_configurator_t CYBSP_SAR_ADC_hal_config = +{ + .config = &CYBSP_SAR_ADC_cfg, + .num_channels = sizeof(CYBSP_SAR_ADC_seq_hs_cfg) / sizeof(CYBSP_SAR_ADC_seq_hs_cfg[0U]), + .clock = NULL, + .adc_index = 0U, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_ADC) */ + +const cy_stc_i3c_config_t CYBSP_I3C_CONTROLLER_config = +{ + .i3cMode = CY_I3C_CONTROLLER, + .i3cBusMode = CY_I3C_BUS_PURE, + .useDma = false, + .manualDataRate = false, + .i3cClockHz = 12500000U, + .i3cSclRate = 12500000U, + .openDrainSclRate = 4000000U, + .txEmptyBufThld = CY_I3C_1_WORD_DEPTH, + .rxBufThld = CY_I3C_1_WORD_DEPTH, + .txBufStartThld = CY_I3C_1_WORD_DEPTH, + .rxBufStartThld = CY_I3C_1_WORD_DEPTH, + .ibaInclude = false, + .hotJoinCtrl = false, + .dynamicAddr = 8U, + .cmdQueueEmptyThld = 1U, + .respQueueThld = 0U, + .ibiQueueThld = 0U, + .ibiDataThld = 15U, + .extLowCnt1 = 11U, + .extLowCnt2 = 16U, + .extLowCnt3 = 27U, + .extLowCnt4 = 58U, + .extTerminationLowCnt = 0U, + .sdaHoldTime = 1U, + .busFreeTime = 32U, + .openDrainLowCnt = 0U, + .openDrainHighCnt = 0U, + .pushPullLowCnt = 0U, + .pushPullHighCnt = 0U, + .i2cFMLowCnt = 0U, + .i2cFMHighCnt = 0U, + .i2cFMPlusLowCnt = 0U, + .i2cFMPlusHighCnt = 0U, + .adaptiveI2CI3C = false, + .staticAddress = 0U, + .pid = 0U, + .dcr = 0U, + .speedLimit = false, + .hdrCapable = false, + .deviceRoleCap = CY_I3C_SECONDARY_CONTROLLER, + .hotjoinEnable = false, + .busAvailTime = 0U, + .busIdleTime = 0U, +}; +const cy_stc_pdm_pcm_config_v2_t CYBSP_PDM_config = +{ + .clkDiv = 7, + .clksel = CY_PDM_PCM_SEL_SRSS_CLOCK, + .halverate = CY_PDM_PCM_RATE_FULL, + .route = 4, + .fir0_coeff_user_value = false, + .fir1_coeff_user_value = false, +}; +const cy_stc_pdm_pcm_channel_config_t channel_2_config = +{ + .sampledelay = 1, + .wordSize = CY_PDM_PCM_WSIZE_16_BIT, + .signExtension = true, + .rxFifoTriggerLevel = 31, + .fir0_enable = false, + .cic_decim_code = CY_PDM_PCM_CHAN_CIC_DECIM_32, + .fir0_decim_code = CY_PDM_PCM_CHAN_FIR0_DECIM_1, + .fir0_scale = 0, + .fir1_decim_code = CY_PDM_PCM_CHAN_FIR1_DECIM_3, + .fir1_scale = 10, + .dc_block_disable = false, + .dc_block_code = CY_PDM_PCM_CHAN_DCBLOCK_CODE_16, +}; +const cy_stc_pdm_pcm_channel_config_t channel_3_config = +{ + .sampledelay = 5, + .wordSize = CY_PDM_PCM_WSIZE_16_BIT, + .signExtension = true, + .rxFifoTriggerLevel = 31, + .fir0_enable = false, + .cic_decim_code = CY_PDM_PCM_CHAN_CIC_DECIM_32, + .fir0_decim_code = CY_PDM_PCM_CHAN_FIR0_DECIM_1, + .fir0_scale = 0, + .fir1_decim_code = CY_PDM_PCM_CHAN_FIR1_DECIM_3, + .fir1_scale = 10, + .dc_block_disable = false, + .dc_block_code = CY_PDM_PCM_CHAN_DCBLOCK_CODE_16, +}; +const cy_stc_scb_i2c_config_t CYBSP_I2C_CONTROLLER_config = +{ + .i2cMode = CY_SCB_I2C_MASTER, + .useRxFifo = true, + .useTxFifo = true, + .slaveAddress = 0U, + .slaveAddressMask = 0U, + .acceptAddrInFifo = false, + .ackGeneralAddr = false, + .enableWakeFromSleep = false, + .enableDigitalFilter = false, + .lowPhaseDutyCycle = 16, + .highPhaseDutyCycle = 9, +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_I2C_CONTROLLER_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, + .div_type = CYBSP_I2C_CONTROLLER_CLK_DIV_HW, + .div_num = CYBSP_I2C_CONTROLLER_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_I2C_CONTROLLER_hal_clock = +{ + .clock_ref = &CYBSP_I2C_CONTROLLER_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) +const mtb_hal_i2c_configurator_t CYBSP_I2C_CONTROLLER_hal_config = +{ + .base = CYBSP_I2C_CONTROLLER_HW, + .config = &CYBSP_I2C_CONTROLLER_config, + .clock = &CYBSP_I2C_CONTROLLER_hal_clock, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) */ + +const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMultiProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 10, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .breaklevel = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_DEBUG_UART_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM, + .div_type = CYBSP_DEBUG_UART_CLK_DIV_HW, + .div_num = CYBSP_DEBUG_UART_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_DEBUG_UART_hal_clock = +{ + .clock_ref = &CYBSP_DEBUG_UART_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) +const mtb_hal_uart_configurator_t CYBSP_DEBUG_UART_hal_config = +{ + .base = CYBSP_DEBUG_UART_HW, + .clock = &CYBSP_DEBUG_UART_hal_clock, + .tx_pin = 7, + #if defined(COMPONENT_MW_ASYNC_TRANSFER) + .rts_pin = 0xFF, + #endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ + .tx_port = 6, + #if defined(COMPONENT_MW_ASYNC_TRANSFER) + .rts_port = 0xFF, + .rts_enable = 0UL, + #endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ + +const cy_stc_scb_spi_config_t CYBSP_SPI_CONTROLLER_config = +{ + .spiMode = CY_SCB_SPI_MASTER, + .subMode = CY_SCB_SPI_MOTOROLA, + .sclkMode = CY_SCB_SPI_CPHA0_CPOL0, + .parity = CY_SCB_SPI_PARITY_NONE, + .dropOnParityError = false, + .oversample = 4, + .rxDataWidth = 8UL, + .txDataWidth = 8UL, + .enableMsbFirst = true, + .enableInputFilter = false, + .enableFreeRunSclk = false, + .enableMisoLateSample = true, + .enableTransferSeparation = false, + .ssPolarity = ((CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT0) | \ + (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT1) | \ + (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT2) | \ + (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT3)), + .ssSetupDelay = false, + .ssHoldDelay = false, + .ssInterFrameDelay = false, + .enableWakeFromSleep = false, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, + .masterSlaveIntEnableMask = 0UL, +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_SPI_CONTROLLER_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_SCB3_CLOCK_SCB_EN, + .div_type = CY_SYSCLK_DIV_8_BIT, + .div_num = 1, +}; +const mtb_hal_clock_t CYBSP_SPI_CONTROLLER_hal_clock = +{ + .clock_ref = &CYBSP_SPI_CONTROLLER_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) +const mtb_hal_spi_configurator_t CYBSP_SPI_CONTROLLER_hal_config = +{ + .base = CYBSP_SPI_CONTROLLER_HW, + .clock = &CYBSP_SPI_CONTROLLER_hal_clock, + .config = &CYBSP_SPI_CONTROLLER_config, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) */ + +const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMultiProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .breaklevel = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_BT_UART_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, + .div_type = CYBSP_BT_UART_CLK_DIV_HW, + .div_num = CYBSP_BT_UART_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_BT_UART_hal_clock = +{ + .clock_ref = &CYBSP_BT_UART_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) +const mtb_hal_uart_configurator_t CYBSP_BT_UART_hal_config = +{ + .base = CYBSP_BT_UART_HW, + .clock = &CYBSP_BT_UART_hal_clock, + .tx_pin = 1, + #if defined(COMPONENT_MW_ASYNC_TRANSFER) + .rts_pin = 3, + #endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ + .tx_port = 10, + #if defined(COMPONENT_MW_ASYNC_TRANSFER) + .rts_port = 10, + .rts_enable = 1UL, + #endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ + +const cy_stc_scb_i2c_config_t CYBSP_I2C_CAM_CONTROLLER_config = +{ + .i2cMode = CY_SCB_I2C_MASTER_SLAVE, + .useRxFifo = true, + .useTxFifo = true, + .slaveAddress = 8, + .slaveAddressMask = 254, + .acceptAddrInFifo = false, + .ackGeneralAddr = false, + .enableWakeFromSleep = false, + .enableDigitalFilter = false, + .lowPhaseDutyCycle = 0, + .highPhaseDutyCycle = 0, +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_I2C_CAM_CONTROLLER_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_GRP_NUM, + .div_type = CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_HW, + .div_num = CYBSP_I2C_CONTROLLER_3V3_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_I2C_CAM_CONTROLLER_hal_clock = +{ + .clock_ref = &CYBSP_I2C_CAM_CONTROLLER_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) +const mtb_hal_i2c_configurator_t CYBSP_I2C_CAM_CONTROLLER_hal_config = +{ + .base = CYBSP_I2C_CAM_CONTROLLER_HW, + .config = &CYBSP_I2C_CAM_CONTROLLER_config, + .clock = &CYBSP_I2C_CAM_CONTROLLER_hal_clock, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) */ + +cy_en_sd_host_card_capacity_t CYBSP_WIFI_SDIO_cardCapacity = CY_SD_HOST_SDSC; +cy_en_sd_host_card_type_t CYBSP_WIFI_SDIO_cardType = CY_SD_HOST_NOT_EMMC; +uint32_t CYBSP_WIFI_SDIO_rca = 0u; +const cy_stc_sd_host_init_config_t CYBSP_WIFI_SDIO_config = +{ + .emmc = false, + .dmaType = CY_SD_HOST_DMA_ADMA2, + .enableLedControl = false, +}; +cy_stc_sd_host_sd_card_config_t CYBSP_WIFI_SDIO_card_cfg = +{ + .lowVoltageSignaling = false, + .busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT, + .cardType = &CYBSP_WIFI_SDIO_cardType, + .rca = &CYBSP_WIFI_SDIO_rca, + .cardCapacity = &CYBSP_WIFI_SDIO_cardCapacity, +}; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) +const mtb_hal_peri_div_t CYBSP_WIFI_SDIO_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, + .div_type = CYBSP_SDHC_0_CLK_DIV_HW, + .div_num = CYBSP_SDHC_0_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_WIFI_SDIO_hal_clock = +{ + .clock_ref = &CYBSP_WIFI_SDIO_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +const mtb_hal_sdhc_configurator_t CYBSP_WIFI_SDIO_sdhc_hal_config = +{ + .base = CYBSP_WIFI_SDIO_HW, + .host_config = &CYBSP_WIFI_SDIO_config, + .card_config = &CYBSP_WIFI_SDIO_card_cfg, + .clock = &CYBSP_WIFI_SDIO_hal_clock, + .gpios = {.clk = { .pin_num = 0, .port_num = 12}, .cmd = { .pin_num = 0, .port_num = 21}, .data = {{ .pin_num = 1, .port_num = 12}, { .pin_num = 2, .port_num = 12}, { .pin_num = 4, .port_num = 12}, { .pin_num = 5, .port_num = 12}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}}}, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) +const mtb_hal_sdio_configurator_t CYBSP_WIFI_SDIO_sdio_hal_config = +{ + .base = CYBSP_WIFI_SDIO_HW, + .host_config = &CYBSP_WIFI_SDIO_config, + .clock = &CYBSP_WIFI_SDIO_hal_clock, + .gpios = {.clk = { .pin_num = 0, .port_num = 12}, .cmd = { .pin_num = 0, .port_num = 21}, .data = {{ .pin_num = 1, .port_num = 12}, { .pin_num = 2, .port_num = 12}, { .pin_num = 4, .port_num = 12}, { .pin_num = 5, .port_num = 12}}}, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) */ + +const cy_stc_smif_config_t CYBSP_SMIF_CORE_0_XSPI_FLASH_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = CYBSP_SMIF_CORE_0_XSPI_FLASH_DESELECT_DELAY, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, + .inputFrequencyMHz = 200, + .enable_internal_dll = false, + .dll_divider_value = CY_SMIF_DLL_DIVIDE_BY_2, + .rx_capture_mode = CY_SMIF_SEL_NORMAL_SPI, + .mdl_tap = CY_SMIF_MDL_8_TAP_DELAY, + .device0_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device1_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device2_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device3_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .tx_sdr_extra = CY_SMIF_TX_TWO_PERIOD_AHEAD, +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_hf_clock_t CYBSP_SMIF_CORE_0_XSPI_FLASH_clock_ref = +{ + .inst_num = 3U, +}; +const mtb_hal_clock_t CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_clock = +{ + .clock_ref = &CYBSP_SMIF_CORE_0_XSPI_FLASH_clock_ref, + .interface = &mtb_hal_clock_hf_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) +const mtb_hal_memoryspi_configurator_t CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_config = +{ + .base = SMIF0_CORE, + .clock = &CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_clock, + .config = &CYBSP_SMIF_CORE_0_XSPI_FLASH_config, + .csel = {false, true, false, false}, + .irqs = CYBSP_SMIF_CORE_0_XSPI_FLASH_MEMORY_MODE_ALIGMENT_ERROR << 5 | CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_DATA_FIFO_UNDERFLOW << 4 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_COMMAND_FIFO_OVERFLOW << 3 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_DATA_FIFO_OVERFLOW << 2 | (uint8_t)(CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_FIFO_TRIGGER_LEVEL != 0) << 1 | (uint8_t)(CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_FIFO_TRIGGER_LEVEL != 0) << 0, + .dmas = CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_DMA_TRIGGER_OUT_USED << 1 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_DMA_TRIGGER_OUT_USED << 0, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) */ + +const cy_stc_smif_config_t CYBSP_SMIF_CORE_1_PSRAM_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = CYBSP_SMIF_CORE_1_PSRAM_DESELECT_DELAY, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, + .inputFrequencyMHz = 400, + .enable_internal_dll = false, + .dll_divider_value = CY_SMIF_DLL_DIVIDE_BY_2, + .rx_capture_mode = CY_SMIF_SEL_NORMAL_SPI, + .mdl_tap = CY_SMIF_MDL_8_TAP_DELAY, + .device0_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device1_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device2_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device3_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .tx_sdr_extra = CY_SMIF_TX_TWO_PERIOD_AHEAD, +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_hf_clock_t CYBSP_SMIF_CORE_1_PSRAM_clock_ref = +{ + .inst_num = 4U, +}; +const mtb_hal_clock_t CYBSP_SMIF_CORE_1_PSRAM_hal_clock = +{ + .clock_ref = &CYBSP_SMIF_CORE_1_PSRAM_clock_ref, + .interface = &mtb_hal_clock_hf_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) +const mtb_hal_memoryspi_configurator_t CYBSP_SMIF_CORE_1_PSRAM_hal_config = +{ + .base = SMIF1_CORE, + .clock = &CYBSP_SMIF_CORE_1_PSRAM_hal_clock, + .config = &CYBSP_SMIF_CORE_1_PSRAM_config, + .csel = {false, false, true, false}, + .irqs = CYBSP_SMIF_CORE_1_PSRAM_MEMORY_MODE_ALIGMENT_ERROR << 5 | CYBSP_SMIF_CORE_1_PSRAM_RX_DATA_FIFO_UNDERFLOW << 4 | CYBSP_SMIF_CORE_1_PSRAM_TX_COMMAND_FIFO_OVERFLOW << 3 | CYBSP_SMIF_CORE_1_PSRAM_TX_DATA_FIFO_OVERFLOW << 2 | (uint8_t)(CYBSP_SMIF_CORE_1_PSRAM_RX_FIFO_TRIGGER_LEVEL != 0) << 1 | (uint8_t)(CYBSP_SMIF_CORE_1_PSRAM_TX_FIFO_TRIGGER_LEVEL != 0) << 0, + .dmas = CYBSP_SMIF_CORE_1_PSRAM_RX_DMA_TRIGGER_OUT_USED << 1 | CYBSP_SMIF_CORE_1_PSRAM_TX_DMA_TRIGGER_OUT_USED << 0, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) */ + +const cy_stc_mcwdt_config_t CYBSP_CM33_LPTIMER_0_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_INT, + .c1Mode = CY_MCWDT_MODE_INT, + .c2ToggleBit = 0U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, + .c0LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, + .c0LowerLimit = 0U, + .c1LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, + .c1LowerLimit = 0U, +}; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) +const mtb_hal_lptimer_configurator_t CYBSP_CM33_LPTIMER_0_hal_config = +{ + .base = CYBSP_CM33_LPTIMER_0_HW, + .lfclk_freqhz = 32768, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) */ + +const cy_stc_mcwdt_config_t CYBSP_CM55_LPTIMER_1_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_INT, + .c1Mode = CY_MCWDT_MODE_INT, + .c2ToggleBit = 0U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, + .c0LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, + .c0LowerLimit = 0U, + .c1LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, + .c1LowerLimit = 0U, +}; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) +const mtb_hal_lptimer_configurator_t CYBSP_CM55_LPTIMER_1_hal_config = +{ + .base = CYBSP_CM55_LPTIMER_1_HW, + .lfclk_freqhz = 32768, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) */ + +cy_stc_tdm_config_tx_t CYBSP_TDM_CONTROLLER_0_tx_config = +{ + .enable = true, + .masterMode = CY_TDM_DEVICE_MASTER, + .wordSize = CY_TDM_SIZE_16, + .format = CY_TDM_LEFT_DELAYED, + .clkDiv = 4, + .clkSel = CY_TDM_SEL_SRSS_CLK0, + .sckPolarity = CY_TDM_CLK, + .fsyncPolarity = CY_TDM_SIGN_INVERTED, + .fsyncFormat = CY_TDM_CH_PERIOD, + .channelNum = 2, + .channelSize = 16, + .fifoTriggerLevel = 64, + .chEn = 0x3, + .signalInput = 0, + .i2sMode = true, +}; +cy_stc_tdm_config_rx_t CYBSP_TDM_CONTROLLER_0_rx_config = +{ + .enable = false, + .masterMode = CY_TDM_DEVICE_SLAVE, + .wordSize = CY_TDM_SIZE_16, + .signExtend = CY_ZERO_EXTEND, + .format = CY_TDM_LEFT_DELAYED, + .clkDiv = 16, + .clkSel = CY_TDM_SEL_SRSS_CLK0, + .sckPolarity = CY_TDM_CLK, + .fsyncPolarity = CY_TDM_SIGN, + .lateSample = false, + .fsyncFormat = CY_TDM_BIT_PERIOD, + .channelNum = 2, + .channelSize = 16, + .fifoTriggerLevel = 0, + .chEn = 0x3, + .signalInput = 0, + .i2sMode = true, +}; +const cy_stc_tdm_config_t CYBSP_TDM_CONTROLLER_0_config = +{ + .tx_config = &CYBSP_TDM_CONTROLLER_0_tx_config, + .rx_config = &CYBSP_TDM_CONTROLLER_0_rx_config, +}; +const cy_stc_tcpwm_pwm_config_t CYBSP_PWM_LED_CTRL_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 2000, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 1000, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_ENABLE, + .killMode = CY_TCPWM_PWM_ASYNC_KILL, + .swapInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .swapOverflowUnderflow = false, + .immediateKill = false, + .tapsEnabled = 45, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .compare0MatchUp = true, + .compare0MatchDown = false, + .compare1MatchUp = true, + .compare1MatchDown = false, + .kill1InputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .kill1Input = CY_TCPWM_INPUT_0, + .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .reloadLineSelect = false, + .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .deadTimeClocks_linecompl_out = 0, + #if defined(CY_IP_MXS40TCPWM) + .hrpwm_enable = false, + .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, + .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, + .deadTimeClocksBuff = 0, + .deadTimeClocksBuff_linecompl_out = 0, + .buffer_swap_enable = false, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, + .dithering_mode = CY_TCPWM_DITHERING_DISABLE, + .period_dithering_value = 128, + .duty_dithering_value = 128, + .limiter = CY_TCPWM_DITHERING_LIMITER_7, + .pwm_tc_sync_kill_dt = false, + .pwm_sync_kill_dt = false, + #endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_PWM_LED_CTRL_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN0, + .div_type = CY_SYSCLK_DIV_16_BIT, + .div_num = 3, +}; +const mtb_hal_clock_t CYBSP_PWM_LED_CTRL_hal_clock = +{ + .clock_ref = &CYBSP_PWM_LED_CTRL_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +const mtb_hal_pwm_configurator_t CYBSP_PWM_LED_CTRL_hal_config = +{ + .base = CYBSP_PWM_LED_CTRL_HW, + .clock = &CYBSP_PWM_LED_CTRL_hal_clock, + .group = 0UL, + .cntnum = 0UL, + .max_count = 2000, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +cy_stc_tcpwm_counter_config_t emUSB_OS_Timer_config = +{ + .period = 99999, + .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1, + .runMode = CY_TCPWM_COUNTER_CONTINUOUS, + .countDirection = CY_TCPWM_COUNTER_COUNT_UP, + .compareOrCapture = CY_TCPWM_COUNTER_MODE_CAPTURE, + .compare0 = 16384U, + .compare1 = 16384U, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0) | (CY_TCPWM_INT_ON_CC1 & 0U), + .captureInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .captureInput = CY_TCPWM_INPUT_0, + .reloadInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .stopInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .stopInput = CY_TCPWM_INPUT_0, + .countInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .capture1InputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .capture1Input = CY_TCPWM_INPUT_0, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, +}; + +#if defined(COMPONENT_MTB_HAL) +mtb_hal_peri_div_t emUSB_OS_Timer_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN1, + .div_type = CY_SYSCLK_DIV_8_BIT, + .div_num = 2, +}; +mtb_hal_clock_t emUSB_OS_Timer_hal_clock = +{ + .clock_ref = &emUSB_OS_Timer_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) +mtb_hal_timer_configurator_t emUSB_OS_Timer_hal_config = +{ + .tcpwm_base = emUSB_OS_Timer_HW, + .clock = &emUSB_OS_Timer_hal_clock, + .tcpwm_cntnum = 1U, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */ + +const cy_stc_tcpwm_counter_config_t CYBSP_GENERAL_PURPOSE_TIMER_config = +{ + .period = 9999, + .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1, + .runMode = CY_TCPWM_COUNTER_CONTINUOUS, + .countDirection = CY_TCPWM_COUNTER_COUNT_UP, + .compareOrCapture = CY_TCPWM_COUNTER_MODE_COMPARE, + .compare0 = 9999, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .captureInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .captureInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .stopInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .stopInput = CY_TCPWM_INPUT_0, + .countInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .capture1InputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .capture1Input = CY_TCPWM_INPUT_0, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + #if defined(CY_IP_MXS40TCPWM) + .buffer_swap_enable = false, + .direction_mode = CY_TCPWM_COUNTER_DIRECTION_DISABLE, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, + #endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_GENERAL_PURPOSE_TIMER_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN2, + .div_type = CY_SYSCLK_DIV_16_BIT, + .div_num = 2, +}; +const mtb_hal_clock_t CYBSP_GENERAL_PURPOSE_TIMER_hal_clock = +{ + .clock_ref = &CYBSP_GENERAL_PURPOSE_TIMER_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) +const mtb_hal_timer_configurator_t CYBSP_GENERAL_PURPOSE_TIMER_hal_config = +{ + .tcpwm_base = CYBSP_GENERAL_PURPOSE_TIMER_HW, + .clock = &CYBSP_GENERAL_PURPOSE_TIMER_hal_clock, + .tcpwm_cntnum = 2U, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */ + +const cy_stc_tcpwm_pwm_config_t CYBSP_PWM_DVP_CAM_CTRL_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 1, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 1, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = CYBSP_PWM_DVP_CAM_CTRL_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CYBSP_PWM_DVP_CAM_CTRL_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CYBSP_PWM_DVP_CAM_CTRL_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CYBSP_PWM_DVP_CAM_CTRL_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CYBSP_PWM_DVP_CAM_CTRL_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .swapOverflowUnderflow = false, + .immediateKill = false, + .tapsEnabled = 45, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .compare0MatchUp = true, + .compare0MatchDown = false, + .compare1MatchUp = true, + .compare1MatchDown = false, + .kill1InputMode = CYBSP_PWM_DVP_CAM_CTRL_INPUT_DISABLED & 0x3U, + .kill1Input = CY_TCPWM_INPUT_0, + .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .reloadLineSelect = false, + .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .deadTimeClocks_linecompl_out = 0, + #if defined(CY_IP_MXS40TCPWM) + .hrpwm_enable = false, + .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, + .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, + .deadTimeClocksBuff = 0, + .deadTimeClocksBuff_linecompl_out = 0, + .buffer_swap_enable = false, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, + .dithering_mode = CY_TCPWM_DITHERING_DISABLE, + .period_dithering_value = 128, + .duty_dithering_value = 128, + .limiter = CY_TCPWM_DITHERING_LIMITER_7, + .pwm_tc_sync_kill_dt = false, + .pwm_sync_kill_dt = false, + #endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_PWM_DVP_CAM_CTRL_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN4, + .div_type = CY_SYSCLK_DIV_16_5_BIT, + .div_num = 1, +}; +const mtb_hal_clock_t CYBSP_PWM_DVP_CAM_CTRL_hal_clock = +{ + .clock_ref = &CYBSP_PWM_DVP_CAM_CTRL_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +const mtb_hal_pwm_configurator_t CYBSP_PWM_DVP_CAM_CTRL_hal_config = +{ + .base = CYBSP_PWM_DVP_CAM_CTRL_HW, + .clock = &CYBSP_PWM_DVP_CAM_CTRL_hal_clock, + .group = 0UL, + .cntnum = 4UL, + .max_count = 1, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +const cy_stc_tcpwm_pwm_config_t CYBSP_DEAD_TIME_PWM_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_DEADTIME, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 100, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 400, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 200, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .swapOverflowUnderflow = false, + .immediateKill = false, + .tapsEnabled = 45, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .compare0MatchUp = true, + .compare0MatchDown = false, + .compare1MatchUp = true, + .compare1MatchDown = false, + .kill1InputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .kill1Input = CY_TCPWM_INPUT_0, + .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .reloadLineSelect = false, + .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .deadTimeClocks_linecompl_out = 100, + #if defined(CY_IP_MXS40TCPWM) + .hrpwm_enable = false, + .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, + .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, + .deadTimeClocksBuff = 0, + .deadTimeClocksBuff_linecompl_out = 0, + .buffer_swap_enable = false, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, + .dithering_mode = CY_TCPWM_DITHERING_DISABLE, + .period_dithering_value = 128, + .duty_dithering_value = 128, + .limiter = CY_TCPWM_DITHERING_LIMITER_7, + .pwm_tc_sync_kill_dt = false, + .pwm_sync_kill_dt = false, + #endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined(COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_DEAD_TIME_PWM_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN7, + .div_type = CY_SYSCLK_DIV_8_BIT, + .div_num = 3, +}; +const mtb_hal_clock_t CYBSP_DEAD_TIME_PWM_hal_clock = +{ + .clock_ref = &CYBSP_DEAD_TIME_PWM_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +const mtb_hal_pwm_configurator_t CYBSP_DEAD_TIME_PWM_hal_config = +{ + .base = CYBSP_DEAD_TIME_PWM_HW, + .clock = &CYBSP_DEAD_TIME_PWM_hal_clock, + .group = 0UL, + .cntnum = 7UL, + .max_count = 400, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +void init_cycfg_peripherals(void) { + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_PASS_PERI_NR, CY_MMIO_PASS_GROUP_NR, CY_MMIO_PASS_SLAVE_NR, CY_MMIO_PASS_CLK_HF_NR); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_I3C_PERI_NR, CY_MMIO_I3C_GROUP_NR, CY_MMIO_I3C_SLAVE_NR, CY_MMIO_I3C_CLK_HF_NR); + Cy_SysClk_PeriphAssignDivider(PCLK_I3C_CLOCK_I3C_EN, CY_SYSCLK_DIV_8_BIT, 0U); + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_PDM0_PERI_NR, CY_MMIO_PDM0_GROUP_NR, CY_MMIO_PDM0_SLAVE_NR, CY_MMIO_PDM0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_PDM0_CLK_IF_SRSS, CY_SYSCLK_DIV_16_5_BIT, 1U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB0_PERI_NR, CY_MMIO_SCB0_GROUP_NR, CY_MMIO_SCB0_SLAVE_NR, CY_MMIO_SCB0_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB0_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB2_PERI_NR, CY_MMIO_SCB2_GROUP_NR, CY_MMIO_SCB2_SLAVE_NR, CY_MMIO_SCB2_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB2_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 1U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB3_PERI_NR, CY_MMIO_SCB3_GROUP_NR, CY_MMIO_SCB3_SLAVE_NR, CY_MMIO_SCB3_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB3_CLOCK_SCB_EN, CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB4_PERI_NR, CY_MMIO_SCB4_GROUP_NR, CY_MMIO_SCB4_SLAVE_NR, CY_MMIO_SCB4_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB4_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_5_BIT, 0U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB5_PERI_NR, CY_MMIO_SCB5_GROUP_NR, CY_MMIO_SCB5_SLAVE_NR, CY_MMIO_SCB5_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB5_CLOCK_SCB_EN, CY_SYSCLK_DIV_8_BIT, 0U); + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SDHC0_PERI_NR, CY_MMIO_SDHC0_GROUP_NR, CY_MMIO_SDHC0_SLAVE_NR, CY_MMIO_SDHC0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_SDHC0_CLK_HF, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_USBHS_PERI_NR, CY_MMIO_USBHS_GROUP_NR, CY_MMIO_USBHS_SLAVE_NR, CY_MMIO_USBHS_CLK_HF_NR); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF0_PERI_NR, CY_MMIO_SMIF0_GROUP_NR, CY_MMIO_SMIF0_SLAVE_NR, CY_MMIO_SMIF0_CLK_HF_NR); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF01_PERI_NR, CY_MMIO_SMIF01_GROUP_NR, CY_MMIO_SMIF01_SLAVE_NR, CY_MMIO_SMIF01_CLK_HF_NR); + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TDM0_PERI_NR, CY_MMIO_TDM0_GROUP_NR, CY_MMIO_TDM0_SLAVE_NR, CY_MMIO_TDM0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_TDM0_CLK_IF_SRSS0, CY_SYSCLK_DIV_16_5_BIT, 0U); + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN0, CY_SYSCLK_DIV_16_BIT, 3U); + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN1, CY_SYSCLK_DIV_8_BIT, 2U); + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN2, CY_SYSCLK_DIV_16_BIT, 2U); + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN4, CY_SYSCLK_DIV_16_5_BIT, 1U); + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN7, CY_SYSCLK_DIV_8_BIT, 3U); +} + +/** + * This function is not part of the generated sources. + * It is added by MicroPython to avoid unused peripheral default allocations. + */ + +void init_cycfg_peripheral_s_minimal(void) { + #if defined(CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SDHC0_PERI_NR, CY_MMIO_SDHC0_GROUP_NR, CY_MMIO_SDHC0_SLAVE_NR, CY_MMIO_SDHC0_CLK_HF_NR); + #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_SDHC0_CLK_HF, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF01_PERI_NR, CY_MMIO_SMIF01_GROUP_NR, CY_MMIO_SMIF01_SLAVE_NR, CY_MMIO_SMIF01_CLK_HF_NR); +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.h new file mode 100644 index 00000000000..66a8747a262 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_peripherals.h @@ -0,0 +1,367 @@ +/******************************************************************************* + * File Name: cycfg_peripherals.h + * + * Description: + * Analog configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_autanalog.h" +#include "cy_sysclk.h" +#include "cy_i3c.h" +#include "cy_pdm_pcm_v2.h" +#include "cy_scb_i2c.h" +#include "cy_scb_uart.h" +#include "cy_scb_spi.h" +#include "cy_sd_host.h" +#include "cy_smif.h" +#include "cycfg_qspi_memslot.h" +#include "cy_mcwdt.h" +#include "cy_tdm.h" +#include "cy_tcpwm_pwm.h" +#include "cycfg_routing.h" +#include "cy_tcpwm_counter.h" + +#if defined(COMPONENT_MTB_HAL) +#include "mtb_hal.h" +#include "cycfg_peripheral_clocks.h" +#include "mtb_hal_hw_types.h" +#include "mtb_hal_clock.h" +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define CYBSP_AUTONOMOUS_ANALOG_ENABLED 1U +#define AUTANALOG_CLOCK_DIV_PRIO_HS_DEFAULT 20 +#define CYBSP_AUTONOMOUS_ANALOG_lppass_IRQ pass_interrupt_lppass_IRQn +#define CYBSP_AUTONOMOUS_ANALOG_fifo_IRQ pass_interrupt_fifo_IRQn +#define CYBSP_AUTONOMOUS_CONTROLLER_ENABLED 1U +#define CYBSP_SAR_ADC_ENABLED 1U +#define CYBSP_AUTONOMOUS_CONTROLLER_STATE_0_ENABLED 1U +#define CYBSP_AUTONOMOUS_CONTROLLER_STATE_1_ENABLED 1U +#define CYBSP_AUTONOMOUS_CONTROLLER_STATE_2_ENABLED 1U +#define CYBSP_SAR_ADC_GPIO_CH_0_ENABLED 1U +#define CYBSP_SAR_ADC_SCAN_GRP_0_ENABLED 1U +#define CYBSP_SAR_ADC_SCAN_GRP_0_SCAN_0_ENABLED 1U +#define CYBSP_I3C_CONTROLLER_ENABLED 1U +#define CYBSP_I3C_CONTROLLER_HW I3C_CORE +#define CYBSP_I3C_CONTROLLER_IRQ i3c_interrupt_IRQn +#define CYBSP_PDM_ENABLED 1U +#define CYBSP_PDM_HW PDM0 +#define CYBSP_PDM_CHANNEL_2_IRQ pdm_0_interrupts_2_IRQn +#define CYBSP_PDM_CHANNEL_3_IRQ pdm_0_interrupts_3_IRQn +#define CYBSP_I2C_CONTROLLER_ENABLED 1U +#define CYBSP_I2C_CONTROLLER_HW SCB0 +#define CYBSP_I2C_CONTROLLER_IRQ scb_0_interrupt_IRQn +#define CYBSP_DEBUG_UART_ENABLED 1U +#define CYBSP_DEBUG_UART_HW SCB2 +#define CYBSP_DEBUG_UART_IRQ scb_2_interrupt_IRQn +#define CYBSP_SPI_CONTROLLER_ENABLED 1U +#define CYBSP_SPI_CONTROLLER_HW SCB3 +#define CYBSP_SPI_CONTROLLER_IRQ scb_3_interrupt_IRQn +#define CYBSP_BT_UART_ENABLED 1U +#define CYBSP_BT_UART_HW SCB4 +#define CYBSP_BT_UART_IRQ scb_4_interrupt_IRQn +#define CYBSP_I2C_CAM_CONTROLLER_ENABLED 1U +#define CYBSP_I2C_DISPLAY_CONTROLLER_ENABLED CYBSP_I2C_CAM_CONTROLLER_ENABLED +#define CYBSP_I2C_CAM_CONTROLLER_HW SCB5 +#define CYBSP_I2C_DISPLAY_CONTROLLER_HW CYBSP_I2C_CAM_CONTROLLER_HW +#define CYBSP_I2C_CAM_CONTROLLER_IRQ scb_5_interrupt_IRQn +#define CYBSP_I2C_DISPLAY_CONTROLLER_IRQ CYBSP_I2C_CAM_CONTROLLER_IRQ +#define CYBSP_WIFI_SDIO_ENABLED 1U +#define CYBSP_WIFI_SDIO_HW SDHC0 +#define CYBSP_WIFI_SDIO_IRQ sdhc_0_interrupt_general_IRQn +#define CYBSP_USB_DEVICE_0_ENABLED 1U +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_ENABLED 1U +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_HW SMIF0_CORE +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_IRQ smif_0_smif0_interrupt_nsec_IRQn +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_DATA_FIFO_UNDERFLOW (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_DATA_FIFO_OVERFLOW (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_DMA_TRIGGER_OUT_USED (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_DMA_TRIGGER_OUT_USED (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_FIFO_TRIGGER_LEVEL (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_FIFO_TRIGGER_LEVEL (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_DATALINES0_1 (1UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_DATALINES2_3 (1UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_DATALINES4_5 (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_DATALINES6_7 (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_SS0 (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_SS1 (1UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_SS2 (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_SS3 (0UL) +#define CYBSP_SMIF_CORE_0_XSPI_FLASH_DESELECT_DELAY 7 +#define CYBSP_SMIF_CORE_1_PSRAM_ENABLED 1U +#define CYBSP_SMIF_CORE_1_PSRAM_HW SMIF1_CORE +#define CYBSP_SMIF_CORE_1_PSRAM_IRQ smif_1_smif0_interrupt_nsec_IRQn +#define CYBSP_SMIF_CORE_1_PSRAM_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_RX_DATA_FIFO_UNDERFLOW (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_TX_DATA_FIFO_OVERFLOW (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_RX_DMA_TRIGGER_OUT_USED (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_TX_DMA_TRIGGER_OUT_USED (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_RX_FIFO_TRIGGER_LEVEL (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_TX_FIFO_TRIGGER_LEVEL (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_DATALINES0_1 (1UL) +#define CYBSP_SMIF_CORE_1_PSRAM_DATALINES2_3 (1UL) +#define CYBSP_SMIF_CORE_1_PSRAM_DATALINES4_5 (1UL) +#define CYBSP_SMIF_CORE_1_PSRAM_DATALINES6_7 (1UL) +#define CYBSP_SMIF_CORE_1_PSRAM_SS0 (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_SS1 (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_SS2 (1UL) +#define CYBSP_SMIF_CORE_1_PSRAM_SS3 (0UL) +#define CYBSP_SMIF_CORE_1_PSRAM_DESELECT_DELAY 7 +#define CYBSP_CM33_LPTIMER_0_ENABLED 1U +#define CYBSP_CM33_LPTIMER_0_HW MCWDT_STRUCT0 +#define CYBSP_CM33_LPTIMER_0_IRQ srss_interrupt_mcwdt_0_IRQn +#define CYBSP_CM55_LPTIMER_1_ENABLED 1U +#define CYBSP_CM55_LPTIMER_1_HW MCWDT_STRUCT1 +#define CYBSP_CM55_LPTIMER_1_IRQ srss_interrupt_mcwdt_1_IRQn +#define CYBSP_TDM_CONTROLLER_0_ENABLED 1U +#define CYBSP_TDM_CONTROLLER_0_HW TDM_STRUCT0 +#define CYBSP_TDM_CONTROLLER_0_TX_HW TDM_STRUCT0_TX +#define CYBSP_TDM_CONTROLLER_0_RX_HW TDM_STRUCT0_RX +#define CYBSP_TDM_CONTROLLER_0_TX_IRQ tdm_0_interrupts_tx_0_IRQn +#define CYBSP_TDM_CONTROLLER_0_RX_IRQ tdm_0_interrupts_rx_0_IRQn +#define CYBSP_PWM_LED_CTRL_ENABLED 1U +#define CYBSP_PWM_LED_CTRL_HW TCPWM0 +#define CYBSP_PWM_LED_CTRL_NUM 0UL +#define CYBSP_USB_OS_TIMER_COUNTER_ENABLED 1U +#define emUSB_OS_Timer_HW TCPWM0 +#define emUSB_OS_Timer_NUM 1UL +#define emUSB_OS_Timer_IRQ tcpwm_0_interrupts_1_IRQn +#define CYBSP_GENERAL_PURPOSE_TIMER_ENABLED 1U +#define CYBSP_GENERAL_PURPOSE_TIMER_HW TCPWM0 +#define CYBSP_GENERAL_PURPOSE_TIMER_NUM 2UL +#define CYBSP_GENERAL_PURPOSE_TIMER_IRQ tcpwm_0_interrupts_2_IRQn +#define CYBSP_PWM_DVP_CAM_CTRL_ENABLED 1U +#define CYBSP_PWM_DVP_CAM_CTRL_HW TCPWM0 +#define CYBSP_PWM_DVP_CAM_CTRL_NUM 4UL +#define CYBSP_DEAD_TIME_PWM_ENABLED 1U +#define CYBSP_DEAD_TIME_PWM_HW TCPWM0 +#define CYBSP_DEAD_TIME_PWM_NUM 7UL + +extern cy_stc_autanalog_cfg_t autonomous_analog_cfg; +extern cy_stc_autanalog_stt_t autonomous_analog_stt[]; +extern cy_stc_autanalog_t autonomous_analog_init; +extern cy_en_autanalog_ac_out_trigger_mask_t CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[]; +extern cy_stc_autanalog_ac_t CYBSP_AUTONOMOUS_CONTROLLER_cfg; +extern cy_stc_autanalog_stt_ac_t CYBSP_AUTONOMOUS_CONTROLLER_stt[]; +extern cy_stc_autanalog_sar_hs_chan_t CYBSP_SAR_ADC_gpio_ch_cfg[]; +extern cy_stc_autanalog_sar_sta_hs_t CYBSP_SAR_ADC_sta_hs_cfg; +extern cy_stc_autanalog_sar_sta_t CYBSP_SAR_ADC_sta_cfg; +extern cy_stc_autanalog_sar_seq_tab_hs_t CYBSP_SAR_ADC_seq_hs_cfg[]; +extern cy_stc_autanalog_sar_t CYBSP_SAR_ADC_cfg; +extern cy_stc_autanalog_stt_sar_t CYBSP_SAR_ADC_stt[]; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_ADC) +extern mtb_hal_adc_configurator_t CYBSP_SAR_ADC_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_ADC) */ + +extern const cy_stc_i3c_config_t CYBSP_I3C_CONTROLLER_config; +extern const cy_stc_pdm_pcm_config_v2_t CYBSP_PDM_config; +extern const cy_stc_pdm_pcm_channel_config_t channel_2_config; +extern const cy_stc_pdm_pcm_channel_config_t channel_3_config; +extern const cy_stc_scb_i2c_config_t CYBSP_I2C_CONTROLLER_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_I2C_CONTROLLER_clock_ref; +extern const mtb_hal_clock_t CYBSP_I2C_CONTROLLER_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) +extern const mtb_hal_i2c_configurator_t CYBSP_I2C_CONTROLLER_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) */ + +extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_DEBUG_UART_clock_ref; +extern const mtb_hal_clock_t CYBSP_DEBUG_UART_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) +extern const mtb_hal_uart_configurator_t CYBSP_DEBUG_UART_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ + +extern const cy_stc_scb_spi_config_t CYBSP_SPI_CONTROLLER_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_SPI_CONTROLLER_clock_ref; +extern const mtb_hal_clock_t CYBSP_SPI_CONTROLLER_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) +extern const mtb_hal_spi_configurator_t CYBSP_SPI_CONTROLLER_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) */ + +extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_BT_UART_clock_ref; +extern const mtb_hal_clock_t CYBSP_BT_UART_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) +extern const mtb_hal_uart_configurator_t CYBSP_BT_UART_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ + +extern const cy_stc_scb_i2c_config_t CYBSP_I2C_CAM_CONTROLLER_config; + +#define CYBSP_I2C_DISPLAY_CONTROLLER_config CYBSP_I2C_CAM_CONTROLLER_config + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_I2C_CAM_CONTROLLER_clock_ref; +#define CYBSP_I2C_DISPLAY_CONTROLLER_clock_ref CYBSP_I2C_CAM_CONTROLLER_clock_ref +extern const mtb_hal_clock_t CYBSP_I2C_CAM_CONTROLLER_hal_clock; +#define CYBSP_I2C_DISPLAY_CONTROLLER_hal_clock CYBSP_I2C_CAM_CONTROLLER_hal_clock +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) +extern const mtb_hal_i2c_configurator_t CYBSP_I2C_CAM_CONTROLLER_hal_config; +#define CYBSP_I2C_DISPLAY_CONTROLLER_hal_config CYBSP_I2C_CAM_CONTROLLER_hal_config +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) */ + +extern cy_en_sd_host_card_capacity_t CYBSP_WIFI_SDIO_cardCapacity; +extern cy_en_sd_host_card_type_t CYBSP_WIFI_SDIO_cardType; +extern uint32_t CYBSP_WIFI_SDIO_rca; +extern const cy_stc_sd_host_init_config_t CYBSP_WIFI_SDIO_config; +extern cy_stc_sd_host_sd_card_config_t CYBSP_WIFI_SDIO_card_cfg; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) +extern const mtb_hal_peri_div_t CYBSP_WIFI_SDIO_clock_ref; +extern const mtb_hal_clock_t CYBSP_WIFI_SDIO_hal_clock; +extern const mtb_hal_sdhc_configurator_t CYBSP_WIFI_SDIO_sdhc_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) +extern const mtb_hal_sdio_configurator_t CYBSP_WIFI_SDIO_sdio_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) */ + +extern const cy_stc_smif_config_t CYBSP_SMIF_CORE_0_XSPI_FLASH_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_hf_clock_t CYBSP_SMIF_CORE_0_XSPI_FLASH_clock_ref; +extern const mtb_hal_clock_t CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) +extern const mtb_hal_memoryspi_configurator_t CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) */ + +extern const cy_stc_smif_config_t CYBSP_SMIF_CORE_1_PSRAM_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_hf_clock_t CYBSP_SMIF_CORE_1_PSRAM_clock_ref; +extern const mtb_hal_clock_t CYBSP_SMIF_CORE_1_PSRAM_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) +extern const mtb_hal_memoryspi_configurator_t CYBSP_SMIF_CORE_1_PSRAM_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) */ + +extern const cy_stc_mcwdt_config_t CYBSP_CM33_LPTIMER_0_config; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) +extern const mtb_hal_lptimer_configurator_t CYBSP_CM33_LPTIMER_0_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) */ + +extern const cy_stc_mcwdt_config_t CYBSP_CM55_LPTIMER_1_config; + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) +extern const mtb_hal_lptimer_configurator_t CYBSP_CM55_LPTIMER_1_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) */ + +extern cy_stc_tdm_config_tx_t CYBSP_TDM_CONTROLLER_0_tx_config; +extern cy_stc_tdm_config_rx_t CYBSP_TDM_CONTROLLER_0_rx_config; +extern const cy_stc_tdm_config_t CYBSP_TDM_CONTROLLER_0_config; +extern const cy_stc_tcpwm_pwm_config_t CYBSP_PWM_LED_CTRL_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_PWM_LED_CTRL_clock_ref; +extern const mtb_hal_clock_t CYBSP_PWM_LED_CTRL_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +extern const mtb_hal_pwm_configurator_t CYBSP_PWM_LED_CTRL_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +extern cy_stc_tcpwm_counter_config_t emUSB_OS_Timer_config; + +#if defined(COMPONENT_MTB_HAL) +extern mtb_hal_peri_div_t emUSB_OS_Timer_clock_ref; +extern mtb_hal_clock_t emUSB_OS_Timer_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) +extern mtb_hal_timer_configurator_t emUSB_OS_Timer_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */ + +extern const cy_stc_tcpwm_counter_config_t CYBSP_GENERAL_PURPOSE_TIMER_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_GENERAL_PURPOSE_TIMER_clock_ref; +extern const mtb_hal_clock_t CYBSP_GENERAL_PURPOSE_TIMER_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) +extern const mtb_hal_timer_configurator_t CYBSP_GENERAL_PURPOSE_TIMER_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */ + +extern const cy_stc_tcpwm_pwm_config_t CYBSP_PWM_DVP_CAM_CTRL_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_PWM_DVP_CAM_CTRL_clock_ref; +extern const mtb_hal_clock_t CYBSP_PWM_DVP_CAM_CTRL_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +extern const mtb_hal_pwm_configurator_t CYBSP_PWM_DVP_CAM_CTRL_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +extern const cy_stc_tcpwm_pwm_config_t CYBSP_DEAD_TIME_PWM_config; + +#if defined(COMPONENT_MTB_HAL) +extern const mtb_hal_peri_div_t CYBSP_DEAD_TIME_PWM_clock_ref; +extern const mtb_hal_clock_t CYBSP_DEAD_TIME_PWM_hal_clock; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined(COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +extern const mtb_hal_pwm_configurator_t CYBSP_DEAD_TIME_PWM_hal_config; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +void init_cycfg_peripherals(void); +void init_cycfg_peripheral_s_minimal(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.c b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.c new file mode 100644 index 00000000000..7c7b064661c --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.c @@ -0,0 +1,1472 @@ +/******************************************************************************* + * File Name: cycfg_pins.c + * + * Description: + * Pin configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_CS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_OSPI_RAM_CS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_CS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_QSPI_CS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I3C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ, + .hsiom = CYBSP_I3C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I3C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ, + .hsiom = CYBSP_I3C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_OSPI_RAM_D0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_OSPI_RAM_D1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_OSPI_RAM_D2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_OSPI_RAM_D3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_OSPI_RAM_D4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D5_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_OSPI_RAM_D5_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D6_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_OSPI_RAM_D6_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D7_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_OSPI_RAM_D7_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DEBUG_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_DEBUG_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_SW1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SW1_HSIOM, + .intEdge = CY_GPIO_INTR_FALLING, + .intMask = 1UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_EXT_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_EXT_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_1V8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_I2C_SCL_1V8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_1V8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_I2C_SDA_1V8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_PDM_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_PDM_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_PDM_DATA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_PDM_DATA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SERIAL_INT_0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SERIAL_INT_2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_BT_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_BT_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_BT_UART_CTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_BT_UART_RTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_BT_HOST_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_USER_LED2_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_USER_LED2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_USER_LED1_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_USER_LED1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_BT_POWER_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_PCLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_PCLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_WIFI_WL_REG_ON_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_WIFI_SDIO_D0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_WIFI_SDIO_D1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_FSYNC_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_I2S_TX_FSYNC_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_WIFI_SDIO_D2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_WIFI_SDIO_D3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_D0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_D1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_D2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_D3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_D4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D5_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_D5_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D6_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_D6_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D7_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_D7_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_3V3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_I2C_SCL_3V3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_3V3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_I2C_SDA_3V3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_VSYNC_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_VSYNC_HSIOM, + .intEdge = CY_GPIO_INTR_FALLING, + .intMask = 1UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_HREF_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DVP_CAM_HREF_HSIOM, + .intEdge = CY_GPIO_INTR_FALLING, + .intMask = 1UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_XCLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_DVP_CAM_XCLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_RESET_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_DVP_CAM_RESET_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_PWDN_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_DVP_CAM_PWDN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_ECO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_ECO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_RADAR_INT_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_PULLDOWN_IN_OFF, + .hsiom = CYBSP_RADAR_INT_HSIOM, + .intEdge = CY_GPIO_INTR_RISING, + .intMask = 1UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_GREEN_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_LED_RGB_GREEN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_BLUE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED_RGB_BLUE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_RED_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_LED_RGB_RED_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_RXRES_L_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_RXRES_L_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_SD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_I2S_TX_SD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_SCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_I2S_TX_SCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_MCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_I2S_TX_MCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_RSPI_MISO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_RSPI_MISO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_RSPI_MOSI_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_RSPI_MOSI_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_RSPI_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_RSPI_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; +const cy_stc_gpio_pin_config_t CYBSP_RSPI_CS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_RSPI_CS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, + .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, + .nonSec = 1, +}; + +void init_cycfg_pins(void) { + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_CS_PORT, CYBSP_OSPI_RAM_CS_PIN, &CYBSP_OSPI_RAM_CS_config); + Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); + Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); + Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); + Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); + Cy_GPIO_Pin_Init(CYBSP_QSPI_CS_PORT, CYBSP_QSPI_CS_PIN, &CYBSP_QSPI_CS_config); + Cy_GPIO_Pin_Init(CYBSP_I3C_SCL_PORT, CYBSP_I3C_SCL_PIN, &CYBSP_I3C_SCL_config); + Cy_GPIO_Pin_Init(CYBSP_I3C_SDA_PORT, CYBSP_I3C_SDA_PIN, &CYBSP_I3C_SDA_config); + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_D0_PORT, CYBSP_OSPI_RAM_D0_PIN, &CYBSP_OSPI_RAM_D0_config); + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_D1_PORT, CYBSP_OSPI_RAM_D1_PIN, &CYBSP_OSPI_RAM_D1_config); + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_D2_PORT, CYBSP_OSPI_RAM_D2_PIN, &CYBSP_OSPI_RAM_D2_config); + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_D3_PORT, CYBSP_OSPI_RAM_D3_PIN, &CYBSP_OSPI_RAM_D3_config); + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_D4_PORT, CYBSP_OSPI_RAM_D4_PIN, &CYBSP_OSPI_RAM_D4_config); + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_D5_PORT, CYBSP_OSPI_RAM_D5_PIN, &CYBSP_OSPI_RAM_D5_config); + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_D6_PORT, CYBSP_OSPI_RAM_D6_PIN, &CYBSP_OSPI_RAM_D6_config); + Cy_GPIO_Pin_Init(CYBSP_OSPI_RAM_D7_PORT, CYBSP_OSPI_RAM_D7_PIN, &CYBSP_OSPI_RAM_D7_config); + Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config); + Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config); + Cy_GPIO_Pin_Init(CYBSP_SW1_PORT, CYBSP_SW1_PIN, &CYBSP_SW1_config); + Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_1V8_PORT, CYBSP_I2C_SCL_1V8_PIN, &CYBSP_I2C_SCL_1V8_config); + Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_1V8_PORT, CYBSP_I2C_SDA_1V8_PIN, &CYBSP_I2C_SDA_1V8_config); + Cy_GPIO_Pin_Init(CYBSP_PDM_CLK_PORT, CYBSP_PDM_CLK_PIN, &CYBSP_PDM_CLK_config); + Cy_GPIO_Pin_Init(CYBSP_PDM_DATA_PORT, CYBSP_PDM_DATA_PIN, &CYBSP_PDM_DATA_config); + Cy_GPIO_Pin_Init(CYBSP_SERIAL_INT_0_PORT, CYBSP_SERIAL_INT_0_PIN, &CYBSP_SERIAL_INT_0_config); + Cy_GPIO_Pin_Init(CYBSP_SERIAL_INT_2_PORT, CYBSP_SERIAL_INT_2_PIN, &CYBSP_SERIAL_INT_2_config); + Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); + Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); + Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); + Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); + Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config); + Cy_GPIO_Pin_Init(CYBSP_USER_LED2_PORT, CYBSP_USER_LED2_PIN, &CYBSP_USER_LED2_config); + Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config); + Cy_GPIO_Pin_Init(CYBSP_USER_LED1_PORT, CYBSP_USER_LED1_PIN, &CYBSP_USER_LED1_config); + Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_PCLK_PORT, CYBSP_DVP_CAM_PCLK_PIN, &CYBSP_DVP_CAM_PCLK_config); + Cy_GPIO_Pin_Init(CYBSP_WIFI_WL_REG_ON_PORT, CYBSP_WIFI_WL_REG_ON_PIN, &CYBSP_WIFI_WL_REG_ON_config); + Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config); + Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config); + Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D0_PORT, CYBSP_WIFI_SDIO_D0_PIN, &CYBSP_WIFI_SDIO_D0_config); + Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D1_PORT, CYBSP_WIFI_SDIO_D1_PIN, &CYBSP_WIFI_SDIO_D1_config); + Cy_GPIO_Pin_Init(CYBSP_I2S_TX_FSYNC_PORT, CYBSP_I2S_TX_FSYNC_PIN, &CYBSP_I2S_TX_FSYNC_config); + Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D2_PORT, CYBSP_WIFI_SDIO_D2_PIN, &CYBSP_WIFI_SDIO_D2_config); + Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D3_PORT, CYBSP_WIFI_SDIO_D3_PIN, &CYBSP_WIFI_SDIO_D3_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_D0_PORT, CYBSP_DVP_CAM_D0_PIN, &CYBSP_DVP_CAM_D0_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_D1_PORT, CYBSP_DVP_CAM_D1_PIN, &CYBSP_DVP_CAM_D1_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_D2_PORT, CYBSP_DVP_CAM_D2_PIN, &CYBSP_DVP_CAM_D2_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_D3_PORT, CYBSP_DVP_CAM_D3_PIN, &CYBSP_DVP_CAM_D3_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_D4_PORT, CYBSP_DVP_CAM_D4_PIN, &CYBSP_DVP_CAM_D4_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_D5_PORT, CYBSP_DVP_CAM_D5_PIN, &CYBSP_DVP_CAM_D5_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_D6_PORT, CYBSP_DVP_CAM_D6_PIN, &CYBSP_DVP_CAM_D6_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_D7_PORT, CYBSP_DVP_CAM_D7_PIN, &CYBSP_DVP_CAM_D7_config); + Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_3V3_PORT, CYBSP_I2C_SCL_3V3_PIN, &CYBSP_I2C_SCL_3V3_config); + Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_3V3_PORT, CYBSP_I2C_SDA_3V3_PIN, &CYBSP_I2C_SDA_3V3_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_VSYNC_PORT, CYBSP_DVP_CAM_VSYNC_PIN, &CYBSP_DVP_CAM_VSYNC_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_HREF_PORT, CYBSP_DVP_CAM_HREF_PIN, &CYBSP_DVP_CAM_HREF_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_XCLK_PORT, CYBSP_DVP_CAM_XCLK_PIN, &CYBSP_DVP_CAM_XCLK_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_RESET_PORT, CYBSP_DVP_CAM_RESET_PIN, &CYBSP_DVP_CAM_RESET_config); + Cy_GPIO_Pin_Init(CYBSP_DVP_CAM_PWDN_PORT, CYBSP_DVP_CAM_PWDN_PIN, &CYBSP_DVP_CAM_PWDN_config); + Cy_GPIO_Pin_Init(CYBSP_RADAR_INT_PORT, CYBSP_RADAR_INT_PIN, &CYBSP_RADAR_INT_config); + Cy_GPIO_Pin_Init(CYBSP_LED_RGB_GREEN_PORT, CYBSP_LED_RGB_GREEN_PIN, &CYBSP_LED_RGB_GREEN_config); + Cy_GPIO_Pin_Init(CYBSP_LED_RGB_BLUE_PORT, CYBSP_LED_RGB_BLUE_PIN, &CYBSP_LED_RGB_BLUE_config); + Cy_GPIO_Pin_Init(CYBSP_LED_RGB_RED_PORT, CYBSP_LED_RGB_RED_PIN, &CYBSP_LED_RGB_RED_config); + Cy_GPIO_Pin_Init(CYBSP_RXRES_L_PORT, CYBSP_RXRES_L_PIN, &CYBSP_RXRES_L_config); + Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config); + Cy_GPIO_Pin_Init(CYBSP_I2S_TX_SD_PORT, CYBSP_I2S_TX_SD_PIN, &CYBSP_I2S_TX_SD_config); + Cy_GPIO_Pin_Init(CYBSP_I2S_TX_SCK_PORT, CYBSP_I2S_TX_SCK_PIN, &CYBSP_I2S_TX_SCK_config); + Cy_GPIO_Pin_Init(CYBSP_I2S_TX_MCK_PORT, CYBSP_I2S_TX_MCK_PIN, &CYBSP_I2S_TX_MCK_config); + Cy_GPIO_Pin_Init(CYBSP_RSPI_MISO_PORT, CYBSP_RSPI_MISO_PIN, &CYBSP_RSPI_MISO_config); + Cy_GPIO_Pin_Init(CYBSP_RSPI_MOSI_PORT, CYBSP_RSPI_MOSI_PIN, &CYBSP_RSPI_MOSI_config); + Cy_GPIO_Pin_Init(CYBSP_RSPI_CLK_PORT, CYBSP_RSPI_CLK_PIN, &CYBSP_RSPI_CLK_config); + Cy_GPIO_Pin_Init(CYBSP_RSPI_CS_PORT, CYBSP_RSPI_CS_PIN, &CYBSP_RSPI_CS_config); +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.h new file mode 100644 index 00000000000..cc63bba0ed5 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_pins.h @@ -0,0 +1,1213 @@ +/******************************************************************************* + * File Name: cycfg_pins.h + * + * Description: + * Pin configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#include "cycfg_routing.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define CYBSP_OSPI_RAM_CS_ENABLED 1U +#define CYBSP_OSPI_RAM_SS_ENABLED CYBSP_OSPI_RAM_CS_ENABLED +#define CYBSP_OSPI_RAM_CS_PORT GPIO_PRT0 +#define CYBSP_OSPI_RAM_SS_PORT CYBSP_OSPI_RAM_CS_PORT +#define CYBSP_OSPI_RAM_CS_PORT_NUM 0U +#define CYBSP_OSPI_RAM_SS_PORT_NUM CYBSP_OSPI_RAM_CS_PORT_NUM +#define CYBSP_OSPI_RAM_CS_PIN 1U +#define CYBSP_OSPI_RAM_SS_PIN CYBSP_OSPI_RAM_CS_PIN +#define CYBSP_OSPI_RAM_CS_NUM 1U +#define CYBSP_OSPI_RAM_SS_NUM CYBSP_OSPI_RAM_CS_NUM +#define CYBSP_OSPI_RAM_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_OSPI_RAM_SS_DRIVEMODE CYBSP_OSPI_RAM_CS_DRIVEMODE +#define CYBSP_OSPI_RAM_CS_INIT_DRIVESTATE 1 +#define CYBSP_OSPI_RAM_SS_INIT_DRIVESTATE CYBSP_OSPI_RAM_CS_INIT_DRIVESTATE +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_OSPI_RAM_CS_HSIOM ioss_0_port_0_pin_1_HSIOM +#define CYBSP_OSPI_RAM_SS_HSIOM CYBSP_OSPI_RAM_CS_HSIOM +#define CYBSP_OSPI_RAM_CS_IRQ ioss_interrupts_gpio_0_IRQn +#define CYBSP_OSPI_RAM_SS_IRQ CYBSP_OSPI_RAM_CS_IRQ +#define CYBSP_QSPI_D0_ENABLED 1U +#define CYBSP_QSPI_D0_PORT (GPIO_PRT_Type *)SMIF0_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_QSPI_D0_PORT_NUM 1U +#define CYBSP_QSPI_D0_PIN 0U +#define CYBSP_QSPI_D0_NUM 0U +#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_QSPI_D0_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_QSPI_D1_ENABLED 1U +#define CYBSP_QSPI_D1_PORT (GPIO_PRT_Type *)SMIF0_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_QSPI_D1_PORT_NUM 1U +#define CYBSP_QSPI_D1_PIN 1U +#define CYBSP_QSPI_D1_NUM 1U +#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_1_HSIOM + #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_QSPI_D1_HSIOM ioss_0_port_1_pin_1_HSIOM +#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_QSPI_D2_ENABLED 1U +#define CYBSP_QSPI_D2_PORT (GPIO_PRT_Type *)SMIF0_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_QSPI_D2_PORT_NUM 1U +#define CYBSP_QSPI_D2_PIN 2U +#define CYBSP_QSPI_D2_NUM 2U +#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_2_HSIOM + #define ioss_0_port_1_pin_2_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_QSPI_D2_HSIOM ioss_0_port_1_pin_2_HSIOM +#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_QSPI_D3_ENABLED 1U +#define CYBSP_QSPI_D3_PORT (GPIO_PRT_Type *)SMIF0_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_QSPI_D3_PORT_NUM 1U +#define CYBSP_QSPI_D3_PIN 3U +#define CYBSP_QSPI_D3_NUM 3U +#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_3_HSIOM + #define ioss_0_port_1_pin_3_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_QSPI_D3_HSIOM ioss_0_port_1_pin_3_HSIOM +#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_QSPI_CS_ENABLED 1U +#define CYBSP_QSPI_SS_ENABLED CYBSP_QSPI_CS_ENABLED +#define CYBSP_QSPI_CS_PORT GPIO_PRT2 +#define CYBSP_QSPI_SS_PORT CYBSP_QSPI_CS_PORT +#define CYBSP_QSPI_CS_PORT_NUM 2U +#define CYBSP_QSPI_SS_PORT_NUM CYBSP_QSPI_CS_PORT_NUM +#define CYBSP_QSPI_CS_PIN 0U +#define CYBSP_QSPI_SS_PIN CYBSP_QSPI_CS_PIN +#define CYBSP_QSPI_CS_NUM 0U +#define CYBSP_QSPI_SS_NUM CYBSP_QSPI_CS_NUM +#define CYBSP_QSPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_QSPI_SS_DRIVEMODE CYBSP_QSPI_CS_DRIVEMODE +#define CYBSP_QSPI_CS_INIT_DRIVESTATE 1 +#define CYBSP_QSPI_SS_INIT_DRIVESTATE CYBSP_QSPI_CS_INIT_DRIVESTATE +#ifndef ioss_0_port_2_pin_0_HSIOM + #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_CS_HSIOM ioss_0_port_2_pin_0_HSIOM +#define CYBSP_QSPI_SS_HSIOM CYBSP_QSPI_CS_HSIOM +#define CYBSP_QSPI_CS_IRQ ioss_interrupts_gpio_2_IRQn +#define CYBSP_QSPI_SS_IRQ CYBSP_QSPI_CS_IRQ +#define CYBSP_I3C_SCL_ENABLED 1U +#define CYBSP_I3C_SCL_PORT GPIO_PRT3 +#define CYBSP_I3C_SCL_PORT_NUM 3U +#define CYBSP_I3C_SCL_PIN 0U +#define CYBSP_I3C_SCL_NUM 0U +#define CYBSP_I3C_SCL_DRIVEMODE CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ +#define CYBSP_I3C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_0_HSIOM + #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I3C_SCL_HSIOM ioss_0_port_3_pin_0_HSIOM +#define CYBSP_I3C_SCL_IRQ ioss_interrupts_gpio_3_IRQn +#define CYBSP_I3C_SDA_ENABLED 1U +#define CYBSP_I3C_SDA_PORT GPIO_PRT3 +#define CYBSP_I3C_SDA_PORT_NUM 3U +#define CYBSP_I3C_SDA_PIN 1U +#define CYBSP_I3C_SDA_NUM 1U +#define CYBSP_I3C_SDA_DRIVEMODE CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ +#define CYBSP_I3C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_1_HSIOM + #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I3C_SDA_HSIOM ioss_0_port_3_pin_1_HSIOM +#define CYBSP_I3C_SDA_IRQ ioss_interrupts_gpio_3_IRQn +#define CYBSP_OSPI_RAM_D0_ENABLED 1U +#define CYBSP_OSPI_RAM_D0_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_OSPI_RAM_D0_PORT_NUM 4U +#define CYBSP_OSPI_RAM_D0_PIN 0U +#define CYBSP_OSPI_RAM_D0_NUM 0U +#define CYBSP_OSPI_RAM_D0_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_OSPI_RAM_D0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_0_HSIOM + #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_OSPI_RAM_D0_HSIOM ioss_0_port_4_pin_0_HSIOM +#define CYBSP_OSPI_RAM_D0_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_OSPI_RAM_D1_ENABLED 1U +#define CYBSP_OSPI_RAM_D1_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_OSPI_RAM_D1_PORT_NUM 4U +#define CYBSP_OSPI_RAM_D1_PIN 1U +#define CYBSP_OSPI_RAM_D1_NUM 1U +#define CYBSP_OSPI_RAM_D1_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_OSPI_RAM_D1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_1_HSIOM + #define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_OSPI_RAM_D1_HSIOM ioss_0_port_4_pin_1_HSIOM +#define CYBSP_OSPI_RAM_D1_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_OSPI_RAM_D2_ENABLED 1U +#define CYBSP_OSPI_RAM_D2_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_OSPI_RAM_D2_PORT_NUM 4U +#define CYBSP_OSPI_RAM_D2_PIN 2U +#define CYBSP_OSPI_RAM_D2_NUM 2U +#define CYBSP_OSPI_RAM_D2_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_OSPI_RAM_D2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_2_HSIOM + #define ioss_0_port_4_pin_2_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_OSPI_RAM_D2_HSIOM ioss_0_port_4_pin_2_HSIOM +#define CYBSP_OSPI_RAM_D2_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_OSPI_RAM_D3_ENABLED 1U +#define CYBSP_OSPI_RAM_D3_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_OSPI_RAM_D3_PORT_NUM 4U +#define CYBSP_OSPI_RAM_D3_PIN 3U +#define CYBSP_OSPI_RAM_D3_NUM 3U +#define CYBSP_OSPI_RAM_D3_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_OSPI_RAM_D3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_3_HSIOM + #define ioss_0_port_4_pin_3_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_OSPI_RAM_D3_HSIOM ioss_0_port_4_pin_3_HSIOM +#define CYBSP_OSPI_RAM_D3_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_OSPI_RAM_D4_ENABLED 1U +#define CYBSP_OSPI_RAM_D4_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_OSPI_RAM_D4_PORT_NUM 4U +#define CYBSP_OSPI_RAM_D4_PIN 4U +#define CYBSP_OSPI_RAM_D4_NUM 4U +#define CYBSP_OSPI_RAM_D4_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_OSPI_RAM_D4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_4_HSIOM + #define ioss_0_port_4_pin_4_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_OSPI_RAM_D4_HSIOM ioss_0_port_4_pin_4_HSIOM +#define CYBSP_OSPI_RAM_D4_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_OSPI_RAM_D5_ENABLED 1U +#define CYBSP_OSPI_RAM_D5_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_OSPI_RAM_D5_PORT_NUM 4U +#define CYBSP_OSPI_RAM_D5_PIN 5U +#define CYBSP_OSPI_RAM_D5_NUM 5U +#define CYBSP_OSPI_RAM_D5_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_OSPI_RAM_D5_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_5_HSIOM + #define ioss_0_port_4_pin_5_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_OSPI_RAM_D5_HSIOM ioss_0_port_4_pin_5_HSIOM +#define CYBSP_OSPI_RAM_D5_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_OSPI_RAM_D6_ENABLED 1U +#define CYBSP_OSPI_RAM_D6_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_OSPI_RAM_D6_PORT_NUM 4U +#define CYBSP_OSPI_RAM_D6_PIN 6U +#define CYBSP_OSPI_RAM_D6_NUM 6U +#define CYBSP_OSPI_RAM_D6_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_OSPI_RAM_D6_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_6_HSIOM + #define ioss_0_port_4_pin_6_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_OSPI_RAM_D6_HSIOM ioss_0_port_4_pin_6_HSIOM +#define CYBSP_OSPI_RAM_D6_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_OSPI_RAM_D7_ENABLED 1U +#define CYBSP_OSPI_RAM_D7_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0 +#define CYBSP_OSPI_RAM_D7_PORT_NUM 4U +#define CYBSP_OSPI_RAM_D7_PIN 7U +#define CYBSP_OSPI_RAM_D7_NUM 7U +#define CYBSP_OSPI_RAM_D7_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_OSPI_RAM_D7_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_7_HSIOM + #define ioss_0_port_4_pin_7_HSIOM HSIOM_SEL_ACT_15 +#endif +#define CYBSP_OSPI_RAM_D7_HSIOM ioss_0_port_4_pin_7_HSIOM +#define CYBSP_OSPI_RAM_D7_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_DEBUG_UART_RX_ENABLED 1U +#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT6 +#define CYBSP_DEBUG_UART_RX_PORT_NUM 6U +#define CYBSP_DEBUG_UART_RX_PIN 5U +#define CYBSP_DEBUG_UART_RX_NUM 5U +#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_5_HSIOM + #define ioss_0_port_6_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_6_pin_5_HSIOM +#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_DEBUG_UART_TX_ENABLED 1U +#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT6 +#define CYBSP_DEBUG_UART_TX_PORT_NUM 6U +#define CYBSP_DEBUG_UART_TX_PIN 7U +#define CYBSP_DEBUG_UART_TX_NUM 7U +#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_6_pin_7_HSIOM +#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_SW1_ENABLED 1U +#define CYBSP_USER_BTN1_ENABLED CYBSP_SW1_ENABLED +#define CYBSP_USER_BTN_ENABLED CYBSP_SW1_ENABLED +#define CYBSP_SW1_PORT GPIO_PRT7 +#define CYBSP_USER_BTN1_PORT CYBSP_SW1_PORT +#define CYBSP_USER_BTN_PORT CYBSP_SW1_PORT +#define CYBSP_SW1_PORT_NUM 7U +#define CYBSP_USER_BTN1_PORT_NUM CYBSP_SW1_PORT_NUM +#define CYBSP_USER_BTN_PORT_NUM CYBSP_SW1_PORT_NUM +#define CYBSP_SW1_PIN 0U +#define CYBSP_USER_BTN1_PIN CYBSP_SW1_PIN +#define CYBSP_USER_BTN_PIN CYBSP_SW1_PIN +#define CYBSP_SW1_NUM 0U +#define CYBSP_USER_BTN1_NUM CYBSP_SW1_NUM +#define CYBSP_USER_BTN_NUM CYBSP_SW1_NUM +#define CYBSP_SW1_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_USER_BTN1_DRIVEMODE CYBSP_SW1_DRIVEMODE +#define CYBSP_USER_BTN_DRIVEMODE CYBSP_SW1_DRIVEMODE +#define CYBSP_SW1_INIT_DRIVESTATE 1 +#define CYBSP_USER_BTN1_INIT_DRIVESTATE CYBSP_SW1_INIT_DRIVESTATE +#define CYBSP_USER_BTN_INIT_DRIVESTATE CYBSP_SW1_INIT_DRIVESTATE +#ifndef ioss_0_port_7_pin_0_HSIOM + #define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SW1_HSIOM ioss_0_port_7_pin_0_HSIOM +#define CYBSP_USER_BTN1_HSIOM CYBSP_SW1_HSIOM +#define CYBSP_USER_BTN_HSIOM CYBSP_SW1_HSIOM +#define CYBSP_SW1_IRQ ioss_interrupts_gpio_7_IRQn +#define CYBSP_USER_BTN1_IRQ CYBSP_SW1_IRQ +#define CYBSP_USER_BTN_IRQ CYBSP_SW1_IRQ +#define CYBSP_EXT_CLK_ENABLED 1U +#define CYBSP_EXT_CLK_PORT GPIO_PRT7 +#define CYBSP_EXT_CLK_PORT_NUM 7U +#define CYBSP_EXT_CLK_PIN 4U +#define CYBSP_EXT_CLK_NUM 4U +#define CYBSP_EXT_CLK_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_EXT_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_4_HSIOM + #define ioss_0_port_7_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_EXT_CLK_HSIOM ioss_0_port_7_pin_4_HSIOM +#define CYBSP_EXT_CLK_IRQ ioss_interrupts_gpio_7_IRQn +#define CYBSP_I2C_SCL_1V8_ENABLED 1U +#define CYBSP_I2C_SCL_ENABLED CYBSP_I2C_SCL_1V8_ENABLED +#define CYBSP_I2C_SCL_1V8_PORT GPIO_PRT8 +#define CYBSP_I2C_SCL_PORT CYBSP_I2C_SCL_1V8_PORT +#define CYBSP_I2C_SCL_1V8_PORT_NUM 8U +#define CYBSP_I2C_SCL_PORT_NUM CYBSP_I2C_SCL_1V8_PORT_NUM +#define CYBSP_I2C_SCL_1V8_PIN 0U +#define CYBSP_I2C_SCL_PIN CYBSP_I2C_SCL_1V8_PIN +#define CYBSP_I2C_SCL_1V8_NUM 0U +#define CYBSP_I2C_SCL_NUM CYBSP_I2C_SCL_1V8_NUM +#define CYBSP_I2C_SCL_1V8_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_I2C_SCL_DRIVEMODE CYBSP_I2C_SCL_1V8_DRIVEMODE +#define CYBSP_I2C_SCL_1V8_INIT_DRIVESTATE 1 +#define CYBSP_I2C_SCL_INIT_DRIVESTATE CYBSP_I2C_SCL_1V8_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_0_HSIOM + #define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2C_SCL_1V8_HSIOM ioss_0_port_8_pin_0_HSIOM +#define CYBSP_I2C_SCL_HSIOM CYBSP_I2C_SCL_1V8_HSIOM +#define CYBSP_I2C_SCL_1V8_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_I2C_SCL_IRQ CYBSP_I2C_SCL_1V8_IRQ +#define CYBSP_I2C_SDA_1V8_ENABLED 1U +#define CYBSP_I2C_SDA_ENABLED CYBSP_I2C_SDA_1V8_ENABLED +#define CYBSP_I2C_SDA_1V8_PORT GPIO_PRT8 +#define CYBSP_I2C_SDA_PORT CYBSP_I2C_SDA_1V8_PORT +#define CYBSP_I2C_SDA_1V8_PORT_NUM 8U +#define CYBSP_I2C_SDA_PORT_NUM CYBSP_I2C_SDA_1V8_PORT_NUM +#define CYBSP_I2C_SDA_1V8_PIN 1U +#define CYBSP_I2C_SDA_PIN CYBSP_I2C_SDA_1V8_PIN +#define CYBSP_I2C_SDA_1V8_NUM 1U +#define CYBSP_I2C_SDA_NUM CYBSP_I2C_SDA_1V8_NUM +#define CYBSP_I2C_SDA_1V8_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_I2C_SDA_DRIVEMODE CYBSP_I2C_SDA_1V8_DRIVEMODE +#define CYBSP_I2C_SDA_1V8_INIT_DRIVESTATE 1 +#define CYBSP_I2C_SDA_INIT_DRIVESTATE CYBSP_I2C_SDA_1V8_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2C_SDA_1V8_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CYBSP_I2C_SDA_HSIOM CYBSP_I2C_SDA_1V8_HSIOM +#define CYBSP_I2C_SDA_1V8_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_I2C_SDA_IRQ CYBSP_I2C_SDA_1V8_IRQ +#define CYBSP_PDM_CLK_ENABLED 1U +#define CYBSP_PDM_CLK_PORT GPIO_PRT8 +#define CYBSP_PDM_CLK_PORT_NUM 8U +#define CYBSP_PDM_CLK_PIN 5U +#define CYBSP_PDM_CLK_NUM 5U +#define CYBSP_PDM_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_PDM_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_5_HSIOM + #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_PDM_CLK_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CYBSP_PDM_CLK_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_PDM_DATA_ENABLED 1U +#define CYBSP_PDM_DATA_PORT GPIO_PRT8 +#define CYBSP_PDM_DATA_PORT_NUM 8U +#define CYBSP_PDM_DATA_PIN 6U +#define CYBSP_PDM_DATA_NUM 6U +#define CYBSP_PDM_DATA_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_PDM_DATA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_6_HSIOM + #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_PDM_DATA_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CYBSP_PDM_DATA_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_SERIAL_INT_0_ENABLED 1U +#define CYBSP_SERIAL_INT_0_PORT GPIO_PRT9 +#define CYBSP_SERIAL_INT_0_PORT_NUM 9U +#define CYBSP_SERIAL_INT_0_PIN 0U +#define CYBSP_SERIAL_INT_0_NUM 0U +#define CYBSP_SERIAL_INT_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SERIAL_INT_0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_0_HSIOM + #define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SERIAL_INT_0_HSIOM ioss_0_port_9_pin_0_HSIOM +#define CYBSP_SERIAL_INT_0_IRQ ioss_interrupts_gpio_9_IRQn +#define CYBSP_SERIAL_INT_2_ENABLED 1U +#define CYBSP_SERIAL_INT_2_PORT GPIO_PRT9 +#define CYBSP_SERIAL_INT_2_PORT_NUM 9U +#define CYBSP_SERIAL_INT_2_PIN 2U +#define CYBSP_SERIAL_INT_2_NUM 2U +#define CYBSP_SERIAL_INT_2_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SERIAL_INT_2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_2_HSIOM + #define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SERIAL_INT_2_HSIOM ioss_0_port_9_pin_2_HSIOM +#define CYBSP_SERIAL_INT_2_IRQ ioss_interrupts_gpio_9_IRQn +#define CYBSP_BT_UART_RX_ENABLED 1U +#define CYBSP_BT_UART_RX_PORT GPIO_PRT10 +#define CYBSP_BT_UART_RX_PORT_NUM 10U +#define CYBSP_BT_UART_RX_PIN 0U +#define CYBSP_BT_UART_RX_NUM 0U +#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_10_pin_0_HSIOM + #define ioss_0_port_10_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_10_pin_0_HSIOM +#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_10_IRQn +#define CYBSP_BT_UART_TX_ENABLED 1U +#define CYBSP_BT_UART_TX_PORT GPIO_PRT10 +#define CYBSP_BT_UART_TX_PORT_NUM 10U +#define CYBSP_BT_UART_TX_PIN 1U +#define CYBSP_BT_UART_TX_NUM 1U +#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_10_pin_1_HSIOM + #define ioss_0_port_10_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_10_pin_1_HSIOM +#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_10_IRQn +#define CYBSP_BT_UART_CTS_ENABLED 1U +#define CYBSP_BT_UART_CTS_PORT GPIO_PRT10 +#define CYBSP_BT_UART_CTS_PORT_NUM 10U +#define CYBSP_BT_UART_CTS_PIN 2U +#define CYBSP_BT_UART_CTS_NUM 2U +#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_10_pin_2_HSIOM + #define ioss_0_port_10_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_10_pin_2_HSIOM +#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_10_IRQn +#define CYBSP_BT_UART_RTS_ENABLED 1U +#define CYBSP_BT_UART_RTS_PORT GPIO_PRT10 +#define CYBSP_BT_UART_RTS_PORT_NUM 10U +#define CYBSP_BT_UART_RTS_PIN 3U +#define CYBSP_BT_UART_RTS_NUM 3U +#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_10_pin_3_HSIOM + #define ioss_0_port_10_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_10_pin_3_HSIOM +#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_10_IRQn +#define CYBSP_BT_HOST_WAKE_ENABLED 1U +#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT10 +#define CYBSP_BT_HOST_WAKE_PORT_NUM 10U +#define CYBSP_BT_HOST_WAKE_PIN 4U +#define CYBSP_BT_HOST_WAKE_NUM 4U +#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_10_pin_4_HSIOM + #define ioss_0_port_10_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_10_pin_4_HSIOM +#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_10_IRQn +#define CYBSP_USER_LED2_ENABLED 1U +#define CYBSP_USER_LED2_PORT GPIO_PRT10 +#define CYBSP_USER_LED2_PORT_NUM 10U +#define CYBSP_USER_LED2_PIN 5U +#define CYBSP_USER_LED2_NUM 5U +#define CYBSP_USER_LED2_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_USER_LED2_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_10_pin_5_HSIOM + #define ioss_0_port_10_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USER_LED2_HSIOM ioss_0_port_10_pin_5_HSIOM +#define CYBSP_USER_LED2_IRQ ioss_interrupts_gpio_10_IRQn +#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U +#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT10 +#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 10U +#define CYBSP_BT_DEVICE_WAKE_PIN 6U +#define CYBSP_BT_DEVICE_WAKE_NUM 6U +#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_10_pin_6_HSIOM + #define ioss_0_port_10_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_10_pin_6_HSIOM +#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_10_IRQn +#define CYBSP_USER_LED1_ENABLED 1U +#define CYBSP_USER_LED_ENABLED CYBSP_USER_LED1_ENABLED +#define CYBSP_USER_LED1_PORT GPIO_PRT10 +#define CYBSP_USER_LED_PORT CYBSP_USER_LED1_PORT +#define CYBSP_USER_LED1_PORT_NUM 10U +#define CYBSP_USER_LED_PORT_NUM CYBSP_USER_LED1_PORT_NUM +#define CYBSP_USER_LED1_PIN 7U +#define CYBSP_USER_LED_PIN CYBSP_USER_LED1_PIN +#define CYBSP_USER_LED1_NUM 7U +#define CYBSP_USER_LED_NUM CYBSP_USER_LED1_NUM +#define CYBSP_USER_LED1_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_USER_LED_DRIVEMODE CYBSP_USER_LED1_DRIVEMODE +#define CYBSP_USER_LED1_INIT_DRIVESTATE 0 +#define CYBSP_USER_LED_INIT_DRIVESTATE CYBSP_USER_LED1_INIT_DRIVESTATE +#ifndef ioss_0_port_10_pin_7_HSIOM + #define ioss_0_port_10_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USER_LED1_HSIOM ioss_0_port_10_pin_7_HSIOM +#define CYBSP_USER_LED_HSIOM CYBSP_USER_LED1_HSIOM +#define CYBSP_USER_LED1_IRQ ioss_interrupts_gpio_10_IRQn +#define CYBSP_USER_LED_IRQ CYBSP_USER_LED1_IRQ +#define CYBSP_BT_POWER_ENABLED 1U +#define CYBSP_BT_POWER_PORT GPIO_PRT11 +#define CYBSP_BT_POWER_PORT_NUM 11U +#define CYBSP_BT_POWER_PIN 0U +#define CYBSP_BT_POWER_NUM 0U +#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_BT_POWER_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_0_HSIOM + #define ioss_0_port_11_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_POWER_HSIOM ioss_0_port_11_pin_0_HSIOM +#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_DVP_CAM_PCLK_ENABLED 1U +#define CYBSP_DVP_CAM_PCLK_PORT GPIO_PRT11 +#define CYBSP_DVP_CAM_PCLK_PORT_NUM 11U +#define CYBSP_DVP_CAM_PCLK_PIN 1U +#define CYBSP_DVP_CAM_PCLK_NUM 1U +#define CYBSP_DVP_CAM_PCLK_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_PCLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_PCLK_HSIOM ioss_0_port_11_pin_1_HSIOM +#define CYBSP_DVP_CAM_PCLK_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_WIFI_WL_REG_ON_ENABLED 1U +#define CYBSP_WIFI_WL_REG_ON_PORT GPIO_PRT11 +#define CYBSP_WIFI_WL_REG_ON_PORT_NUM 11U +#define CYBSP_WIFI_WL_REG_ON_PIN 4U +#define CYBSP_WIFI_WL_REG_ON_NUM 4U +#define CYBSP_WIFI_WL_REG_ON_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_WIFI_WL_REG_ON_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_WL_REG_ON_HSIOM ioss_0_port_11_pin_4_HSIOM +#define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U +#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT11 +#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 11U +#define CYBSP_WIFI_HOST_WAKE_PIN 6U +#define CYBSP_WIFI_HOST_WAKE_NUM 6U +#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_11_pin_6_HSIOM +#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U +#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT12 +#define CYBSP_WIFI_SDIO_CLK_PORT_NUM 12U +#define CYBSP_WIFI_SDIO_CLK_PIN 0U +#define CYBSP_WIFI_SDIO_CLK_NUM 0U +#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_0_HSIOM + #define ioss_0_port_12_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_12_pin_0_HSIOM +#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_12_IRQn +#define CYBSP_WIFI_SDIO_D0_ENABLED 1U +#define CYBSP_WIFI_SDIO_D0_PORT GPIO_PRT12 +#define CYBSP_WIFI_SDIO_D0_PORT_NUM 12U +#define CYBSP_WIFI_SDIO_D0_PIN 1U +#define CYBSP_WIFI_SDIO_D0_NUM 1U +#define CYBSP_WIFI_SDIO_D0_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_WIFI_SDIO_D0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_1_HSIOM + #define ioss_0_port_12_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_SDIO_D0_HSIOM ioss_0_port_12_pin_1_HSIOM +#define CYBSP_WIFI_SDIO_D0_IRQ ioss_interrupts_gpio_12_IRQn +#define CYBSP_WIFI_SDIO_D1_ENABLED 1U +#define CYBSP_WIFI_SDIO_D1_PORT GPIO_PRT12 +#define CYBSP_WIFI_SDIO_D1_PORT_NUM 12U +#define CYBSP_WIFI_SDIO_D1_PIN 2U +#define CYBSP_WIFI_SDIO_D1_NUM 2U +#define CYBSP_WIFI_SDIO_D1_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_WIFI_SDIO_D1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_2_HSIOM + #define ioss_0_port_12_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_SDIO_D1_HSIOM ioss_0_port_12_pin_2_HSIOM +#define CYBSP_WIFI_SDIO_D1_IRQ ioss_interrupts_gpio_12_IRQn +#define CYBSP_I2S_TX_FSYNC_ENABLED 1U +#define CYBSP_I2S_TX_FSYNC_PORT GPIO_PRT12 +#define CYBSP_I2S_TX_FSYNC_PORT_NUM 12U +#define CYBSP_I2S_TX_FSYNC_PIN 3U +#define CYBSP_I2S_TX_FSYNC_NUM 3U +#define CYBSP_I2S_TX_FSYNC_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_I2S_TX_FSYNC_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_3_HSIOM + #define ioss_0_port_12_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2S_TX_FSYNC_HSIOM ioss_0_port_12_pin_3_HSIOM +#define CYBSP_I2S_TX_FSYNC_IRQ ioss_interrupts_gpio_12_IRQn +#define CYBSP_WIFI_SDIO_D2_ENABLED 1U +#define CYBSP_WIFI_SDIO_D2_PORT GPIO_PRT12 +#define CYBSP_WIFI_SDIO_D2_PORT_NUM 12U +#define CYBSP_WIFI_SDIO_D2_PIN 4U +#define CYBSP_WIFI_SDIO_D2_NUM 4U +#define CYBSP_WIFI_SDIO_D2_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_WIFI_SDIO_D2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_4_HSIOM + #define ioss_0_port_12_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_SDIO_D2_HSIOM ioss_0_port_12_pin_4_HSIOM +#define CYBSP_WIFI_SDIO_D2_IRQ ioss_interrupts_gpio_12_IRQn +#define CYBSP_WIFI_SDIO_D3_ENABLED 1U +#define CYBSP_WIFI_SDIO_D3_PORT GPIO_PRT12 +#define CYBSP_WIFI_SDIO_D3_PORT_NUM 12U +#define CYBSP_WIFI_SDIO_D3_PIN 5U +#define CYBSP_WIFI_SDIO_D3_NUM 5U +#define CYBSP_WIFI_SDIO_D3_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_WIFI_SDIO_D3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_5_HSIOM + #define ioss_0_port_12_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_12_pin_5_HSIOM +#define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_12_IRQn +#define CYBSP_DVP_CAM_D0_ENABLED 1U +#define CYBSP_DVP_CAM_D0_PORT GPIO_PRT16 +#define CYBSP_DVP_CAM_D0_PORT_NUM 16U +#define CYBSP_DVP_CAM_D0_PIN 0U +#define CYBSP_DVP_CAM_D0_NUM 0U +#define CYBSP_DVP_CAM_D0_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_D0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_16_pin_0_HSIOM + #define ioss_0_port_16_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_D0_HSIOM ioss_0_port_16_pin_0_HSIOM +#define CYBSP_DVP_CAM_D0_IRQ ioss_interrupts_gpio_16_IRQn +#define CYBSP_DVP_CAM_D1_ENABLED 1U +#define CYBSP_DVP_CAM_D1_PORT GPIO_PRT16 +#define CYBSP_DVP_CAM_D1_PORT_NUM 16U +#define CYBSP_DVP_CAM_D1_PIN 1U +#define CYBSP_DVP_CAM_D1_NUM 1U +#define CYBSP_DVP_CAM_D1_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_D1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_16_pin_1_HSIOM + #define ioss_0_port_16_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_D1_HSIOM ioss_0_port_16_pin_1_HSIOM +#define CYBSP_DVP_CAM_D1_IRQ ioss_interrupts_gpio_16_IRQn +#define CYBSP_DVP_CAM_D2_ENABLED 1U +#define CYBSP_DVP_CAM_D2_PORT GPIO_PRT16 +#define CYBSP_DVP_CAM_D2_PORT_NUM 16U +#define CYBSP_DVP_CAM_D2_PIN 2U +#define CYBSP_DVP_CAM_D2_NUM 2U +#define CYBSP_DVP_CAM_D2_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_D2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_16_pin_2_HSIOM + #define ioss_0_port_16_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_D2_HSIOM ioss_0_port_16_pin_2_HSIOM +#define CYBSP_DVP_CAM_D2_IRQ ioss_interrupts_gpio_16_IRQn +#define CYBSP_DVP_CAM_D3_ENABLED 1U +#define CYBSP_DVP_CAM_D3_PORT GPIO_PRT16 +#define CYBSP_DVP_CAM_D3_PORT_NUM 16U +#define CYBSP_DVP_CAM_D3_PIN 3U +#define CYBSP_DVP_CAM_D3_NUM 3U +#define CYBSP_DVP_CAM_D3_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_D3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_16_pin_3_HSIOM + #define ioss_0_port_16_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_D3_HSIOM ioss_0_port_16_pin_3_HSIOM +#define CYBSP_DVP_CAM_D3_IRQ ioss_interrupts_gpio_16_IRQn +#define CYBSP_DVP_CAM_D4_ENABLED 1U +#define CYBSP_DVP_CAM_D4_PORT GPIO_PRT16 +#define CYBSP_DVP_CAM_D4_PORT_NUM 16U +#define CYBSP_DVP_CAM_D4_PIN 4U +#define CYBSP_DVP_CAM_D4_NUM 4U +#define CYBSP_DVP_CAM_D4_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_D4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_16_pin_4_HSIOM + #define ioss_0_port_16_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_D4_HSIOM ioss_0_port_16_pin_4_HSIOM +#define CYBSP_DVP_CAM_D4_IRQ ioss_interrupts_gpio_16_IRQn +#define CYBSP_DVP_CAM_D5_ENABLED 1U +#define CYBSP_DVP_CAM_D5_PORT GPIO_PRT16 +#define CYBSP_DVP_CAM_D5_PORT_NUM 16U +#define CYBSP_DVP_CAM_D5_PIN 5U +#define CYBSP_DVP_CAM_D5_NUM 5U +#define CYBSP_DVP_CAM_D5_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_D5_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_16_pin_5_HSIOM + #define ioss_0_port_16_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_D5_HSIOM ioss_0_port_16_pin_5_HSIOM +#define CYBSP_DVP_CAM_D5_IRQ ioss_interrupts_gpio_16_IRQn +#define CYBSP_DVP_CAM_D6_ENABLED 1U +#define CYBSP_DVP_CAM_D6_PORT GPIO_PRT16 +#define CYBSP_DVP_CAM_D6_PORT_NUM 16U +#define CYBSP_DVP_CAM_D6_PIN 6U +#define CYBSP_DVP_CAM_D6_NUM 6U +#define CYBSP_DVP_CAM_D6_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_D6_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_16_pin_6_HSIOM + #define ioss_0_port_16_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_D6_HSIOM ioss_0_port_16_pin_6_HSIOM +#define CYBSP_DVP_CAM_D6_IRQ ioss_interrupts_gpio_16_IRQn +#define CYBSP_DVP_CAM_D7_ENABLED 1U +#define CYBSP_DVP_CAM_D7_PORT GPIO_PRT16 +#define CYBSP_DVP_CAM_D7_PORT_NUM 16U +#define CYBSP_DVP_CAM_D7_PIN 7U +#define CYBSP_DVP_CAM_D7_NUM 7U +#define CYBSP_DVP_CAM_D7_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_D7_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_16_pin_7_HSIOM + #define ioss_0_port_16_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_D7_HSIOM ioss_0_port_16_pin_7_HSIOM +#define CYBSP_DVP_CAM_D7_IRQ ioss_interrupts_gpio_16_IRQn +#define CYBSP_I2C_SCL_3V3_ENABLED 1U +#define CYBSP_I2C_SCL_3V3_PORT GPIO_PRT17 +#define CYBSP_I2C_SCL_3V3_PORT_NUM 17U +#define CYBSP_I2C_SCL_3V3_PIN 0U +#define CYBSP_I2C_SCL_3V3_NUM 0U +#define CYBSP_I2C_SCL_3V3_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_I2C_SCL_3V3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_17_pin_0_HSIOM + #define ioss_0_port_17_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2C_SCL_3V3_HSIOM ioss_0_port_17_pin_0_HSIOM +#define CYBSP_I2C_SCL_3V3_IRQ ioss_interrupts_gpio_17_IRQn +#define CYBSP_I2C_SDA_3V3_ENABLED 1U +#define CYBSP_I2C_SDA_3V3_PORT GPIO_PRT17 +#define CYBSP_I2C_SDA_3V3_PORT_NUM 17U +#define CYBSP_I2C_SDA_3V3_PIN 1U +#define CYBSP_I2C_SDA_3V3_NUM 1U +#define CYBSP_I2C_SDA_3V3_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_I2C_SDA_3V3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_17_pin_1_HSIOM + #define ioss_0_port_17_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2C_SDA_3V3_HSIOM ioss_0_port_17_pin_1_HSIOM +#define CYBSP_I2C_SDA_3V3_IRQ ioss_interrupts_gpio_17_IRQn +#define CYBSP_DVP_CAM_VSYNC_ENABLED 1U +#define CYBSP_DVP_CAM_VSYNC_PORT GPIO_PRT17 +#define CYBSP_DVP_CAM_VSYNC_PORT_NUM 17U +#define CYBSP_DVP_CAM_VSYNC_PIN 2U +#define CYBSP_DVP_CAM_VSYNC_NUM 2U +#define CYBSP_DVP_CAM_VSYNC_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_VSYNC_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_17_pin_2_HSIOM + #define ioss_0_port_17_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_VSYNC_HSIOM ioss_0_port_17_pin_2_HSIOM +#define CYBSP_DVP_CAM_VSYNC_IRQ ioss_interrupts_gpio_17_IRQn +#define CYBSP_DVP_CAM_HREF_ENABLED 1U +#define CYBSP_DVP_CAM_HREF_PORT GPIO_PRT17 +#define CYBSP_DVP_CAM_HREF_PORT_NUM 17U +#define CYBSP_DVP_CAM_HREF_PIN 3U +#define CYBSP_DVP_CAM_HREF_NUM 3U +#define CYBSP_DVP_CAM_HREF_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DVP_CAM_HREF_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_17_pin_3_HSIOM + #define ioss_0_port_17_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_HREF_HSIOM ioss_0_port_17_pin_3_HSIOM +#define CYBSP_DVP_CAM_HREF_IRQ ioss_interrupts_gpio_17_IRQn +#define CYBSP_DVP_CAM_XCLK_ENABLED 1U +#define CYBSP_DVP_CAM_XCLK_PORT GPIO_PRT17 +#define CYBSP_DVP_CAM_XCLK_PORT_NUM 17U +#define CYBSP_DVP_CAM_XCLK_PIN 4U +#define CYBSP_DVP_CAM_XCLK_NUM 4U +#define CYBSP_DVP_CAM_XCLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_DVP_CAM_XCLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_17_pin_4_HSIOM + #define ioss_0_port_17_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_XCLK_HSIOM ioss_0_port_17_pin_4_HSIOM +#define CYBSP_DVP_CAM_XCLK_IRQ ioss_interrupts_gpio_17_IRQn +#define CYBSP_DVP_CAM_RESET_ENABLED 1U +#define CYBSP_DVP_CAM_RESET_PORT GPIO_PRT17 +#define CYBSP_DVP_CAM_RESET_PORT_NUM 17U +#define CYBSP_DVP_CAM_RESET_PIN 5U +#define CYBSP_DVP_CAM_RESET_NUM 5U +#define CYBSP_DVP_CAM_RESET_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_DVP_CAM_RESET_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_17_pin_5_HSIOM + #define ioss_0_port_17_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_RESET_HSIOM ioss_0_port_17_pin_5_HSIOM +#define CYBSP_DVP_CAM_RESET_IRQ ioss_interrupts_gpio_17_IRQn +#define CYBSP_DVP_CAM_PWDN_ENABLED 1U +#define CYBSP_DVP_CAM_PWDN_PORT GPIO_PRT17 +#define CYBSP_DVP_CAM_PWDN_PORT_NUM 17U +#define CYBSP_DVP_CAM_PWDN_PIN 7U +#define CYBSP_DVP_CAM_PWDN_NUM 7U +#define CYBSP_DVP_CAM_PWDN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_DVP_CAM_PWDN_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_17_pin_7_HSIOM + #define ioss_0_port_17_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DVP_CAM_PWDN_HSIOM ioss_0_port_17_pin_7_HSIOM +#define CYBSP_DVP_CAM_PWDN_IRQ ioss_interrupts_gpio_17_IRQn +#define CYBSP_WCO_OUT_ENABLED 1U +#define CYBSP_WCO_OUT_PORT GPIO_PRT18 +#define CYBSP_WCO_OUT_PORT_NUM 18U +#define CYBSP_WCO_OUT_PIN 0U +#define CYBSP_WCO_OUT_NUM 0U +#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_18_pin_0_HSIOM + #define ioss_0_port_18_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_OUT_HSIOM ioss_0_port_18_pin_0_HSIOM +#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_18_IRQn +#define CYBSP_WCO_IN_ENABLED 1U +#define CYBSP_WCO_IN_PORT GPIO_PRT18 +#define CYBSP_WCO_IN_PORT_NUM 18U +#define CYBSP_WCO_IN_PIN 1U +#define CYBSP_WCO_IN_NUM 1U +#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_18_pin_1_HSIOM + #define ioss_0_port_18_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_IN_HSIOM ioss_0_port_18_pin_1_HSIOM +#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_18_IRQn +#define CYBSP_ECO_IN_ENABLED 1U +#define CYBSP_ECO_IN_PORT GPIO_PRT19 +#define CYBSP_ECO_IN_PORT_NUM 19U +#define CYBSP_ECO_IN_PIN 0U +#define CYBSP_ECO_IN_NUM 0U +#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_ECO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_19_pin_0_HSIOM + #define ioss_0_port_19_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_ECO_IN_HSIOM ioss_0_port_19_pin_0_HSIOM +#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_19_IRQn +#define CYBSP_ECO_OUT_ENABLED 1U +#define CYBSP_ECO_OUT_PORT GPIO_PRT19 +#define CYBSP_ECO_OUT_PORT_NUM 19U +#define CYBSP_ECO_OUT_PIN 1U +#define CYBSP_ECO_OUT_NUM 1U +#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_19_pin_1_HSIOM + #define ioss_0_port_19_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_ECO_OUT_HSIOM ioss_0_port_19_pin_1_HSIOM +#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_19_IRQn +#define CYBSP_RADAR_INT_ENABLED 1U +#define CYBSP_RADAR_INT_PORT GPIO_PRT20 +#define CYBSP_RADAR_INT_PORT_NUM 20U +#define CYBSP_RADAR_INT_PIN 3U +#define CYBSP_RADAR_INT_NUM 3U +#define CYBSP_RADAR_INT_DRIVEMODE CY_GPIO_DM_PULLDOWN_IN_OFF +#define CYBSP_RADAR_INT_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_20_pin_3_HSIOM + #define ioss_0_port_20_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_RADAR_INT_HSIOM ioss_0_port_20_pin_3_HSIOM +#define CYBSP_RADAR_INT_IRQ ioss_interrupts_gpio_20_IRQn +#define CYBSP_LED_RGB_GREEN_ENABLED 1U +#define CYBSP_USER_LED5_ENABLED CYBSP_LED_RGB_GREEN_ENABLED +#define CYBSP_LED_RGB_GREEN_PORT GPIO_PRT20 +#define CYBSP_USER_LED5_PORT CYBSP_LED_RGB_GREEN_PORT +#define CYBSP_LED_RGB_GREEN_PORT_NUM 20U +#define CYBSP_USER_LED5_PORT_NUM CYBSP_LED_RGB_GREEN_PORT_NUM +#define CYBSP_LED_RGB_GREEN_PIN 4U +#define CYBSP_USER_LED5_PIN CYBSP_LED_RGB_GREEN_PIN +#define CYBSP_LED_RGB_GREEN_NUM 4U +#define CYBSP_USER_LED5_NUM CYBSP_LED_RGB_GREEN_NUM +#define CYBSP_LED_RGB_GREEN_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_USER_LED5_DRIVEMODE CYBSP_LED_RGB_GREEN_DRIVEMODE +#define CYBSP_LED_RGB_GREEN_INIT_DRIVESTATE 0 +#define CYBSP_USER_LED5_INIT_DRIVESTATE CYBSP_LED_RGB_GREEN_INIT_DRIVESTATE +#ifndef ioss_0_port_20_pin_4_HSIOM + #define ioss_0_port_20_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED_RGB_GREEN_HSIOM ioss_0_port_20_pin_4_HSIOM +#define CYBSP_USER_LED5_HSIOM CYBSP_LED_RGB_GREEN_HSIOM +#define CYBSP_LED_RGB_GREEN_IRQ ioss_interrupts_gpio_20_IRQn +#define CYBSP_USER_LED5_IRQ CYBSP_LED_RGB_GREEN_IRQ +#define CYBSP_LED_RGB_BLUE_ENABLED 1U +#define CYBSP_USER_LED4_ENABLED CYBSP_LED_RGB_BLUE_ENABLED +#define CYBSP_LED_RGB_BLUE_PORT GPIO_PRT20 +#define CYBSP_USER_LED4_PORT CYBSP_LED_RGB_BLUE_PORT +#define CYBSP_LED_RGB_BLUE_PORT_NUM 20U +#define CYBSP_USER_LED4_PORT_NUM CYBSP_LED_RGB_BLUE_PORT_NUM +#define CYBSP_LED_RGB_BLUE_PIN 5U +#define CYBSP_USER_LED4_PIN CYBSP_LED_RGB_BLUE_PIN +#define CYBSP_LED_RGB_BLUE_NUM 5U +#define CYBSP_USER_LED4_NUM CYBSP_LED_RGB_BLUE_NUM +#define CYBSP_LED_RGB_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_USER_LED4_DRIVEMODE CYBSP_LED_RGB_BLUE_DRIVEMODE +#define CYBSP_LED_RGB_BLUE_INIT_DRIVESTATE 0 +#define CYBSP_USER_LED4_INIT_DRIVESTATE CYBSP_LED_RGB_BLUE_INIT_DRIVESTATE +#ifndef ioss_0_port_20_pin_5_HSIOM + #define ioss_0_port_20_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED_RGB_BLUE_HSIOM ioss_0_port_20_pin_5_HSIOM +#define CYBSP_USER_LED4_HSIOM CYBSP_LED_RGB_BLUE_HSIOM +#define CYBSP_LED_RGB_BLUE_IRQ ioss_interrupts_gpio_20_IRQn +#define CYBSP_USER_LED4_IRQ CYBSP_LED_RGB_BLUE_IRQ +#define CYBSP_LED_RGB_RED_ENABLED 1U +#define CYBSP_USER_LED3_ENABLED CYBSP_LED_RGB_RED_ENABLED +#define CYBSP_LED_RGB_RED_PORT GPIO_PRT20 +#define CYBSP_USER_LED3_PORT CYBSP_LED_RGB_RED_PORT +#define CYBSP_LED_RGB_RED_PORT_NUM 20U +#define CYBSP_USER_LED3_PORT_NUM CYBSP_LED_RGB_RED_PORT_NUM +#define CYBSP_LED_RGB_RED_PIN 6U +#define CYBSP_USER_LED3_PIN CYBSP_LED_RGB_RED_PIN +#define CYBSP_LED_RGB_RED_NUM 6U +#define CYBSP_USER_LED3_NUM CYBSP_LED_RGB_RED_NUM +#define CYBSP_LED_RGB_RED_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_USER_LED3_DRIVEMODE CYBSP_LED_RGB_RED_DRIVEMODE +#define CYBSP_LED_RGB_RED_INIT_DRIVESTATE 0 +#define CYBSP_USER_LED3_INIT_DRIVESTATE CYBSP_LED_RGB_RED_INIT_DRIVESTATE +#ifndef ioss_0_port_20_pin_6_HSIOM + #define ioss_0_port_20_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED_RGB_RED_HSIOM ioss_0_port_20_pin_6_HSIOM +#define CYBSP_USER_LED3_HSIOM CYBSP_LED_RGB_RED_HSIOM +#define CYBSP_LED_RGB_RED_IRQ ioss_interrupts_gpio_20_IRQn +#define CYBSP_USER_LED3_IRQ CYBSP_LED_RGB_RED_IRQ +#define CYBSP_RXRES_L_ENABLED 1U +#define CYBSP_RADAR_RESET_ENABLED CYBSP_RXRES_L_ENABLED +#define CYBSP_RXRES_L_PORT GPIO_PRT20 +#define CYBSP_RADAR_RESET_PORT CYBSP_RXRES_L_PORT +#define CYBSP_RXRES_L_PORT_NUM 20U +#define CYBSP_RADAR_RESET_PORT_NUM CYBSP_RXRES_L_PORT_NUM +#define CYBSP_RXRES_L_PIN 7U +#define CYBSP_RADAR_RESET_PIN CYBSP_RXRES_L_PIN +#define CYBSP_RXRES_L_NUM 7U +#define CYBSP_RADAR_RESET_NUM CYBSP_RXRES_L_NUM +#define CYBSP_RXRES_L_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_RADAR_RESET_DRIVEMODE CYBSP_RXRES_L_DRIVEMODE +#define CYBSP_RXRES_L_INIT_DRIVESTATE 1 +#define CYBSP_RADAR_RESET_INIT_DRIVESTATE CYBSP_RXRES_L_INIT_DRIVESTATE +#ifndef ioss_0_port_20_pin_7_HSIOM + #define ioss_0_port_20_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_RXRES_L_HSIOM ioss_0_port_20_pin_7_HSIOM +#define CYBSP_RADAR_RESET_HSIOM CYBSP_RXRES_L_HSIOM +#define CYBSP_RXRES_L_IRQ ioss_interrupts_gpio_20_IRQn +#define CYBSP_RADAR_RESET_IRQ CYBSP_RXRES_L_IRQ +#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U +#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT21 +#define CYBSP_WIFI_SDIO_CMD_PORT_NUM 21U +#define CYBSP_WIFI_SDIO_CMD_PIN 0U +#define CYBSP_WIFI_SDIO_CMD_NUM 0U +#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_21_pin_0_HSIOM + #define ioss_0_port_21_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_21_pin_0_HSIOM +#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_21_IRQn +#define CYBSP_I2S_TX_SD_ENABLED 1U +#define CYBSP_I2S_TX_SD_PORT GPIO_PRT21 +#define CYBSP_I2S_TX_SD_PORT_NUM 21U +#define CYBSP_I2S_TX_SD_PIN 1U +#define CYBSP_I2S_TX_SD_NUM 1U +#define CYBSP_I2S_TX_SD_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_I2S_TX_SD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_21_pin_1_HSIOM + #define ioss_0_port_21_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2S_TX_SD_HSIOM ioss_0_port_21_pin_1_HSIOM +#define CYBSP_I2S_TX_SD_IRQ ioss_interrupts_gpio_21_IRQn +#define CYBSP_I2S_TX_SCK_ENABLED 1U +#define CYBSP_I2S_TX_SCK_PORT GPIO_PRT21 +#define CYBSP_I2S_TX_SCK_PORT_NUM 21U +#define CYBSP_I2S_TX_SCK_PIN 2U +#define CYBSP_I2S_TX_SCK_NUM 2U +#define CYBSP_I2S_TX_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_I2S_TX_SCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_21_pin_2_HSIOM + #define ioss_0_port_21_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2S_TX_SCK_HSIOM ioss_0_port_21_pin_2_HSIOM +#define CYBSP_I2S_TX_SCK_IRQ ioss_interrupts_gpio_21_IRQn +#define CYBSP_I2S_TX_MCK_ENABLED 1U +#define CYBSP_I2S_TX_MCK_PORT GPIO_PRT21 +#define CYBSP_I2S_TX_MCK_PORT_NUM 21U +#define CYBSP_I2S_TX_MCK_PIN 3U +#define CYBSP_I2S_TX_MCK_NUM 3U +#define CYBSP_I2S_TX_MCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_I2S_TX_MCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_21_pin_3_HSIOM + #define ioss_0_port_21_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2S_TX_MCK_HSIOM ioss_0_port_21_pin_3_HSIOM +#define CYBSP_I2S_TX_MCK_IRQ ioss_interrupts_gpio_21_IRQn +#define CYBSP_RSPI_MISO_ENABLED 1U +#define CYBSP_SPI_MISO_ENABLED CYBSP_RSPI_MISO_ENABLED +#define CYBSP_RSPI_MISO_PORT GPIO_PRT21 +#define CYBSP_SPI_MISO_PORT CYBSP_RSPI_MISO_PORT +#define CYBSP_RSPI_MISO_PORT_NUM 21U +#define CYBSP_SPI_MISO_PORT_NUM CYBSP_RSPI_MISO_PORT_NUM +#define CYBSP_RSPI_MISO_PIN 4U +#define CYBSP_SPI_MISO_PIN CYBSP_RSPI_MISO_PIN +#define CYBSP_RSPI_MISO_NUM 4U +#define CYBSP_SPI_MISO_NUM CYBSP_RSPI_MISO_NUM +#define CYBSP_RSPI_MISO_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_SPI_MISO_DRIVEMODE CYBSP_RSPI_MISO_DRIVEMODE +#define CYBSP_RSPI_MISO_INIT_DRIVESTATE 1 +#define CYBSP_SPI_MISO_INIT_DRIVESTATE CYBSP_RSPI_MISO_INIT_DRIVESTATE +#ifndef ioss_0_port_21_pin_4_HSIOM + #define ioss_0_port_21_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_RSPI_MISO_HSIOM ioss_0_port_21_pin_4_HSIOM +#define CYBSP_SPI_MISO_HSIOM CYBSP_RSPI_MISO_HSIOM +#define CYBSP_RSPI_MISO_IRQ ioss_interrupts_gpio_21_IRQn +#define CYBSP_SPI_MISO_IRQ CYBSP_RSPI_MISO_IRQ +#define CYBSP_RSPI_MOSI_ENABLED 1U +#define CYBSP_SPI_MOSI_ENABLED CYBSP_RSPI_MOSI_ENABLED +#define CYBSP_RSPI_MOSI_PORT GPIO_PRT21 +#define CYBSP_SPI_MOSI_PORT CYBSP_RSPI_MOSI_PORT +#define CYBSP_RSPI_MOSI_PORT_NUM 21U +#define CYBSP_SPI_MOSI_PORT_NUM CYBSP_RSPI_MOSI_PORT_NUM +#define CYBSP_RSPI_MOSI_PIN 5U +#define CYBSP_SPI_MOSI_PIN CYBSP_RSPI_MOSI_PIN +#define CYBSP_RSPI_MOSI_NUM 5U +#define CYBSP_SPI_MOSI_NUM CYBSP_RSPI_MOSI_NUM +#define CYBSP_RSPI_MOSI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SPI_MOSI_DRIVEMODE CYBSP_RSPI_MOSI_DRIVEMODE +#define CYBSP_RSPI_MOSI_INIT_DRIVESTATE 1 +#define CYBSP_SPI_MOSI_INIT_DRIVESTATE CYBSP_RSPI_MOSI_INIT_DRIVESTATE +#ifndef ioss_0_port_21_pin_5_HSIOM + #define ioss_0_port_21_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_RSPI_MOSI_HSIOM ioss_0_port_21_pin_5_HSIOM +#define CYBSP_SPI_MOSI_HSIOM CYBSP_RSPI_MOSI_HSIOM +#define CYBSP_RSPI_MOSI_IRQ ioss_interrupts_gpio_21_IRQn +#define CYBSP_SPI_MOSI_IRQ CYBSP_RSPI_MOSI_IRQ +#define CYBSP_RSPI_CLK_ENABLED 1U +#define CYBSP_SPI_CLK_ENABLED CYBSP_RSPI_CLK_ENABLED +#define CYBSP_RSPI_CLK_PORT GPIO_PRT21 +#define CYBSP_SPI_CLK_PORT CYBSP_RSPI_CLK_PORT +#define CYBSP_RSPI_CLK_PORT_NUM 21U +#define CYBSP_SPI_CLK_PORT_NUM CYBSP_RSPI_CLK_PORT_NUM +#define CYBSP_RSPI_CLK_PIN 6U +#define CYBSP_SPI_CLK_PIN CYBSP_RSPI_CLK_PIN +#define CYBSP_RSPI_CLK_NUM 6U +#define CYBSP_SPI_CLK_NUM CYBSP_RSPI_CLK_NUM +#define CYBSP_RSPI_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SPI_CLK_DRIVEMODE CYBSP_RSPI_CLK_DRIVEMODE +#define CYBSP_RSPI_CLK_INIT_DRIVESTATE 1 +#define CYBSP_SPI_CLK_INIT_DRIVESTATE CYBSP_RSPI_CLK_INIT_DRIVESTATE +#ifndef ioss_0_port_21_pin_6_HSIOM + #define ioss_0_port_21_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_RSPI_CLK_HSIOM ioss_0_port_21_pin_6_HSIOM +#define CYBSP_SPI_CLK_HSIOM CYBSP_RSPI_CLK_HSIOM +#define CYBSP_RSPI_CLK_IRQ ioss_interrupts_gpio_21_IRQn +#define CYBSP_SPI_CLK_IRQ CYBSP_RSPI_CLK_IRQ +#define CYBSP_RSPI_CS_ENABLED 1U +#define CYBSP_SPI_CS_ENABLED CYBSP_RSPI_CS_ENABLED +#define CYBSP_RSPI_CS_PORT GPIO_PRT21 +#define CYBSP_SPI_CS_PORT CYBSP_RSPI_CS_PORT +#define CYBSP_RSPI_CS_PORT_NUM 21U +#define CYBSP_SPI_CS_PORT_NUM CYBSP_RSPI_CS_PORT_NUM +#define CYBSP_RSPI_CS_PIN 7U +#define CYBSP_SPI_CS_PIN CYBSP_RSPI_CS_PIN +#define CYBSP_RSPI_CS_NUM 7U +#define CYBSP_SPI_CS_NUM CYBSP_RSPI_CS_NUM +#define CYBSP_RSPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SPI_CS_DRIVEMODE CYBSP_RSPI_CS_DRIVEMODE +#define CYBSP_RSPI_CS_INIT_DRIVESTATE 1 +#define CYBSP_SPI_CS_INIT_DRIVESTATE CYBSP_RSPI_CS_INIT_DRIVESTATE +#ifndef ioss_0_port_21_pin_7_HSIOM + #define ioss_0_port_21_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_RSPI_CS_HSIOM ioss_0_port_21_pin_7_HSIOM +#define CYBSP_SPI_CS_HSIOM CYBSP_RSPI_CS_HSIOM +#define CYBSP_RSPI_CS_IRQ ioss_interrupts_gpio_21_IRQn +#define CYBSP_SPI_CS_IRQ CYBSP_RSPI_CS_IRQ + +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_CS_config; + +#define CYBSP_OSPI_RAM_SS_config CYBSP_OSPI_RAM_CS_config + +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_CS_config; + +#define CYBSP_QSPI_SS_config CYBSP_QSPI_CS_config + +extern const cy_stc_gpio_pin_config_t CYBSP_I3C_SCL_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I3C_SDA_config; +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D4_config; +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D5_config; +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D6_config; +extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D7_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SW1_config; + +#define CYBSP_USER_BTN1_config CYBSP_SW1_config +#define CYBSP_USER_BTN_config CYBSP_SW1_config + +extern const cy_stc_gpio_pin_config_t CYBSP_EXT_CLK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_1V8_config; + +#define CYBSP_I2C_SCL_config CYBSP_I2C_SCL_1V8_config + +extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_1V8_config; + +#define CYBSP_I2C_SDA_config CYBSP_I2C_SDA_1V8_config + +extern const cy_stc_gpio_pin_config_t CYBSP_PDM_CLK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_PDM_DATA_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config; +extern const cy_stc_gpio_pin_config_t CYBSP_USER_LED2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config; +extern const cy_stc_gpio_pin_config_t CYBSP_USER_LED1_config; + +#define CYBSP_USER_LED_config CYBSP_USER_LED1_config + +extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_PCLK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_FSYNC_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D4_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D5_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D6_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D7_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_3V3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_3V3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_VSYNC_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_HREF_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_XCLK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_RESET_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_PWDN_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; +extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config; +extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config; +extern const cy_stc_gpio_pin_config_t CYBSP_RADAR_INT_config; +extern const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_GREEN_config; + +#define CYBSP_USER_LED5_config CYBSP_LED_RGB_GREEN_config + +extern const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_BLUE_config; + +#define CYBSP_USER_LED4_config CYBSP_LED_RGB_BLUE_config + +extern const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_RED_config; + +#define CYBSP_USER_LED3_config CYBSP_LED_RGB_RED_config + +extern const cy_stc_gpio_pin_config_t CYBSP_RXRES_L_config; + +#define CYBSP_RADAR_RESET_config CYBSP_RXRES_L_config + +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_SD_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_SCK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_MCK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_RSPI_MISO_config; + +#define CYBSP_SPI_MISO_config CYBSP_RSPI_MISO_config + +extern const cy_stc_gpio_pin_config_t CYBSP_RSPI_MOSI_config; + +#define CYBSP_SPI_MOSI_config CYBSP_RSPI_MOSI_config + +extern const cy_stc_gpio_pin_config_t CYBSP_RSPI_CLK_config; + +#define CYBSP_SPI_CLK_config CYBSP_RSPI_CLK_config + +extern const cy_stc_gpio_pin_config_t CYBSP_RSPI_CS_config; + +#define CYBSP_SPI_CS_config CYBSP_RSPI_CS_config + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_PINS_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_ppc.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_ppc.h new file mode 100644 index 00000000000..9d84655e6b1 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_ppc.h @@ -0,0 +1,489 @@ +/* This file is automatically generated. */ +#ifndef CYCFG_PPC_H +#define CYCFG_PPC_H + +#define CYCFG_PPC_SECURED_PERI0_MAIN 0U +#define CYCFG_PPC_SECURED_PERI0_GR0_GROUP 1U +#define CYCFG_PPC_SECURED_PERI0_GR1_GROUP 0U +#define CYCFG_PPC_SECURED_PERI0_GR2_GROUP 0U +#define CYCFG_PPC_SECURED_PERI0_GR3_GROUP 0U +#define CYCFG_PPC_SECURED_PERI0_GR4_GROUP 0U +#define CYCFG_PPC_SECURED_PERI0_GR5_GROUP 0U +#define CYCFG_PPC_SECURED_PERI0_GR0_BOOT 1U +#define CYCFG_PPC_SECURED_PERI0_GR1_BOOT 1U +#define CYCFG_PPC_SECURED_PERI0_GR2_BOOT 1U +#define CYCFG_PPC_SECURED_PERI0_GR3_BOOT 1U +#define CYCFG_PPC_SECURED_PERI0_GR4_BOOT 1U +#define CYCFG_PPC_SECURED_PERI0_GR5_BOOT 1U +#define CYCFG_PPC_SECURED_PERI0_TR 0U +#define CYCFG_PPC_SECURED_PPC0_PPC_PPC_SECURE 1U +#define CYCFG_PPC_SECURED_PPC0_PPC_PPC_NONSECURE 1U +#define CYCFG_PPC_SECURED_PERI_PCLK0_MAIN 0U +#define CYCFG_PPC_SECURED_RRAMC0_RRAM_EXTRA_AREA_RRAMC_PROTECTED 1U +#define CYCFG_PPC_SECURED_RRAMC0_RRAM_EXTRA_AREA_RRAMC_GENERAL 0U +#define CYCFG_PPC_SECURED_RRAMC0_RRAM_EXTRA_AREA_RRAMC_REPAIR 1U +#define CYCFG_PPC_SECURED_RRAMC0_RRAM_EXTRA_AREA_RRAMC_EXTRA 1U +#define CYCFG_PPC_SECURED_RRAMC0_RRAMC0_RRAMC_USER 0U +#define CYCFG_PPC_SECURED_RRAMC0_RRAMC0_RRAMC_ALLUSER 0U +#define CYCFG_PPC_SECURED_RRAMC0_RRAMC0_RRAMC_M0SEC 1U +#define CYCFG_PPC_SECURED_RRAMC0_MPC0_PPC_MPC_MAIN 1U +#define CYCFG_PPC_SECURED_RRAMC0_MPC1_PPC_MPC_MAIN 1U +#define CYCFG_PPC_SECURED_RRAMC0_MPC0_PPC_MPC_PC 1U +#define CYCFG_PPC_SECURED_RRAMC0_MPC1_PPC_MPC_PC 1U +#define CYCFG_PPC_SECURED_RRAMC0_MPC0_PPC_MPC_ROT 1U +#define CYCFG_PPC_SECURED_RRAMC0_MPC1_PPC_MPC_ROT 1U +#define CYCFG_PPC_SECURED_RRAMC0_RRAM_SFR_RRAMC_SFR_USER 0U +#define CYCFG_PPC_SECURED_RRAMC0_RRAM_SFR_RRAMC_SFR_FPGA 1U +#define CYCFG_PPC_SECURED_RRAMC0_RRAM_SFR_RRAMC_SFR_NONUSER 1U +#define CYCFG_PPC_SECURED_M33SYSCPUSS 0U +#define CYCFG_PPC_SECURED_PASS 0U +#define CYCFG_PPC_SECURED_RAMC0_CM33 0U +#define CYCFG_PPC_SECURED_RAMC1_CM33 0U +#define CYCFG_PPC_SECURED_RAMC0_BOOT 1U +#define CYCFG_PPC_SECURED_RAMC1_BOOT 1U +#define CYCFG_PPC_SECURED_RAMC0_RAM_PWR 0U +#define CYCFG_PPC_SECURED_RAMC1_RAM_PWR 0U +#define CYCFG_PPC_SECURED_RAMC0_MPC0_PPC_MPC_MAIN 0U +#define CYCFG_PPC_SECURED_RAMC1_MPC0_PPC_MPC_MAIN 0U +#define CYCFG_PPC_SECURED_RAMC0_MPC0_PPC_MPC_PC 0U +#define CYCFG_PPC_SECURED_RAMC1_MPC0_PPC_MPC_PC 0U +#define CYCFG_PPC_SECURED_RAMC0_MPC0_PPC_MPC_ROT 0U +#define CYCFG_PPC_SECURED_RAMC1_MPC0_PPC_MPC_ROT 0U +#define CYCFG_PPC_SECURED_MXCM33_CM33 0U +#define CYCFG_PPC_SECURED_MXCM33_CM33_S 0U +#define CYCFG_PPC_SECURED_MXCM33_CM33_NS 0U +#define CYCFG_PPC_SECURED_MXCM33_BOOT_PC0 1U +#define CYCFG_PPC_SECURED_MXCM33_BOOT_PC1 1U +#define CYCFG_PPC_SECURED_MXCM33_BOOT_PC2 0U +#define CYCFG_PPC_SECURED_MXCM33_BOOT_PC3 1U +#define CYCFG_PPC_SECURED_MXCM33_BOOT 1U +#define CYCFG_PPC_SECURED_MXCM33_CM33_INT 0U +#define CYCFG_PPC_SECURED_DW0_DW 0U +#define CYCFG_PPC_SECURED_DW1_DW 0U +#define CYCFG_PPC_SECURED_DW0_DW_CRC 0U +#define CYCFG_PPC_SECURED_DW1_DW_CRC 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT0_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT1_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT2_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT3_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT4_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT5_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT6_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT7_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT8_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT9_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT10_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT11_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT12_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT13_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT14_CH 0U +#define CYCFG_PPC_SECURED_DW0_CH_STRUCT15_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT0_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT1_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT2_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT3_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT4_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT5_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT6_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT7_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT8_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT9_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT10_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT11_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT12_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT13_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT14_CH 0U +#define CYCFG_PPC_SECURED_DW1_CH_STRUCT15_CH 0U +#define CYCFG_PPC_SECURED_CPUSS_ALL_PC 0U +#define CYCFG_PPC_SECURED_CPUSS_DDFT 0U +#define CYCFG_PPC_SECURED_CPUSS_CM33_S 0U +#define CYCFG_PPC_SECURED_CPUSS_CM33_NS 0U +#define CYCFG_PPC_SECURED_CPUSS_MSC_INT 0U +#define CYCFG_PPC_SECURED_CPUSS_AP 1U +#define CYCFG_PPC_SECURED_CPUSS_BOOT 0U +#define CYCFG_PPC_SECURED_MS0_MAIN 1U +#define CYCFG_PPC_SECURED_MS4_MAIN 1U +#define CYCFG_PPC_SECURED_MS5_MAIN 1U +#define CYCFG_PPC_SECURED_MS6_MAIN 1U +#define CYCFG_PPC_SECURED_MS7_MAIN 1U +#define CYCFG_PPC_SECURED_MS8_MAIN 1U +#define CYCFG_PPC_SECURED_MS9_MAIN 1U +#define CYCFG_PPC_SECURED_MS10_MAIN 1U +#define CYCFG_PPC_SECURED_MS11_MAIN 1U +#define CYCFG_PPC_SECURED_MS29_MAIN 1U +#define CYCFG_PPC_SECURED_MS31_MAIN 1U +#define CYCFG_PPC_SECURED_MS_PC0_PRIV 0U +#define CYCFG_PPC_SECURED_MS_PC6_PRIV 0U +#define CYCFG_PPC_SECURED_MS_PC9_PRIV 0U +#define CYCFG_PPC_SECURED_MS_PC11_PRIV 0U +#define CYCFG_PPC_SECURED_MS_PC31_PRIV 1U +#define CYCFG_PPC_SECURED_MS_PC0_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_PC6_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_PC9_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_PC11_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_PC31_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MSC_ACG 0U +#define CYCFG_PPC_SECURED_CPUSS_SL_CTL_GROUP 1U +#define CYCFG_PPC_SECURED_IPC0_STRUCT0_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT1_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT2_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT3_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT4_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT5_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT6_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT7_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT8_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT9_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT10_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT11_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT12_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT13_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT14_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_STRUCT15_IPC 0U +#define CYCFG_PPC_SECURED_IPC0_INTR_STRUCT0_INTR 0U +#define CYCFG_PPC_SECURED_IPC0_INTR_STRUCT1_INTR 0U +#define CYCFG_PPC_SECURED_IPC0_INTR_STRUCT2_INTR 0U +#define CYCFG_PPC_SECURED_IPC0_INTR_STRUCT3_INTR 0U +#define CYCFG_PPC_SECURED_IPC0_INTR_STRUCT4_INTR 0U +#define CYCFG_PPC_SECURED_IPC0_INTR_STRUCT5_INTR 0U +#define CYCFG_PPC_SECURED_IPC0_INTR_STRUCT6_INTR 0U +#define CYCFG_PPC_SECURED_IPC0_INTR_STRUCT7_INTR 0U +#define CYCFG_PPC_SECURED_FAULT_STRUCT0_MAIN 0U +#define CYCFG_PPC_SECURED_FAULT_STRUCT1_MAIN 0U +#define CYCFG_PPC_SECURED_SRSS_GENERAL 0U +#define CYCFG_PPC_SECURED_SRSS_GENERAL2 0U +#define CYCFG_PPC_SECURED_SRSS_HIB_DATA 0U +#define CYCFG_PPC_SECURED_SRSS_SECURE2 1U +#define CYCFG_PPC_SECURED_SRSS_MAIN 0U +#define CYCFG_PPC_SECURED_SRSS_SECURE 1U +#define CYCFG_PPC_SECURED_RAM_TRIM_SRSS_SRAM 0U +#define CYCFG_PPC_SECURED_SRSS_WDT 0U +#define CYCFG_PPC_SECURED_SRSS_MCWDTA 0U +#define CYCFG_PPC_SECURED_PWRMODE_PWRMODE 0U +#define CYCFG_PPC_SECURED_RTC_BACKUP 0U +#define CYCFG_PPC_SECURED_RTC_B_BREG0 0U +#define CYCFG_PPC_SECURED_RTC_B_BREG1 0U +#define CYCFG_PPC_SECURED_RTC_B_BREG2 0U +#define CYCFG_PPC_SECURED_DEBUG600_DEBUG600 0U +#define CYCFG_PPC_SECURED_M0SECCPUSS_STATUS_MAIN 1U +#define CYCFG_PPC_SECURED_M0SECCPUSS_STATUS_PC1 1U +#define CYCFG_PPC_SECURED_CRYPTO_MAIN 0U +#define CYCFG_PPC_SECURED_CRYPTO_CRYPTO 0U +#define CYCFG_PPC_SECURED_CRYPTO_BOOT 0U +#define CYCFG_PPC_SECURED_CRYPTO_KEY0 0U +#define CYCFG_PPC_SECURED_CRYPTO_KEY1 0U +#define CYCFG_PPC_SECURED_CRYPTO_BUF 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT0_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT1_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT2_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT3_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT4_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT5_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT6_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT7_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT8_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT9_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT10_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT11_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT12_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT13_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT14_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT15_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT16_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT17_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT18_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT19_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT20_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_PRT21_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT0_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT1_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT2_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT3_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT4_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT5_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT6_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT7_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT8_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT9_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT10_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT11_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT12_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT13_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT14_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT15_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT16_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT17_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT18_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT19_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT20_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_SECURE_PRT21_SECURE_PRT 0U +#define CYCFG_PPC_SECURED_HSIOM_AMUX 0U +#define CYCFG_PPC_SECURED_HSIOM_MON 0U +#define CYCFG_PPC_SECURED_GPIO_PRT0_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT1_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT2_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT3_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT4_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT5_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT6_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT7_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT8_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT9_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT10_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT11_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT12_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT13_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT14_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT15_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT16_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT17_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT18_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT19_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT20_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT21_PRT 0U +#define CYCFG_PPC_SECURED_GPIO_PRT0_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT1_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT2_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT3_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT4_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT5_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT6_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT7_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT8_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT9_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT10_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT11_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT12_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT13_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT14_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT15_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT16_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT17_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT18_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT19_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT20_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_PRT21_CFG 0U +#define CYCFG_PPC_SECURED_GPIO_SEC_GPIO 0U +#define CYCFG_PPC_SECURED_GPIO_GPIO 0U +#define CYCFG_PPC_SECURED_GPIO_TEST 0U +#define CYCFG_PPC_SECURED_SMARTIO_PRT11_PRT 0U +#define CYCFG_PPC_SECURED_SMARTIO_PRT17_PRT 0U +#define CYCFG_PPC_SECURED_CANFD0_CH0_CH 0U +#define CYCFG_PPC_SECURED_CANFD0_CH1_CH 0U +#define CYCFG_PPC_SECURED_CANFD0_MAIN 0U +#define CYCFG_PPC_SECURED_CANFD0_BUF 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP0_CNT0_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP0_CNT1_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP0_CNT2_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP0_CNT3_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP0_CNT4_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP0_CNT5_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP0_CNT6_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP0_CNT7_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT0_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT1_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT2_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT3_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT4_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT5_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT6_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT7_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT8_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT9_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT10_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT11_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT12_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT13_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT14_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT15_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT16_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT17_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT18_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT19_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT20_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT21_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT22_CNT 0U +#define CYCFG_PPC_SECURED_TCPWM0_GRP1_CNT23_CNT 0U +#define CYCFG_PPC_SECURED_LPCOMP 0U +#define CYCFG_PPC_SECURED_SCB0 0U +#define CYCFG_PPC_SECURED_SCB2 0U +#define CYCFG_PPC_SECURED_SCB3 0U +#define CYCFG_PPC_SECURED_SCB4 0U +#define CYCFG_PPC_SECURED_SCB5 0U +#define CYCFG_PPC_SECURED_SCB6 0U +#define CYCFG_PPC_SECURED_SCB7 0U +#define CYCFG_PPC_SECURED_SCB8 0U +#define CYCFG_PPC_SECURED_SCB9 0U +#define CYCFG_PPC_SECURED_SCB10 0U +#define CYCFG_PPC_SECURED_SCB11 0U +#define CYCFG_PPC_SECURED_SCB1 0U +#define CYCFG_PPC_SECURED_I3C 0U +#define CYCFG_PPC_SECURED_DFT 0U +#define CYCFG_PPC_SECURED_ETH0 0U +#define CYCFG_PPC_SECURED_MXNNLITE_2_0 0U +#define CYCFG_PPC_SECURED_PERI1_MAIN 0U +#define CYCFG_PPC_SECURED_PERI1_GR0_GROUP 0U +#define CYCFG_PPC_SECURED_PERI1_GR1_GROUP 0U +#define CYCFG_PPC_SECURED_PERI1_GR2_GROUP 0U +#define CYCFG_PPC_SECURED_PERI1_GR3_GROUP 0U +#define CYCFG_PPC_SECURED_PERI1_GR4_GROUP 0U +#define CYCFG_PPC_SECURED_PERI1_GR0_BOOT 0U +#define CYCFG_PPC_SECURED_PERI1_GR1_BOOT 0U +#define CYCFG_PPC_SECURED_PERI1_GR2_BOOT 0U +#define CYCFG_PPC_SECURED_PERI1_GR3_BOOT 0U +#define CYCFG_PPC_SECURED_PERI1_GR4_BOOT 0U +#define CYCFG_PPC_SECURED_PERI1_TR 0U +#define CYCFG_PPC_SECURED_PPC1_PPC_PPC_SECURE 1U +#define CYCFG_PPC_SECURED_PPC1_PPC_PPC_NONSECURE 1U +#define CYCFG_PPC_SECURED_PERI_PCLK1_MAIN 0U +#define CYCFG_PPC_SECURED_M55APPCPUSS 0U +#define CYCFG_PPC_SECURED_MXCM55_CM55 0U +#define CYCFG_PPC_SECURED_MXCM55_CM55_S 0U +#define CYCFG_PPC_SECURED_MXCM55_CM55_NS 0U +#define CYCFG_PPC_SECURED_MXCM55_BOOT 0U +#define CYCFG_PPC_SECURED_MXCM55_CM55_INT 0U +#define CYCFG_PPC_SECURED_SAXI_DMAC_TOP 0U +#define CYCFG_PPC_SECURED_SAXI_DMAC_CH0_CH 0U +#define CYCFG_PPC_SECURED_SAXI_DMAC_CH1_CH 0U +#define CYCFG_PPC_SECURED_SAXI_DMAC_CH2_CH 0U +#define CYCFG_PPC_SECURED_SAXI_DMAC_CH3_CH 0U +#define CYCFG_PPC_SECURED_APPCPUSS_ALL_PC 0U +#define CYCFG_PPC_SECURED_APPCPUSS_CM33_NS 0U +#define CYCFG_PPC_SECURED_APPCPUSS_MSC_INT 0U +#define CYCFG_PPC_SECURED_APPCPUSS_AHB2AXI_INT 0U +#define CYCFG_PPC_SECURED_APPCPUSS_AP 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS13_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS14_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS15_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS19_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS23_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS25_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS26_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS27_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS28_MAIN 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC13_PRIV 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC14_PRIV 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC15_PRIV 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC19_PRIV 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC25_PRIV 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC26_PRIV 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC27_PRIV 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC28_PRIV 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC13_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC14_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC15_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC19_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC25_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC26_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC27_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_CTL_MS_PC28_PRIV_MIR 0U +#define CYCFG_PPC_SECURED_MS_CTL_MSC_ACG 0U +#define CYCFG_PPC_SECURED_APPCPUSS_SL_CTL_GROUP 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT0_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT1_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT2_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT3_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT4_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT5_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT6_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT7_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT8_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT9_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT10_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT11_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT12_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT13_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT14_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_STRUCT15_IPC 0U +#define CYCFG_PPC_SECURED_IPC1_INTR_STRUCT0_INTR 0U +#define CYCFG_PPC_SECURED_IPC1_INTR_STRUCT1_INTR 0U +#define CYCFG_PPC_SECURED_IPC1_INTR_STRUCT2_INTR 0U +#define CYCFG_PPC_SECURED_IPC1_INTR_STRUCT3_INTR 0U +#define CYCFG_PPC_SECURED_IPC1_INTR_STRUCT4_INTR 0U +#define CYCFG_PPC_SECURED_IPC1_INTR_STRUCT5_INTR 0U +#define CYCFG_PPC_SECURED_IPC1_INTR_STRUCT6_INTR 0U +#define CYCFG_PPC_SECURED_IPC1_INTR_STRUCT7_INTR 0U +#define CYCFG_PPC_SECURED_PDM0_MAIN 0U +#define CYCFG_PPC_SECURED_PDM0_CH0_RX 0U +#define CYCFG_PPC_SECURED_PDM0_CH1_RX 0U +#define CYCFG_PPC_SECURED_PDM0_CH2_RX 0U +#define CYCFG_PPC_SECURED_PDM0_CH3_RX 0U +#define CYCFG_PPC_SECURED_PDM0_CH4_RX 0U +#define CYCFG_PPC_SECURED_PDM0_CH5_RX 0U +#define CYCFG_PPC_SECURED_TDM0_TDM_STRUCT0_TDM_TX_STRUCT_TX 0U +#define CYCFG_PPC_SECURED_TDM0_TDM_STRUCT1_TDM_TX_STRUCT_TX 0U +#define CYCFG_PPC_SECURED_TDM0_TDM_STRUCT0_TDM_RX_STRUCT_RX 0U +#define CYCFG_PPC_SECURED_TDM0_TDM_STRUCT1_TDM_RX_STRUCT_RX 0U +#define CYCFG_PPC_SECURED_SMIF0_CACHE_BLOCK_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF1_CACHE_BLOCK_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF0_CACHE_BLOCK_MMIO_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF1_CACHE_BLOCK_MMIO_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF1_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_PC 0U +#define CYCFG_PPC_SECURED_SMIF1_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_PC 0U +#define CYCFG_PPC_SECURED_SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_ROT 0U +#define CYCFG_PPC_SECURED_SMIF1_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_ROT 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_CRYPTO 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_CRYPTO 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_MAIN2 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_MAIN2 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_DEVICE 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_DEVICE 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_AXI_MPC0_PPC_MPC_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_AXI_MPC0_PPC_MPC_MAIN 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_AXI_MPC0_PPC_MPC_PC 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_AXI_MPC0_PPC_MPC_PC 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_AXI_MPC0_PPC_MPC_ROT 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_AXI_MPC0_PPC_MPC_ROT 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_HSIOM_SMIF_PRT0_PRT 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_HSIOM_SMIF_PRT1_PRT 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_HSIOM_SMIF_PRT2_PRT 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_HSIOM_SMIF_PRT0_PRT 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_HSIOM_SMIF_PRT1_PRT 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_HSIOM_SMIF_PRT2_PRT 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_HSIOM_MON 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_HSIOM_MON 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_GPIO_SMIF_PRT0_PRT 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_GPIO_SMIF_PRT1_PRT 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_GPIO_SMIF_PRT2_PRT 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_GPIO_SMIF_PRT0_PRT 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_GPIO_SMIF_PRT1_PRT 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_GPIO_SMIF_PRT2_PRT 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_GPIO_SMIF_PRT0_CFG 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_GPIO_SMIF_PRT1_CFG 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_GPIO_SMIF_PRT2_CFG 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_GPIO_SMIF_PRT0_CFG 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_GPIO_SMIF_PRT1_CFG 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_GPIO_SMIF_PRT2_CFG 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_GPIO_GPIO 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_GPIO_GPIO 0U +#define CYCFG_PPC_SECURED_SMIF0_CORE_SMIF_GPIO_TEST 0U +#define CYCFG_PPC_SECURED_SMIF1_CORE_SMIF_GPIO_TEST 0U +#define CYCFG_PPC_SECURED_U550_U55 0U +#define CYCFG_PPC_SECURED_U550_ROT 0U +#define CYCFG_PPC_SECURED_U550_ACG 0U +#define CYCFG_PPC_SECURED_U550_MXU55_PPU_PPU 0U +#define CYCFG_PPC_SECURED_U550_PD_PD 0U +#define CYCFG_PPC_SECURED_SOCMEM_MAIN 0U +#define CYCFG_PPC_SECURED_SOCMEM_BOOT 0U +#define CYCFG_PPC_SECURED_SOCMEM_SOCMEM_PWR 0U +#define CYCFG_PPC_SECURED_SOCMEM_SRAM_MPC0_PPC_MPC_MAIN 0U +#define CYCFG_PPC_SECURED_SOCMEM_SRAM_MPC0_PPC_MPC_PC 0U +#define CYCFG_PPC_SECURED_SOCMEM_SRAM_MPC0_PPC_MPC_ROT 0U +#define CYCFG_PPC_SECURED_SOCMEM_MAIN_PORT 0U +#define CYCFG_PPC_SECURED_SOCMEM_PPU_SOCMEM_PPU 0U +#define CYCFG_PPC_SECURED_SOCMEM_SOCMEM_PD_PD 0U +#define CYCFG_PPC_SECURED_GFXSS_GPU_GFXSS 0U +#define CYCFG_PPC_SECURED_GFXSS_DC_GFXSS 0U +#define CYCFG_PPC_SECURED_GFXSS_MIPIDSI_GFXSS 0U +#define CYCFG_PPC_SECURED_SDHC0 0U +#define CYCFG_PPC_SECURED_SDHC1 0U +#define CYCFG_PPC_SECURED_USBHS_DWC_otg_intreg_CONTROLLER 0U +#define CYCFG_PPC_SECURED_USBHS_SS_SUBSYSTEM 0U +#define CYCFG_PPC_SECURED_ITCM 0U +#define CYCFG_PPC_SECURED_DTCM 0U + +#endif /* #ifndef CYCFG_PPC_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_protection.c b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_protection.c new file mode 100644 index 00000000000..2c93a61dd18 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_protection.c @@ -0,0 +1,46 @@ +/******************************************************************************* + * File Name: cycfg_protection.c + * + * Description: + * System configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_protection.h" +#include "cycfg_system.h" + +void init_cycfg_protection(void) { + #if (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && !defined(CYBSP_SKIP_SAU_INIT) + Cy_SAU_Init(SAU, SAU_config, sizeof(SAU_config) / sizeof(SAU_config[0])); + #endif /* (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && !defined(CYBSP_SKIP_SAU_INIT) */ + #if (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYBSP_SKIP_MPC_INIT) + init_cycfg_mpc(); + #endif /* (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYBSP_SKIP_MPC_INIT) */ + #if (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYBSP_SKIP_PPC_INIT) + init_cycfg_ppc0(); + init_cycfg_ppc1(); + #endif /* (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYBSP_SKIP_PPC_INIT) */ + #if (CY_SYSTEM_CPU_M55) && !defined(CYBSP_SKIP_MPU_INIT) + Cy_MPU_Init(cycfg_mpu_cm55_ns_0_config, sizeof(cycfg_mpu_cm55_ns_0_config) / sizeof(cycfg_mpu_cm55_ns_0_config[0])); + #endif /* (CY_SYSTEM_CPU_M55) && !defined(CYBSP_SKIP_MPU_INIT) */ +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_protection.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_protection.h new file mode 100644 index 00000000000..2f2e1cf5a1c --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_protection.h @@ -0,0 +1,46 @@ +/******************************************************************************* + * File Name: cycfg_protection.h + * + * Description: + * System configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_PROTECTION_H) +#define CYCFG_PROTECTION_H + +#include "cycfg_notices.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define vres_0_protection_0_ENABLED 1U + +void init_cycfg_protection(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_PROTECTION_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.c b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.c new file mode 100644 index 00000000000..86f9d2dfff3 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.c @@ -0,0 +1,550 @@ +/******************************************************************************* + * File Name: cycfg_qspi_memslot.c + * + * Description: + * Provides definitions of the SMIF-driver memory configuration. + * This file was automatically generated and should not be modified. + * QSPI Configurator 4.60.0.2742 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_qspi_memslot.h" + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_readCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xECU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_QUAD, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0x01U, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 8U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_PRESENT_1BYTE, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_writeEnCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x06U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_writeDisCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x04U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_eraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xDCU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_chipEraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x60U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_programCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x12U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_readStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x35U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_readStsRegWipCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x05U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_writeStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x01U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50) +static cy_stc_smif_hybrid_region_info_t S25HS512T_SMIF0_SlaveSlot_1_region0 = +{ + /* The region start address. */ + .regionAddress = 0x0U, + /* The number of sectors in this region. */ + .sectorsCount = 32U, + /* The erase command to use for erasing sectors in this region. */ + .eraseCmd = 0x21U, + /* The sector size in bytes. */ + .eraseSize = 0x1000U, + /* The erase time for these sectors in ms. */ + .eraseTime = 335U, +}; + +static cy_stc_smif_hybrid_region_info_t S25HS512T_SMIF0_SlaveSlot_1_region1 = +{ + /* The region start address. */ + .regionAddress = 0x20000U, + /* The number of sectors in this region. */ + .sectorsCount = 1U, + /* The erase command to use for erasing sectors in this region. */ + .eraseCmd = 0xDCU, + /* The sector size in bytes. */ + .eraseSize = 0x20000U, + /* The erase time for these sectors in ms. */ + .eraseTime = 5869U, +}; + +static cy_stc_smif_hybrid_region_info_t S25HS512T_SMIF0_SlaveSlot_1_region2 = +{ + /* The region start address. */ + .regionAddress = 0x40000U, + /* The number of sectors in this region. */ + .sectorsCount = 255U, + /* The erase command to use for erasing sectors in this region. */ + .eraseCmd = 0xDCU, + /* The sector size in bytes. */ + .eraseSize = 0x40000U, + /* The erase time for these sectors in ms. */ + .eraseTime = 5869U, +}; + +static cy_stc_smif_hybrid_region_info_t *S25HS512T_SMIF0_SlaveSlot_1_regionInfo[3] = { + &S25HS512T_SMIF0_SlaveSlot_1_region0, + &S25HS512T_SMIF0_SlaveSlot_1_region1, + &S25HS512T_SMIF0_SlaveSlot_1_region2 +}; + +#endif + +cy_stc_smif_mem_device_cfg_t deviceCfg_S25HS512T_SMIF0_SlaveSlot_1 = +{ + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x04U, + /* The size of the memory. */ + .memSize = 0x04000000U, + /* Specifies the Read command. */ + .readCmd = &S25HS512T_SMIF0_SlaveSlot_1_readCmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = &S25HS512T_SMIF0_SlaveSlot_1_writeEnCmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = &S25HS512T_SMIF0_SlaveSlot_1_writeDisCmd, + /* Specifies the Erase command. */ + .eraseCmd = &S25HS512T_SMIF0_SlaveSlot_1_eraseCmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x0040000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = &S25HS512T_SMIF0_SlaveSlot_1_chipEraseCmd, + /* Specifies the Program command. */ + .programCmd = &S25HS512T_SMIF0_SlaveSlot_1_programCmd, + /* Specifies the page size for programming. */ + .programSize = 0x0000100U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = &S25HS512T_SMIF0_SlaveSlot_1_readStsRegQeCmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = &S25HS512T_SMIF0_SlaveSlot_1_readStsRegWipCmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = &S25HS512T_SMIF0_SlaveSlot_1_writeStsRegQeCmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x01U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x02U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 5869U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 696000U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 2175U, + #if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50) + /* Points to NULL or to structure with info about sectors for hybrid memory. */ + .hybridRegionCount = 3U, + .hybridRegionInfo = S25HS512T_SMIF0_SlaveSlot_1_regionInfo, + #else + #error Hybrid erase sectors require SMIF driver 1.50 or greater. + #endif + /* Specifies the command to read variable latency cycles configuration register */ + .readLatencyCmd = 0, + /* Specifies the command to write variable latency cycles configuration register */ + .writeLatencyCmd = 0, + /* Specifies the address for variable latency cycle address */ + .latencyCyclesRegAddr = 0x00U, + /* Specifies variable latency cycles Mask */ + .latencyCyclesMask = 0x00U, + #if (CY_IP_MXSMIF_VERSION >= 2) + /* Specifies data for memory with hybrid sectors */ + .octalDDREnableSeq = 0, + /* Specifies the command to read the OE-containing status register. */ + .readStsRegOeCmd = 0, + /* Specifies the command to write the OE-containing status register. */ + .writeStsRegOeCmd = 0, + /* QE mask for the status registers */ + .stsRegOctalEnableMask = 0x00U, + /* Octal enable register address */ + .octalEnableRegAddr = 0x00U, + /* Frequency of operation used in Octal mode */ + .freq_of_operation = CY_SMIF_100MHZ_OPERATION, + #endif +}; + +cy_stc_smif_mem_config_t S25HS512T_SMIF0_SlaveSlot_1 = +{ + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_1, + /* Flags. */ + #if (CY_IP_MXSMIF_VERSION >= 2) + .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_MERGE_ENABLE, + #else + .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_MERGE_ENABLE, + #endif /* CY_IP_MXSMIF_VERSION */ + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave is mapped to in the PSoC memory map. + Valid when the memory-mapped mode is enabled. */ + .baseAddress = 0x60000000U, + /* The size allocated in the PSoC memory map, for the memory slave device. + The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ + .memMappedSize = 0x4000000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + Valid when the memory mapped mode is enabled. */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = &deviceCfg_S25HS512T_SMIF0_SlaveSlot_1, + #if (CY_IP_MXSMIF_VERSION >= 2) + /** Continous transfer merge timeout. + * After this period the memory device is deselected. A later transfer, even from a + * continuous address, starts with the overhead phases (command, address, mode, dummy cycles). + * This configuration parameter is available for CAT1B devices. */ + .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_256_CYCLES, + #else + #error Features used by this file require CY_IP_MXSMIF_VERSION >= 2. + #endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_config_t *smif0MemConfigs[CY_SMIF_DEVICE_NUM0] = { + &S25HS512T_SMIF0_SlaveSlot_1, +}; + +cy_stc_smif_block_config_t smif0BlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM0, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t **)smif0MemConfigs, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR, +}; +cy_stc_smif_block_config_t smif1BlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM1, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = 0, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR, +}; diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.h new file mode 100644 index 00000000000..83cc09046d7 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.h @@ -0,0 +1,76 @@ +/******************************************************************************* + * File Name: cycfg_qspi_memslot.h + * + * Description: + * Provides declarations of the SMIF-driver memory configuration. + * This file was automatically generated and should not be modified. + * QSPI Configurator 4.60.0.2742 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#ifndef CYCFG_QSPI_MEMSLOT_H +#define CYCFG_QSPI_MEMSLOT_H +#include "cy_smif_memslot.h" + +#define CY_SMIF_CFG_TOOL_VERSION (460) + +/* Supported QSPI Driver version */ +#define CY_SMIF_DRV_VERSION_REQUIRED (100) + +#if !defined(CY_SMIF_DRV_VERSION) + #define CY_SMIF_DRV_VERSION (100) +#endif + +/* Check the used Driver version */ +#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION) + #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project. +#endif + +typedef cy_stc_smif_mem_config_t cy_serial_flash_mem_config_t; +typedef cy_stc_smif_block_config_t cy_serial_flash_block_config_t; + +#define CY_SMIF_DEVICE_NUM0 1 + +#define CY_SMIF_DEVICE_NUM1 0 + +#define smifBlockConfig smif0BlockConfig +#define smifMemConfigs smif0MemConfigs + +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_readCmd; +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_writeEnCmd; +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_writeDisCmd; +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_eraseCmd; +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_chipEraseCmd; +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_programCmd; +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_readStsRegQeCmd; +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_readStsRegWipCmd; +extern cy_stc_smif_mem_cmd_t S25HS512T_SMIF0_SlaveSlot_1_writeStsRegQeCmd; + +extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25HS512T_SMIF0_SlaveSlot_1; + +extern cy_stc_smif_mem_config_t S25HS512T_SMIF0_SlaveSlot_1; + +extern cy_stc_smif_mem_config_t *smif0MemConfigs[CY_SMIF_DEVICE_NUM0]; + +extern cy_stc_smif_block_config_t smif0BlockConfig; + +extern cy_stc_smif_block_config_t smif1BlockConfig; + + +#endif /*CYCFG_QSPI_MEMSLOT_H*/ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.timestamp b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.timestamp new file mode 100644 index 00000000000..8d7d13aaa47 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_qspi_memslot.timestamp @@ -0,0 +1,25 @@ +/******************************************************************************* + * File Name: cycfg_qspi_memslot.timestamp + * + * Description: + * Sentinel file for determining if generated source is up to date. + * This file was automatically generated and should not be modified. + * QSPI Configurator 4.60.0.2742 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_routing.c b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_routing.c new file mode 100644 index 00000000000..676d9ca453f --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_routing.c @@ -0,0 +1,37 @@ +/******************************************************************************* + * File Name: cycfg_routing.c + * + * Description: + * Establishes all necessary connections between hardware elements. + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_routing.h" +#include "cy_trigmux.h" +#include "stdbool.h" +#include "cy_device_headers.h" + +void init_cycfg_routing(void) { + Cy_TrigMux_Connect(PERI_0_TRIG_IN_MUX_0_PERI0_HSIOM_TR_OUT1, PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN0, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(PERI_1_TRIG_IN_MUX_0_PDMA0_TR_OUT0, PERI_1_TRIG_OUT_MUX_0_AXIDMAC_TR_IN0, false, TRIGGER_TYPE_EDGE); +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_routing.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_routing.h new file mode 100644 index 00000000000..2bdea29957e --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_routing.h @@ -0,0 +1,85 @@ +/******************************************************************************* + * File Name: cycfg_routing.h + * + * Description: + * Establishes all necessary connections between hardware elements. + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#include "cycfg_notices.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define ioss_0_port_0_pin_1_HSIOM P0_1_SMIF1_SMIF0_SPIHB_SELECT2 +#define ioss_0_port_2_pin_0_HSIOM P2_0_SMIF0_SMIF0_SPIHB_SELECT1 +#define ioss_0_port_3_pin_0_HSIOM P3_0_I3C_I3C_SCL +#define ioss_0_port_3_pin_1_HSIOM P3_1_I3C_I3C_SDA +#define ioss_0_port_6_pin_5_HSIOM P6_5_SCB2_UART_RX +#define ioss_0_port_6_pin_7_HSIOM P6_7_SCB2_UART_TX +#define ioss_0_port_7_pin_4_HSIOM P7_4_SRSS_EXT_CLK +#define ioss_0_port_8_pin_0_HSIOM P8_0_SCB0_I2C_SCL +#define ioss_0_port_8_pin_1_HSIOM P8_1_SCB0_I2C_SDA +#define ioss_0_port_8_pin_5_HSIOM P8_5_PDM_PDM_CLK3 +#define ioss_0_port_8_pin_6_HSIOM P8_6_PDM_PDM_DATA3 +#define ioss_0_port_9_pin_0_HSIOM P9_0_TCPWM0_LINE7 +#define ioss_0_port_9_pin_2_HSIOM P9_2_TCPWM0_LINE_COMPL7 +#define ioss_0_port_10_pin_0_HSIOM P10_0_SCB4_UART_RX +#define ioss_0_port_10_pin_1_HSIOM P10_1_SCB4_UART_TX +#define ioss_0_port_10_pin_2_HSIOM P10_2_SCB4_UART_CTS +#define ioss_0_port_10_pin_3_HSIOM P10_3_SCB4_UART_RTS +#define ioss_0_port_11_pin_1_HSIOM P11_1_PERI0_TR_IO_INPUT1 +#define ioss_0_port_12_pin_0_HSIOM P12_0_SDHC0_CLK_CARD +#define ioss_0_port_12_pin_1_HSIOM P12_1_SDHC0_CARD_DAT_3TO00 +#define ioss_0_port_12_pin_2_HSIOM P12_2_SDHC0_CARD_DAT_3TO01 +#define ioss_0_port_12_pin_3_HSIOM P12_3_TDM_TDM_TX_FSYNC0 +#define ioss_0_port_12_pin_4_HSIOM P12_4_SDHC0_CARD_DAT_3TO02 +#define ioss_0_port_12_pin_5_HSIOM P12_5_SDHC0_CARD_DAT_3TO03 +#define ioss_0_port_17_pin_0_HSIOM P17_0_SCB5_I2C_SCL +#define ioss_0_port_17_pin_1_HSIOM P17_1_SCB5_I2C_SDA +#define ioss_0_port_17_pin_4_HSIOM P17_4_TCPWM0_LINE_COMPL4 +#define ioss_0_port_20_pin_5_HSIOM P20_5_TCPWM0_LINE_COMPL0 +#define ioss_0_port_21_pin_0_HSIOM P21_0_SDHC0_CARD_CMD +#define ioss_0_port_21_pin_1_HSIOM P21_1_TDM_TDM_TX_SD0 +#define ioss_0_port_21_pin_2_HSIOM P21_2_TDM_TDM_TX_SCK0 +#define ioss_0_port_21_pin_3_HSIOM P21_3_TDM_TDM_TX_MCK0 +#define ioss_0_port_21_pin_4_HSIOM P21_4_SCB3_SPI_MISO +#define ioss_0_port_21_pin_5_HSIOM P21_5_SCB3_SPI_MOSI +#define ioss_0_port_21_pin_6_HSIOM P21_6_SCB3_SPI_CLK +#define ioss_0_port_21_pin_7_HSIOM P21_7_SCB3_SPI_SELECT1 +#define CYBSP_AXIDMAC_DVP_CAM_CONTROLLER_tr_in_0_TRIGGER_OUT PERI_1_TRIG_OUT_MUX_0_AXIDMAC_TR_IN0 +#define CYBSP_DMA_DVP_CAM_CONTROLLER_tr_in_0_TRIGGER_OUT PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN0 +#define CYBSP_DMA_DVP_CAM_CONTROLLER_tr_out_0_TRIGGER_IN PERI_1_TRIG_IN_MUX_0_PDMA0_TR_OUT0 +#define CYBSP_DVP_CAM_PCLK_digital_in_0_TRIGGER_IN PERI_0_TRIG_IN_MUX_0_PERI0_HSIOM_TR_OUT1 + +void init_cycfg_routing(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_ROUTING_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_system.c b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_system.c new file mode 100644 index 00000000000..6c6ac5a5ba0 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_system.c @@ -0,0 +1,1169 @@ +/******************************************************************************* + * File Name: cycfg_system.c + * + * Description: + * System configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_system.h" +#include "stdbool.h" +#include "stdint.h" +#include "string.h" + +#if defined(CY_PDL_TZ_ENABLED) +#include "ifx_se_platform.h" +#endif /* defined(CY_PDL_TZ_ENABLED) */ + +#if (smif_0_mpc_0_REGION_COUNT > 0U) || (smif_1_mpc_0_REGION_COUNT > 0U) +#include "cy_smif.h" +#endif /* (smif_0_mpc_0_REGION_COUNT > 0U) || (smif_1_mpc_0_REGION_COUNT > 0U) */ + +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_INIT 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 +#define CY_CFG_PWR_REGULATOR_MODE_MIN 0 +#define CY_CFG_PWR_USING_ULP 0 +#define CY_CFG_PWR_USING_LP 0 +#define CY_CFG_PWR_USING_HP 1 + +#if (smif_0_mpc_0_REGION_COUNT > 0U) || (smif_1_mpc_0_REGION_COUNT > 0U) +#define SMIF_DESELECT_DELAY (7U) +#define TIMEOUT_1_MS (1000U) +#endif /* (smif_0_mpc_0_REGION_COUNT > 0U) || (smif_1_mpc_0_REGION_COUNT > 0U) */ + +#define CY_MPC_PC_LAST (8) + +#if defined(CY_PDL_TZ_ENABLED) +const cy_stc_mpc_rot_cfg_t M33S_mpc_cfg[] = +{ + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_RW, + }, +}; +const cy_stc_mpc_rot_cfg_t M33_mpc_cfg[] = +{ + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_5, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, +}; +const cy_stc_mpc_rot_cfg_t M55_mpc_cfg[] = +{ + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_6, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, +}; +const cy_stc_mpc_rot_cfg_t M33NSC_mpc_cfg[] = +{ + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_R, + }, + { + .pc = CY_MPC_PC_5, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_R, + }, + { + .pc = CY_MPC_PC_6, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_R, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_R, + }, +}; +const cy_stc_mpc_rot_cfg_t M33_M55_mpc_cfg[] = +{ + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_5, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_6, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, +}; +const cy_stc_mpc_regions_t M33S_mpc_regions[] = +{ + { + .base = (MPC_Type *)RRAMC0_MPC0, + .offset = 0x00011000, + .size = 0x0004A000, + }, + { + .base = (MPC_Type *)SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0, + .offset = 0x00100000, + .size = 0x00240000, + }, + { + .base = (MPC_Type *)SMIF0_CORE_AXI_MPC0, + .offset = 0x00100000, + .size = 0x00240000, + }, + { + .base = (MPC_Type *)RAMC0_MPC0, + .offset = 0x00001000, + .size = 0x00057000, + }, +}; +const cy_stc_mpc_regions_t M33_mpc_regions[] = +{ + { + .base = (MPC_Type *)SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0, + .offset = 0x00340000, + .size = 0x00240000, + }, + { + .base = (MPC_Type *)SMIF0_CORE_AXI_MPC0, + .offset = 0x00340000, + .size = 0x00240000, + }, + { + .base = (MPC_Type *)RAMC0_MPC0, + .offset = 0x00058000, + .size = 0x00028000, + }, + { + .base = (MPC_Type *)RAMC1_MPC0, + .offset = 0x00000000, + .size = 0x0003D000, + }, +}; +const cy_stc_mpc_regions_t M55_mpc_regions[] = +{ + { + .base = (MPC_Type *)SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0, + .offset = 0x00580000, + .size = 0x00300000, + }, + { + .base = (MPC_Type *)SMIF0_CORE_AXI_MPC0, + .offset = 0x00580000, + .size = 0x00300000, + }, + { + .base = (MPC_Type *)SOCMEM_SRAM_MPC0, + .offset = 0x00000000, + .size = 0x00040000, + }, +}; +const cy_stc_mpc_regions_t M33NSC_mpc_regions[] = {0}; +const cy_stc_mpc_regions_t M33_M55_mpc_regions[] = +{ + { + .base = (MPC_Type *)RRAMC0_MPC0, + .offset = 0x0005B000, + .size = 0x00008000, + }, + { + .base = (MPC_Type *)SOCMEM_SRAM_MPC0, + .offset = 0x00040000, + .size = 0x004C0000, + }, + { + .base = (MPC_Type *)RAMC1_MPC0, + .offset = 0x0003D000, + .size = 0x00043000, + }, +}; +const cy_stc_mpc_resp_cfg_t cy_response_mpcs[] = +{ + { + .base = (MPC_Type *)SOCMEM_SRAM_MPC0, + .response = CY_MPC_BUS_ERR, + }, + { + .base = (MPC_Type *)RAMC0_MPC0, + .response = CY_MPC_BUS_ERR, + }, + { + .base = (MPC_Type *)RAMC1_MPC0, + .response = CY_MPC_BUS_ERR, + }, + { + .base = (MPC_Type *)SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0, + .response = CY_MPC_BUS_ERR, + }, + { + .base = (MPC_Type *)SMIF0_CORE_AXI_MPC0, + .response = CY_MPC_BUS_ERR, + }, +}; +const size_t cy_response_mpcs_count = sizeof(cy_response_mpcs) / sizeof(cy_stc_mpc_resp_cfg_t); +const cy_stc_mpc_unified_t unified_mpc_domains[] = +{ + { + .regions = M33S_mpc_regions, + .region_count = sizeof(M33S_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = M33S_mpc_cfg, + .cfg_count = sizeof(M33S_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, + { + .regions = M33_mpc_regions, + .region_count = sizeof(M33_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = M33_mpc_cfg, + .cfg_count = sizeof(M33_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, + { + .regions = M55_mpc_regions, + .region_count = sizeof(M55_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = M55_mpc_cfg, + .cfg_count = sizeof(M55_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, + { + .regions = M33NSC_mpc_regions, + .region_count = sizeof(M33NSC_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = M33NSC_mpc_cfg, + .cfg_count = sizeof(M33NSC_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, + { + .regions = M33_M55_mpc_regions, + .region_count = sizeof(M33_M55_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = M33_M55_mpc_cfg, + .cfg_count = sizeof(M33_M55_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, +}; +const size_t unified_mpc_domains_count = sizeof(unified_mpc_domains) / sizeof(cy_stc_mpc_unified_t); +#endif /* defined (CY_PDL_TZ_ENABLED) */ + +#if defined(COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) +const mtb_srf_memory_protection_s_t mtb_srf_memory_protection_s[] = +{ + { + .ranges = mxrramc_0_mpc_0_srf_protection_range_s, + .size = 4U, + }, + { + .ranges = smif_0_mpc_0_srf_protection_range_s, + .size = 6U, + }, + { + .ranges = socmem_0_mpc_0_srf_protection_range_s, + .size = 2U, + }, + { + .ranges = mxsramc_0_mpc_0_srf_protection_range_s, + .size = 3U, + }, + { + .ranges = mxsramc_1_mpc_0_srf_protection_range_s, + .size = 2U, + }, +}; +const uint8_t mtb_srf_protection_range_s_count = sizeof(mtb_srf_memory_protection_s) / sizeof(mtb_srf_memory_protection_s_t); +#endif /* defined (COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) */ + +const cy_stc_ppc_attribute_t cycfg_unused_ppc_cfg = +{ + .pcMask = 0xFF, + .secAttribute = CY_PPC_NON_SECURE, + .privAttribute = CY_PPC_NONPRIV, +}; +const cy_en_prot_region_t cycfg_unused_ppc_0_regions[] = +{ + PROT_PERI0_MAIN, + PROT_PERI0_GR1_GROUP, + PROT_PERI0_GR2_GROUP, + PROT_PERI0_GR3_GROUP, + PROT_PERI0_GR4_GROUP, + PROT_PERI0_GR5_GROUP, + PROT_PERI0_TR, + PROT_PERI0_PERI_PCLK0_MAIN, + PROT_PERI0_RRAMC0_RRAM_EXTRA_AREA_RRAMC_GENERAL, + PROT_PERI0_RRAMC0_RRAMC0_RRAMC_USER, + PROT_PERI0_RRAMC0_RRAMC0_RRAMC_ALLUSER, + PROT_PERI0_RRAMC0_RRAM_SFR_RRAMC_SFR_USER, + PROT_PERI0_M33SYSCPUSS, + PROT_PERI0_PASS, + PROT_PERI0_RAMC0_CM33, + PROT_PERI0_RAMC1_CM33, + PROT_PERI0_RAMC0_RAM_PWR, + PROT_PERI0_RAMC1_RAM_PWR, + PROT_PERI0_RAMC0_MPC0_PPC_MPC_MAIN, + PROT_PERI0_RAMC1_MPC0_PPC_MPC_MAIN, + PROT_PERI0_RAMC0_MPC0_PPC_MPC_PC, + PROT_PERI0_RAMC1_MPC0_PPC_MPC_PC, + PROT_PERI0_RAMC0_MPC0_PPC_MPC_ROT, + PROT_PERI0_RAMC1_MPC0_PPC_MPC_ROT, + PROT_PERI0_MXCM33_CM33, + PROT_PERI0_MXCM33_CM33_S, + PROT_PERI0_MXCM33_CM33_NS, + PROT_PERI0_MXCM33_BOOT_PC2, + PROT_PERI0_MXCM33_CM33_INT, + PROT_PERI0_DW0_DW, + PROT_PERI0_DW1_DW, + PROT_PERI0_DW0_DW_CRC, + PROT_PERI0_DW1_DW_CRC, + PROT_PERI0_DW0_CH_STRUCT0_CH, + PROT_PERI0_DW0_CH_STRUCT1_CH, + PROT_PERI0_DW0_CH_STRUCT2_CH, + PROT_PERI0_DW0_CH_STRUCT3_CH, + PROT_PERI0_DW0_CH_STRUCT4_CH, + PROT_PERI0_DW0_CH_STRUCT5_CH, + PROT_PERI0_DW0_CH_STRUCT6_CH, + PROT_PERI0_DW0_CH_STRUCT7_CH, + PROT_PERI0_DW0_CH_STRUCT8_CH, + PROT_PERI0_DW0_CH_STRUCT9_CH, + PROT_PERI0_DW0_CH_STRUCT10_CH, + PROT_PERI0_DW0_CH_STRUCT11_CH, + PROT_PERI0_DW0_CH_STRUCT12_CH, + PROT_PERI0_DW0_CH_STRUCT13_CH, + PROT_PERI0_DW0_CH_STRUCT14_CH, + PROT_PERI0_DW0_CH_STRUCT15_CH, + PROT_PERI0_DW1_CH_STRUCT0_CH, + PROT_PERI0_DW1_CH_STRUCT1_CH, + PROT_PERI0_DW1_CH_STRUCT2_CH, + PROT_PERI0_DW1_CH_STRUCT3_CH, + PROT_PERI0_DW1_CH_STRUCT4_CH, + PROT_PERI0_DW1_CH_STRUCT5_CH, + PROT_PERI0_DW1_CH_STRUCT6_CH, + PROT_PERI0_DW1_CH_STRUCT7_CH, + PROT_PERI0_DW1_CH_STRUCT8_CH, + PROT_PERI0_DW1_CH_STRUCT9_CH, + PROT_PERI0_DW1_CH_STRUCT10_CH, + PROT_PERI0_DW1_CH_STRUCT11_CH, + PROT_PERI0_DW1_CH_STRUCT12_CH, + PROT_PERI0_DW1_CH_STRUCT13_CH, + PROT_PERI0_DW1_CH_STRUCT14_CH, + PROT_PERI0_DW1_CH_STRUCT15_CH, + PROT_PERI0_CPUSS_ALL_PC, + PROT_PERI0_CPUSS_DDFT, + PROT_PERI0_CPUSS_CM33_S, + PROT_PERI0_CPUSS_CM33_NS, + PROT_PERI0_CPUSS_MSC_INT, + PROT_PERI0_CPUSS_BOOT, + PROT_PERI0_MS_PC0_PRIV, + PROT_PERI0_MS_PC6_PRIV, + PROT_PERI0_MS_PC9_PRIV, + PROT_PERI0_MS_PC11_PRIV, + PROT_PERI0_MS_PC0_PRIV_MIR, + PROT_PERI0_MS_PC6_PRIV_MIR, + PROT_PERI0_MS_PC9_PRIV_MIR, + PROT_PERI0_MS_PC11_PRIV_MIR, + PROT_PERI0_MS_PC31_PRIV_MIR, + PROT_PERI0_MSC_ACG, + PROT_PERI0_IPC0_STRUCT0_IPC, + PROT_PERI0_IPC0_STRUCT1_IPC, + PROT_PERI0_IPC0_STRUCT2_IPC, + PROT_PERI0_IPC0_STRUCT3_IPC, + PROT_PERI0_IPC0_STRUCT4_IPC, + PROT_PERI0_IPC0_STRUCT5_IPC, + PROT_PERI0_IPC0_STRUCT6_IPC, + PROT_PERI0_IPC0_STRUCT7_IPC, + PROT_PERI0_IPC0_STRUCT8_IPC, + PROT_PERI0_IPC0_STRUCT9_IPC, + PROT_PERI0_IPC0_STRUCT10_IPC, + PROT_PERI0_IPC0_STRUCT11_IPC, + PROT_PERI0_IPC0_STRUCT12_IPC, + PROT_PERI0_IPC0_STRUCT13_IPC, + PROT_PERI0_IPC0_STRUCT14_IPC, + PROT_PERI0_IPC0_STRUCT15_IPC, + PROT_PERI0_IPC0_INTR_STRUCT0_INTR, + PROT_PERI0_IPC0_INTR_STRUCT1_INTR, + PROT_PERI0_IPC0_INTR_STRUCT2_INTR, + PROT_PERI0_IPC0_INTR_STRUCT3_INTR, + PROT_PERI0_IPC0_INTR_STRUCT4_INTR, + PROT_PERI0_IPC0_INTR_STRUCT5_INTR, + PROT_PERI0_IPC0_INTR_STRUCT6_INTR, + PROT_PERI0_IPC0_INTR_STRUCT7_INTR, + PROT_PERI0_FAULT_STRUCT0_MAIN, + PROT_PERI0_FAULT_STRUCT1_MAIN, + PROT_PERI0_SRSS_GENERAL, + PROT_PERI0_SRSS_GENERAL2, + PROT_PERI0_SRSS_HIB_DATA, + PROT_PERI0_SRSS_MAIN, + PROT_PERI0_RAM_TRIM_SRSS_SRAM, + PROT_PERI0_SRSS_WDT, + PROT_PERI0_SRSS_MCWDTA, + PROT_PERI0_PWRMODE_PWRMODE, + PROT_PERI0_RTC_BACKUP, + PROT_PERI0_RTC_B_BREG0, + PROT_PERI0_RTC_B_BREG1, + PROT_PERI0_RTC_B_BREG2, + PROT_PERI0_DEBUG600_DEBUG600, + PROT_PERI0_CRYPTO_MAIN, + PROT_PERI0_CRYPTO_CRYPTO, + PROT_PERI0_CRYPTO_BOOT, + PROT_PERI0_CRYPTO_KEY0, + PROT_PERI0_CRYPTO_KEY1, + PROT_PERI0_CRYPTO_BUF, + PROT_PERI0_HSIOM_PRT0_PRT, + PROT_PERI0_HSIOM_PRT1_PRT, + PROT_PERI0_HSIOM_PRT2_PRT, + PROT_PERI0_HSIOM_PRT3_PRT, + PROT_PERI0_HSIOM_PRT4_PRT, + PROT_PERI0_HSIOM_PRT5_PRT, + PROT_PERI0_HSIOM_PRT6_PRT, + PROT_PERI0_HSIOM_PRT7_PRT, + PROT_PERI0_HSIOM_PRT8_PRT, + PROT_PERI0_HSIOM_PRT9_PRT, + PROT_PERI0_HSIOM_PRT10_PRT, + PROT_PERI0_HSIOM_PRT11_PRT, + PROT_PERI0_HSIOM_PRT12_PRT, + PROT_PERI0_HSIOM_PRT13_PRT, + PROT_PERI0_HSIOM_PRT14_PRT, + PROT_PERI0_HSIOM_PRT15_PRT, + PROT_PERI0_HSIOM_PRT16_PRT, + PROT_PERI0_HSIOM_PRT17_PRT, + PROT_PERI0_HSIOM_PRT18_PRT, + PROT_PERI0_HSIOM_PRT19_PRT, + PROT_PERI0_HSIOM_PRT20_PRT, + PROT_PERI0_HSIOM_PRT21_PRT, + PROT_PERI0_HSIOM_SECURE_PRT0_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT1_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT2_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT3_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT4_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT5_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT6_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT7_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT8_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT9_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT10_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT11_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT12_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT13_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT14_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT15_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT16_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT17_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT18_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT19_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT20_SECURE_PRT, + PROT_PERI0_HSIOM_SECURE_PRT21_SECURE_PRT, + PROT_PERI0_HSIOM_AMUX, + PROT_PERI0_HSIOM_MON, + PROT_PERI0_GPIO_PRT0_PRT, + PROT_PERI0_GPIO_PRT1_PRT, + PROT_PERI0_GPIO_PRT2_PRT, + PROT_PERI0_GPIO_PRT3_PRT, + PROT_PERI0_GPIO_PRT4_PRT, + PROT_PERI0_GPIO_PRT5_PRT, + PROT_PERI0_GPIO_PRT6_PRT, + PROT_PERI0_GPIO_PRT7_PRT, + PROT_PERI0_GPIO_PRT8_PRT, + PROT_PERI0_GPIO_PRT9_PRT, + PROT_PERI0_GPIO_PRT10_PRT, + PROT_PERI0_GPIO_PRT11_PRT, + PROT_PERI0_GPIO_PRT12_PRT, + PROT_PERI0_GPIO_PRT13_PRT, + PROT_PERI0_GPIO_PRT14_PRT, + PROT_PERI0_GPIO_PRT15_PRT, + PROT_PERI0_GPIO_PRT16_PRT, + PROT_PERI0_GPIO_PRT17_PRT, + PROT_PERI0_GPIO_PRT18_PRT, + PROT_PERI0_GPIO_PRT19_PRT, + PROT_PERI0_GPIO_PRT20_PRT, + PROT_PERI0_GPIO_PRT21_PRT, + PROT_PERI0_GPIO_PRT0_CFG, + PROT_PERI0_GPIO_PRT1_CFG, + PROT_PERI0_GPIO_PRT2_CFG, + PROT_PERI0_GPIO_PRT3_CFG, + PROT_PERI0_GPIO_PRT4_CFG, + PROT_PERI0_GPIO_PRT5_CFG, + PROT_PERI0_GPIO_PRT6_CFG, + PROT_PERI0_GPIO_PRT7_CFG, + PROT_PERI0_GPIO_PRT8_CFG, + PROT_PERI0_GPIO_PRT9_CFG, + PROT_PERI0_GPIO_PRT10_CFG, + PROT_PERI0_GPIO_PRT11_CFG, + PROT_PERI0_GPIO_PRT12_CFG, + PROT_PERI0_GPIO_PRT13_CFG, + PROT_PERI0_GPIO_PRT14_CFG, + PROT_PERI0_GPIO_PRT15_CFG, + PROT_PERI0_GPIO_PRT16_CFG, + PROT_PERI0_GPIO_PRT17_CFG, + PROT_PERI0_GPIO_PRT18_CFG, + PROT_PERI0_GPIO_PRT19_CFG, + PROT_PERI0_GPIO_PRT20_CFG, + PROT_PERI0_GPIO_PRT21_CFG, + PROT_PERI0_GPIO_SEC_GPIO, + PROT_PERI0_GPIO_GPIO, + PROT_PERI0_GPIO_TEST, + PROT_PERI0_SMARTIO_PRT11_PRT, + PROT_PERI0_SMARTIO_PRT17_PRT, + PROT_PERI0_CANFD0_CH0_CH, + PROT_PERI0_CANFD0_CH1_CH, + PROT_PERI0_CANFD0_MAIN, + PROT_PERI0_CANFD0_BUF, + PROT_PERI0_TCPWM0_GRP0_CNT0_CNT, + PROT_PERI0_TCPWM0_GRP0_CNT1_CNT, + PROT_PERI0_TCPWM0_GRP0_CNT2_CNT, + PROT_PERI0_TCPWM0_GRP0_CNT3_CNT, + PROT_PERI0_TCPWM0_GRP0_CNT4_CNT, + PROT_PERI0_TCPWM0_GRP0_CNT5_CNT, + PROT_PERI0_TCPWM0_GRP0_CNT6_CNT, + PROT_PERI0_TCPWM0_GRP0_CNT7_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT0_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT1_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT2_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT3_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT4_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT5_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT6_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT7_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT8_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT9_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT10_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT11_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT12_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT13_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT14_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT15_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT16_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT17_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT18_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT19_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT20_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT21_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT22_CNT, + PROT_PERI0_TCPWM0_GRP1_CNT23_CNT, + PROT_PERI0_LPCOMP, + PROT_PERI0_SCB0, + PROT_PERI0_SCB2, + PROT_PERI0_SCB3, + PROT_PERI0_SCB4, + PROT_PERI0_SCB5, + PROT_PERI0_SCB6, + PROT_PERI0_SCB7, + PROT_PERI0_SCB8, + PROT_PERI0_SCB9, + PROT_PERI0_SCB10, + PROT_PERI0_SCB11, + PROT_PERI0_SCB1, + PROT_PERI0_I3C, + PROT_PERI0_DFT, + PROT_PERI0_ETH0, + PROT_PERI0_MXNNLITE_2_0, +}; +const cy_en_prot_region_t cycfg_unused_ppc_1_regions[] = +{ + PROT_PERI1_MAIN, + PROT_PERI1_GR0_GROUP, + PROT_PERI1_GR1_GROUP, + PROT_PERI1_GR2_GROUP, + PROT_PERI1_GR3_GROUP, + PROT_PERI1_GR4_GROUP, + PROT_PERI1_GR0_BOOT, + PROT_PERI1_GR1_BOOT, + PROT_PERI1_GR2_BOOT, + PROT_PERI1_GR3_BOOT, + PROT_PERI1_GR4_BOOT, + PROT_PERI1_TR, + PROT_PERI1_PERI_PCLK1_MAIN, + PROT_PERI1_M55APPCPUSS, + PROT_PERI1_MXCM55_CM55, + PROT_PERI1_MXCM55_CM55_S, + PROT_PERI1_MXCM55_CM55_NS, + PROT_PERI1_MXCM55_BOOT, + PROT_PERI1_MXCM55_CM55_INT, + PROT_PERI1_SAXI_DMAC_TOP, + PROT_PERI1_SAXI_DMAC_CH0_CH, + PROT_PERI1_SAXI_DMAC_CH1_CH, + PROT_PERI1_SAXI_DMAC_CH2_CH, + PROT_PERI1_SAXI_DMAC_CH3_CH, + PROT_PERI1_APPCPUSS_ALL_PC, + PROT_PERI1_APPCPUSS_CM33_NS, + PROT_PERI1_APPCPUSS_MSC_INT, + PROT_PERI1_APPCPUSS_AHB2AXI_INT, + PROT_PERI1_APPCPUSS_AP, + PROT_PERI1_MS_CTL_MS13_MAIN, + PROT_PERI1_MS_CTL_MS14_MAIN, + PROT_PERI1_MS_CTL_MS15_MAIN, + PROT_PERI1_MS_CTL_MS19_MAIN, + PROT_PERI1_MS_CTL_MS23_MAIN, + PROT_PERI1_MS_CTL_MS25_MAIN, + PROT_PERI1_MS_CTL_MS26_MAIN, + PROT_PERI1_MS_CTL_MS27_MAIN, + PROT_PERI1_MS_CTL_MS28_MAIN, + PROT_PERI1_MS_CTL_MS_PC13_PRIV, + PROT_PERI1_MS_CTL_MS_PC14_PRIV, + PROT_PERI1_MS_CTL_MS_PC15_PRIV, + PROT_PERI1_MS_CTL_MS_PC19_PRIV, + PROT_PERI1_MS_CTL_MS_PC25_PRIV, + PROT_PERI1_MS_CTL_MS_PC26_PRIV, + PROT_PERI1_MS_CTL_MS_PC27_PRIV, + PROT_PERI1_MS_CTL_MS_PC28_PRIV, + PROT_PERI1_MS_CTL_MS_PC13_PRIV_MIR, + PROT_PERI1_MS_CTL_MS_PC14_PRIV_MIR, + PROT_PERI1_MS_CTL_MS_PC15_PRIV_MIR, + PROT_PERI1_MS_CTL_MS_PC19_PRIV_MIR, + PROT_PERI1_MS_CTL_MS_PC25_PRIV_MIR, + PROT_PERI1_MS_CTL_MS_PC26_PRIV_MIR, + PROT_PERI1_MS_CTL_MS_PC27_PRIV_MIR, + PROT_PERI1_MS_CTL_MS_PC28_PRIV_MIR, + PROT_PERI1_MS_CTL_MSC_ACG, + PROT_PERI1_APPCPUSS_SL_CTL_GROUP, + PROT_PERI1_IPC1_STRUCT0_IPC, + PROT_PERI1_IPC1_STRUCT1_IPC, + PROT_PERI1_IPC1_STRUCT2_IPC, + PROT_PERI1_IPC1_STRUCT3_IPC, + PROT_PERI1_IPC1_STRUCT4_IPC, + PROT_PERI1_IPC1_STRUCT5_IPC, + PROT_PERI1_IPC1_STRUCT6_IPC, + PROT_PERI1_IPC1_STRUCT7_IPC, + PROT_PERI1_IPC1_STRUCT8_IPC, + PROT_PERI1_IPC1_STRUCT9_IPC, + PROT_PERI1_IPC1_STRUCT10_IPC, + PROT_PERI1_IPC1_STRUCT11_IPC, + PROT_PERI1_IPC1_STRUCT12_IPC, + PROT_PERI1_IPC1_STRUCT13_IPC, + PROT_PERI1_IPC1_STRUCT14_IPC, + PROT_PERI1_IPC1_STRUCT15_IPC, + PROT_PERI1_IPC1_INTR_STRUCT0_INTR, + PROT_PERI1_IPC1_INTR_STRUCT1_INTR, + PROT_PERI1_IPC1_INTR_STRUCT2_INTR, + PROT_PERI1_IPC1_INTR_STRUCT3_INTR, + PROT_PERI1_IPC1_INTR_STRUCT4_INTR, + PROT_PERI1_IPC1_INTR_STRUCT5_INTR, + PROT_PERI1_IPC1_INTR_STRUCT6_INTR, + PROT_PERI1_IPC1_INTR_STRUCT7_INTR, + PROT_PERI1_PDM0_MAIN, + PROT_PERI1_PDM0_CH0_RX, + PROT_PERI1_PDM0_CH1_RX, + PROT_PERI1_PDM0_CH2_RX, + PROT_PERI1_PDM0_CH3_RX, + PROT_PERI1_PDM0_CH4_RX, + PROT_PERI1_PDM0_CH5_RX, + PROT_PERI1_TDM0_TDM_STRUCT0_TDM_TX_STRUCT_TX, + PROT_PERI1_TDM0_TDM_STRUCT1_TDM_TX_STRUCT_TX, + PROT_PERI1_TDM0_TDM_STRUCT0_TDM_RX_STRUCT_RX, + PROT_PERI1_TDM0_TDM_STRUCT1_TDM_RX_STRUCT_RX, + PROT_PERI1_SMIF0_CACHE_BLOCK_MAIN, + PROT_PERI1_SMIF1_CACHE_BLOCK_MAIN, + PROT_PERI1_SMIF0_CACHE_BLOCK_MMIO_MAIN, + PROT_PERI1_SMIF1_CACHE_BLOCK_MMIO_MAIN, + PROT_PERI1_SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_MAIN, + PROT_PERI1_SMIF1_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_MAIN, + PROT_PERI1_SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_PC, + PROT_PERI1_SMIF1_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_PC, + PROT_PERI1_SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_ROT, + PROT_PERI1_SMIF1_CACHE_BLOCK_CACHEBLK_AHB_MPC0_PPC_MPC_ROT, + PROT_PERI1_SMIF0_CORE_MAIN, + PROT_PERI1_SMIF1_CORE_MAIN, + PROT_PERI1_SMIF0_CORE_CRYPTO, + PROT_PERI1_SMIF1_CORE_CRYPTO, + PROT_PERI1_SMIF0_CORE_MAIN2, + PROT_PERI1_SMIF1_CORE_MAIN2, + PROT_PERI1_SMIF0_CORE_DEVICE, + PROT_PERI1_SMIF1_CORE_DEVICE, + PROT_PERI1_SMIF0_CORE_AXI_MPC0_PPC_MPC_MAIN, + PROT_PERI1_SMIF1_CORE_AXI_MPC0_PPC_MPC_MAIN, + PROT_PERI1_SMIF0_CORE_AXI_MPC0_PPC_MPC_PC, + PROT_PERI1_SMIF1_CORE_AXI_MPC0_PPC_MPC_PC, + PROT_PERI1_SMIF0_CORE_AXI_MPC0_PPC_MPC_ROT, + PROT_PERI1_SMIF1_CORE_AXI_MPC0_PPC_MPC_ROT, + PROT_PERI1_SMIF0_CORE_SMIF_HSIOM_SMIF_PRT0_PRT, + PROT_PERI1_SMIF0_CORE_SMIF_HSIOM_SMIF_PRT1_PRT, + PROT_PERI1_SMIF0_CORE_SMIF_HSIOM_SMIF_PRT2_PRT, + PROT_PERI1_SMIF1_CORE_SMIF_HSIOM_SMIF_PRT0_PRT, + PROT_PERI1_SMIF1_CORE_SMIF_HSIOM_SMIF_PRT1_PRT, + PROT_PERI1_SMIF1_CORE_SMIF_HSIOM_SMIF_PRT2_PRT, + PROT_PERI1_SMIF0_CORE_SMIF_HSIOM_MON, + PROT_PERI1_SMIF1_CORE_SMIF_HSIOM_MON, + PROT_PERI1_SMIF0_CORE_SMIF_GPIO_SMIF_PRT0_PRT, + PROT_PERI1_SMIF0_CORE_SMIF_GPIO_SMIF_PRT1_PRT, + PROT_PERI1_SMIF0_CORE_SMIF_GPIO_SMIF_PRT2_PRT, + PROT_PERI1_SMIF1_CORE_SMIF_GPIO_SMIF_PRT0_PRT, + PROT_PERI1_SMIF1_CORE_SMIF_GPIO_SMIF_PRT1_PRT, + PROT_PERI1_SMIF1_CORE_SMIF_GPIO_SMIF_PRT2_PRT, + PROT_PERI1_SMIF0_CORE_SMIF_GPIO_SMIF_PRT0_CFG, + PROT_PERI1_SMIF0_CORE_SMIF_GPIO_SMIF_PRT1_CFG, + PROT_PERI1_SMIF0_CORE_SMIF_GPIO_SMIF_PRT2_CFG, + PROT_PERI1_SMIF1_CORE_SMIF_GPIO_SMIF_PRT0_CFG, + PROT_PERI1_SMIF1_CORE_SMIF_GPIO_SMIF_PRT1_CFG, + PROT_PERI1_SMIF1_CORE_SMIF_GPIO_SMIF_PRT2_CFG, + PROT_PERI1_SMIF0_CORE_SMIF_GPIO_GPIO, + PROT_PERI1_SMIF1_CORE_SMIF_GPIO_GPIO, + PROT_PERI1_SMIF0_CORE_SMIF_GPIO_TEST, + PROT_PERI1_SMIF1_CORE_SMIF_GPIO_TEST, + PROT_PERI1_U550_U55, + PROT_PERI1_U550_ROT, + PROT_PERI1_U550_ACG, + PROT_PERI1_U550_MXU55_PPU_PPU, + PROT_PERI1_U550_PD_PD, + PROT_PERI1_SOCMEM_MAIN, + PROT_PERI1_SOCMEM_BOOT, + PROT_PERI1_SOCMEM_SOCMEM_PWR, + PROT_PERI1_SOCMEM_SRAM_MPC0_PPC_MPC_MAIN, + PROT_PERI1_SOCMEM_SRAM_MPC0_PPC_MPC_PC, + PROT_PERI1_SOCMEM_SRAM_MPC0_PPC_MPC_ROT, + PROT_PERI1_SOCMEM_MAIN_PORT, + PROT_PERI1_SOCMEM_PPU_SOCMEM_PPU, + PROT_PERI1_SOCMEM_SOCMEM_PD_PD, + PROT_PERI1_GFXSS_GPU_GFXSS, + PROT_PERI1_GFXSS_DC_GFXSS, + PROT_PERI1_GFXSS_MIPIDSI_GFXSS, + PROT_PERI1_SDHC0, + PROT_PERI1_SDHC1, + PROT_PERI1_USBHS_DWC_otg_intreg_CONTROLLER, + PROT_PERI1_USBHS_SS_SUBSYSTEM, + PROT_PERI1_ITCM, + PROT_PERI1_DTCM, +}; +const size_t cycfg_unused_ppc_0_regions_count = sizeof(cycfg_unused_ppc_0_regions) / sizeof(cy_en_prot_region_t); +const size_t cycfg_unused_ppc_1_regions_count = sizeof(cycfg_unused_ppc_1_regions) / sizeof(cy_en_prot_region_t); + +#if defined(CY_PDL_TZ_ENABLED) +const cy_stc_sau_config_t SAU_config[4] = +{ + { + .reg_num = 0U, + .base_addr = 0x00000000, + .size = 0x10000000, + .nsc = false, + }, + { + .reg_num = 1U, + .base_addr = 0x20000000, + .size = 0x10000000, + .nsc = false, + }, + { + .reg_num = 2U, + .base_addr = 0x40000000, + .size = 0xc0000000, + .nsc = false, + }, + { + .reg_num = 3, + .base_addr = NSC_START_ADDRESS, + .size = NSC_SIZE, + .nsc = true, + }, +}; +#endif /* defined(CY_PDL_TZ_ENABLED) */ + +const cy_stc_mpu_config_t cycfg_mpu_cm55_ns_0_config[3] = +{ + { + .reg_num = 1U, + .base_addr = 0x240FD000, + .end_addr = 0x240FFFFF, + .writable = true, + .require_privileged = false, + .shareable = false, + .executable = false, + .cacheable = 4, + .is_device = false, + .device_attrs = 0, + }, + { + .reg_num = 2U, + .base_addr = 0x262FC000, + .end_addr = 0x2633BFFF, + .writable = true, + .require_privileged = false, + .shareable = false, + .executable = false, + .cacheable = 4, + .is_device = false, + .device_attrs = 0, + }, + { + .reg_num = 3U, + .base_addr = 0x2633C000, + .end_addr = 0x264FFFFF, + .writable = true, + .require_privileged = false, + .shareable = false, + .executable = false, + .cacheable = 4, + .is_device = false, + .device_attrs = 0, + }, +}; + +#if defined(COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) +const mtb_srf_protection_range_s_t mxrramc_0_mpc_0_srf_protection_range_s[mxrramc_0_mpc_0_REGION_COUNT] = +{ + { + .start = (void *)0x22011000, + .length = 0x4A000U, + .is_secure = true, + }, + { + .start = (void *)0x2205B000, + .length = 0x8000U, + .is_secure = false, + }, +}; +const mtb_srf_protection_range_s_t mxsramc_0_mpc_0_srf_protection_range_s[mxsramc_0_mpc_0_REGION_COUNT] = +{ + { + .start = (void *)0x24001000, + .length = 0x57000U, + .is_secure = true, + }, + { + .start = (void *)0x24058000, + .length = 0x28000U, + .is_secure = false, + }, +}; +const mtb_srf_protection_range_s_t mxsramc_1_mpc_0_srf_protection_range_s[mxsramc_1_mpc_0_REGION_COUNT] = +{ + { + .start = (void *)0x24080000, + .length = 0x3D000U, + .is_secure = false, + }, + { + .start = (void *)0x240BD000, + .length = 0x43000U, + .is_secure = false, + }, +}; +const mtb_srf_protection_range_s_t smif_0_mpc_0_srf_protection_range_s[smif_0_mpc_0_REGION_COUNT] = +{ + { + .start = (void *)0x60100000, + .length = 0x240000U, + .is_secure = true, + }, + { + .start = (void *)0x60340000, + .length = 0x240000U, + .is_secure = false, + }, + { + .start = (void *)0x60580000, + .length = 0x300000U, + .is_secure = false, + }, + { + .start = (void *)0x60100000, + .length = 0x240000U, + .is_secure = true, + }, + { + .start = (void *)0x60340000, + .length = 0x240000U, + .is_secure = false, + }, + { + .start = (void *)0x60580000, + .length = 0x300000U, + .is_secure = false, + }, +}; +const mtb_srf_protection_range_s_t socmem_0_mpc_0_srf_protection_range_s[socmem_0_mpc_0_REGION_COUNT] = +{ + { + .start = (void *)0x26000000, + .length = 0x40000U, + .is_secure = false, + }, + { + .start = (void *)0x26040000, + .length = 0x4C0000U, + .is_secure = false, + }, +}; +#endif /* defined(COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) */ + +#if defined(CY_PDL_TZ_ENABLED) +cy_rslt_t _cycfg_mpc_init_regions_rram(const cy_stc_mpc_regions_t *region, const cy_stc_mpc_rot_cfg_t *cfg, uint8_t cfg_count); +cy_rslt_t _cycfg_mpc_init_regions(const cy_stc_mpc_regions_t *region, const cy_stc_mpc_rot_cfg_t *config, uint8_t cfg_count); +#endif /* defined(CY_PDL_TZ_ENABLED) */ + +cy_rslt_t cycfg_ppc_init_unsecure(PPC_Type *base, const cy_en_prot_region_t regions[], size_t count); + +void init_cycfg_ns_power(void) { + /* Update global variables used by DeepSleep functions */ + #if (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP) + Cy_SysPm_DeepSleepSetup(CY_SYSPM_MODE_DEEPSLEEP); + #elif (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_RAM) + Cy_SysPm_DeepSleepSetup(CY_SYSPM_MODE_DEEPSLEEP_RAM); + #elif (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_OFF) + Cy_SysPm_DeepSleepSetup(CY_SYSPM_MODE_DEEPSLEEP_OFF); + #endif /* CY_CFG_PWR_SYS_IDLE_MODE */ + +} +void init_cycfg_power(void) { + Cy_SysPm_Init(); + + /* **System Active Power Mode Profile Configuration** */ + #if (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_HP) + Cy_SysPm_SystemEnterHp(); + #elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_ULP) + Cy_SysPm_SystemEnterUlp(); + #elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_LP) + Cy_SysPm_SystemEnterLp(); + #endif /* CY_CFG_PWR_SYS_IDLE_MODE */ + + /* **System Domain Idle Power Mode Configuration** */ + #if (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP) + Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP); + Cy_SysPm_SetAppDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP); + #elif (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_RAM) + Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_RAM); + Cy_SysPm_SetAppDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_RAM); + #elif (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_OFF) + Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_OFF); + Cy_SysPm_SetAppDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_OFF); + #endif /* CY_CFG_PWR_SYS_IDLE_MODE */ + + + Cy_SysPm_DeepSleepUpdate(); + + /* **Power domains Configuration** */ + #if (CY_CFG_PWR_PD1_DOMAIN) + #if defined(CORE_NAME_CM33_0) && defined(CY_PDL_TZ_ENABLED) + /* Enables PD1 power domain */ + Cy_System_EnablePD1(); + /* Enables APP_MMIO_TCM memory for CM55 core */ + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_CM55_TCM_512K_PERI_NR, CY_MMIO_CM55_TCM_512K_GROUP_NR, \ + CY_MMIO_CM55_TCM_512K_SLAVE_NR, CY_MMIO_CM55_TCM_512K_CLK_HF_NR); + + /* Clear SYSCPU and APPCPU power domain dependency set by boot code */ + cy_pd_pdcm_clear_dependency(CY_PD_PDCM_APPCPU, CY_PD_PDCM_SYSCPU); + + #endif /* defined(CORE_NAME_CM33_0) && defined(CY_PDL_TZ_ENABLED) */ + #endif /* (CY_CFG_PWR_PD1_DOMAIN) */ +} + +#if defined(CY_PDL_TZ_ENABLED) +cy_rslt_t _cycfg_mpc_init_regions_rram(const cy_stc_mpc_regions_t *region, const cy_stc_mpc_rot_cfg_t *cfg, uint8_t cfg_count) { + cy_rslt_t result = CY_RSLT_SUCCESS; + ifx_se_mpc_rot_cfg_t rotConfigRram; + ifx_se_mpc_rot_cfg_crc_t rotConfigCrcRram; + + memset((void *)&rotConfigRram, 0, sizeof(ifx_se_mpc_rot_cfg_t)); + memset((void *)&rotConfigCrcRram, 0, sizeof(ifx_se_mpc_rot_cfg_crc_t)); + + // Set up rotConfig based on region + rotConfigRram.addr_offset = region->offset; + rotConfigRram.size = region->size; + rotConfigRram.region_size = IFX_SE_MPC_SIZE_4KB; + + for (uint32_t cfg_idx = 0; cfg_idx < cfg_count; ++cfg_idx) + { + rotConfigRram.pc = (ifx_se_mpc_prot_context_t)cfg[cfg_idx].pc; + rotConfigRram.secure = (ifx_se_mpc_sec_attr_t)cfg[cfg_idx].secure; + rotConfigRram.access = (ifx_se_mpc_access_attr_t)cfg[cfg_idx].access; + rotConfigCrcRram.mpc_config = rotConfigRram; + rotConfigCrcRram.crc = + IFX_CRC32_CALC((uint8_t *)(&rotConfigCrcRram), sizeof(rotConfigCrcRram) - sizeof(uint32_t)); + // Call the configuration function for each region and config + ifx_se_status_t cfg_rslt = ifx_se_mpc_config_rot_mpc_struct(&rotConfigCrcRram, + IFX_SE_NULL_CTX); + + if (!IFX_SE_IS_STATUS_SUCCESS(cfg_rslt)) { + result = CY_MPC_FAILURE; + } + } + + return result; +} +cy_rslt_t _cycfg_mpc_init_regions(const cy_stc_mpc_regions_t *region, const cy_stc_mpc_rot_cfg_t *config, uint8_t cfg_count) { + // Will return an error if one occurs at all in the setup process + cy_rslt_t retResult = CY_RSLT_SUCCESS; + // Will track the current iteration for errors + cy_rslt_t currentResult = CY_RSLT_SUCCESS; + + for (uint32_t cfg_idx = 0; cfg_idx < cfg_count; ++cfg_idx) + { + // Call the configuration function for each region and config + currentResult = Cy_Mpc_ConfigRotMpcStruct(region->base, region->offset, region->size, &config[cfg_idx]); + if (CY_RSLT_SUCCESS != currentResult) { + retResult = currentResult; + } + } + + return retResult; +} +cy_rslt_t init_cycfg_mpc(void) { + // Will return an error if one occurs at all in the setup process + cy_rslt_t retResult = CY_RSLT_SUCCESS; + // Will track the current iteration for errors + cy_rslt_t currentResult = CY_RSLT_SUCCESS; + + // When executing from RRAM, the SMIF must be initialized and enabled to + // hold onto any MPC configurations performed on the SMIF memory regions. + // We can disable them after performing the MPC configurations. + #if (smif_0_mpc_0_REGION_COUNT > 0U) + bool isSmif0Uninitialized = false; + if (!Cy_SMIF_IsEnabled(SMIF0_CORE)) { + isSmif0Uninitialized = true; + + cy_stc_smif_context_t SMIF_CORE0_Context; + + static const cy_stc_smif_config_t SMIF_0_CORE_0_config = + { + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = SMIF_DESELECT_DELAY, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, + .enable_internal_dll = false + }; + + /* Enable IP with default configuration */ + (void)Cy_SMIF_Init(SMIF0_CORE, &SMIF_0_CORE_0_config, TIMEOUT_1_MS, &SMIF_CORE0_Context); + Cy_SMIF_Enable(SMIF0_CORE, &SMIF_CORE0_Context); + } + #endif // (smif_0_mpc_0_REGION_COUNT > 0U) + + #if (smif_1_mpc_0_REGION_COUNT > 0U) + bool isSmif1Uninitialized = false; + if (!Cy_SMIF_IsEnabled(SMIF1_CORE)) { + isSmif1Uninitialized = true; + + cy_stc_smif_context_t SMIF_CORE1_Context; + + static const cy_stc_smif_config_t SMIF_0_CORE_1_config = + { + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = SMIF_DESELECT_DELAY, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, + .enable_internal_dll = false + }; + + /* Enable IP with default configuration */ + (void)Cy_SMIF_Init(SMIF1_CORE, &SMIF_0_CORE_1_config, TIMEOUT_1_MS, &SMIF_CORE1_Context); + Cy_SMIF_Enable(SMIF1_CORE, &SMIF_CORE1_Context); + } + #endif // (smif_1_mpc_0_REGION_COUNT > 0U) + + #if (socmem_0_mpc_0_REGION_COUNT > 0U) + /* Enable SOCMEM */ + Cy_SysEnableSOCMEM(true); + #endif // (socmem_0_mpc_0_REGION_COUNT > 0U) + + for (size_t memory_idx = 0; memory_idx < cy_response_mpcs_count; memory_idx++) + { + Cy_Mpc_SetViolationResponse(cy_response_mpcs[memory_idx].base, cy_response_mpcs[memory_idx].response); + } + + + for (size_t domain_idx = 0; domain_idx < unified_mpc_domains_count; ++domain_idx) + { + const cy_stc_mpc_unified_t *domain = &unified_mpc_domains[domain_idx]; + + for (uint32_t region_idx = 0; region_idx < domain->region_count; ++region_idx) + { + const cy_stc_mpc_regions_t *region = &domain->regions[region_idx]; + + if (region->base == (MPC_Type *)RRAMC0_MPC0) { + currentResult = _cycfg_mpc_init_regions_rram(region, &(domain->cfg[0]), domain->cfg_count); + } else { + // Check for an empty regions struct + if (region->base != NULL) { + currentResult = _cycfg_mpc_init_regions(region, &(domain->cfg[0]), domain->cfg_count); + } + } + + if (CY_RSLT_SUCCESS != currentResult) { + retResult = currentResult; + } + } + } + + #if (smif_1_mpc_0_REGION_COUNT > 0U) + if (isSmif1Uninitialized) { + /* Disable IP as MPC configuration is complete*/ + Cy_SMIF_Disable(SMIF1_CORE); + } + #endif // (smif_1_mpc_0_REGION_COUNT > 0U) + + #if (smif_0_mpc_0_REGION_COUNT > 0U) + if (isSmif0Uninitialized) { + /* Disable IP as MPC configuration is complete*/ + Cy_SMIF_Disable(SMIF0_CORE); + } + #endif // (smif_0_mpc_0_REGION_COUNT > 0U) + + return retResult; +} +#endif /* defined(CY_PDL_TZ_ENABLED) */ + +cy_rslt_t cycfg_ppc_init_unsecure(PPC_Type *base, const cy_en_prot_region_t regions[], size_t count) { + cy_rslt_t ret = Cy_Ppc_InitPpc(base, CY_PPC_BUS_ERR); + + for (size_t index = 0; ret == CY_PPC_SUCCESS && index < count; index++) + { + ret = Cy_Ppc_ConfigAttrib(base, regions[index], &cycfg_unused_ppc_cfg); + if (ret == CY_RSLT_SUCCESS) { + ret = Cy_Ppc_SetPcMask(base, regions[index], PPC_PC_MASK_ALL_ACCESS); + } + } + return ret; +} +cy_rslt_t init_cycfg_ppc0(void) { + return cycfg_ppc_init_unsecure(PPC0, cycfg_unused_ppc_0_regions, cycfg_unused_ppc_0_regions_count); +} +cy_rslt_t init_cycfg_ppc1(void) { + return cycfg_ppc_init_unsecure(PPC1, cycfg_unused_ppc_1_regions, cycfg_unused_ppc_1_regions_count); +} +void init_cycfg_system(void) { + #if defined(CY_CFG_PWR_ENABLED) && defined(CY_CFG_PWR_INIT) + init_cycfg_power(); + #endif /* defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_PWR_INIT) */ +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_system.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_system.h new file mode 100644 index 00000000000..1b9cab5a442 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cycfg_system.h @@ -0,0 +1,172 @@ +/******************************************************************************* + * File Name: cycfg_system.h + * + * Description: + * System configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.60.0 + * device-db 4.34.0.9502 + * mtb-dsl-pse8xxgp 1.2.0.895 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#include "cy_syspm.h" +#include "system_edge.h" +#include "cy_sysclk.h" +#include "cy_syspm_pdcm.h" +#include "cy_device.h" +#include "cy_mpc.h" +#include "cy_ppc.h" +#include "cy_cmsis_utils.h" + +#if defined(CY_PDL_TZ_ENABLED) +#include "cy_cmsis_utils.h" +#endif /* defined(CY_PDL_TZ_ENABLED) */ + +#if defined(COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) +#include "mtb_srf.h" +#endif /* defined (COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) */ + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define srss_0_power_0_ENABLED 1U +#define CY_CFG_PWR_MODE_LP 0x01UL +#define CY_CFG_PWR_MODE_ULP 0x02UL +#define CY_CFG_PWR_MODE_HP 0x03UL +#define CY_CFG_PWR_MODE_ACTIVE 0x04UL +#define CY_CFG_PWR_MODE_SLEEP 0x08UL +#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL +#define CY_CFG_PWR_MODE_DEEPSLEEP_RAM 0x11UL +#define CY_CFG_PWR_MODE_DEEPSLEEP_OFF 0x12UL +#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP +#define CY_CFG_PWR_DEEPSLEEP_LATENCY 20UL +#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_HP +#define CY_CFG_PWR_SYS_ACTIVE_PROFILE CY_CFG_PWR_MODE_HP +#define CY_CFG_PWR_VDDA_MV 1800 +#define CY_CFG_PWR_VDDD_MV 1800 +#define CY_CFG_PWR_VDDIO0_MV 1800 +#define CY_CFG_PWR_VDDIO1_MV 1800 +#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_0_90V +#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP +#define CY_CFG_PWR_SRAMLDO_VOLT CY_SYSPM_SRAMLDO_VOLTAGE_0_80V +#define CY_CFG_PWR_PD1_DOMAIN 1 +#define CY_CFG_PWR_PPU_MAIN PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_PD1 PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_SRAM0 PPU_V1_MODE_MEM_RET +#define CY_CFG_PWR_PPU_SRAM1 PPU_V1_MODE_MEM_RET +#define CY_CFG_PWR_PPU_SYSCPU PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_APPCPUSS PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_APPCPU PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_SOCMEM PPU_V1_MODE_MEM_RET +#define CY_CFG_PWR_PPU_U55 PPU_V1_MODE_ON +#define M33S_ENABLED 1U +#define M33_ENABLED 1U +#define M55_ENABLED 1U +#define M33NSC_ENABLED 1U +#define M33_M55_ENABLED 1U +#define reserved_ENABLED 1U +#define vres_0_protection_0_mpc_0_ENABLED 1U +#define M33S_UNIFIED_MPC_DOMAIN_IDX 0U +#define M33_UNIFIED_MPC_DOMAIN_IDX 1U +#define M55_UNIFIED_MPC_DOMAIN_IDX 2U +#define M33NSC_UNIFIED_MPC_DOMAIN_IDX 3U +#define M33_M55_UNIFIED_MPC_DOMAIN_IDX 4U +#define Cy_MPC_Init init_cycfg_mpc +#define PPC_PC_MASK_ALL_ACCESS 0xFFU +#define Cy_PPC0_Init init_cycfg_ppc0 +#define Cy_PPC1_Init init_cycfg_ppc1 +#define m33syscpuss_0_cm33_0_sau_0_ENABLED 1U +#define m55appcpuss_0_cm55_0_mpu_ns_0_ENABLED 1U +#define mxrramc_0_mpc_0_RESPONSE CY_MPC_BUS_ERR +#define mxrramc_0_mpc_0_REGION_COUNT 4U +#define mxsramc_0_mpc_0_RESPONSE CY_MPC_BUS_ERR +#define mxsramc_0_mpc_0_REGION_COUNT 3U +#define mxsramc_1_mpc_0_RESPONSE CY_MPC_BUS_ERR +#define mxsramc_1_mpc_0_REGION_COUNT 2U +#define smif_0_mpc_0_RESPONSE CY_MPC_BUS_ERR +#define smif_0_mpc_0_REGION_COUNT 6U +#define smif_1_mpc_0_RESPONSE CY_MPC_RZWI +#define smif_1_mpc_0_REGION_COUNT 0U +#define socmem_0_mpc_0_RESPONSE CY_MPC_BUS_ERR +#define socmem_0_mpc_0_REGION_COUNT 2U + +#if defined(CY_PDL_TZ_ENABLED) +extern const cy_stc_mpc_rot_cfg_t M33S_mpc_cfg[]; +extern const cy_stc_mpc_rot_cfg_t M33_mpc_cfg[]; +extern const cy_stc_mpc_rot_cfg_t M55_mpc_cfg[]; +extern const cy_stc_mpc_rot_cfg_t M33NSC_mpc_cfg[]; +extern const cy_stc_mpc_rot_cfg_t M33_M55_mpc_cfg[]; +extern const cy_stc_mpc_regions_t M33S_mpc_regions[]; +extern const cy_stc_mpc_regions_t M33_mpc_regions[]; +extern const cy_stc_mpc_regions_t M55_mpc_regions[]; +extern const cy_stc_mpc_regions_t M33NSC_mpc_regions[]; +extern const cy_stc_mpc_regions_t M33_M55_mpc_regions[]; +extern const cy_stc_mpc_resp_cfg_t cy_response_mpcs[]; +extern const size_t cy_response_mpcs_count; +extern const cy_stc_mpc_unified_t unified_mpc_domains[]; +extern const size_t unified_mpc_domains_count; +#endif /* defined (CY_PDL_TZ_ENABLED) */ + +#if defined(COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) +extern const mtb_srf_memory_protection_s_t mtb_srf_memory_protection_s[]; +extern const uint8_t mtb_srf_protection_range_s_count; +#endif /* defined (COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) */ + +extern const cy_stc_ppc_attribute_t cycfg_unused_ppc_cfg; +extern const cy_en_prot_region_t cycfg_unused_ppc_0_regions[]; +extern const cy_en_prot_region_t cycfg_unused_ppc_1_regions[]; +extern const size_t cycfg_unused_ppc_0_regions_count; +extern const size_t cycfg_unused_ppc_1_regions_count; + +#if defined(CY_PDL_TZ_ENABLED) +extern const cy_stc_sau_config_t SAU_config[4]; +#endif /* defined(CY_PDL_TZ_ENABLED) */ + +extern const cy_stc_mpu_config_t cycfg_mpu_cm55_ns_0_config[3]; + +#if defined(COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) +extern const mtb_srf_protection_range_s_t mxrramc_0_mpc_0_srf_protection_range_s[mxrramc_0_mpc_0_REGION_COUNT]; +extern const mtb_srf_protection_range_s_t mxsramc_0_mpc_0_srf_protection_range_s[mxsramc_0_mpc_0_REGION_COUNT]; +extern const mtb_srf_protection_range_s_t mxsramc_1_mpc_0_srf_protection_range_s[mxsramc_1_mpc_0_REGION_COUNT]; +extern const mtb_srf_protection_range_s_t smif_0_mpc_0_srf_protection_range_s[smif_0_mpc_0_REGION_COUNT]; +extern const mtb_srf_protection_range_s_t socmem_0_mpc_0_srf_protection_range_s[socmem_0_mpc_0_REGION_COUNT]; +#endif /* defined(COMPONENT_SECURE_DEVICE) && defined(COMPONENT_MW_MTB_SRF) */ + +void init_cycfg_ns_power(void); +void init_cycfg_power(void); + +#if defined(CY_PDL_TZ_ENABLED) +cy_rslt_t init_cycfg_mpc(void); +#endif /* defined(CY_PDL_TZ_ENABLED) */ + +cy_rslt_t init_cycfg_ppc0(void); +cy_rslt_t init_cycfg_ppc1(void); +void init_cycfg_system(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_SYSTEM_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM33_0.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM33_0.h new file mode 100644 index 00000000000..fb2a3e11379 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM33_0.h @@ -0,0 +1,92 @@ +/* This file is automatically generated. */ +#if !defined(CYMEM_CM33_0_H) +#define CYMEM_CM33_0_H + +#define CYMEM_CM33_0_m55_data_START 0x48040000u +#define CYMEM_CM33_0_m55_data_SIZE 0x00040000u +#define CYMEM_CM33_0_m55_data_OFFSET 0x00000000u +#define CYMEM_CM33_0_m55_code_START 0x48000000u +#define CYMEM_CM33_0_m55_code_SIZE 0x00040000u +#define CYMEM_CM33_0_m55_code_OFFSET 0x00000000u +#define CYMEM_CM33_0_user_programmable_START 0x22011000u +#define CYMEM_CM33_0_user_programmable_C_START 0x02011000u +#define CYMEM_CM33_0_user_programmable_SIZE 0x0004A000u +#define CYMEM_CM33_0_user_programmable_OFFSET 0x00011000u +#define CYMEM_CM33_0_user_nvm_START 0x2205B000u +#define CYMEM_CM33_0_user_nvm_C_START 0x0205B000u +#define CYMEM_CM33_0_user_nvm_SIZE 0x00008000u +#define CYMEM_CM33_0_user_nvm_OFFSET 0x0005B000u +#define CYMEM_CM33_0_m33s_nvm_START 0x60100000u +#define CYMEM_CM33_0_m33s_nvm_C_START 0x08100000u +#define CYMEM_CM33_0_m33s_nvm_SIZE 0x00200000u +#define CYMEM_CM33_0_m33s_nvm_OFFSET 0x00100000u +#define CYMEM_CM33_0_m33s_trailer_START 0x60300000u +#define CYMEM_CM33_0_m33s_trailer_C_START 0x08300000u +#define CYMEM_CM33_0_m33s_trailer_SIZE 0x00040000u +#define CYMEM_CM33_0_m33s_trailer_OFFSET 0x00300000u +#define CYMEM_CM33_0_m33_nvm_START 0x60340000u +#define CYMEM_CM33_0_m33_nvm_C_START 0x08340000u +#define CYMEM_CM33_0_m33_nvm_SIZE 0x00200000u +#define CYMEM_CM33_0_m33_nvm_OFFSET 0x00340000u +#define CYMEM_CM33_0_m33_trailer_START 0x60540000u +#define CYMEM_CM33_0_m33_trailer_C_START 0x08540000u +#define CYMEM_CM33_0_m33_trailer_SIZE 0x00040000u +#define CYMEM_CM33_0_m33_trailer_OFFSET 0x00540000u +#define CYMEM_CM33_0_m55_nvm_START 0x60580000u +#define CYMEM_CM33_0_m55_nvm_C_START 0x08580000u +#define CYMEM_CM33_0_m55_nvm_SIZE 0x002C0000u +#define CYMEM_CM33_0_m55_nvm_OFFSET 0x00580000u +#define CYMEM_CM33_0_m55_trailer_START 0x60840000u +#define CYMEM_CM33_0_m55_trailer_C_START 0x08840000u +#define CYMEM_CM33_0_m55_trailer_SIZE 0x00040000u +#define CYMEM_CM33_0_m55_trailer_OFFSET 0x00840000u +#define CYMEM_CM33_0_m55_code_secondary_START 0x26000000u +#define CYMEM_CM33_0_m55_code_secondary_C_START 0x06000000u +#define CYMEM_CM33_0_m55_code_secondary_SIZE 0x00040000u +#define CYMEM_CM33_0_m55_code_secondary_OFFSET 0x00000000u +#define CYMEM_CM33_0_m55_data_secondary_START 0x26040000u +#define CYMEM_CM33_0_m55_data_secondary_C_START 0x06040000u +#define CYMEM_CM33_0_m55_data_secondary_SIZE 0x002BC000u +#define CYMEM_CM33_0_m55_data_secondary_OFFSET 0x00040000u +#define CYMEM_CM33_0_m33_m55_shared_START 0x262FC000u +#define CYMEM_CM33_0_m33_m55_shared_C_START 0x062FC000u +#define CYMEM_CM33_0_m33_m55_shared_SIZE 0x00040000u +#define CYMEM_CM33_0_m33_m55_shared_OFFSET 0x002FC000u +#define CYMEM_CM33_0_gfx_mem_START 0x2633C000u +#define CYMEM_CM33_0_gfx_mem_C_START 0x0633C000u +#define CYMEM_CM33_0_gfx_mem_SIZE 0x001C4000u +#define CYMEM_CM33_0_gfx_mem_OFFSET 0x0033C000u +#define CYMEM_CM33_0_m33s_shared_START 0x24001000u +#define CYMEM_CM33_0_m33s_shared_C_START 0x04001000u +#define CYMEM_CM33_0_m33s_shared_SIZE 0x00001000u +#define CYMEM_CM33_0_m33s_shared_OFFSET 0x00001000u +#define CYMEM_CM33_0_m33s_code_START 0x24002000u +#define CYMEM_CM33_0_m33s_code_C_START 0x04002000u +#define CYMEM_CM33_0_m33s_code_SIZE 0x00035000u +#define CYMEM_CM33_0_m33s_code_OFFSET 0x00002000u +#define CYMEM_CM33_0_m33s_data_START 0x24037000u +#define CYMEM_CM33_0_m33s_data_C_START 0x04037000u +#define CYMEM_CM33_0_m33s_data_SIZE 0x00021000u +#define CYMEM_CM33_0_m33s_data_OFFSET 0x00037000u +#define CYMEM_CM33_0_m33_code_START 0x24058000u +#define CYMEM_CM33_0_m33_code_C_START 0x04058000u +#define CYMEM_CM33_0_m33_code_SIZE 0x00065000u +#define CYMEM_CM33_0_m33_code_OFFSET 0x00058000u +#define CYMEM_CM33_0_m33_data_START 0x240BD000u +#define CYMEM_CM33_0_m33_data_C_START 0x040BD000u +#define CYMEM_CM33_0_m33_data_SIZE 0x00040000u +#define CYMEM_CM33_0_m33_data_OFFSET 0x000BD000u +#define CYMEM_CM33_0_m33s_allocatable_shared_START 0x240FD000u +#define CYMEM_CM33_0_m33s_allocatable_shared_C_START 0x040FD000u +#define CYMEM_CM33_0_m33s_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM33_0_m33s_allocatable_shared_OFFSET 0x000FD000u +#define CYMEM_CM33_0_m33_allocatable_shared_START 0x240FE000u +#define CYMEM_CM33_0_m33_allocatable_shared_C_START 0x040FE000u +#define CYMEM_CM33_0_m33_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM33_0_m33_allocatable_shared_OFFSET 0x000FE000u +#define CYMEM_CM33_0_m55_allocatable_shared_START 0x240FF000u +#define CYMEM_CM33_0_m55_allocatable_shared_C_START 0x040FF000u +#define CYMEM_CM33_0_m55_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM33_0_m55_allocatable_shared_OFFSET 0x000FF000u + +#endif /* CYMEM_CM33_0_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM33_0_S.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM33_0_S.h new file mode 100644 index 00000000000..bc7a5281c9a --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM33_0_S.h @@ -0,0 +1,134 @@ +/* This file is automatically generated. */ +#if !defined(CYMEM_CM33_0_S_H) +#define CYMEM_CM33_0_S_H + +#define CYMEM_CM33_0_S_m55_data_START 0x48040000u +#define CYMEM_CM33_0_S_m55_data_S_START 0x58040000u +#define CYMEM_CM33_0_S_m55_data_SIZE 0x00040000u +#define CYMEM_CM33_0_S_m55_data_OFFSET 0x00000000u +#define CYMEM_CM33_0_S_m55_code_START 0x48000000u +#define CYMEM_CM33_0_S_m55_code_S_START 0x58000000u +#define CYMEM_CM33_0_S_m55_code_SIZE 0x00040000u +#define CYMEM_CM33_0_S_m55_code_OFFSET 0x00000000u +#define CYMEM_CM33_0_S_user_programmable_START 0x22011000u +#define CYMEM_CM33_0_S_user_programmable_C_START 0x02011000u +#define CYMEM_CM33_0_S_user_programmable_C_S_START 0x12011000u +#define CYMEM_CM33_0_S_user_programmable_S_START 0x32011000u +#define CYMEM_CM33_0_S_user_programmable_SIZE 0x0004A000u +#define CYMEM_CM33_0_S_user_programmable_OFFSET 0x00011000u +#define CYMEM_CM33_0_S_user_nvm_START 0x2205B000u +#define CYMEM_CM33_0_S_user_nvm_C_START 0x0205B000u +#define CYMEM_CM33_0_S_user_nvm_C_S_START 0x1205B000u +#define CYMEM_CM33_0_S_user_nvm_S_START 0x3205B000u +#define CYMEM_CM33_0_S_user_nvm_SIZE 0x00008000u +#define CYMEM_CM33_0_S_user_nvm_OFFSET 0x0005B000u +#define CYMEM_CM33_0_S_m33s_nvm_START 0x60100000u +#define CYMEM_CM33_0_S_m33s_nvm_C_START 0x08100000u +#define CYMEM_CM33_0_S_m33s_nvm_C_S_START 0x18100000u +#define CYMEM_CM33_0_S_m33s_nvm_S_START 0x70100000u +#define CYMEM_CM33_0_S_m33s_nvm_SIZE 0x00200000u +#define CYMEM_CM33_0_S_m33s_nvm_OFFSET 0x00100000u +#define CYMEM_CM33_0_S_m33s_trailer_START 0x60300000u +#define CYMEM_CM33_0_S_m33s_trailer_C_START 0x08300000u +#define CYMEM_CM33_0_S_m33s_trailer_C_S_START 0x18300000u +#define CYMEM_CM33_0_S_m33s_trailer_S_START 0x70300000u +#define CYMEM_CM33_0_S_m33s_trailer_SIZE 0x00040000u +#define CYMEM_CM33_0_S_m33s_trailer_OFFSET 0x00300000u +#define CYMEM_CM33_0_S_m33_nvm_START 0x60340000u +#define CYMEM_CM33_0_S_m33_nvm_C_START 0x08340000u +#define CYMEM_CM33_0_S_m33_nvm_C_S_START 0x18340000u +#define CYMEM_CM33_0_S_m33_nvm_S_START 0x70340000u +#define CYMEM_CM33_0_S_m33_nvm_SIZE 0x00200000u +#define CYMEM_CM33_0_S_m33_nvm_OFFSET 0x00340000u +#define CYMEM_CM33_0_S_m33_trailer_START 0x60540000u +#define CYMEM_CM33_0_S_m33_trailer_C_START 0x08540000u +#define CYMEM_CM33_0_S_m33_trailer_C_S_START 0x18540000u +#define CYMEM_CM33_0_S_m33_trailer_S_START 0x70540000u +#define CYMEM_CM33_0_S_m33_trailer_SIZE 0x00040000u +#define CYMEM_CM33_0_S_m33_trailer_OFFSET 0x00540000u +#define CYMEM_CM33_0_S_m55_nvm_START 0x60580000u +#define CYMEM_CM33_0_S_m55_nvm_C_START 0x08580000u +#define CYMEM_CM33_0_S_m55_nvm_C_S_START 0x18580000u +#define CYMEM_CM33_0_S_m55_nvm_S_START 0x70580000u +#define CYMEM_CM33_0_S_m55_nvm_SIZE 0x002C0000u +#define CYMEM_CM33_0_S_m55_nvm_OFFSET 0x00580000u +#define CYMEM_CM33_0_S_m55_trailer_START 0x60840000u +#define CYMEM_CM33_0_S_m55_trailer_C_START 0x08840000u +#define CYMEM_CM33_0_S_m55_trailer_C_S_START 0x18840000u +#define CYMEM_CM33_0_S_m55_trailer_S_START 0x70840000u +#define CYMEM_CM33_0_S_m55_trailer_SIZE 0x00040000u +#define CYMEM_CM33_0_S_m55_trailer_OFFSET 0x00840000u +#define CYMEM_CM33_0_S_m55_code_secondary_START 0x26000000u +#define CYMEM_CM33_0_S_m55_code_secondary_C_START 0x06000000u +#define CYMEM_CM33_0_S_m55_code_secondary_C_S_START 0x16000000u +#define CYMEM_CM33_0_S_m55_code_secondary_S_START 0x36000000u +#define CYMEM_CM33_0_S_m55_code_secondary_SIZE 0x00040000u +#define CYMEM_CM33_0_S_m55_code_secondary_OFFSET 0x00000000u +#define CYMEM_CM33_0_S_m55_data_secondary_START 0x26040000u +#define CYMEM_CM33_0_S_m55_data_secondary_C_START 0x06040000u +#define CYMEM_CM33_0_S_m55_data_secondary_C_S_START 0x16040000u +#define CYMEM_CM33_0_S_m55_data_secondary_S_START 0x36040000u +#define CYMEM_CM33_0_S_m55_data_secondary_SIZE 0x002BC000u +#define CYMEM_CM33_0_S_m55_data_secondary_OFFSET 0x00040000u +#define CYMEM_CM33_0_S_m33_m55_shared_START 0x262FC000u +#define CYMEM_CM33_0_S_m33_m55_shared_C_START 0x062FC000u +#define CYMEM_CM33_0_S_m33_m55_shared_C_S_START 0x162FC000u +#define CYMEM_CM33_0_S_m33_m55_shared_S_START 0x362FC000u +#define CYMEM_CM33_0_S_m33_m55_shared_SIZE 0x00040000u +#define CYMEM_CM33_0_S_m33_m55_shared_OFFSET 0x002FC000u +#define CYMEM_CM33_0_S_gfx_mem_START 0x2633C000u +#define CYMEM_CM33_0_S_gfx_mem_C_START 0x0633C000u +#define CYMEM_CM33_0_S_gfx_mem_C_S_START 0x1633C000u +#define CYMEM_CM33_0_S_gfx_mem_S_START 0x3633C000u +#define CYMEM_CM33_0_S_gfx_mem_SIZE 0x001C4000u +#define CYMEM_CM33_0_S_gfx_mem_OFFSET 0x0033C000u +#define CYMEM_CM33_0_S_m33s_shared_START 0x24001000u +#define CYMEM_CM33_0_S_m33s_shared_C_START 0x04001000u +#define CYMEM_CM33_0_S_m33s_shared_C_S_START 0x14001000u +#define CYMEM_CM33_0_S_m33s_shared_S_START 0x34001000u +#define CYMEM_CM33_0_S_m33s_shared_SIZE 0x00001000u +#define CYMEM_CM33_0_S_m33s_shared_OFFSET 0x00001000u +#define CYMEM_CM33_0_S_m33s_code_START 0x24002000u +#define CYMEM_CM33_0_S_m33s_code_C_START 0x04002000u +#define CYMEM_CM33_0_S_m33s_code_C_S_START 0x14002000u +#define CYMEM_CM33_0_S_m33s_code_S_START 0x34002000u +#define CYMEM_CM33_0_S_m33s_code_SIZE 0x00035000u +#define CYMEM_CM33_0_S_m33s_code_OFFSET 0x00002000u +#define CYMEM_CM33_0_S_m33s_data_START 0x24037000u +#define CYMEM_CM33_0_S_m33s_data_C_START 0x04037000u +#define CYMEM_CM33_0_S_m33s_data_C_S_START 0x14037000u +#define CYMEM_CM33_0_S_m33s_data_S_START 0x34037000u +#define CYMEM_CM33_0_S_m33s_data_SIZE 0x00021000u +#define CYMEM_CM33_0_S_m33s_data_OFFSET 0x00037000u +#define CYMEM_CM33_0_S_m33_code_START 0x24058000u +#define CYMEM_CM33_0_S_m33_code_C_START 0x04058000u +#define CYMEM_CM33_0_S_m33_code_C_S_START 0x14058000u +#define CYMEM_CM33_0_S_m33_code_S_START 0x34058000u +#define CYMEM_CM33_0_S_m33_code_SIZE 0x00065000u +#define CYMEM_CM33_0_S_m33_code_OFFSET 0x00058000u +#define CYMEM_CM33_0_S_m33_data_START 0x240BD000u +#define CYMEM_CM33_0_S_m33_data_C_START 0x040BD000u +#define CYMEM_CM33_0_S_m33_data_C_S_START 0x140BD000u +#define CYMEM_CM33_0_S_m33_data_S_START 0x340BD000u +#define CYMEM_CM33_0_S_m33_data_SIZE 0x00040000u +#define CYMEM_CM33_0_S_m33_data_OFFSET 0x000BD000u +#define CYMEM_CM33_0_S_m33s_allocatable_shared_START 0x240FD000u +#define CYMEM_CM33_0_S_m33s_allocatable_shared_C_START 0x040FD000u +#define CYMEM_CM33_0_S_m33s_allocatable_shared_C_S_START 0x140FD000u +#define CYMEM_CM33_0_S_m33s_allocatable_shared_S_START 0x340FD000u +#define CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM33_0_S_m33s_allocatable_shared_OFFSET 0x000FD000u +#define CYMEM_CM33_0_S_m33_allocatable_shared_START 0x240FE000u +#define CYMEM_CM33_0_S_m33_allocatable_shared_C_START 0x040FE000u +#define CYMEM_CM33_0_S_m33_allocatable_shared_C_S_START 0x140FE000u +#define CYMEM_CM33_0_S_m33_allocatable_shared_S_START 0x340FE000u +#define CYMEM_CM33_0_S_m33_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM33_0_S_m33_allocatable_shared_OFFSET 0x000FE000u +#define CYMEM_CM33_0_S_m55_allocatable_shared_START 0x240FF000u +#define CYMEM_CM33_0_S_m55_allocatable_shared_C_START 0x040FF000u +#define CYMEM_CM33_0_S_m55_allocatable_shared_C_S_START 0x140FF000u +#define CYMEM_CM33_0_S_m55_allocatable_shared_S_START 0x340FF000u +#define CYMEM_CM33_0_S_m55_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM33_0_S_m55_allocatable_shared_OFFSET 0x000FF000u + +#endif /* CYMEM_CM33_0_S_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM55_0.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM55_0.h new file mode 100644 index 00000000000..f83e6e5ddb2 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_CM55_0.h @@ -0,0 +1,45 @@ +/* This file is automatically generated. */ +#if !defined(CYMEM_CM55_0_H) +#define CYMEM_CM55_0_H + +#define CYMEM_CM55_0_m55_data_INTERNAL_START 0x20000000u +#define CYMEM_CM55_0_m55_data_SIZE 0x00040000u +#define CYMEM_CM55_0_m55_data_OFFSET 0x00000000u +#define CYMEM_CM55_0_m55_code_INTERNAL_START 0x00000000u +#define CYMEM_CM55_0_m55_code_SIZE 0x00040000u +#define CYMEM_CM55_0_m55_code_OFFSET 0x00000000u +#define CYMEM_CM55_0_user_nvm_C_START 0x0205B000u +#define CYMEM_CM55_0_user_nvm_SIZE 0x00008000u +#define CYMEM_CM55_0_user_nvm_OFFSET 0x0005B000u +#define CYMEM_CM55_0_m55_nvm_START 0x60580000u +#define CYMEM_CM55_0_m55_nvm_SIZE 0x002C0000u +#define CYMEM_CM55_0_m55_nvm_OFFSET 0x00580000u +#define CYMEM_CM55_0_m55_trailer_START 0x60840000u +#define CYMEM_CM55_0_m55_trailer_SIZE 0x00040000u +#define CYMEM_CM55_0_m55_trailer_OFFSET 0x00840000u +#define CYMEM_CM55_0_m55_code_secondary_START 0x26000000u +#define CYMEM_CM55_0_m55_code_secondary_SIZE 0x00040000u +#define CYMEM_CM55_0_m55_code_secondary_OFFSET 0x00000000u +#define CYMEM_CM55_0_m55_data_secondary_START 0x26040000u +#define CYMEM_CM55_0_m55_data_secondary_SIZE 0x002BC000u +#define CYMEM_CM55_0_m55_data_secondary_OFFSET 0x00040000u +#define CYMEM_CM55_0_m33_m55_shared_START 0x262FC000u +#define CYMEM_CM55_0_m33_m55_shared_SIZE 0x00040000u +#define CYMEM_CM55_0_m33_m55_shared_OFFSET 0x002FC000u +#define CYMEM_CM55_0_gfx_mem_START 0x2633C000u +#define CYMEM_CM55_0_gfx_mem_SIZE 0x001C4000u +#define CYMEM_CM55_0_gfx_mem_OFFSET 0x0033C000u +#define CYMEM_CM55_0_m33_data_START 0x240BD000u +#define CYMEM_CM55_0_m33_data_SIZE 0x00040000u +#define CYMEM_CM55_0_m33_data_OFFSET 0x000BD000u +#define CYMEM_CM55_0_m33s_allocatable_shared_START 0x240FD000u +#define CYMEM_CM55_0_m33s_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM55_0_m33s_allocatable_shared_OFFSET 0x000FD000u +#define CYMEM_CM55_0_m33_allocatable_shared_START 0x240FE000u +#define CYMEM_CM55_0_m33_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM55_0_m33_allocatable_shared_OFFSET 0x000FE000u +#define CYMEM_CM55_0_m55_allocatable_shared_START 0x240FF000u +#define CYMEM_CM55_0_m55_allocatable_shared_SIZE 0x00001000u +#define CYMEM_CM55_0_m55_allocatable_shared_OFFSET 0x000FF000u + +#endif /* CYMEM_CM55_0_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM33_0.sct b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM33_0.sct new file mode 100644 index 00000000000..ccf5ef994d7 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM33_0.sct @@ -0,0 +1,109 @@ +; This file is automatically generated. +#define CYMEM_CM33_0_m55_data_START 0x48040000 +#define CYMEM_CM33_0_m55_data_SIZE 0x00040000 +#define CYMEM_CM33_0_m55_data_OFFSET 0x00000000 +#define CYMEM_CM33_0_m55_data_sel_START CYMEM_CM33_0_m55_data_START +#define CYMEM_CM33_0_m55_code_START 0x48000000 +#define CYMEM_CM33_0_m55_code_SIZE 0x00040000 +#define CYMEM_CM33_0_m55_code_OFFSET 0x00000000 +#define CYMEM_CM33_0_m55_code_sel_START CYMEM_CM33_0_m55_code_START +#define CYMEM_CM33_0_user_programmable_START 0x22011000 +#define CYMEM_CM33_0_user_programmable_C_START 0x02011000 +#define CYMEM_CM33_0_user_programmable_SIZE 0x0004A000 +#define CYMEM_CM33_0_user_programmable_OFFSET 0x00011000 +#define CYMEM_CM33_0_user_programmable_sel_START CYMEM_CM33_0_user_programmable_C_START +#define CYMEM_CM33_0_user_nvm_START 0x2205B000 +#define CYMEM_CM33_0_user_nvm_C_START 0x0205B000 +#define CYMEM_CM33_0_user_nvm_SIZE 0x00008000 +#define CYMEM_CM33_0_user_nvm_OFFSET 0x0005B000 +#define CYMEM_CM33_0_user_nvm_sel_START CYMEM_CM33_0_user_nvm_C_START +#define CYMEM_CM33_0_m33s_nvm_START 0x60100000 +#define CYMEM_CM33_0_m33s_nvm_C_START 0x08100000 +#define CYMEM_CM33_0_m33s_nvm_SIZE 0x00200000 +#define CYMEM_CM33_0_m33s_nvm_OFFSET 0x00100000 +#define CYMEM_CM33_0_m33s_nvm_sel_START CYMEM_CM33_0_m33s_nvm_C_START +#define CYMEM_CM33_0_m33s_trailer_START 0x60300000 +#define CYMEM_CM33_0_m33s_trailer_C_START 0x08300000 +#define CYMEM_CM33_0_m33s_trailer_SIZE 0x00040000 +#define CYMEM_CM33_0_m33s_trailer_OFFSET 0x00300000 +#define CYMEM_CM33_0_m33s_trailer_sel_START CYMEM_CM33_0_m33s_trailer_C_START +#define CYMEM_CM33_0_m33_nvm_START 0x60340000 +#define CYMEM_CM33_0_m33_nvm_C_START 0x08340000 +#define CYMEM_CM33_0_m33_nvm_SIZE 0x00200000 +#define CYMEM_CM33_0_m33_nvm_OFFSET 0x00340000 +#define CYMEM_CM33_0_m33_nvm_sel_START CYMEM_CM33_0_m33_nvm_C_START +#define CYMEM_CM33_0_m33_trailer_START 0x60540000 +#define CYMEM_CM33_0_m33_trailer_C_START 0x08540000 +#define CYMEM_CM33_0_m33_trailer_SIZE 0x00040000 +#define CYMEM_CM33_0_m33_trailer_OFFSET 0x00540000 +#define CYMEM_CM33_0_m33_trailer_sel_START CYMEM_CM33_0_m33_trailer_C_START +#define CYMEM_CM33_0_m55_nvm_START 0x60580000 +#define CYMEM_CM33_0_m55_nvm_C_START 0x08580000 +#define CYMEM_CM33_0_m55_nvm_SIZE 0x002C0000 +#define CYMEM_CM33_0_m55_nvm_OFFSET 0x00580000 +#define CYMEM_CM33_0_m55_nvm_sel_START CYMEM_CM33_0_m55_nvm_C_START +#define CYMEM_CM33_0_m55_trailer_START 0x60840000 +#define CYMEM_CM33_0_m55_trailer_C_START 0x08840000 +#define CYMEM_CM33_0_m55_trailer_SIZE 0x00040000 +#define CYMEM_CM33_0_m55_trailer_OFFSET 0x00840000 +#define CYMEM_CM33_0_m55_trailer_sel_START CYMEM_CM33_0_m55_trailer_C_START +#define CYMEM_CM33_0_m55_code_secondary_START 0x26000000 +#define CYMEM_CM33_0_m55_code_secondary_C_START 0x06000000 +#define CYMEM_CM33_0_m55_code_secondary_SIZE 0x00040000 +#define CYMEM_CM33_0_m55_code_secondary_OFFSET 0x00000000 +#define CYMEM_CM33_0_m55_code_secondary_sel_START CYMEM_CM33_0_m55_code_secondary_C_START +#define CYMEM_CM33_0_m55_data_secondary_START 0x26040000 +#define CYMEM_CM33_0_m55_data_secondary_C_START 0x06040000 +#define CYMEM_CM33_0_m55_data_secondary_SIZE 0x002BC000 +#define CYMEM_CM33_0_m55_data_secondary_OFFSET 0x00040000 +#define CYMEM_CM33_0_m55_data_secondary_sel_START CYMEM_CM33_0_m55_data_secondary_C_START +#define CYMEM_CM33_0_m33_m55_shared_START 0x262FC000 +#define CYMEM_CM33_0_m33_m55_shared_C_START 0x062FC000 +#define CYMEM_CM33_0_m33_m55_shared_SIZE 0x00040000 +#define CYMEM_CM33_0_m33_m55_shared_OFFSET 0x002FC000 +#define CYMEM_CM33_0_m33_m55_shared_sel_START CYMEM_CM33_0_m33_m55_shared_C_START +#define CYMEM_CM33_0_gfx_mem_START 0x2633C000 +#define CYMEM_CM33_0_gfx_mem_C_START 0x0633C000 +#define CYMEM_CM33_0_gfx_mem_SIZE 0x001C4000 +#define CYMEM_CM33_0_gfx_mem_OFFSET 0x0033C000 +#define CYMEM_CM33_0_gfx_mem_sel_START CYMEM_CM33_0_gfx_mem_C_START +#define CYMEM_CM33_0_m33s_shared_START 0x24001000 +#define CYMEM_CM33_0_m33s_shared_C_START 0x04001000 +#define CYMEM_CM33_0_m33s_shared_SIZE 0x00001000 +#define CYMEM_CM33_0_m33s_shared_OFFSET 0x00001000 +#define CYMEM_CM33_0_m33s_shared_sel_START CYMEM_CM33_0_m33s_shared_C_START +#define CYMEM_CM33_0_m33s_code_START 0x24002000 +#define CYMEM_CM33_0_m33s_code_C_START 0x04002000 +#define CYMEM_CM33_0_m33s_code_SIZE 0x00035000 +#define CYMEM_CM33_0_m33s_code_OFFSET 0x00002000 +#define CYMEM_CM33_0_m33s_code_sel_START CYMEM_CM33_0_m33s_code_C_START +#define CYMEM_CM33_0_m33s_data_START 0x24037000 +#define CYMEM_CM33_0_m33s_data_C_START 0x04037000 +#define CYMEM_CM33_0_m33s_data_SIZE 0x00021000 +#define CYMEM_CM33_0_m33s_data_OFFSET 0x00037000 +#define CYMEM_CM33_0_m33s_data_sel_START CYMEM_CM33_0_m33s_data_C_START +#define CYMEM_CM33_0_m33_code_START 0x24058000 +#define CYMEM_CM33_0_m33_code_C_START 0x04058000 +#define CYMEM_CM33_0_m33_code_SIZE 0x00065000 +#define CYMEM_CM33_0_m33_code_OFFSET 0x00058000 +#define CYMEM_CM33_0_m33_code_sel_START CYMEM_CM33_0_m33_code_C_START +#define CYMEM_CM33_0_m33_data_START 0x240BD000 +#define CYMEM_CM33_0_m33_data_C_START 0x040BD000 +#define CYMEM_CM33_0_m33_data_SIZE 0x00040000 +#define CYMEM_CM33_0_m33_data_OFFSET 0x000BD000 +#define CYMEM_CM33_0_m33_data_sel_START CYMEM_CM33_0_m33_data_C_START +#define CYMEM_CM33_0_m33s_allocatable_shared_START 0x240FD000 +#define CYMEM_CM33_0_m33s_allocatable_shared_C_START 0x040FD000 +#define CYMEM_CM33_0_m33s_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM33_0_m33s_allocatable_shared_OFFSET 0x000FD000 +#define CYMEM_CM33_0_m33s_allocatable_shared_sel_START CYMEM_CM33_0_m33s_allocatable_shared_C_START +#define CYMEM_CM33_0_m33_allocatable_shared_START 0x240FE000 +#define CYMEM_CM33_0_m33_allocatable_shared_C_START 0x040FE000 +#define CYMEM_CM33_0_m33_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM33_0_m33_allocatable_shared_OFFSET 0x000FE000 +#define CYMEM_CM33_0_m33_allocatable_shared_sel_START CYMEM_CM33_0_m33_allocatable_shared_C_START +#define CYMEM_CM33_0_m55_allocatable_shared_START 0x240FF000 +#define CYMEM_CM33_0_m55_allocatable_shared_C_START 0x040FF000 +#define CYMEM_CM33_0_m55_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM33_0_m55_allocatable_shared_OFFSET 0x000FF000 +#define CYMEM_CM33_0_m55_allocatable_shared_sel_START CYMEM_CM33_0_m55_allocatable_shared_C_START diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM33_0_S.sct b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM33_0_S.sct new file mode 100644 index 00000000000..f73b0c497b1 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM33_0_S.sct @@ -0,0 +1,173 @@ +; This file is automatically generated. +#define CYMEM_CM33_0_S_m55_data_START 0x48040000 +#define CYMEM_CM33_0_S_m55_data_S_START 0x58040000 +#define CYMEM_CM33_0_S_m55_data_SIZE 0x00040000 +#define CYMEM_CM33_0_S_m55_data_OFFSET 0x00000000 +#define CYMEM_CM33_0_S_m55_data_sel_START CYMEM_CM33_0_S_m55_data_START +#define CYMEM_CM33_0_S_m55_data_sel_S_START CYMEM_CM33_0_S_m55_data_S_START +#define CYMEM_CM33_0_S_m55_code_START 0x48000000 +#define CYMEM_CM33_0_S_m55_code_S_START 0x58000000 +#define CYMEM_CM33_0_S_m55_code_SIZE 0x00040000 +#define CYMEM_CM33_0_S_m55_code_OFFSET 0x00000000 +#define CYMEM_CM33_0_S_m55_code_sel_START CYMEM_CM33_0_S_m55_code_START +#define CYMEM_CM33_0_S_m55_code_sel_S_START CYMEM_CM33_0_S_m55_code_S_START +#define CYMEM_CM33_0_S_user_programmable_START 0x22011000 +#define CYMEM_CM33_0_S_user_programmable_C_START 0x02011000 +#define CYMEM_CM33_0_S_user_programmable_C_S_START 0x12011000 +#define CYMEM_CM33_0_S_user_programmable_S_START 0x32011000 +#define CYMEM_CM33_0_S_user_programmable_SIZE 0x0004A000 +#define CYMEM_CM33_0_S_user_programmable_OFFSET 0x00011000 +#define CYMEM_CM33_0_S_user_programmable_sel_START CYMEM_CM33_0_S_user_programmable_C_START +#define CYMEM_CM33_0_S_user_programmable_sel_S_START CYMEM_CM33_0_S_user_programmable_C_S_START +#define CYMEM_CM33_0_S_user_nvm_START 0x2205B000 +#define CYMEM_CM33_0_S_user_nvm_C_START 0x0205B000 +#define CYMEM_CM33_0_S_user_nvm_C_S_START 0x1205B000 +#define CYMEM_CM33_0_S_user_nvm_S_START 0x3205B000 +#define CYMEM_CM33_0_S_user_nvm_SIZE 0x00008000 +#define CYMEM_CM33_0_S_user_nvm_OFFSET 0x0005B000 +#define CYMEM_CM33_0_S_user_nvm_sel_START CYMEM_CM33_0_S_user_nvm_C_START +#define CYMEM_CM33_0_S_user_nvm_sel_S_START CYMEM_CM33_0_S_user_nvm_C_S_START +#define CYMEM_CM33_0_S_m33s_nvm_START 0x60100000 +#define CYMEM_CM33_0_S_m33s_nvm_C_START 0x08100000 +#define CYMEM_CM33_0_S_m33s_nvm_C_S_START 0x18100000 +#define CYMEM_CM33_0_S_m33s_nvm_S_START 0x70100000 +#define CYMEM_CM33_0_S_m33s_nvm_SIZE 0x00200000 +#define CYMEM_CM33_0_S_m33s_nvm_OFFSET 0x00100000 +#define CYMEM_CM33_0_S_m33s_nvm_sel_START CYMEM_CM33_0_S_m33s_nvm_C_START +#define CYMEM_CM33_0_S_m33s_nvm_sel_S_START CYMEM_CM33_0_S_m33s_nvm_C_S_START +#define CYMEM_CM33_0_S_m33s_trailer_START 0x60300000 +#define CYMEM_CM33_0_S_m33s_trailer_C_START 0x08300000 +#define CYMEM_CM33_0_S_m33s_trailer_C_S_START 0x18300000 +#define CYMEM_CM33_0_S_m33s_trailer_S_START 0x70300000 +#define CYMEM_CM33_0_S_m33s_trailer_SIZE 0x00040000 +#define CYMEM_CM33_0_S_m33s_trailer_OFFSET 0x00300000 +#define CYMEM_CM33_0_S_m33s_trailer_sel_START CYMEM_CM33_0_S_m33s_trailer_C_START +#define CYMEM_CM33_0_S_m33s_trailer_sel_S_START CYMEM_CM33_0_S_m33s_trailer_C_S_START +#define CYMEM_CM33_0_S_m33_nvm_START 0x60340000 +#define CYMEM_CM33_0_S_m33_nvm_C_START 0x08340000 +#define CYMEM_CM33_0_S_m33_nvm_C_S_START 0x18340000 +#define CYMEM_CM33_0_S_m33_nvm_S_START 0x70340000 +#define CYMEM_CM33_0_S_m33_nvm_SIZE 0x00200000 +#define CYMEM_CM33_0_S_m33_nvm_OFFSET 0x00340000 +#define CYMEM_CM33_0_S_m33_nvm_sel_START CYMEM_CM33_0_S_m33_nvm_C_START +#define CYMEM_CM33_0_S_m33_nvm_sel_S_START CYMEM_CM33_0_S_m33_nvm_C_S_START +#define CYMEM_CM33_0_S_m33_trailer_START 0x60540000 +#define CYMEM_CM33_0_S_m33_trailer_C_START 0x08540000 +#define CYMEM_CM33_0_S_m33_trailer_C_S_START 0x18540000 +#define CYMEM_CM33_0_S_m33_trailer_S_START 0x70540000 +#define CYMEM_CM33_0_S_m33_trailer_SIZE 0x00040000 +#define CYMEM_CM33_0_S_m33_trailer_OFFSET 0x00540000 +#define CYMEM_CM33_0_S_m33_trailer_sel_START CYMEM_CM33_0_S_m33_trailer_C_START +#define CYMEM_CM33_0_S_m33_trailer_sel_S_START CYMEM_CM33_0_S_m33_trailer_C_S_START +#define CYMEM_CM33_0_S_m55_nvm_START 0x60580000 +#define CYMEM_CM33_0_S_m55_nvm_C_START 0x08580000 +#define CYMEM_CM33_0_S_m55_nvm_C_S_START 0x18580000 +#define CYMEM_CM33_0_S_m55_nvm_S_START 0x70580000 +#define CYMEM_CM33_0_S_m55_nvm_SIZE 0x002C0000 +#define CYMEM_CM33_0_S_m55_nvm_OFFSET 0x00580000 +#define CYMEM_CM33_0_S_m55_nvm_sel_START CYMEM_CM33_0_S_m55_nvm_C_START +#define CYMEM_CM33_0_S_m55_nvm_sel_S_START CYMEM_CM33_0_S_m55_nvm_C_S_START +#define CYMEM_CM33_0_S_m55_trailer_START 0x60840000 +#define CYMEM_CM33_0_S_m55_trailer_C_START 0x08840000 +#define CYMEM_CM33_0_S_m55_trailer_C_S_START 0x18840000 +#define CYMEM_CM33_0_S_m55_trailer_S_START 0x70840000 +#define CYMEM_CM33_0_S_m55_trailer_SIZE 0x00040000 +#define CYMEM_CM33_0_S_m55_trailer_OFFSET 0x00840000 +#define CYMEM_CM33_0_S_m55_trailer_sel_START CYMEM_CM33_0_S_m55_trailer_C_START +#define CYMEM_CM33_0_S_m55_trailer_sel_S_START CYMEM_CM33_0_S_m55_trailer_C_S_START +#define CYMEM_CM33_0_S_m55_code_secondary_START 0x26000000 +#define CYMEM_CM33_0_S_m55_code_secondary_C_START 0x06000000 +#define CYMEM_CM33_0_S_m55_code_secondary_C_S_START 0x16000000 +#define CYMEM_CM33_0_S_m55_code_secondary_S_START 0x36000000 +#define CYMEM_CM33_0_S_m55_code_secondary_SIZE 0x00040000 +#define CYMEM_CM33_0_S_m55_code_secondary_OFFSET 0x00000000 +#define CYMEM_CM33_0_S_m55_code_secondary_sel_START CYMEM_CM33_0_S_m55_code_secondary_C_START +#define CYMEM_CM33_0_S_m55_code_secondary_sel_S_START CYMEM_CM33_0_S_m55_code_secondary_C_S_START +#define CYMEM_CM33_0_S_m55_data_secondary_START 0x26040000 +#define CYMEM_CM33_0_S_m55_data_secondary_C_START 0x06040000 +#define CYMEM_CM33_0_S_m55_data_secondary_C_S_START 0x16040000 +#define CYMEM_CM33_0_S_m55_data_secondary_S_START 0x36040000 +#define CYMEM_CM33_0_S_m55_data_secondary_SIZE 0x002BC000 +#define CYMEM_CM33_0_S_m55_data_secondary_OFFSET 0x00040000 +#define CYMEM_CM33_0_S_m55_data_secondary_sel_START CYMEM_CM33_0_S_m55_data_secondary_C_START +#define CYMEM_CM33_0_S_m55_data_secondary_sel_S_START CYMEM_CM33_0_S_m55_data_secondary_C_S_START +#define CYMEM_CM33_0_S_m33_m55_shared_START 0x262FC000 +#define CYMEM_CM33_0_S_m33_m55_shared_C_START 0x062FC000 +#define CYMEM_CM33_0_S_m33_m55_shared_C_S_START 0x162FC000 +#define CYMEM_CM33_0_S_m33_m55_shared_S_START 0x362FC000 +#define CYMEM_CM33_0_S_m33_m55_shared_SIZE 0x00040000 +#define CYMEM_CM33_0_S_m33_m55_shared_OFFSET 0x002FC000 +#define CYMEM_CM33_0_S_m33_m55_shared_sel_START CYMEM_CM33_0_S_m33_m55_shared_C_START +#define CYMEM_CM33_0_S_m33_m55_shared_sel_S_START CYMEM_CM33_0_S_m33_m55_shared_C_S_START +#define CYMEM_CM33_0_S_gfx_mem_START 0x2633C000 +#define CYMEM_CM33_0_S_gfx_mem_C_START 0x0633C000 +#define CYMEM_CM33_0_S_gfx_mem_C_S_START 0x1633C000 +#define CYMEM_CM33_0_S_gfx_mem_S_START 0x3633C000 +#define CYMEM_CM33_0_S_gfx_mem_SIZE 0x001C4000 +#define CYMEM_CM33_0_S_gfx_mem_OFFSET 0x0033C000 +#define CYMEM_CM33_0_S_gfx_mem_sel_START CYMEM_CM33_0_S_gfx_mem_C_START +#define CYMEM_CM33_0_S_gfx_mem_sel_S_START CYMEM_CM33_0_S_gfx_mem_C_S_START +#define CYMEM_CM33_0_S_m33s_shared_START 0x24001000 +#define CYMEM_CM33_0_S_m33s_shared_C_START 0x04001000 +#define CYMEM_CM33_0_S_m33s_shared_C_S_START 0x14001000 +#define CYMEM_CM33_0_S_m33s_shared_S_START 0x34001000 +#define CYMEM_CM33_0_S_m33s_shared_SIZE 0x00001000 +#define CYMEM_CM33_0_S_m33s_shared_OFFSET 0x00001000 +#define CYMEM_CM33_0_S_m33s_shared_sel_START CYMEM_CM33_0_S_m33s_shared_C_START +#define CYMEM_CM33_0_S_m33s_shared_sel_S_START CYMEM_CM33_0_S_m33s_shared_C_S_START +#define CYMEM_CM33_0_S_m33s_code_START 0x24002000 +#define CYMEM_CM33_0_S_m33s_code_C_START 0x04002000 +#define CYMEM_CM33_0_S_m33s_code_C_S_START 0x14002000 +#define CYMEM_CM33_0_S_m33s_code_S_START 0x34002000 +#define CYMEM_CM33_0_S_m33s_code_SIZE 0x00035000 +#define CYMEM_CM33_0_S_m33s_code_OFFSET 0x00002000 +#define CYMEM_CM33_0_S_m33s_code_sel_START CYMEM_CM33_0_S_m33s_code_C_START +#define CYMEM_CM33_0_S_m33s_code_sel_S_START CYMEM_CM33_0_S_m33s_code_C_S_START +#define CYMEM_CM33_0_S_m33s_data_START 0x24037000 +#define CYMEM_CM33_0_S_m33s_data_C_START 0x04037000 +#define CYMEM_CM33_0_S_m33s_data_C_S_START 0x14037000 +#define CYMEM_CM33_0_S_m33s_data_S_START 0x34037000 +#define CYMEM_CM33_0_S_m33s_data_SIZE 0x00021000 +#define CYMEM_CM33_0_S_m33s_data_OFFSET 0x00037000 +#define CYMEM_CM33_0_S_m33s_data_sel_START CYMEM_CM33_0_S_m33s_data_C_START +#define CYMEM_CM33_0_S_m33s_data_sel_S_START CYMEM_CM33_0_S_m33s_data_C_S_START +#define CYMEM_CM33_0_S_m33_code_START 0x24058000 +#define CYMEM_CM33_0_S_m33_code_C_START 0x04058000 +#define CYMEM_CM33_0_S_m33_code_C_S_START 0x14058000 +#define CYMEM_CM33_0_S_m33_code_S_START 0x34058000 +#define CYMEM_CM33_0_S_m33_code_SIZE 0x00065000 +#define CYMEM_CM33_0_S_m33_code_OFFSET 0x00058000 +#define CYMEM_CM33_0_S_m33_code_sel_START CYMEM_CM33_0_S_m33_code_C_START +#define CYMEM_CM33_0_S_m33_code_sel_S_START CYMEM_CM33_0_S_m33_code_C_S_START +#define CYMEM_CM33_0_S_m33_data_START 0x240BD000 +#define CYMEM_CM33_0_S_m33_data_C_START 0x040BD000 +#define CYMEM_CM33_0_S_m33_data_C_S_START 0x140BD000 +#define CYMEM_CM33_0_S_m33_data_S_START 0x340BD000 +#define CYMEM_CM33_0_S_m33_data_SIZE 0x00040000 +#define CYMEM_CM33_0_S_m33_data_OFFSET 0x000BD000 +#define CYMEM_CM33_0_S_m33_data_sel_START CYMEM_CM33_0_S_m33_data_C_START +#define CYMEM_CM33_0_S_m33_data_sel_S_START CYMEM_CM33_0_S_m33_data_C_S_START +#define CYMEM_CM33_0_S_m33s_allocatable_shared_START 0x240FD000 +#define CYMEM_CM33_0_S_m33s_allocatable_shared_C_START 0x040FD000 +#define CYMEM_CM33_0_S_m33s_allocatable_shared_C_S_START 0x140FD000 +#define CYMEM_CM33_0_S_m33s_allocatable_shared_S_START 0x340FD000 +#define CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM33_0_S_m33s_allocatable_shared_OFFSET 0x000FD000 +#define CYMEM_CM33_0_S_m33s_allocatable_shared_sel_START CYMEM_CM33_0_S_m33s_allocatable_shared_C_START +#define CYMEM_CM33_0_S_m33s_allocatable_shared_sel_S_START CYMEM_CM33_0_S_m33s_allocatable_shared_C_S_START +#define CYMEM_CM33_0_S_m33_allocatable_shared_START 0x240FE000 +#define CYMEM_CM33_0_S_m33_allocatable_shared_C_START 0x040FE000 +#define CYMEM_CM33_0_S_m33_allocatable_shared_C_S_START 0x140FE000 +#define CYMEM_CM33_0_S_m33_allocatable_shared_S_START 0x340FE000 +#define CYMEM_CM33_0_S_m33_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM33_0_S_m33_allocatable_shared_OFFSET 0x000FE000 +#define CYMEM_CM33_0_S_m33_allocatable_shared_sel_START CYMEM_CM33_0_S_m33_allocatable_shared_C_START +#define CYMEM_CM33_0_S_m33_allocatable_shared_sel_S_START CYMEM_CM33_0_S_m33_allocatable_shared_C_S_START +#define CYMEM_CM33_0_S_m55_allocatable_shared_START 0x240FF000 +#define CYMEM_CM33_0_S_m55_allocatable_shared_C_START 0x040FF000 +#define CYMEM_CM33_0_S_m55_allocatable_shared_C_S_START 0x140FF000 +#define CYMEM_CM33_0_S_m55_allocatable_shared_S_START 0x340FF000 +#define CYMEM_CM33_0_S_m55_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM33_0_S_m55_allocatable_shared_OFFSET 0x000FF000 +#define CYMEM_CM33_0_S_m55_allocatable_shared_sel_START CYMEM_CM33_0_S_m55_allocatable_shared_C_START +#define CYMEM_CM33_0_S_m55_allocatable_shared_sel_S_START CYMEM_CM33_0_S_m55_allocatable_shared_C_S_START diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM55_0.sct b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM55_0.sct new file mode 100644 index 00000000000..b8eba3deae5 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_armlink_CM55_0.sct @@ -0,0 +1,53 @@ +; This file is automatically generated. +#define CYMEM_CM55_0_m55_data_INTERNAL_START 0x20000000 +#define CYMEM_CM55_0_m55_data_SIZE 0x00040000 +#define CYMEM_CM55_0_m55_data_OFFSET 0x00000000 +#define CYMEM_CM55_0_m55_data_sel_START CYMEM_CM55_0_m55_data_INTERNAL_START +#define CYMEM_CM55_0_m55_code_INTERNAL_START 0x00000000 +#define CYMEM_CM55_0_m55_code_SIZE 0x00040000 +#define CYMEM_CM55_0_m55_code_OFFSET 0x00000000 +#define CYMEM_CM55_0_m55_code_sel_START CYMEM_CM55_0_m55_code_INTERNAL_START +#define CYMEM_CM55_0_user_nvm_C_START 0x0205B000 +#define CYMEM_CM55_0_user_nvm_SIZE 0x00008000 +#define CYMEM_CM55_0_user_nvm_OFFSET 0x0005B000 +#define CYMEM_CM55_0_user_nvm_sel_START CYMEM_CM55_0_user_nvm_C_START +#define CYMEM_CM55_0_m55_nvm_START 0x60580000 +#define CYMEM_CM55_0_m55_nvm_SIZE 0x002C0000 +#define CYMEM_CM55_0_m55_nvm_OFFSET 0x00580000 +#define CYMEM_CM55_0_m55_nvm_sel_START CYMEM_CM55_0_m55_nvm_START +#define CYMEM_CM55_0_m55_trailer_START 0x60840000 +#define CYMEM_CM55_0_m55_trailer_SIZE 0x00040000 +#define CYMEM_CM55_0_m55_trailer_OFFSET 0x00840000 +#define CYMEM_CM55_0_m55_trailer_sel_START CYMEM_CM55_0_m55_trailer_START +#define CYMEM_CM55_0_m55_code_secondary_START 0x26000000 +#define CYMEM_CM55_0_m55_code_secondary_SIZE 0x00040000 +#define CYMEM_CM55_0_m55_code_secondary_OFFSET 0x00000000 +#define CYMEM_CM55_0_m55_code_secondary_sel_START CYMEM_CM55_0_m55_code_secondary_START +#define CYMEM_CM55_0_m55_data_secondary_START 0x26040000 +#define CYMEM_CM55_0_m55_data_secondary_SIZE 0x002BC000 +#define CYMEM_CM55_0_m55_data_secondary_OFFSET 0x00040000 +#define CYMEM_CM55_0_m55_data_secondary_sel_START CYMEM_CM55_0_m55_data_secondary_START +#define CYMEM_CM55_0_m33_m55_shared_START 0x262FC000 +#define CYMEM_CM55_0_m33_m55_shared_SIZE 0x00040000 +#define CYMEM_CM55_0_m33_m55_shared_OFFSET 0x002FC000 +#define CYMEM_CM55_0_m33_m55_shared_sel_START CYMEM_CM55_0_m33_m55_shared_START +#define CYMEM_CM55_0_gfx_mem_START 0x2633C000 +#define CYMEM_CM55_0_gfx_mem_SIZE 0x001C4000 +#define CYMEM_CM55_0_gfx_mem_OFFSET 0x0033C000 +#define CYMEM_CM55_0_gfx_mem_sel_START CYMEM_CM55_0_gfx_mem_START +#define CYMEM_CM55_0_m33_data_START 0x240BD000 +#define CYMEM_CM55_0_m33_data_SIZE 0x00040000 +#define CYMEM_CM55_0_m33_data_OFFSET 0x000BD000 +#define CYMEM_CM55_0_m33_data_sel_START CYMEM_CM55_0_m33_data_START +#define CYMEM_CM55_0_m33s_allocatable_shared_START 0x240FD000 +#define CYMEM_CM55_0_m33s_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM55_0_m33s_allocatable_shared_OFFSET 0x000FD000 +#define CYMEM_CM55_0_m33s_allocatable_shared_sel_START CYMEM_CM55_0_m33s_allocatable_shared_START +#define CYMEM_CM55_0_m33_allocatable_shared_START 0x240FE000 +#define CYMEM_CM55_0_m33_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM55_0_m33_allocatable_shared_OFFSET 0x000FE000 +#define CYMEM_CM55_0_m33_allocatable_shared_sel_START CYMEM_CM55_0_m33_allocatable_shared_START +#define CYMEM_CM55_0_m55_allocatable_shared_START 0x240FF000 +#define CYMEM_CM55_0_m55_allocatable_shared_SIZE 0x00001000 +#define CYMEM_CM55_0_m55_allocatable_shared_OFFSET 0x000FF000 +#define CYMEM_CM55_0_m55_allocatable_shared_sel_START CYMEM_CM55_0_m55_allocatable_shared_START diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0.ld b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0.ld new file mode 100644 index 00000000000..dce74513018 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0.ld @@ -0,0 +1,157 @@ +/* This file is automatically generated. */ + +CYMEM_CM33_0_m55_data_START = 0x48040000; +CYMEM_CM33_0_m55_data_SIZE = 0x00040000; +CYMEM_CM33_0_m55_data_OFFSET = 0x00000000; +CYMEM_CM33_0_m55_code_START = 0x48000000; +CYMEM_CM33_0_m55_code_SIZE = 0x00040000; +CYMEM_CM33_0_m55_code_OFFSET = 0x00000000; +CYMEM_CM33_0_user_programmable_START = 0x22011000; +CYMEM_CM33_0_user_programmable_C_START = 0x02011000; +CYMEM_CM33_0_user_programmable_SIZE = 0x0004A000; +CYMEM_CM33_0_user_programmable_OFFSET = 0x00011000; +CYMEM_CM33_0_user_nvm_START = 0x2205B000; +CYMEM_CM33_0_user_nvm_C_START = 0x0205B000; +CYMEM_CM33_0_user_nvm_SIZE = 0x00008000; +CYMEM_CM33_0_user_nvm_OFFSET = 0x0005B000; +CYMEM_CM33_0_m33s_nvm_START = 0x60100000; +CYMEM_CM33_0_m33s_nvm_C_START = 0x08100000; +CYMEM_CM33_0_m33s_nvm_SIZE = 0x00200000; +CYMEM_CM33_0_m33s_nvm_OFFSET = 0x00100000; +CYMEM_CM33_0_m33s_trailer_START = 0x60300000; +CYMEM_CM33_0_m33s_trailer_C_START = 0x08300000; +CYMEM_CM33_0_m33s_trailer_SIZE = 0x00040000; +CYMEM_CM33_0_m33s_trailer_OFFSET = 0x00300000; +CYMEM_CM33_0_m33_nvm_START = 0x60340000; +CYMEM_CM33_0_m33_nvm_C_START = 0x08340000; +CYMEM_CM33_0_m33_nvm_SIZE = 0x00200000; +CYMEM_CM33_0_m33_nvm_OFFSET = 0x00340000; +CYMEM_CM33_0_m33_trailer_START = 0x60540000; +CYMEM_CM33_0_m33_trailer_C_START = 0x08540000; +CYMEM_CM33_0_m33_trailer_SIZE = 0x00040000; +CYMEM_CM33_0_m33_trailer_OFFSET = 0x00540000; +CYMEM_CM33_0_m55_nvm_START = 0x60580000; +CYMEM_CM33_0_m55_nvm_C_START = 0x08580000; +CYMEM_CM33_0_m55_nvm_SIZE = 0x002C0000; +CYMEM_CM33_0_m55_nvm_OFFSET = 0x00580000; +CYMEM_CM33_0_m55_trailer_START = 0x60840000; +CYMEM_CM33_0_m55_trailer_C_START = 0x08840000; +CYMEM_CM33_0_m55_trailer_SIZE = 0x00040000; +CYMEM_CM33_0_m55_trailer_OFFSET = 0x00840000; +CYMEM_CM33_0_m55_code_secondary_START = 0x26000000; +CYMEM_CM33_0_m55_code_secondary_C_START = 0x06000000; +CYMEM_CM33_0_m55_code_secondary_SIZE = 0x00040000; +CYMEM_CM33_0_m55_code_secondary_OFFSET = 0x00000000; +CYMEM_CM33_0_m55_data_secondary_START = 0x26040000; +CYMEM_CM33_0_m55_data_secondary_C_START = 0x06040000; +CYMEM_CM33_0_m55_data_secondary_SIZE = 0x002BC000; +CYMEM_CM33_0_m55_data_secondary_OFFSET = 0x00040000; +CYMEM_CM33_0_m33_m55_shared_START = 0x262FC000; +CYMEM_CM33_0_m33_m55_shared_C_START = 0x062FC000; +CYMEM_CM33_0_m33_m55_shared_SIZE = 0x00040000; +CYMEM_CM33_0_m33_m55_shared_OFFSET = 0x002FC000; +CYMEM_CM33_0_gfx_mem_START = 0x2633C000; +CYMEM_CM33_0_gfx_mem_C_START = 0x0633C000; +CYMEM_CM33_0_gfx_mem_SIZE = 0x001C4000; +CYMEM_CM33_0_gfx_mem_OFFSET = 0x0033C000; +CYMEM_CM33_0_m33s_shared_START = 0x24001000; +CYMEM_CM33_0_m33s_shared_C_START = 0x04001000; +CYMEM_CM33_0_m33s_shared_SIZE = 0x00001000; +CYMEM_CM33_0_m33s_shared_OFFSET = 0x00001000; +CYMEM_CM33_0_m33s_code_START = 0x24002000; +CYMEM_CM33_0_m33s_code_C_START = 0x04002000; +CYMEM_CM33_0_m33s_code_SIZE = 0x00035000; +CYMEM_CM33_0_m33s_code_OFFSET = 0x00002000; +CYMEM_CM33_0_m33s_data_START = 0x24037000; +CYMEM_CM33_0_m33s_data_C_START = 0x04037000; +CYMEM_CM33_0_m33s_data_SIZE = 0x00021000; +CYMEM_CM33_0_m33s_data_OFFSET = 0x00037000; +CYMEM_CM33_0_m33_code_START = 0x24058000; +CYMEM_CM33_0_m33_code_C_START = 0x04058000; +CYMEM_CM33_0_m33_code_SIZE = 0x00065000; +CYMEM_CM33_0_m33_code_OFFSET = 0x00058000; +CYMEM_CM33_0_m33_data_START = 0x240BD000; +CYMEM_CM33_0_m33_data_C_START = 0x040BD000; +CYMEM_CM33_0_m33_data_SIZE = 0x00040000; +CYMEM_CM33_0_m33_data_OFFSET = 0x000BD000; +CYMEM_CM33_0_m33s_allocatable_shared_START = 0x240FD000; +CYMEM_CM33_0_m33s_allocatable_shared_C_START = 0x040FD000; +CYMEM_CM33_0_m33s_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM33_0_m33s_allocatable_shared_OFFSET = 0x000FD000; +CYMEM_CM33_0_m33_allocatable_shared_START = 0x240FE000; +CYMEM_CM33_0_m33_allocatable_shared_C_START = 0x040FE000; +CYMEM_CM33_0_m33_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM33_0_m33_allocatable_shared_OFFSET = 0x000FE000; +CYMEM_CM33_0_m55_allocatable_shared_START = 0x240FF000; +CYMEM_CM33_0_m55_allocatable_shared_C_START = 0x040FF000; +CYMEM_CM33_0_m55_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM33_0_m55_allocatable_shared_OFFSET = 0x000FF000; + +MEMORY +{ + m55_data : ORIGIN = 0x48040000, LENGTH = 0x00040000 + m55_code : ORIGIN = 0x48000000, LENGTH = 0x00040000 + user_programmable : ORIGIN = 0x22011000, LENGTH = 0x0004A000 + user_programmable_C : ORIGIN = 0x02011000, LENGTH = 0x0004A000 + user_nvm : ORIGIN = 0x2205B000, LENGTH = 0x00008000 + user_nvm_C : ORIGIN = 0x0205B000, LENGTH = 0x00008000 + m33s_nvm : ORIGIN = 0x60100000, LENGTH = 0x00200000 + m33s_nvm_C : ORIGIN = 0x08100000, LENGTH = 0x00200000 + m33s_trailer : ORIGIN = 0x60300000, LENGTH = 0x00040000 + m33s_trailer_C : ORIGIN = 0x08300000, LENGTH = 0x00040000 + m33_nvm : ORIGIN = 0x60340000, LENGTH = 0x00200000 + m33_nvm_C : ORIGIN = 0x08340000, LENGTH = 0x00200000 + m33_trailer : ORIGIN = 0x60540000, LENGTH = 0x00040000 + m33_trailer_C : ORIGIN = 0x08540000, LENGTH = 0x00040000 + m55_nvm : ORIGIN = 0x60580000, LENGTH = 0x002C0000 + m55_nvm_C : ORIGIN = 0x08580000, LENGTH = 0x002C0000 + m55_trailer : ORIGIN = 0x60840000, LENGTH = 0x00040000 + m55_trailer_C : ORIGIN = 0x08840000, LENGTH = 0x00040000 + m55_code_secondary : ORIGIN = 0x26000000, LENGTH = 0x00040000 + m55_code_secondary_C : ORIGIN = 0x06000000, LENGTH = 0x00040000 + m55_data_secondary : ORIGIN = 0x26040000, LENGTH = 0x002BC000 + m55_data_secondary_C : ORIGIN = 0x06040000, LENGTH = 0x002BC000 + m33_m55_shared : ORIGIN = 0x262FC000, LENGTH = 0x00040000 + m33_m55_shared_C : ORIGIN = 0x062FC000, LENGTH = 0x00040000 + gfx_mem : ORIGIN = 0x2633C000, LENGTH = 0x001C4000 + gfx_mem_C : ORIGIN = 0x0633C000, LENGTH = 0x001C4000 + m33s_shared : ORIGIN = 0x24001000, LENGTH = 0x00001000 + m33s_shared_C : ORIGIN = 0x04001000, LENGTH = 0x00001000 + m33s_code : ORIGIN = 0x24002000, LENGTH = 0x00035000 + m33s_code_C : ORIGIN = 0x04002000, LENGTH = 0x00035000 + m33s_data : ORIGIN = 0x24037000, LENGTH = 0x00021000 + m33s_data_C : ORIGIN = 0x04037000, LENGTH = 0x00021000 + m33_code : ORIGIN = 0x24058000, LENGTH = 0x00065000 + m33_code_C : ORIGIN = 0x04058000, LENGTH = 0x00065000 + m33_data : ORIGIN = 0x240BD000, LENGTH = 0x00040000 + m33_data_C : ORIGIN = 0x040BD000, LENGTH = 0x00040000 + m33s_allocatable_shared : ORIGIN = 0x240FD000, LENGTH = 0x00001000 + m33s_allocatable_shared_C : ORIGIN = 0x040FD000, LENGTH = 0x00001000 + m33_allocatable_shared : ORIGIN = 0x240FE000, LENGTH = 0x00001000 + m33_allocatable_shared_C : ORIGIN = 0x040FE000, LENGTH = 0x00001000 + m55_allocatable_shared : ORIGIN = 0x240FF000, LENGTH = 0x00001000 + m55_allocatable_shared_C : ORIGIN = 0x040FF000, LENGTH = 0x00001000 +} + +REGION_ALIAS("m55_data_sel", m55_data) +REGION_ALIAS("m55_code_sel", m55_code) +REGION_ALIAS("user_programmable_sel", user_programmable_C) +REGION_ALIAS("user_nvm_sel", user_nvm_C) +REGION_ALIAS("m33s_nvm_sel", m33s_nvm_C) +REGION_ALIAS("m33s_trailer_sel", m33s_trailer_C) +REGION_ALIAS("m33_nvm_sel", m33_nvm_C) +REGION_ALIAS("m33_trailer_sel", m33_trailer_C) +REGION_ALIAS("m55_nvm_sel", m55_nvm_C) +REGION_ALIAS("m55_trailer_sel", m55_trailer_C) +REGION_ALIAS("m55_code_secondary_sel", m55_code_secondary_C) +REGION_ALIAS("m55_data_secondary_sel", m55_data_secondary_C) +REGION_ALIAS("m33_m55_shared_sel", m33_m55_shared_C) +REGION_ALIAS("gfx_mem_sel", gfx_mem_C) +REGION_ALIAS("m33s_shared_sel", m33s_shared_C) +REGION_ALIAS("m33s_code_sel", m33s_code_C) +REGION_ALIAS("m33s_data_sel", m33s_data_C) +REGION_ALIAS("m33_code_sel", m33_code_C) +REGION_ALIAS("m33_data_sel", m33_data_C) +REGION_ALIAS("m33s_allocatable_shared_sel", m33s_allocatable_shared_C) +REGION_ALIAS("m33_allocatable_shared_sel", m33_allocatable_shared_C) +REGION_ALIAS("m55_allocatable_shared_sel", m55_allocatable_shared_C) diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0_S.ld b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0_S.ld new file mode 100644 index 00000000000..910aea74878 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM33_0_S.ld @@ -0,0 +1,263 @@ +/* This file is automatically generated. */ + +CYMEM_CM33_0_S_m55_data_START = 0x48040000; +CYMEM_CM33_0_S_m55_data_S_START = 0x58040000; +CYMEM_CM33_0_S_m55_data_SIZE = 0x00040000; +CYMEM_CM33_0_S_m55_data_OFFSET = 0x00000000; +CYMEM_CM33_0_S_m55_code_START = 0x48000000; +CYMEM_CM33_0_S_m55_code_S_START = 0x58000000; +CYMEM_CM33_0_S_m55_code_SIZE = 0x00040000; +CYMEM_CM33_0_S_m55_code_OFFSET = 0x00000000; +CYMEM_CM33_0_S_user_programmable_START = 0x22011000; +CYMEM_CM33_0_S_user_programmable_C_START = 0x02011000; +CYMEM_CM33_0_S_user_programmable_C_S_START = 0x12011000; +CYMEM_CM33_0_S_user_programmable_S_START = 0x32011000; +CYMEM_CM33_0_S_user_programmable_SIZE = 0x0004A000; +CYMEM_CM33_0_S_user_programmable_OFFSET = 0x00011000; +CYMEM_CM33_0_S_user_nvm_START = 0x2205B000; +CYMEM_CM33_0_S_user_nvm_C_START = 0x0205B000; +CYMEM_CM33_0_S_user_nvm_C_S_START = 0x1205B000; +CYMEM_CM33_0_S_user_nvm_S_START = 0x3205B000; +CYMEM_CM33_0_S_user_nvm_SIZE = 0x00008000; +CYMEM_CM33_0_S_user_nvm_OFFSET = 0x0005B000; +CYMEM_CM33_0_S_m33s_nvm_START = 0x60100000; +CYMEM_CM33_0_S_m33s_nvm_C_START = 0x08100000; +CYMEM_CM33_0_S_m33s_nvm_C_S_START = 0x18100000; +CYMEM_CM33_0_S_m33s_nvm_S_START = 0x70100000; +CYMEM_CM33_0_S_m33s_nvm_SIZE = 0x00200000; +CYMEM_CM33_0_S_m33s_nvm_OFFSET = 0x00100000; +CYMEM_CM33_0_S_m33s_trailer_START = 0x60300000; +CYMEM_CM33_0_S_m33s_trailer_C_START = 0x08300000; +CYMEM_CM33_0_S_m33s_trailer_C_S_START = 0x18300000; +CYMEM_CM33_0_S_m33s_trailer_S_START = 0x70300000; +CYMEM_CM33_0_S_m33s_trailer_SIZE = 0x00040000; +CYMEM_CM33_0_S_m33s_trailer_OFFSET = 0x00300000; +CYMEM_CM33_0_S_m33_nvm_START = 0x60340000; +CYMEM_CM33_0_S_m33_nvm_C_START = 0x08340000; +CYMEM_CM33_0_S_m33_nvm_C_S_START = 0x18340000; +CYMEM_CM33_0_S_m33_nvm_S_START = 0x70340000; +CYMEM_CM33_0_S_m33_nvm_SIZE = 0x00200000; +CYMEM_CM33_0_S_m33_nvm_OFFSET = 0x00340000; +CYMEM_CM33_0_S_m33_trailer_START = 0x60540000; +CYMEM_CM33_0_S_m33_trailer_C_START = 0x08540000; +CYMEM_CM33_0_S_m33_trailer_C_S_START = 0x18540000; +CYMEM_CM33_0_S_m33_trailer_S_START = 0x70540000; +CYMEM_CM33_0_S_m33_trailer_SIZE = 0x00040000; +CYMEM_CM33_0_S_m33_trailer_OFFSET = 0x00540000; +CYMEM_CM33_0_S_m55_nvm_START = 0x60580000; +CYMEM_CM33_0_S_m55_nvm_C_START = 0x08580000; +CYMEM_CM33_0_S_m55_nvm_C_S_START = 0x18580000; +CYMEM_CM33_0_S_m55_nvm_S_START = 0x70580000; +CYMEM_CM33_0_S_m55_nvm_SIZE = 0x002C0000; +CYMEM_CM33_0_S_m55_nvm_OFFSET = 0x00580000; +CYMEM_CM33_0_S_m55_trailer_START = 0x60840000; +CYMEM_CM33_0_S_m55_trailer_C_START = 0x08840000; +CYMEM_CM33_0_S_m55_trailer_C_S_START = 0x18840000; +CYMEM_CM33_0_S_m55_trailer_S_START = 0x70840000; +CYMEM_CM33_0_S_m55_trailer_SIZE = 0x00040000; +CYMEM_CM33_0_S_m55_trailer_OFFSET = 0x00840000; +CYMEM_CM33_0_S_m55_code_secondary_START = 0x26000000; +CYMEM_CM33_0_S_m55_code_secondary_C_START = 0x06000000; +CYMEM_CM33_0_S_m55_code_secondary_C_S_START = 0x16000000; +CYMEM_CM33_0_S_m55_code_secondary_S_START = 0x36000000; +CYMEM_CM33_0_S_m55_code_secondary_SIZE = 0x00040000; +CYMEM_CM33_0_S_m55_code_secondary_OFFSET = 0x00000000; +CYMEM_CM33_0_S_m55_data_secondary_START = 0x26040000; +CYMEM_CM33_0_S_m55_data_secondary_C_START = 0x06040000; +CYMEM_CM33_0_S_m55_data_secondary_C_S_START = 0x16040000; +CYMEM_CM33_0_S_m55_data_secondary_S_START = 0x36040000; +CYMEM_CM33_0_S_m55_data_secondary_SIZE = 0x002BC000; +CYMEM_CM33_0_S_m55_data_secondary_OFFSET = 0x00040000; +CYMEM_CM33_0_S_m33_m55_shared_START = 0x262FC000; +CYMEM_CM33_0_S_m33_m55_shared_C_START = 0x062FC000; +CYMEM_CM33_0_S_m33_m55_shared_C_S_START = 0x162FC000; +CYMEM_CM33_0_S_m33_m55_shared_S_START = 0x362FC000; +CYMEM_CM33_0_S_m33_m55_shared_SIZE = 0x00040000; +CYMEM_CM33_0_S_m33_m55_shared_OFFSET = 0x002FC000; +CYMEM_CM33_0_S_gfx_mem_START = 0x2633C000; +CYMEM_CM33_0_S_gfx_mem_C_START = 0x0633C000; +CYMEM_CM33_0_S_gfx_mem_C_S_START = 0x1633C000; +CYMEM_CM33_0_S_gfx_mem_S_START = 0x3633C000; +CYMEM_CM33_0_S_gfx_mem_SIZE = 0x001C4000; +CYMEM_CM33_0_S_gfx_mem_OFFSET = 0x0033C000; +CYMEM_CM33_0_S_m33s_shared_START = 0x24001000; +CYMEM_CM33_0_S_m33s_shared_C_START = 0x04001000; +CYMEM_CM33_0_S_m33s_shared_C_S_START = 0x14001000; +CYMEM_CM33_0_S_m33s_shared_S_START = 0x34001000; +CYMEM_CM33_0_S_m33s_shared_SIZE = 0x00001000; +CYMEM_CM33_0_S_m33s_shared_OFFSET = 0x00001000; +CYMEM_CM33_0_S_m33s_code_START = 0x24002000; +CYMEM_CM33_0_S_m33s_code_C_START = 0x04002000; +CYMEM_CM33_0_S_m33s_code_C_S_START = 0x14002000; +CYMEM_CM33_0_S_m33s_code_S_START = 0x34002000; +CYMEM_CM33_0_S_m33s_code_SIZE = 0x00035000; +CYMEM_CM33_0_S_m33s_code_OFFSET = 0x00002000; +CYMEM_CM33_0_S_m33s_data_START = 0x24037000; +CYMEM_CM33_0_S_m33s_data_C_START = 0x04037000; +CYMEM_CM33_0_S_m33s_data_C_S_START = 0x14037000; +CYMEM_CM33_0_S_m33s_data_S_START = 0x34037000; +CYMEM_CM33_0_S_m33s_data_SIZE = 0x00021000; +CYMEM_CM33_0_S_m33s_data_OFFSET = 0x00037000; +CYMEM_CM33_0_S_m33_code_START = 0x24058000; +CYMEM_CM33_0_S_m33_code_C_START = 0x04058000; +CYMEM_CM33_0_S_m33_code_C_S_START = 0x14058000; +CYMEM_CM33_0_S_m33_code_S_START = 0x34058000; +CYMEM_CM33_0_S_m33_code_SIZE = 0x00065000; +CYMEM_CM33_0_S_m33_code_OFFSET = 0x00058000; +CYMEM_CM33_0_S_m33_data_START = 0x240BD000; +CYMEM_CM33_0_S_m33_data_C_START = 0x040BD000; +CYMEM_CM33_0_S_m33_data_C_S_START = 0x140BD000; +CYMEM_CM33_0_S_m33_data_S_START = 0x340BD000; +CYMEM_CM33_0_S_m33_data_SIZE = 0x00040000; +CYMEM_CM33_0_S_m33_data_OFFSET = 0x000BD000; +CYMEM_CM33_0_S_m33s_allocatable_shared_START = 0x240FD000; +CYMEM_CM33_0_S_m33s_allocatable_shared_C_START = 0x040FD000; +CYMEM_CM33_0_S_m33s_allocatable_shared_C_S_START = 0x140FD000; +CYMEM_CM33_0_S_m33s_allocatable_shared_S_START = 0x340FD000; +CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM33_0_S_m33s_allocatable_shared_OFFSET = 0x000FD000; +CYMEM_CM33_0_S_m33_allocatable_shared_START = 0x240FE000; +CYMEM_CM33_0_S_m33_allocatable_shared_C_START = 0x040FE000; +CYMEM_CM33_0_S_m33_allocatable_shared_C_S_START = 0x140FE000; +CYMEM_CM33_0_S_m33_allocatable_shared_S_START = 0x340FE000; +CYMEM_CM33_0_S_m33_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM33_0_S_m33_allocatable_shared_OFFSET = 0x000FE000; +CYMEM_CM33_0_S_m55_allocatable_shared_START = 0x240FF000; +CYMEM_CM33_0_S_m55_allocatable_shared_C_START = 0x040FF000; +CYMEM_CM33_0_S_m55_allocatable_shared_C_S_START = 0x140FF000; +CYMEM_CM33_0_S_m55_allocatable_shared_S_START = 0x340FF000; +CYMEM_CM33_0_S_m55_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM33_0_S_m55_allocatable_shared_OFFSET = 0x000FF000; + +MEMORY +{ + m55_data : ORIGIN = 0x48040000, LENGTH = 0x00040000 + m55_data_S : ORIGIN = 0x58040000, LENGTH = 0x00040000 + m55_code : ORIGIN = 0x48000000, LENGTH = 0x00040000 + m55_code_S : ORIGIN = 0x58000000, LENGTH = 0x00040000 + user_programmable : ORIGIN = 0x22011000, LENGTH = 0x0004A000 + user_programmable_C : ORIGIN = 0x02011000, LENGTH = 0x0004A000 + user_programmable_C_S : ORIGIN = 0x12011000, LENGTH = 0x0004A000 + user_programmable_S : ORIGIN = 0x32011000, LENGTH = 0x0004A000 + user_nvm : ORIGIN = 0x2205B000, LENGTH = 0x00008000 + user_nvm_C : ORIGIN = 0x0205B000, LENGTH = 0x00008000 + user_nvm_C_S : ORIGIN = 0x1205B000, LENGTH = 0x00008000 + user_nvm_S : ORIGIN = 0x3205B000, LENGTH = 0x00008000 + m33s_nvm : ORIGIN = 0x60100000, LENGTH = 0x00200000 + m33s_nvm_C : ORIGIN = 0x08100000, LENGTH = 0x00200000 + m33s_nvm_C_S : ORIGIN = 0x18100000, LENGTH = 0x00200000 + m33s_nvm_S : ORIGIN = 0x70100000, LENGTH = 0x00200000 + m33s_trailer : ORIGIN = 0x60300000, LENGTH = 0x00040000 + m33s_trailer_C : ORIGIN = 0x08300000, LENGTH = 0x00040000 + m33s_trailer_C_S : ORIGIN = 0x18300000, LENGTH = 0x00040000 + m33s_trailer_S : ORIGIN = 0x70300000, LENGTH = 0x00040000 + m33_nvm : ORIGIN = 0x60340000, LENGTH = 0x00200000 + m33_nvm_C : ORIGIN = 0x08340000, LENGTH = 0x00200000 + m33_nvm_C_S : ORIGIN = 0x18340000, LENGTH = 0x00200000 + m33_nvm_S : ORIGIN = 0x70340000, LENGTH = 0x00200000 + m33_trailer : ORIGIN = 0x60540000, LENGTH = 0x00040000 + m33_trailer_C : ORIGIN = 0x08540000, LENGTH = 0x00040000 + m33_trailer_C_S : ORIGIN = 0x18540000, LENGTH = 0x00040000 + m33_trailer_S : ORIGIN = 0x70540000, LENGTH = 0x00040000 + m55_nvm : ORIGIN = 0x60580000, LENGTH = 0x002C0000 + m55_nvm_C : ORIGIN = 0x08580000, LENGTH = 0x002C0000 + m55_nvm_C_S : ORIGIN = 0x18580000, LENGTH = 0x002C0000 + m55_nvm_S : ORIGIN = 0x70580000, LENGTH = 0x002C0000 + m55_trailer : ORIGIN = 0x60840000, LENGTH = 0x00040000 + m55_trailer_C : ORIGIN = 0x08840000, LENGTH = 0x00040000 + m55_trailer_C_S : ORIGIN = 0x18840000, LENGTH = 0x00040000 + m55_trailer_S : ORIGIN = 0x70840000, LENGTH = 0x00040000 + m55_code_secondary : ORIGIN = 0x26000000, LENGTH = 0x00040000 + m55_code_secondary_C : ORIGIN = 0x06000000, LENGTH = 0x00040000 + m55_code_secondary_C_S : ORIGIN = 0x16000000, LENGTH = 0x00040000 + m55_code_secondary_S : ORIGIN = 0x36000000, LENGTH = 0x00040000 + m55_data_secondary : ORIGIN = 0x26040000, LENGTH = 0x002BC000 + m55_data_secondary_C : ORIGIN = 0x06040000, LENGTH = 0x002BC000 + m55_data_secondary_C_S : ORIGIN = 0x16040000, LENGTH = 0x002BC000 + m55_data_secondary_S : ORIGIN = 0x36040000, LENGTH = 0x002BC000 + m33_m55_shared : ORIGIN = 0x262FC000, LENGTH = 0x00040000 + m33_m55_shared_C : ORIGIN = 0x062FC000, LENGTH = 0x00040000 + m33_m55_shared_C_S : ORIGIN = 0x162FC000, LENGTH = 0x00040000 + m33_m55_shared_S : ORIGIN = 0x362FC000, LENGTH = 0x00040000 + gfx_mem : ORIGIN = 0x2633C000, LENGTH = 0x001C4000 + gfx_mem_C : ORIGIN = 0x0633C000, LENGTH = 0x001C4000 + gfx_mem_C_S : ORIGIN = 0x1633C000, LENGTH = 0x001C4000 + gfx_mem_S : ORIGIN = 0x3633C000, LENGTH = 0x001C4000 + m33s_shared : ORIGIN = 0x24001000, LENGTH = 0x00001000 + m33s_shared_C : ORIGIN = 0x04001000, LENGTH = 0x00001000 + m33s_shared_C_S : ORIGIN = 0x14001000, LENGTH = 0x00001000 + m33s_shared_S : ORIGIN = 0x34001000, LENGTH = 0x00001000 + m33s_code : ORIGIN = 0x24002000, LENGTH = 0x00035000 + m33s_code_C : ORIGIN = 0x04002000, LENGTH = 0x00035000 + m33s_code_C_S : ORIGIN = 0x14002000, LENGTH = 0x00035000 + m33s_code_S : ORIGIN = 0x34002000, LENGTH = 0x00035000 + m33s_data : ORIGIN = 0x24037000, LENGTH = 0x00021000 + m33s_data_C : ORIGIN = 0x04037000, LENGTH = 0x00021000 + m33s_data_C_S : ORIGIN = 0x14037000, LENGTH = 0x00021000 + m33s_data_S : ORIGIN = 0x34037000, LENGTH = 0x00021000 + m33_code : ORIGIN = 0x24058000, LENGTH = 0x00065000 + m33_code_C : ORIGIN = 0x04058000, LENGTH = 0x00065000 + m33_code_C_S : ORIGIN = 0x14058000, LENGTH = 0x00065000 + m33_code_S : ORIGIN = 0x34058000, LENGTH = 0x00065000 + m33_data : ORIGIN = 0x240BD000, LENGTH = 0x00040000 + m33_data_C : ORIGIN = 0x040BD000, LENGTH = 0x00040000 + m33_data_C_S : ORIGIN = 0x140BD000, LENGTH = 0x00040000 + m33_data_S : ORIGIN = 0x340BD000, LENGTH = 0x00040000 + m33s_allocatable_shared : ORIGIN = 0x240FD000, LENGTH = 0x00001000 + m33s_allocatable_shared_C : ORIGIN = 0x040FD000, LENGTH = 0x00001000 + m33s_allocatable_shared_C_S : ORIGIN = 0x140FD000, LENGTH = 0x00001000 + m33s_allocatable_shared_S : ORIGIN = 0x340FD000, LENGTH = 0x00001000 + m33_allocatable_shared : ORIGIN = 0x240FE000, LENGTH = 0x00001000 + m33_allocatable_shared_C : ORIGIN = 0x040FE000, LENGTH = 0x00001000 + m33_allocatable_shared_C_S : ORIGIN = 0x140FE000, LENGTH = 0x00001000 + m33_allocatable_shared_S : ORIGIN = 0x340FE000, LENGTH = 0x00001000 + m55_allocatable_shared : ORIGIN = 0x240FF000, LENGTH = 0x00001000 + m55_allocatable_shared_C : ORIGIN = 0x040FF000, LENGTH = 0x00001000 + m55_allocatable_shared_C_S : ORIGIN = 0x140FF000, LENGTH = 0x00001000 + m55_allocatable_shared_S : ORIGIN = 0x340FF000, LENGTH = 0x00001000 +} + +REGION_ALIAS("m55_data_sel", m55_data) +REGION_ALIAS("m55_data_sel_S", m55_data_S) +REGION_ALIAS("m55_code_sel", m55_code) +REGION_ALIAS("m55_code_sel_S", m55_code_S) +REGION_ALIAS("user_programmable_sel", user_programmable_C) +REGION_ALIAS("user_programmable_sel_S", user_programmable_C_S) +REGION_ALIAS("user_nvm_sel", user_nvm_C) +REGION_ALIAS("user_nvm_sel_S", user_nvm_C_S) +REGION_ALIAS("m33s_nvm_sel", m33s_nvm_C) +REGION_ALIAS("m33s_nvm_sel_S", m33s_nvm_C_S) +REGION_ALIAS("m33s_trailer_sel", m33s_trailer_C) +REGION_ALIAS("m33s_trailer_sel_S", m33s_trailer_C_S) +REGION_ALIAS("m33_nvm_sel", m33_nvm_C) +REGION_ALIAS("m33_nvm_sel_S", m33_nvm_C_S) +REGION_ALIAS("m33_trailer_sel", m33_trailer_C) +REGION_ALIAS("m33_trailer_sel_S", m33_trailer_C_S) +REGION_ALIAS("m55_nvm_sel", m55_nvm_C) +REGION_ALIAS("m55_nvm_sel_S", m55_nvm_C_S) +REGION_ALIAS("m55_trailer_sel", m55_trailer_C) +REGION_ALIAS("m55_trailer_sel_S", m55_trailer_C_S) +REGION_ALIAS("m55_code_secondary_sel", m55_code_secondary_C) +REGION_ALIAS("m55_code_secondary_sel_S", m55_code_secondary_C_S) +REGION_ALIAS("m55_data_secondary_sel", m55_data_secondary_C) +REGION_ALIAS("m55_data_secondary_sel_S", m55_data_secondary_C_S) +REGION_ALIAS("m33_m55_shared_sel", m33_m55_shared_C) +REGION_ALIAS("m33_m55_shared_sel_S", m33_m55_shared_C_S) +REGION_ALIAS("gfx_mem_sel", gfx_mem_C) +REGION_ALIAS("gfx_mem_sel_S", gfx_mem_C_S) +REGION_ALIAS("m33s_shared_sel", m33s_shared_C) +REGION_ALIAS("m33s_shared_sel_S", m33s_shared_C_S) +REGION_ALIAS("m33s_code_sel", m33s_code_C) +REGION_ALIAS("m33s_code_sel_S", m33s_code_C_S) +REGION_ALIAS("m33s_data_sel", m33s_data_C) +REGION_ALIAS("m33s_data_sel_S", m33s_data_C_S) +REGION_ALIAS("m33_code_sel", m33_code_C) +REGION_ALIAS("m33_code_sel_S", m33_code_C_S) +REGION_ALIAS("m33_data_sel", m33_data_C) +REGION_ALIAS("m33_data_sel_S", m33_data_C_S) +REGION_ALIAS("m33s_allocatable_shared_sel", m33s_allocatable_shared_C) +REGION_ALIAS("m33s_allocatable_shared_sel_S", m33s_allocatable_shared_C_S) +REGION_ALIAS("m33_allocatable_shared_sel", m33_allocatable_shared_C) +REGION_ALIAS("m33_allocatable_shared_sel_S", m33_allocatable_shared_C_S) +REGION_ALIAS("m55_allocatable_shared_sel", m55_allocatable_shared_C) +REGION_ALIAS("m55_allocatable_shared_sel_S", m55_allocatable_shared_C_S) diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM55_0.ld b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM55_0.ld new file mode 100644 index 00000000000..14f631ec105 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_gnu_CM55_0.ld @@ -0,0 +1,72 @@ +/* This file is automatically generated. */ + +CYMEM_CM55_0_m55_data_INTERNAL_START = 0x20000000; +CYMEM_CM55_0_m55_data_SIZE = 0x00040000; +CYMEM_CM55_0_m55_data_OFFSET = 0x00000000; +CYMEM_CM55_0_m55_code_INTERNAL_START = 0x00000000; +CYMEM_CM55_0_m55_code_SIZE = 0x00040000; +CYMEM_CM55_0_m55_code_OFFSET = 0x00000000; +CYMEM_CM55_0_user_nvm_C_START = 0x0205B000; +CYMEM_CM55_0_user_nvm_SIZE = 0x00008000; +CYMEM_CM55_0_user_nvm_OFFSET = 0x0005B000; +CYMEM_CM55_0_m55_nvm_START = 0x60580000; +CYMEM_CM55_0_m55_nvm_SIZE = 0x002C0000; +CYMEM_CM55_0_m55_nvm_OFFSET = 0x00580000; +CYMEM_CM55_0_m55_trailer_START = 0x60840000; +CYMEM_CM55_0_m55_trailer_SIZE = 0x00040000; +CYMEM_CM55_0_m55_trailer_OFFSET = 0x00840000; +CYMEM_CM55_0_m55_code_secondary_START = 0x26000000; +CYMEM_CM55_0_m55_code_secondary_SIZE = 0x00040000; +CYMEM_CM55_0_m55_code_secondary_OFFSET = 0x00000000; +CYMEM_CM55_0_m55_data_secondary_START = 0x26040000; +CYMEM_CM55_0_m55_data_secondary_SIZE = 0x002BC000; +CYMEM_CM55_0_m55_data_secondary_OFFSET = 0x00040000; +CYMEM_CM55_0_m33_m55_shared_START = 0x262FC000; +CYMEM_CM55_0_m33_m55_shared_SIZE = 0x00040000; +CYMEM_CM55_0_m33_m55_shared_OFFSET = 0x002FC000; +CYMEM_CM55_0_gfx_mem_START = 0x2633C000; +CYMEM_CM55_0_gfx_mem_SIZE = 0x001C4000; +CYMEM_CM55_0_gfx_mem_OFFSET = 0x0033C000; +CYMEM_CM55_0_m33_data_START = 0x240BD000; +CYMEM_CM55_0_m33_data_SIZE = 0x00040000; +CYMEM_CM55_0_m33_data_OFFSET = 0x000BD000; +CYMEM_CM55_0_m33s_allocatable_shared_START = 0x240FD000; +CYMEM_CM55_0_m33s_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM55_0_m33s_allocatable_shared_OFFSET = 0x000FD000; +CYMEM_CM55_0_m33_allocatable_shared_START = 0x240FE000; +CYMEM_CM55_0_m33_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM55_0_m33_allocatable_shared_OFFSET = 0x000FE000; +CYMEM_CM55_0_m55_allocatable_shared_START = 0x240FF000; +CYMEM_CM55_0_m55_allocatable_shared_SIZE = 0x00001000; +CYMEM_CM55_0_m55_allocatable_shared_OFFSET = 0x000FF000; + +MEMORY +{ + m55_data_INTERNAL : ORIGIN = 0x20000000, LENGTH = 0x00040000 + m55_code_INTERNAL : ORIGIN = 0x00000000, LENGTH = 0x00040000 + user_nvm_C : ORIGIN = 0x0205B000, LENGTH = 0x00008000 + m55_nvm : ORIGIN = 0x60580000, LENGTH = 0x002C0000 + m55_trailer : ORIGIN = 0x60840000, LENGTH = 0x00040000 + m55_code_secondary : ORIGIN = 0x26000000, LENGTH = 0x00040000 + m55_data_secondary : ORIGIN = 0x26040000, LENGTH = 0x002BC000 + m33_m55_shared : ORIGIN = 0x262FC000, LENGTH = 0x00040000 + gfx_mem : ORIGIN = 0x2633C000, LENGTH = 0x001C4000 + m33_data : ORIGIN = 0x240BD000, LENGTH = 0x00040000 + m33s_allocatable_shared : ORIGIN = 0x240FD000, LENGTH = 0x00001000 + m33_allocatable_shared : ORIGIN = 0x240FE000, LENGTH = 0x00001000 + m55_allocatable_shared : ORIGIN = 0x240FF000, LENGTH = 0x00001000 +} + +REGION_ALIAS("m55_data_sel", m55_data_INTERNAL) +REGION_ALIAS("m55_code_sel", m55_code_INTERNAL) +REGION_ALIAS("user_nvm_sel", user_nvm_C) +REGION_ALIAS("m55_nvm_sel", m55_nvm) +REGION_ALIAS("m55_trailer_sel", m55_trailer) +REGION_ALIAS("m55_code_secondary_sel", m55_code_secondary) +REGION_ALIAS("m55_data_secondary_sel", m55_data_secondary) +REGION_ALIAS("m33_m55_shared_sel", m33_m55_shared) +REGION_ALIAS("gfx_mem_sel", gfx_mem) +REGION_ALIAS("m33_data_sel", m33_data) +REGION_ALIAS("m33s_allocatable_shared_sel", m33s_allocatable_shared) +REGION_ALIAS("m33_allocatable_shared_sel", m33_allocatable_shared) +REGION_ALIAS("m55_allocatable_shared_sel", m55_allocatable_shared) diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM33_0.icf b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM33_0.icf new file mode 100644 index 00000000000..d988272a7e9 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM33_0.icf @@ -0,0 +1,109 @@ +// This file is automatically generated. +define exported symbol CYMEM_CM33_0_m55_data_START = 0x48040000; +define exported symbol CYMEM_CM33_0_m55_data_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_m55_data_OFFSET = 0x00000000; +define exported symbol CYMEM_CM33_0_m55_data_sel_START = CYMEM_CM33_0_m55_data_START; +define exported symbol CYMEM_CM33_0_m55_code_START = 0x48000000; +define exported symbol CYMEM_CM33_0_m55_code_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_m55_code_OFFSET = 0x00000000; +define exported symbol CYMEM_CM33_0_m55_code_sel_START = CYMEM_CM33_0_m55_code_START; +define exported symbol CYMEM_CM33_0_user_programmable_START = 0x22011000; +define exported symbol CYMEM_CM33_0_user_programmable_C_START = 0x02011000; +define exported symbol CYMEM_CM33_0_user_programmable_SIZE = 0x0004A000; +define exported symbol CYMEM_CM33_0_user_programmable_OFFSET = 0x00011000; +define exported symbol CYMEM_CM33_0_user_programmable_sel_START = CYMEM_CM33_0_user_programmable_C_START; +define exported symbol CYMEM_CM33_0_user_nvm_START = 0x2205B000; +define exported symbol CYMEM_CM33_0_user_nvm_C_START = 0x0205B000; +define exported symbol CYMEM_CM33_0_user_nvm_SIZE = 0x00008000; +define exported symbol CYMEM_CM33_0_user_nvm_OFFSET = 0x0005B000; +define exported symbol CYMEM_CM33_0_user_nvm_sel_START = CYMEM_CM33_0_user_nvm_C_START; +define exported symbol CYMEM_CM33_0_m33s_nvm_START = 0x60100000; +define exported symbol CYMEM_CM33_0_m33s_nvm_C_START = 0x08100000; +define exported symbol CYMEM_CM33_0_m33s_nvm_SIZE = 0x00200000; +define exported symbol CYMEM_CM33_0_m33s_nvm_OFFSET = 0x00100000; +define exported symbol CYMEM_CM33_0_m33s_nvm_sel_START = CYMEM_CM33_0_m33s_nvm_C_START; +define exported symbol CYMEM_CM33_0_m33s_trailer_START = 0x60300000; +define exported symbol CYMEM_CM33_0_m33s_trailer_C_START = 0x08300000; +define exported symbol CYMEM_CM33_0_m33s_trailer_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_m33s_trailer_OFFSET = 0x00300000; +define exported symbol CYMEM_CM33_0_m33s_trailer_sel_START = CYMEM_CM33_0_m33s_trailer_C_START; +define exported symbol CYMEM_CM33_0_m33_nvm_START = 0x60340000; +define exported symbol CYMEM_CM33_0_m33_nvm_C_START = 0x08340000; +define exported symbol CYMEM_CM33_0_m33_nvm_SIZE = 0x00200000; +define exported symbol CYMEM_CM33_0_m33_nvm_OFFSET = 0x00340000; +define exported symbol CYMEM_CM33_0_m33_nvm_sel_START = CYMEM_CM33_0_m33_nvm_C_START; +define exported symbol CYMEM_CM33_0_m33_trailer_START = 0x60540000; +define exported symbol CYMEM_CM33_0_m33_trailer_C_START = 0x08540000; +define exported symbol CYMEM_CM33_0_m33_trailer_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_m33_trailer_OFFSET = 0x00540000; +define exported symbol CYMEM_CM33_0_m33_trailer_sel_START = CYMEM_CM33_0_m33_trailer_C_START; +define exported symbol CYMEM_CM33_0_m55_nvm_START = 0x60580000; +define exported symbol CYMEM_CM33_0_m55_nvm_C_START = 0x08580000; +define exported symbol CYMEM_CM33_0_m55_nvm_SIZE = 0x002C0000; +define exported symbol CYMEM_CM33_0_m55_nvm_OFFSET = 0x00580000; +define exported symbol CYMEM_CM33_0_m55_nvm_sel_START = CYMEM_CM33_0_m55_nvm_C_START; +define exported symbol CYMEM_CM33_0_m55_trailer_START = 0x60840000; +define exported symbol CYMEM_CM33_0_m55_trailer_C_START = 0x08840000; +define exported symbol CYMEM_CM33_0_m55_trailer_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_m55_trailer_OFFSET = 0x00840000; +define exported symbol CYMEM_CM33_0_m55_trailer_sel_START = CYMEM_CM33_0_m55_trailer_C_START; +define exported symbol CYMEM_CM33_0_m55_code_secondary_START = 0x26000000; +define exported symbol CYMEM_CM33_0_m55_code_secondary_C_START = 0x06000000; +define exported symbol CYMEM_CM33_0_m55_code_secondary_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_m55_code_secondary_OFFSET = 0x00000000; +define exported symbol CYMEM_CM33_0_m55_code_secondary_sel_START = CYMEM_CM33_0_m55_code_secondary_C_START; +define exported symbol CYMEM_CM33_0_m55_data_secondary_START = 0x26040000; +define exported symbol CYMEM_CM33_0_m55_data_secondary_C_START = 0x06040000; +define exported symbol CYMEM_CM33_0_m55_data_secondary_SIZE = 0x002BC000; +define exported symbol CYMEM_CM33_0_m55_data_secondary_OFFSET = 0x00040000; +define exported symbol CYMEM_CM33_0_m55_data_secondary_sel_START = CYMEM_CM33_0_m55_data_secondary_C_START; +define exported symbol CYMEM_CM33_0_m33_m55_shared_START = 0x262FC000; +define exported symbol CYMEM_CM33_0_m33_m55_shared_C_START = 0x062FC000; +define exported symbol CYMEM_CM33_0_m33_m55_shared_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_m33_m55_shared_OFFSET = 0x002FC000; +define exported symbol CYMEM_CM33_0_m33_m55_shared_sel_START = CYMEM_CM33_0_m33_m55_shared_C_START; +define exported symbol CYMEM_CM33_0_gfx_mem_START = 0x2633C000; +define exported symbol CYMEM_CM33_0_gfx_mem_C_START = 0x0633C000; +define exported symbol CYMEM_CM33_0_gfx_mem_SIZE = 0x001C4000; +define exported symbol CYMEM_CM33_0_gfx_mem_OFFSET = 0x0033C000; +define exported symbol CYMEM_CM33_0_gfx_mem_sel_START = CYMEM_CM33_0_gfx_mem_C_START; +define exported symbol CYMEM_CM33_0_m33s_shared_START = 0x24001000; +define exported symbol CYMEM_CM33_0_m33s_shared_C_START = 0x04001000; +define exported symbol CYMEM_CM33_0_m33s_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM33_0_m33s_shared_OFFSET = 0x00001000; +define exported symbol CYMEM_CM33_0_m33s_shared_sel_START = CYMEM_CM33_0_m33s_shared_C_START; +define exported symbol CYMEM_CM33_0_m33s_code_START = 0x24002000; +define exported symbol CYMEM_CM33_0_m33s_code_C_START = 0x04002000; +define exported symbol CYMEM_CM33_0_m33s_code_SIZE = 0x00035000; +define exported symbol CYMEM_CM33_0_m33s_code_OFFSET = 0x00002000; +define exported symbol CYMEM_CM33_0_m33s_code_sel_START = CYMEM_CM33_0_m33s_code_C_START; +define exported symbol CYMEM_CM33_0_m33s_data_START = 0x24037000; +define exported symbol CYMEM_CM33_0_m33s_data_C_START = 0x04037000; +define exported symbol CYMEM_CM33_0_m33s_data_SIZE = 0x00021000; +define exported symbol CYMEM_CM33_0_m33s_data_OFFSET = 0x00037000; +define exported symbol CYMEM_CM33_0_m33s_data_sel_START = CYMEM_CM33_0_m33s_data_C_START; +define exported symbol CYMEM_CM33_0_m33_code_START = 0x24058000; +define exported symbol CYMEM_CM33_0_m33_code_C_START = 0x04058000; +define exported symbol CYMEM_CM33_0_m33_code_SIZE = 0x00065000; +define exported symbol CYMEM_CM33_0_m33_code_OFFSET = 0x00058000; +define exported symbol CYMEM_CM33_0_m33_code_sel_START = CYMEM_CM33_0_m33_code_C_START; +define exported symbol CYMEM_CM33_0_m33_data_START = 0x240BD000; +define exported symbol CYMEM_CM33_0_m33_data_C_START = 0x040BD000; +define exported symbol CYMEM_CM33_0_m33_data_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_m33_data_OFFSET = 0x000BD000; +define exported symbol CYMEM_CM33_0_m33_data_sel_START = CYMEM_CM33_0_m33_data_C_START; +define exported symbol CYMEM_CM33_0_m33s_allocatable_shared_START = 0x240FD000; +define exported symbol CYMEM_CM33_0_m33s_allocatable_shared_C_START = 0x040FD000; +define exported symbol CYMEM_CM33_0_m33s_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM33_0_m33s_allocatable_shared_OFFSET = 0x000FD000; +define exported symbol CYMEM_CM33_0_m33s_allocatable_shared_sel_START = CYMEM_CM33_0_m33s_allocatable_shared_C_START; +define exported symbol CYMEM_CM33_0_m33_allocatable_shared_START = 0x240FE000; +define exported symbol CYMEM_CM33_0_m33_allocatable_shared_C_START = 0x040FE000; +define exported symbol CYMEM_CM33_0_m33_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM33_0_m33_allocatable_shared_OFFSET = 0x000FE000; +define exported symbol CYMEM_CM33_0_m33_allocatable_shared_sel_START = CYMEM_CM33_0_m33_allocatable_shared_C_START; +define exported symbol CYMEM_CM33_0_m55_allocatable_shared_START = 0x240FF000; +define exported symbol CYMEM_CM33_0_m55_allocatable_shared_C_START = 0x040FF000; +define exported symbol CYMEM_CM33_0_m55_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM33_0_m55_allocatable_shared_OFFSET = 0x000FF000; +define exported symbol CYMEM_CM33_0_m55_allocatable_shared_sel_START = CYMEM_CM33_0_m55_allocatable_shared_C_START; diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM33_0_S.icf b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM33_0_S.icf new file mode 100644 index 00000000000..1d6f82dbeff --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM33_0_S.icf @@ -0,0 +1,173 @@ +// This file is automatically generated. +define exported symbol CYMEM_CM33_0_S_m55_data_START = 0x48040000; +define exported symbol CYMEM_CM33_0_S_m55_data_S_START = 0x58040000; +define exported symbol CYMEM_CM33_0_S_m55_data_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m55_data_OFFSET = 0x00000000; +define exported symbol CYMEM_CM33_0_S_m55_data_sel_START = CYMEM_CM33_0_S_m55_data_START; +define exported symbol CYMEM_CM33_0_S_m55_data_sel_S_START = CYMEM_CM33_0_S_m55_data_S_START; +define exported symbol CYMEM_CM33_0_S_m55_code_START = 0x48000000; +define exported symbol CYMEM_CM33_0_S_m55_code_S_START = 0x58000000; +define exported symbol CYMEM_CM33_0_S_m55_code_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m55_code_OFFSET = 0x00000000; +define exported symbol CYMEM_CM33_0_S_m55_code_sel_START = CYMEM_CM33_0_S_m55_code_START; +define exported symbol CYMEM_CM33_0_S_m55_code_sel_S_START = CYMEM_CM33_0_S_m55_code_S_START; +define exported symbol CYMEM_CM33_0_S_user_programmable_START = 0x22011000; +define exported symbol CYMEM_CM33_0_S_user_programmable_C_START = 0x02011000; +define exported symbol CYMEM_CM33_0_S_user_programmable_C_S_START = 0x12011000; +define exported symbol CYMEM_CM33_0_S_user_programmable_S_START = 0x32011000; +define exported symbol CYMEM_CM33_0_S_user_programmable_SIZE = 0x0004A000; +define exported symbol CYMEM_CM33_0_S_user_programmable_OFFSET = 0x00011000; +define exported symbol CYMEM_CM33_0_S_user_programmable_sel_START = CYMEM_CM33_0_S_user_programmable_C_START; +define exported symbol CYMEM_CM33_0_S_user_programmable_sel_S_START = CYMEM_CM33_0_S_user_programmable_C_S_START; +define exported symbol CYMEM_CM33_0_S_user_nvm_START = 0x2205B000; +define exported symbol CYMEM_CM33_0_S_user_nvm_C_START = 0x0205B000; +define exported symbol CYMEM_CM33_0_S_user_nvm_C_S_START = 0x1205B000; +define exported symbol CYMEM_CM33_0_S_user_nvm_S_START = 0x3205B000; +define exported symbol CYMEM_CM33_0_S_user_nvm_SIZE = 0x00008000; +define exported symbol CYMEM_CM33_0_S_user_nvm_OFFSET = 0x0005B000; +define exported symbol CYMEM_CM33_0_S_user_nvm_sel_START = CYMEM_CM33_0_S_user_nvm_C_START; +define exported symbol CYMEM_CM33_0_S_user_nvm_sel_S_START = CYMEM_CM33_0_S_user_nvm_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33s_nvm_START = 0x60100000; +define exported symbol CYMEM_CM33_0_S_m33s_nvm_C_START = 0x08100000; +define exported symbol CYMEM_CM33_0_S_m33s_nvm_C_S_START = 0x18100000; +define exported symbol CYMEM_CM33_0_S_m33s_nvm_S_START = 0x70100000; +define exported symbol CYMEM_CM33_0_S_m33s_nvm_SIZE = 0x00200000; +define exported symbol CYMEM_CM33_0_S_m33s_nvm_OFFSET = 0x00100000; +define exported symbol CYMEM_CM33_0_S_m33s_nvm_sel_START = CYMEM_CM33_0_S_m33s_nvm_C_START; +define exported symbol CYMEM_CM33_0_S_m33s_nvm_sel_S_START = CYMEM_CM33_0_S_m33s_nvm_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33s_trailer_START = 0x60300000; +define exported symbol CYMEM_CM33_0_S_m33s_trailer_C_START = 0x08300000; +define exported symbol CYMEM_CM33_0_S_m33s_trailer_C_S_START = 0x18300000; +define exported symbol CYMEM_CM33_0_S_m33s_trailer_S_START = 0x70300000; +define exported symbol CYMEM_CM33_0_S_m33s_trailer_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m33s_trailer_OFFSET = 0x00300000; +define exported symbol CYMEM_CM33_0_S_m33s_trailer_sel_START = CYMEM_CM33_0_S_m33s_trailer_C_START; +define exported symbol CYMEM_CM33_0_S_m33s_trailer_sel_S_START = CYMEM_CM33_0_S_m33s_trailer_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33_nvm_START = 0x60340000; +define exported symbol CYMEM_CM33_0_S_m33_nvm_C_START = 0x08340000; +define exported symbol CYMEM_CM33_0_S_m33_nvm_C_S_START = 0x18340000; +define exported symbol CYMEM_CM33_0_S_m33_nvm_S_START = 0x70340000; +define exported symbol CYMEM_CM33_0_S_m33_nvm_SIZE = 0x00200000; +define exported symbol CYMEM_CM33_0_S_m33_nvm_OFFSET = 0x00340000; +define exported symbol CYMEM_CM33_0_S_m33_nvm_sel_START = CYMEM_CM33_0_S_m33_nvm_C_START; +define exported symbol CYMEM_CM33_0_S_m33_nvm_sel_S_START = CYMEM_CM33_0_S_m33_nvm_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33_trailer_START = 0x60540000; +define exported symbol CYMEM_CM33_0_S_m33_trailer_C_START = 0x08540000; +define exported symbol CYMEM_CM33_0_S_m33_trailer_C_S_START = 0x18540000; +define exported symbol CYMEM_CM33_0_S_m33_trailer_S_START = 0x70540000; +define exported symbol CYMEM_CM33_0_S_m33_trailer_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m33_trailer_OFFSET = 0x00540000; +define exported symbol CYMEM_CM33_0_S_m33_trailer_sel_START = CYMEM_CM33_0_S_m33_trailer_C_START; +define exported symbol CYMEM_CM33_0_S_m33_trailer_sel_S_START = CYMEM_CM33_0_S_m33_trailer_C_S_START; +define exported symbol CYMEM_CM33_0_S_m55_nvm_START = 0x60580000; +define exported symbol CYMEM_CM33_0_S_m55_nvm_C_START = 0x08580000; +define exported symbol CYMEM_CM33_0_S_m55_nvm_C_S_START = 0x18580000; +define exported symbol CYMEM_CM33_0_S_m55_nvm_S_START = 0x70580000; +define exported symbol CYMEM_CM33_0_S_m55_nvm_SIZE = 0x002C0000; +define exported symbol CYMEM_CM33_0_S_m55_nvm_OFFSET = 0x00580000; +define exported symbol CYMEM_CM33_0_S_m55_nvm_sel_START = CYMEM_CM33_0_S_m55_nvm_C_START; +define exported symbol CYMEM_CM33_0_S_m55_nvm_sel_S_START = CYMEM_CM33_0_S_m55_nvm_C_S_START; +define exported symbol CYMEM_CM33_0_S_m55_trailer_START = 0x60840000; +define exported symbol CYMEM_CM33_0_S_m55_trailer_C_START = 0x08840000; +define exported symbol CYMEM_CM33_0_S_m55_trailer_C_S_START = 0x18840000; +define exported symbol CYMEM_CM33_0_S_m55_trailer_S_START = 0x70840000; +define exported symbol CYMEM_CM33_0_S_m55_trailer_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m55_trailer_OFFSET = 0x00840000; +define exported symbol CYMEM_CM33_0_S_m55_trailer_sel_START = CYMEM_CM33_0_S_m55_trailer_C_START; +define exported symbol CYMEM_CM33_0_S_m55_trailer_sel_S_START = CYMEM_CM33_0_S_m55_trailer_C_S_START; +define exported symbol CYMEM_CM33_0_S_m55_code_secondary_START = 0x26000000; +define exported symbol CYMEM_CM33_0_S_m55_code_secondary_C_START = 0x06000000; +define exported symbol CYMEM_CM33_0_S_m55_code_secondary_C_S_START = 0x16000000; +define exported symbol CYMEM_CM33_0_S_m55_code_secondary_S_START = 0x36000000; +define exported symbol CYMEM_CM33_0_S_m55_code_secondary_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m55_code_secondary_OFFSET = 0x00000000; +define exported symbol CYMEM_CM33_0_S_m55_code_secondary_sel_START = CYMEM_CM33_0_S_m55_code_secondary_C_START; +define exported symbol CYMEM_CM33_0_S_m55_code_secondary_sel_S_START = CYMEM_CM33_0_S_m55_code_secondary_C_S_START; +define exported symbol CYMEM_CM33_0_S_m55_data_secondary_START = 0x26040000; +define exported symbol CYMEM_CM33_0_S_m55_data_secondary_C_START = 0x06040000; +define exported symbol CYMEM_CM33_0_S_m55_data_secondary_C_S_START = 0x16040000; +define exported symbol CYMEM_CM33_0_S_m55_data_secondary_S_START = 0x36040000; +define exported symbol CYMEM_CM33_0_S_m55_data_secondary_SIZE = 0x002BC000; +define exported symbol CYMEM_CM33_0_S_m55_data_secondary_OFFSET = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m55_data_secondary_sel_START = CYMEM_CM33_0_S_m55_data_secondary_C_START; +define exported symbol CYMEM_CM33_0_S_m55_data_secondary_sel_S_START = CYMEM_CM33_0_S_m55_data_secondary_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33_m55_shared_START = 0x262FC000; +define exported symbol CYMEM_CM33_0_S_m33_m55_shared_C_START = 0x062FC000; +define exported symbol CYMEM_CM33_0_S_m33_m55_shared_C_S_START = 0x162FC000; +define exported symbol CYMEM_CM33_0_S_m33_m55_shared_S_START = 0x362FC000; +define exported symbol CYMEM_CM33_0_S_m33_m55_shared_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m33_m55_shared_OFFSET = 0x002FC000; +define exported symbol CYMEM_CM33_0_S_m33_m55_shared_sel_START = CYMEM_CM33_0_S_m33_m55_shared_C_START; +define exported symbol CYMEM_CM33_0_S_m33_m55_shared_sel_S_START = CYMEM_CM33_0_S_m33_m55_shared_C_S_START; +define exported symbol CYMEM_CM33_0_S_gfx_mem_START = 0x2633C000; +define exported symbol CYMEM_CM33_0_S_gfx_mem_C_START = 0x0633C000; +define exported symbol CYMEM_CM33_0_S_gfx_mem_C_S_START = 0x1633C000; +define exported symbol CYMEM_CM33_0_S_gfx_mem_S_START = 0x3633C000; +define exported symbol CYMEM_CM33_0_S_gfx_mem_SIZE = 0x001C4000; +define exported symbol CYMEM_CM33_0_S_gfx_mem_OFFSET = 0x0033C000; +define exported symbol CYMEM_CM33_0_S_gfx_mem_sel_START = CYMEM_CM33_0_S_gfx_mem_C_START; +define exported symbol CYMEM_CM33_0_S_gfx_mem_sel_S_START = CYMEM_CM33_0_S_gfx_mem_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33s_shared_START = 0x24001000; +define exported symbol CYMEM_CM33_0_S_m33s_shared_C_START = 0x04001000; +define exported symbol CYMEM_CM33_0_S_m33s_shared_C_S_START = 0x14001000; +define exported symbol CYMEM_CM33_0_S_m33s_shared_S_START = 0x34001000; +define exported symbol CYMEM_CM33_0_S_m33s_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM33_0_S_m33s_shared_OFFSET = 0x00001000; +define exported symbol CYMEM_CM33_0_S_m33s_shared_sel_START = CYMEM_CM33_0_S_m33s_shared_C_START; +define exported symbol CYMEM_CM33_0_S_m33s_shared_sel_S_START = CYMEM_CM33_0_S_m33s_shared_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33s_code_START = 0x24002000; +define exported symbol CYMEM_CM33_0_S_m33s_code_C_START = 0x04002000; +define exported symbol CYMEM_CM33_0_S_m33s_code_C_S_START = 0x14002000; +define exported symbol CYMEM_CM33_0_S_m33s_code_S_START = 0x34002000; +define exported symbol CYMEM_CM33_0_S_m33s_code_SIZE = 0x00035000; +define exported symbol CYMEM_CM33_0_S_m33s_code_OFFSET = 0x00002000; +define exported symbol CYMEM_CM33_0_S_m33s_code_sel_START = CYMEM_CM33_0_S_m33s_code_C_START; +define exported symbol CYMEM_CM33_0_S_m33s_code_sel_S_START = CYMEM_CM33_0_S_m33s_code_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33s_data_START = 0x24037000; +define exported symbol CYMEM_CM33_0_S_m33s_data_C_START = 0x04037000; +define exported symbol CYMEM_CM33_0_S_m33s_data_C_S_START = 0x14037000; +define exported symbol CYMEM_CM33_0_S_m33s_data_S_START = 0x34037000; +define exported symbol CYMEM_CM33_0_S_m33s_data_SIZE = 0x00021000; +define exported symbol CYMEM_CM33_0_S_m33s_data_OFFSET = 0x00037000; +define exported symbol CYMEM_CM33_0_S_m33s_data_sel_START = CYMEM_CM33_0_S_m33s_data_C_START; +define exported symbol CYMEM_CM33_0_S_m33s_data_sel_S_START = CYMEM_CM33_0_S_m33s_data_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33_code_START = 0x24058000; +define exported symbol CYMEM_CM33_0_S_m33_code_C_START = 0x04058000; +define exported symbol CYMEM_CM33_0_S_m33_code_C_S_START = 0x14058000; +define exported symbol CYMEM_CM33_0_S_m33_code_S_START = 0x34058000; +define exported symbol CYMEM_CM33_0_S_m33_code_SIZE = 0x00065000; +define exported symbol CYMEM_CM33_0_S_m33_code_OFFSET = 0x00058000; +define exported symbol CYMEM_CM33_0_S_m33_code_sel_START = CYMEM_CM33_0_S_m33_code_C_START; +define exported symbol CYMEM_CM33_0_S_m33_code_sel_S_START = CYMEM_CM33_0_S_m33_code_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33_data_START = 0x240BD000; +define exported symbol CYMEM_CM33_0_S_m33_data_C_START = 0x040BD000; +define exported symbol CYMEM_CM33_0_S_m33_data_C_S_START = 0x140BD000; +define exported symbol CYMEM_CM33_0_S_m33_data_S_START = 0x340BD000; +define exported symbol CYMEM_CM33_0_S_m33_data_SIZE = 0x00040000; +define exported symbol CYMEM_CM33_0_S_m33_data_OFFSET = 0x000BD000; +define exported symbol CYMEM_CM33_0_S_m33_data_sel_START = CYMEM_CM33_0_S_m33_data_C_START; +define exported symbol CYMEM_CM33_0_S_m33_data_sel_S_START = CYMEM_CM33_0_S_m33_data_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33s_allocatable_shared_START = 0x240FD000; +define exported symbol CYMEM_CM33_0_S_m33s_allocatable_shared_C_START = 0x040FD000; +define exported symbol CYMEM_CM33_0_S_m33s_allocatable_shared_C_S_START = 0x140FD000; +define exported symbol CYMEM_CM33_0_S_m33s_allocatable_shared_S_START = 0x340FD000; +define exported symbol CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM33_0_S_m33s_allocatable_shared_OFFSET = 0x000FD000; +define exported symbol CYMEM_CM33_0_S_m33s_allocatable_shared_sel_START = CYMEM_CM33_0_S_m33s_allocatable_shared_C_START; +define exported symbol CYMEM_CM33_0_S_m33s_allocatable_shared_sel_S_START = CYMEM_CM33_0_S_m33s_allocatable_shared_C_S_START; +define exported symbol CYMEM_CM33_0_S_m33_allocatable_shared_START = 0x240FE000; +define exported symbol CYMEM_CM33_0_S_m33_allocatable_shared_C_START = 0x040FE000; +define exported symbol CYMEM_CM33_0_S_m33_allocatable_shared_C_S_START = 0x140FE000; +define exported symbol CYMEM_CM33_0_S_m33_allocatable_shared_S_START = 0x340FE000; +define exported symbol CYMEM_CM33_0_S_m33_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM33_0_S_m33_allocatable_shared_OFFSET = 0x000FE000; +define exported symbol CYMEM_CM33_0_S_m33_allocatable_shared_sel_START = CYMEM_CM33_0_S_m33_allocatable_shared_C_START; +define exported symbol CYMEM_CM33_0_S_m33_allocatable_shared_sel_S_START = CYMEM_CM33_0_S_m33_allocatable_shared_C_S_START; +define exported symbol CYMEM_CM33_0_S_m55_allocatable_shared_START = 0x240FF000; +define exported symbol CYMEM_CM33_0_S_m55_allocatable_shared_C_START = 0x040FF000; +define exported symbol CYMEM_CM33_0_S_m55_allocatable_shared_C_S_START = 0x140FF000; +define exported symbol CYMEM_CM33_0_S_m55_allocatable_shared_S_START = 0x340FF000; +define exported symbol CYMEM_CM33_0_S_m55_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM33_0_S_m55_allocatable_shared_OFFSET = 0x000FF000; +define exported symbol CYMEM_CM33_0_S_m55_allocatable_shared_sel_START = CYMEM_CM33_0_S_m55_allocatable_shared_C_START; +define exported symbol CYMEM_CM33_0_S_m55_allocatable_shared_sel_S_START = CYMEM_CM33_0_S_m55_allocatable_shared_C_S_START; diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM55_0.icf b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM55_0.icf new file mode 100644 index 00000000000..83a3e249e53 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_CM55_0.icf @@ -0,0 +1,53 @@ +// This file is automatically generated. +define exported symbol CYMEM_CM55_0_m55_data_INTERNAL_START = 0x20000000; +define exported symbol CYMEM_CM55_0_m55_data_SIZE = 0x00040000; +define exported symbol CYMEM_CM55_0_m55_data_OFFSET = 0x00000000; +define exported symbol CYMEM_CM55_0_m55_data_sel_START = CYMEM_CM55_0_m55_data_INTERNAL_START; +define exported symbol CYMEM_CM55_0_m55_code_INTERNAL_START = 0x00000000; +define exported symbol CYMEM_CM55_0_m55_code_SIZE = 0x00040000; +define exported symbol CYMEM_CM55_0_m55_code_OFFSET = 0x00000000; +define exported symbol CYMEM_CM55_0_m55_code_sel_START = CYMEM_CM55_0_m55_code_INTERNAL_START; +define exported symbol CYMEM_CM55_0_user_nvm_C_START = 0x0205B000; +define exported symbol CYMEM_CM55_0_user_nvm_SIZE = 0x00008000; +define exported symbol CYMEM_CM55_0_user_nvm_OFFSET = 0x0005B000; +define exported symbol CYMEM_CM55_0_user_nvm_sel_START = CYMEM_CM55_0_user_nvm_C_START; +define exported symbol CYMEM_CM55_0_m55_nvm_START = 0x60580000; +define exported symbol CYMEM_CM55_0_m55_nvm_SIZE = 0x002C0000; +define exported symbol CYMEM_CM55_0_m55_nvm_OFFSET = 0x00580000; +define exported symbol CYMEM_CM55_0_m55_nvm_sel_START = CYMEM_CM55_0_m55_nvm_START; +define exported symbol CYMEM_CM55_0_m55_trailer_START = 0x60840000; +define exported symbol CYMEM_CM55_0_m55_trailer_SIZE = 0x00040000; +define exported symbol CYMEM_CM55_0_m55_trailer_OFFSET = 0x00840000; +define exported symbol CYMEM_CM55_0_m55_trailer_sel_START = CYMEM_CM55_0_m55_trailer_START; +define exported symbol CYMEM_CM55_0_m55_code_secondary_START = 0x26000000; +define exported symbol CYMEM_CM55_0_m55_code_secondary_SIZE = 0x00040000; +define exported symbol CYMEM_CM55_0_m55_code_secondary_OFFSET = 0x00000000; +define exported symbol CYMEM_CM55_0_m55_code_secondary_sel_START = CYMEM_CM55_0_m55_code_secondary_START; +define exported symbol CYMEM_CM55_0_m55_data_secondary_START = 0x26040000; +define exported symbol CYMEM_CM55_0_m55_data_secondary_SIZE = 0x002BC000; +define exported symbol CYMEM_CM55_0_m55_data_secondary_OFFSET = 0x00040000; +define exported symbol CYMEM_CM55_0_m55_data_secondary_sel_START = CYMEM_CM55_0_m55_data_secondary_START; +define exported symbol CYMEM_CM55_0_m33_m55_shared_START = 0x262FC000; +define exported symbol CYMEM_CM55_0_m33_m55_shared_SIZE = 0x00040000; +define exported symbol CYMEM_CM55_0_m33_m55_shared_OFFSET = 0x002FC000; +define exported symbol CYMEM_CM55_0_m33_m55_shared_sel_START = CYMEM_CM55_0_m33_m55_shared_START; +define exported symbol CYMEM_CM55_0_gfx_mem_START = 0x2633C000; +define exported symbol CYMEM_CM55_0_gfx_mem_SIZE = 0x001C4000; +define exported symbol CYMEM_CM55_0_gfx_mem_OFFSET = 0x0033C000; +define exported symbol CYMEM_CM55_0_gfx_mem_sel_START = CYMEM_CM55_0_gfx_mem_START; +define exported symbol CYMEM_CM55_0_m33_data_START = 0x240BD000; +define exported symbol CYMEM_CM55_0_m33_data_SIZE = 0x00040000; +define exported symbol CYMEM_CM55_0_m33_data_OFFSET = 0x000BD000; +define exported symbol CYMEM_CM55_0_m33_data_sel_START = CYMEM_CM55_0_m33_data_START; +define exported symbol CYMEM_CM55_0_m33s_allocatable_shared_START = 0x240FD000; +define exported symbol CYMEM_CM55_0_m33s_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM55_0_m33s_allocatable_shared_OFFSET = 0x000FD000; +define exported symbol CYMEM_CM55_0_m33s_allocatable_shared_sel_START = CYMEM_CM55_0_m33s_allocatable_shared_START; +define exported symbol CYMEM_CM55_0_m33_allocatable_shared_START = 0x240FE000; +define exported symbol CYMEM_CM55_0_m33_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM55_0_m33_allocatable_shared_OFFSET = 0x000FE000; +define exported symbol CYMEM_CM55_0_m33_allocatable_shared_sel_START = CYMEM_CM55_0_m33_allocatable_shared_START; +define exported symbol CYMEM_CM55_0_m55_allocatable_shared_START = 0x240FF000; +define exported symbol CYMEM_CM55_0_m55_allocatable_shared_SIZE = 0x00001000; +define exported symbol CYMEM_CM55_0_m55_allocatable_shared_OFFSET = 0x000FF000; +define exported symbol CYMEM_CM55_0_m55_allocatable_shared_sel_START = CYMEM_CM55_0_m55_allocatable_shared_START; diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM33_0.icf b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM33_0.icf new file mode 100644 index 00000000000..02a1d18cad3 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM33_0.icf @@ -0,0 +1,66 @@ +// This file is automatically generated. +// define memory with size = 4G; +define region m55_data = [from CYMEM_CM33_0_m55_data_START size CYMEM_CM33_0_m55_data_SIZE]; +define region m55_data_sel = [from CYMEM_CM33_0_m55_data_START size CYMEM_CM33_0_m55_data_SIZE]; +define region m55_code = [from CYMEM_CM33_0_m55_code_START size CYMEM_CM33_0_m55_code_SIZE]; +define region m55_code_sel = [from CYMEM_CM33_0_m55_code_START size CYMEM_CM33_0_m55_code_SIZE]; +define region user_programmable = [from CYMEM_CM33_0_user_programmable_START size CYMEM_CM33_0_user_programmable_SIZE]; +define region user_programmable_C = [from CYMEM_CM33_0_user_programmable_C_START size CYMEM_CM33_0_user_programmable_SIZE]; +define region user_programmable_sel = [from CYMEM_CM33_0_user_programmable_C_START size CYMEM_CM33_0_user_programmable_SIZE]; +define region user_nvm = [from CYMEM_CM33_0_user_nvm_START size CYMEM_CM33_0_user_nvm_SIZE]; +define region user_nvm_C = [from CYMEM_CM33_0_user_nvm_C_START size CYMEM_CM33_0_user_nvm_SIZE]; +define region user_nvm_sel = [from CYMEM_CM33_0_user_nvm_C_START size CYMEM_CM33_0_user_nvm_SIZE]; +define region m33s_nvm = [from CYMEM_CM33_0_m33s_nvm_START size CYMEM_CM33_0_m33s_nvm_SIZE]; +define region m33s_nvm_C = [from CYMEM_CM33_0_m33s_nvm_C_START size CYMEM_CM33_0_m33s_nvm_SIZE]; +define region m33s_nvm_sel = [from CYMEM_CM33_0_m33s_nvm_C_START size CYMEM_CM33_0_m33s_nvm_SIZE]; +define region m33s_trailer = [from CYMEM_CM33_0_m33s_trailer_START size CYMEM_CM33_0_m33s_trailer_SIZE]; +define region m33s_trailer_C = [from CYMEM_CM33_0_m33s_trailer_C_START size CYMEM_CM33_0_m33s_trailer_SIZE]; +define region m33s_trailer_sel = [from CYMEM_CM33_0_m33s_trailer_C_START size CYMEM_CM33_0_m33s_trailer_SIZE]; +define region m33_nvm = [from CYMEM_CM33_0_m33_nvm_START size CYMEM_CM33_0_m33_nvm_SIZE]; +define region m33_nvm_C = [from CYMEM_CM33_0_m33_nvm_C_START size CYMEM_CM33_0_m33_nvm_SIZE]; +define region m33_nvm_sel = [from CYMEM_CM33_0_m33_nvm_C_START size CYMEM_CM33_0_m33_nvm_SIZE]; +define region m33_trailer = [from CYMEM_CM33_0_m33_trailer_START size CYMEM_CM33_0_m33_trailer_SIZE]; +define region m33_trailer_C = [from CYMEM_CM33_0_m33_trailer_C_START size CYMEM_CM33_0_m33_trailer_SIZE]; +define region m33_trailer_sel = [from CYMEM_CM33_0_m33_trailer_C_START size CYMEM_CM33_0_m33_trailer_SIZE]; +define region m55_nvm = [from CYMEM_CM33_0_m55_nvm_START size CYMEM_CM33_0_m55_nvm_SIZE]; +define region m55_nvm_C = [from CYMEM_CM33_0_m55_nvm_C_START size CYMEM_CM33_0_m55_nvm_SIZE]; +define region m55_nvm_sel = [from CYMEM_CM33_0_m55_nvm_C_START size CYMEM_CM33_0_m55_nvm_SIZE]; +define region m55_trailer = [from CYMEM_CM33_0_m55_trailer_START size CYMEM_CM33_0_m55_trailer_SIZE]; +define region m55_trailer_C = [from CYMEM_CM33_0_m55_trailer_C_START size CYMEM_CM33_0_m55_trailer_SIZE]; +define region m55_trailer_sel = [from CYMEM_CM33_0_m55_trailer_C_START size CYMEM_CM33_0_m55_trailer_SIZE]; +define region m55_code_secondary = [from CYMEM_CM33_0_m55_code_secondary_START size CYMEM_CM33_0_m55_code_secondary_SIZE]; +define region m55_code_secondary_C = [from CYMEM_CM33_0_m55_code_secondary_C_START size CYMEM_CM33_0_m55_code_secondary_SIZE]; +define region m55_code_secondary_sel = [from CYMEM_CM33_0_m55_code_secondary_C_START size CYMEM_CM33_0_m55_code_secondary_SIZE]; +define region m55_data_secondary = [from CYMEM_CM33_0_m55_data_secondary_START size CYMEM_CM33_0_m55_data_secondary_SIZE]; +define region m55_data_secondary_C = [from CYMEM_CM33_0_m55_data_secondary_C_START size CYMEM_CM33_0_m55_data_secondary_SIZE]; +define region m55_data_secondary_sel = [from CYMEM_CM33_0_m55_data_secondary_C_START size CYMEM_CM33_0_m55_data_secondary_SIZE]; +define region m33_m55_shared = [from CYMEM_CM33_0_m33_m55_shared_START size CYMEM_CM33_0_m33_m55_shared_SIZE]; +define region m33_m55_shared_C = [from CYMEM_CM33_0_m33_m55_shared_C_START size CYMEM_CM33_0_m33_m55_shared_SIZE]; +define region m33_m55_shared_sel = [from CYMEM_CM33_0_m33_m55_shared_C_START size CYMEM_CM33_0_m33_m55_shared_SIZE]; +define region gfx_mem = [from CYMEM_CM33_0_gfx_mem_START size CYMEM_CM33_0_gfx_mem_SIZE]; +define region gfx_mem_C = [from CYMEM_CM33_0_gfx_mem_C_START size CYMEM_CM33_0_gfx_mem_SIZE]; +define region gfx_mem_sel = [from CYMEM_CM33_0_gfx_mem_C_START size CYMEM_CM33_0_gfx_mem_SIZE]; +define region m33s_shared = [from CYMEM_CM33_0_m33s_shared_START size CYMEM_CM33_0_m33s_shared_SIZE]; +define region m33s_shared_C = [from CYMEM_CM33_0_m33s_shared_C_START size CYMEM_CM33_0_m33s_shared_SIZE]; +define region m33s_shared_sel = [from CYMEM_CM33_0_m33s_shared_C_START size CYMEM_CM33_0_m33s_shared_SIZE]; +define region m33s_code = [from CYMEM_CM33_0_m33s_code_START size CYMEM_CM33_0_m33s_code_SIZE]; +define region m33s_code_C = [from CYMEM_CM33_0_m33s_code_C_START size CYMEM_CM33_0_m33s_code_SIZE]; +define region m33s_code_sel = [from CYMEM_CM33_0_m33s_code_C_START size CYMEM_CM33_0_m33s_code_SIZE]; +define region m33s_data = [from CYMEM_CM33_0_m33s_data_START size CYMEM_CM33_0_m33s_data_SIZE]; +define region m33s_data_C = [from CYMEM_CM33_0_m33s_data_C_START size CYMEM_CM33_0_m33s_data_SIZE]; +define region m33s_data_sel = [from CYMEM_CM33_0_m33s_data_C_START size CYMEM_CM33_0_m33s_data_SIZE]; +define region m33_code = [from CYMEM_CM33_0_m33_code_START size CYMEM_CM33_0_m33_code_SIZE]; +define region m33_code_C = [from CYMEM_CM33_0_m33_code_C_START size CYMEM_CM33_0_m33_code_SIZE]; +define region m33_code_sel = [from CYMEM_CM33_0_m33_code_C_START size CYMEM_CM33_0_m33_code_SIZE]; +define region m33_data = [from CYMEM_CM33_0_m33_data_START size CYMEM_CM33_0_m33_data_SIZE]; +define region m33_data_C = [from CYMEM_CM33_0_m33_data_C_START size CYMEM_CM33_0_m33_data_SIZE]; +define region m33_data_sel = [from CYMEM_CM33_0_m33_data_C_START size CYMEM_CM33_0_m33_data_SIZE]; +define region m33s_allocatable_shared = [from CYMEM_CM33_0_m33s_allocatable_shared_START size CYMEM_CM33_0_m33s_allocatable_shared_SIZE]; +define region m33s_allocatable_shared_C = [from CYMEM_CM33_0_m33s_allocatable_shared_C_START size CYMEM_CM33_0_m33s_allocatable_shared_SIZE]; +define region m33s_allocatable_shared_sel = [from CYMEM_CM33_0_m33s_allocatable_shared_C_START size CYMEM_CM33_0_m33s_allocatable_shared_SIZE]; +define region m33_allocatable_shared = [from CYMEM_CM33_0_m33_allocatable_shared_START size CYMEM_CM33_0_m33_allocatable_shared_SIZE]; +define region m33_allocatable_shared_C = [from CYMEM_CM33_0_m33_allocatable_shared_C_START size CYMEM_CM33_0_m33_allocatable_shared_SIZE]; +define region m33_allocatable_shared_sel = [from CYMEM_CM33_0_m33_allocatable_shared_C_START size CYMEM_CM33_0_m33_allocatable_shared_SIZE]; +define region m55_allocatable_shared = [from CYMEM_CM33_0_m55_allocatable_shared_START size CYMEM_CM33_0_m55_allocatable_shared_SIZE]; +define region m55_allocatable_shared_C = [from CYMEM_CM33_0_m55_allocatable_shared_C_START size CYMEM_CM33_0_m55_allocatable_shared_SIZE]; +define region m55_allocatable_shared_sel = [from CYMEM_CM33_0_m55_allocatable_shared_C_START size CYMEM_CM33_0_m55_allocatable_shared_SIZE]; diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM33_0_S.icf b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM33_0_S.icf new file mode 100644 index 00000000000..ed4864e728b --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM33_0_S.icf @@ -0,0 +1,130 @@ +// This file is automatically generated. +// define memory with size = 4G; +define region m55_data = [from CYMEM_CM33_0_S_m55_data_START size CYMEM_CM33_0_S_m55_data_SIZE]; +define region m55_data_S = [from CYMEM_CM33_0_S_m55_data_S_START size CYMEM_CM33_0_S_m55_data_SIZE]; +define region m55_data_sel = [from CYMEM_CM33_0_S_m55_data_START size CYMEM_CM33_0_S_m55_data_SIZE]; +define region m55_data_sel_S = [from CYMEM_CM33_0_S_m55_data_S_START size CYMEM_CM33_0_S_m55_data_SIZE]; +define region m55_code = [from CYMEM_CM33_0_S_m55_code_START size CYMEM_CM33_0_S_m55_code_SIZE]; +define region m55_code_S = [from CYMEM_CM33_0_S_m55_code_S_START size CYMEM_CM33_0_S_m55_code_SIZE]; +define region m55_code_sel = [from CYMEM_CM33_0_S_m55_code_START size CYMEM_CM33_0_S_m55_code_SIZE]; +define region m55_code_sel_S = [from CYMEM_CM33_0_S_m55_code_S_START size CYMEM_CM33_0_S_m55_code_SIZE]; +define region user_programmable = [from CYMEM_CM33_0_S_user_programmable_START size CYMEM_CM33_0_S_user_programmable_SIZE]; +define region user_programmable_C = [from CYMEM_CM33_0_S_user_programmable_C_START size CYMEM_CM33_0_S_user_programmable_SIZE]; +define region user_programmable_C_S = [from CYMEM_CM33_0_S_user_programmable_C_S_START size CYMEM_CM33_0_S_user_programmable_SIZE]; +define region user_programmable_S = [from CYMEM_CM33_0_S_user_programmable_S_START size CYMEM_CM33_0_S_user_programmable_SIZE]; +define region user_programmable_sel = [from CYMEM_CM33_0_S_user_programmable_C_START size CYMEM_CM33_0_S_user_programmable_SIZE]; +define region user_programmable_sel_S = [from CYMEM_CM33_0_S_user_programmable_C_S_START size CYMEM_CM33_0_S_user_programmable_SIZE]; +define region user_nvm = [from CYMEM_CM33_0_S_user_nvm_START size CYMEM_CM33_0_S_user_nvm_SIZE]; +define region user_nvm_C = [from CYMEM_CM33_0_S_user_nvm_C_START size CYMEM_CM33_0_S_user_nvm_SIZE]; +define region user_nvm_C_S = [from CYMEM_CM33_0_S_user_nvm_C_S_START size CYMEM_CM33_0_S_user_nvm_SIZE]; +define region user_nvm_S = [from CYMEM_CM33_0_S_user_nvm_S_START size CYMEM_CM33_0_S_user_nvm_SIZE]; +define region user_nvm_sel = [from CYMEM_CM33_0_S_user_nvm_C_START size CYMEM_CM33_0_S_user_nvm_SIZE]; +define region user_nvm_sel_S = [from CYMEM_CM33_0_S_user_nvm_C_S_START size CYMEM_CM33_0_S_user_nvm_SIZE]; +define region m33s_nvm = [from CYMEM_CM33_0_S_m33s_nvm_START size CYMEM_CM33_0_S_m33s_nvm_SIZE]; +define region m33s_nvm_C = [from CYMEM_CM33_0_S_m33s_nvm_C_START size CYMEM_CM33_0_S_m33s_nvm_SIZE]; +define region m33s_nvm_C_S = [from CYMEM_CM33_0_S_m33s_nvm_C_S_START size CYMEM_CM33_0_S_m33s_nvm_SIZE]; +define region m33s_nvm_S = [from CYMEM_CM33_0_S_m33s_nvm_S_START size CYMEM_CM33_0_S_m33s_nvm_SIZE]; +define region m33s_nvm_sel = [from CYMEM_CM33_0_S_m33s_nvm_C_START size CYMEM_CM33_0_S_m33s_nvm_SIZE]; +define region m33s_nvm_sel_S = [from CYMEM_CM33_0_S_m33s_nvm_C_S_START size CYMEM_CM33_0_S_m33s_nvm_SIZE]; +define region m33s_trailer = [from CYMEM_CM33_0_S_m33s_trailer_START size CYMEM_CM33_0_S_m33s_trailer_SIZE]; +define region m33s_trailer_C = [from CYMEM_CM33_0_S_m33s_trailer_C_START size CYMEM_CM33_0_S_m33s_trailer_SIZE]; +define region m33s_trailer_C_S = [from CYMEM_CM33_0_S_m33s_trailer_C_S_START size CYMEM_CM33_0_S_m33s_trailer_SIZE]; +define region m33s_trailer_S = [from CYMEM_CM33_0_S_m33s_trailer_S_START size CYMEM_CM33_0_S_m33s_trailer_SIZE]; +define region m33s_trailer_sel = [from CYMEM_CM33_0_S_m33s_trailer_C_START size CYMEM_CM33_0_S_m33s_trailer_SIZE]; +define region m33s_trailer_sel_S = [from CYMEM_CM33_0_S_m33s_trailer_C_S_START size CYMEM_CM33_0_S_m33s_trailer_SIZE]; +define region m33_nvm = [from CYMEM_CM33_0_S_m33_nvm_START size CYMEM_CM33_0_S_m33_nvm_SIZE]; +define region m33_nvm_C = [from CYMEM_CM33_0_S_m33_nvm_C_START size CYMEM_CM33_0_S_m33_nvm_SIZE]; +define region m33_nvm_C_S = [from CYMEM_CM33_0_S_m33_nvm_C_S_START size CYMEM_CM33_0_S_m33_nvm_SIZE]; +define region m33_nvm_S = [from CYMEM_CM33_0_S_m33_nvm_S_START size CYMEM_CM33_0_S_m33_nvm_SIZE]; +define region m33_nvm_sel = [from CYMEM_CM33_0_S_m33_nvm_C_START size CYMEM_CM33_0_S_m33_nvm_SIZE]; +define region m33_nvm_sel_S = [from CYMEM_CM33_0_S_m33_nvm_C_S_START size CYMEM_CM33_0_S_m33_nvm_SIZE]; +define region m33_trailer = [from CYMEM_CM33_0_S_m33_trailer_START size CYMEM_CM33_0_S_m33_trailer_SIZE]; +define region m33_trailer_C = [from CYMEM_CM33_0_S_m33_trailer_C_START size CYMEM_CM33_0_S_m33_trailer_SIZE]; +define region m33_trailer_C_S = [from CYMEM_CM33_0_S_m33_trailer_C_S_START size CYMEM_CM33_0_S_m33_trailer_SIZE]; +define region m33_trailer_S = [from CYMEM_CM33_0_S_m33_trailer_S_START size CYMEM_CM33_0_S_m33_trailer_SIZE]; +define region m33_trailer_sel = [from CYMEM_CM33_0_S_m33_trailer_C_START size CYMEM_CM33_0_S_m33_trailer_SIZE]; +define region m33_trailer_sel_S = [from CYMEM_CM33_0_S_m33_trailer_C_S_START size CYMEM_CM33_0_S_m33_trailer_SIZE]; +define region m55_nvm = [from CYMEM_CM33_0_S_m55_nvm_START size CYMEM_CM33_0_S_m55_nvm_SIZE]; +define region m55_nvm_C = [from CYMEM_CM33_0_S_m55_nvm_C_START size CYMEM_CM33_0_S_m55_nvm_SIZE]; +define region m55_nvm_C_S = [from CYMEM_CM33_0_S_m55_nvm_C_S_START size CYMEM_CM33_0_S_m55_nvm_SIZE]; +define region m55_nvm_S = [from CYMEM_CM33_0_S_m55_nvm_S_START size CYMEM_CM33_0_S_m55_nvm_SIZE]; +define region m55_nvm_sel = [from CYMEM_CM33_0_S_m55_nvm_C_START size CYMEM_CM33_0_S_m55_nvm_SIZE]; +define region m55_nvm_sel_S = [from CYMEM_CM33_0_S_m55_nvm_C_S_START size CYMEM_CM33_0_S_m55_nvm_SIZE]; +define region m55_trailer = [from CYMEM_CM33_0_S_m55_trailer_START size CYMEM_CM33_0_S_m55_trailer_SIZE]; +define region m55_trailer_C = [from CYMEM_CM33_0_S_m55_trailer_C_START size CYMEM_CM33_0_S_m55_trailer_SIZE]; +define region m55_trailer_C_S = [from CYMEM_CM33_0_S_m55_trailer_C_S_START size CYMEM_CM33_0_S_m55_trailer_SIZE]; +define region m55_trailer_S = [from CYMEM_CM33_0_S_m55_trailer_S_START size CYMEM_CM33_0_S_m55_trailer_SIZE]; +define region m55_trailer_sel = [from CYMEM_CM33_0_S_m55_trailer_C_START size CYMEM_CM33_0_S_m55_trailer_SIZE]; +define region m55_trailer_sel_S = [from CYMEM_CM33_0_S_m55_trailer_C_S_START size CYMEM_CM33_0_S_m55_trailer_SIZE]; +define region m55_code_secondary = [from CYMEM_CM33_0_S_m55_code_secondary_START size CYMEM_CM33_0_S_m55_code_secondary_SIZE]; +define region m55_code_secondary_C = [from CYMEM_CM33_0_S_m55_code_secondary_C_START size CYMEM_CM33_0_S_m55_code_secondary_SIZE]; +define region m55_code_secondary_C_S = [from CYMEM_CM33_0_S_m55_code_secondary_C_S_START size CYMEM_CM33_0_S_m55_code_secondary_SIZE]; +define region m55_code_secondary_S = [from CYMEM_CM33_0_S_m55_code_secondary_S_START size CYMEM_CM33_0_S_m55_code_secondary_SIZE]; +define region m55_code_secondary_sel = [from CYMEM_CM33_0_S_m55_code_secondary_C_START size CYMEM_CM33_0_S_m55_code_secondary_SIZE]; +define region m55_code_secondary_sel_S = [from CYMEM_CM33_0_S_m55_code_secondary_C_S_START size CYMEM_CM33_0_S_m55_code_secondary_SIZE]; +define region m55_data_secondary = [from CYMEM_CM33_0_S_m55_data_secondary_START size CYMEM_CM33_0_S_m55_data_secondary_SIZE]; +define region m55_data_secondary_C = [from CYMEM_CM33_0_S_m55_data_secondary_C_START size CYMEM_CM33_0_S_m55_data_secondary_SIZE]; +define region m55_data_secondary_C_S = [from CYMEM_CM33_0_S_m55_data_secondary_C_S_START size CYMEM_CM33_0_S_m55_data_secondary_SIZE]; +define region m55_data_secondary_S = [from CYMEM_CM33_0_S_m55_data_secondary_S_START size CYMEM_CM33_0_S_m55_data_secondary_SIZE]; +define region m55_data_secondary_sel = [from CYMEM_CM33_0_S_m55_data_secondary_C_START size CYMEM_CM33_0_S_m55_data_secondary_SIZE]; +define region m55_data_secondary_sel_S = [from CYMEM_CM33_0_S_m55_data_secondary_C_S_START size CYMEM_CM33_0_S_m55_data_secondary_SIZE]; +define region m33_m55_shared = [from CYMEM_CM33_0_S_m33_m55_shared_START size CYMEM_CM33_0_S_m33_m55_shared_SIZE]; +define region m33_m55_shared_C = [from CYMEM_CM33_0_S_m33_m55_shared_C_START size CYMEM_CM33_0_S_m33_m55_shared_SIZE]; +define region m33_m55_shared_C_S = [from CYMEM_CM33_0_S_m33_m55_shared_C_S_START size CYMEM_CM33_0_S_m33_m55_shared_SIZE]; +define region m33_m55_shared_S = [from CYMEM_CM33_0_S_m33_m55_shared_S_START size CYMEM_CM33_0_S_m33_m55_shared_SIZE]; +define region m33_m55_shared_sel = [from CYMEM_CM33_0_S_m33_m55_shared_C_START size CYMEM_CM33_0_S_m33_m55_shared_SIZE]; +define region m33_m55_shared_sel_S = [from CYMEM_CM33_0_S_m33_m55_shared_C_S_START size CYMEM_CM33_0_S_m33_m55_shared_SIZE]; +define region gfx_mem = [from CYMEM_CM33_0_S_gfx_mem_START size CYMEM_CM33_0_S_gfx_mem_SIZE]; +define region gfx_mem_C = [from CYMEM_CM33_0_S_gfx_mem_C_START size CYMEM_CM33_0_S_gfx_mem_SIZE]; +define region gfx_mem_C_S = [from CYMEM_CM33_0_S_gfx_mem_C_S_START size CYMEM_CM33_0_S_gfx_mem_SIZE]; +define region gfx_mem_S = [from CYMEM_CM33_0_S_gfx_mem_S_START size CYMEM_CM33_0_S_gfx_mem_SIZE]; +define region gfx_mem_sel = [from CYMEM_CM33_0_S_gfx_mem_C_START size CYMEM_CM33_0_S_gfx_mem_SIZE]; +define region gfx_mem_sel_S = [from CYMEM_CM33_0_S_gfx_mem_C_S_START size CYMEM_CM33_0_S_gfx_mem_SIZE]; +define region m33s_shared = [from CYMEM_CM33_0_S_m33s_shared_START size CYMEM_CM33_0_S_m33s_shared_SIZE]; +define region m33s_shared_C = [from CYMEM_CM33_0_S_m33s_shared_C_START size CYMEM_CM33_0_S_m33s_shared_SIZE]; +define region m33s_shared_C_S = [from CYMEM_CM33_0_S_m33s_shared_C_S_START size CYMEM_CM33_0_S_m33s_shared_SIZE]; +define region m33s_shared_S = [from CYMEM_CM33_0_S_m33s_shared_S_START size CYMEM_CM33_0_S_m33s_shared_SIZE]; +define region m33s_shared_sel = [from CYMEM_CM33_0_S_m33s_shared_C_START size CYMEM_CM33_0_S_m33s_shared_SIZE]; +define region m33s_shared_sel_S = [from CYMEM_CM33_0_S_m33s_shared_C_S_START size CYMEM_CM33_0_S_m33s_shared_SIZE]; +define region m33s_code = [from CYMEM_CM33_0_S_m33s_code_START size CYMEM_CM33_0_S_m33s_code_SIZE]; +define region m33s_code_C = [from CYMEM_CM33_0_S_m33s_code_C_START size CYMEM_CM33_0_S_m33s_code_SIZE]; +define region m33s_code_C_S = [from CYMEM_CM33_0_S_m33s_code_C_S_START size CYMEM_CM33_0_S_m33s_code_SIZE]; +define region m33s_code_S = [from CYMEM_CM33_0_S_m33s_code_S_START size CYMEM_CM33_0_S_m33s_code_SIZE]; +define region m33s_code_sel = [from CYMEM_CM33_0_S_m33s_code_C_START size CYMEM_CM33_0_S_m33s_code_SIZE]; +define region m33s_code_sel_S = [from CYMEM_CM33_0_S_m33s_code_C_S_START size CYMEM_CM33_0_S_m33s_code_SIZE]; +define region m33s_data = [from CYMEM_CM33_0_S_m33s_data_START size CYMEM_CM33_0_S_m33s_data_SIZE]; +define region m33s_data_C = [from CYMEM_CM33_0_S_m33s_data_C_START size CYMEM_CM33_0_S_m33s_data_SIZE]; +define region m33s_data_C_S = [from CYMEM_CM33_0_S_m33s_data_C_S_START size CYMEM_CM33_0_S_m33s_data_SIZE]; +define region m33s_data_S = [from CYMEM_CM33_0_S_m33s_data_S_START size CYMEM_CM33_0_S_m33s_data_SIZE]; +define region m33s_data_sel = [from CYMEM_CM33_0_S_m33s_data_C_START size CYMEM_CM33_0_S_m33s_data_SIZE]; +define region m33s_data_sel_S = [from CYMEM_CM33_0_S_m33s_data_C_S_START size CYMEM_CM33_0_S_m33s_data_SIZE]; +define region m33_code = [from CYMEM_CM33_0_S_m33_code_START size CYMEM_CM33_0_S_m33_code_SIZE]; +define region m33_code_C = [from CYMEM_CM33_0_S_m33_code_C_START size CYMEM_CM33_0_S_m33_code_SIZE]; +define region m33_code_C_S = [from CYMEM_CM33_0_S_m33_code_C_S_START size CYMEM_CM33_0_S_m33_code_SIZE]; +define region m33_code_S = [from CYMEM_CM33_0_S_m33_code_S_START size CYMEM_CM33_0_S_m33_code_SIZE]; +define region m33_code_sel = [from CYMEM_CM33_0_S_m33_code_C_START size CYMEM_CM33_0_S_m33_code_SIZE]; +define region m33_code_sel_S = [from CYMEM_CM33_0_S_m33_code_C_S_START size CYMEM_CM33_0_S_m33_code_SIZE]; +define region m33_data = [from CYMEM_CM33_0_S_m33_data_START size CYMEM_CM33_0_S_m33_data_SIZE]; +define region m33_data_C = [from CYMEM_CM33_0_S_m33_data_C_START size CYMEM_CM33_0_S_m33_data_SIZE]; +define region m33_data_C_S = [from CYMEM_CM33_0_S_m33_data_C_S_START size CYMEM_CM33_0_S_m33_data_SIZE]; +define region m33_data_S = [from CYMEM_CM33_0_S_m33_data_S_START size CYMEM_CM33_0_S_m33_data_SIZE]; +define region m33_data_sel = [from CYMEM_CM33_0_S_m33_data_C_START size CYMEM_CM33_0_S_m33_data_SIZE]; +define region m33_data_sel_S = [from CYMEM_CM33_0_S_m33_data_C_S_START size CYMEM_CM33_0_S_m33_data_SIZE]; +define region m33s_allocatable_shared = [from CYMEM_CM33_0_S_m33s_allocatable_shared_START size CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE]; +define region m33s_allocatable_shared_C = [from CYMEM_CM33_0_S_m33s_allocatable_shared_C_START size CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE]; +define region m33s_allocatable_shared_C_S = [from CYMEM_CM33_0_S_m33s_allocatable_shared_C_S_START size CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE]; +define region m33s_allocatable_shared_S = [from CYMEM_CM33_0_S_m33s_allocatable_shared_S_START size CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE]; +define region m33s_allocatable_shared_sel = [from CYMEM_CM33_0_S_m33s_allocatable_shared_C_START size CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE]; +define region m33s_allocatable_shared_sel_S = [from CYMEM_CM33_0_S_m33s_allocatable_shared_C_S_START size CYMEM_CM33_0_S_m33s_allocatable_shared_SIZE]; +define region m33_allocatable_shared = [from CYMEM_CM33_0_S_m33_allocatable_shared_START size CYMEM_CM33_0_S_m33_allocatable_shared_SIZE]; +define region m33_allocatable_shared_C = [from CYMEM_CM33_0_S_m33_allocatable_shared_C_START size CYMEM_CM33_0_S_m33_allocatable_shared_SIZE]; +define region m33_allocatable_shared_C_S = [from CYMEM_CM33_0_S_m33_allocatable_shared_C_S_START size CYMEM_CM33_0_S_m33_allocatable_shared_SIZE]; +define region m33_allocatable_shared_S = [from CYMEM_CM33_0_S_m33_allocatable_shared_S_START size CYMEM_CM33_0_S_m33_allocatable_shared_SIZE]; +define region m33_allocatable_shared_sel = [from CYMEM_CM33_0_S_m33_allocatable_shared_C_START size CYMEM_CM33_0_S_m33_allocatable_shared_SIZE]; +define region m33_allocatable_shared_sel_S = [from CYMEM_CM33_0_S_m33_allocatable_shared_C_S_START size CYMEM_CM33_0_S_m33_allocatable_shared_SIZE]; +define region m55_allocatable_shared = [from CYMEM_CM33_0_S_m55_allocatable_shared_START size CYMEM_CM33_0_S_m55_allocatable_shared_SIZE]; +define region m55_allocatable_shared_C = [from CYMEM_CM33_0_S_m55_allocatable_shared_C_START size CYMEM_CM33_0_S_m55_allocatable_shared_SIZE]; +define region m55_allocatable_shared_C_S = [from CYMEM_CM33_0_S_m55_allocatable_shared_C_S_START size CYMEM_CM33_0_S_m55_allocatable_shared_SIZE]; +define region m55_allocatable_shared_S = [from CYMEM_CM33_0_S_m55_allocatable_shared_S_START size CYMEM_CM33_0_S_m55_allocatable_shared_SIZE]; +define region m55_allocatable_shared_sel = [from CYMEM_CM33_0_S_m55_allocatable_shared_C_START size CYMEM_CM33_0_S_m55_allocatable_shared_SIZE]; +define region m55_allocatable_shared_sel_S = [from CYMEM_CM33_0_S_m55_allocatable_shared_C_S_START size CYMEM_CM33_0_S_m55_allocatable_shared_SIZE]; diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM55_0.icf b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM55_0.icf new file mode 100644 index 00000000000..6f005ef80b7 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_ilinkarm_regions_CM55_0.icf @@ -0,0 +1,28 @@ +// This file is automatically generated. +// define memory with size = 4G; +define region m55_data_INTERNAL = [from CYMEM_CM55_0_m55_data_INTERNAL_START size CYMEM_CM55_0_m55_data_SIZE]; +define region m55_data_sel = [from CYMEM_CM55_0_m55_data_INTERNAL_START size CYMEM_CM55_0_m55_data_SIZE]; +define region m55_code_INTERNAL = [from CYMEM_CM55_0_m55_code_INTERNAL_START size CYMEM_CM55_0_m55_code_SIZE]; +define region m55_code_sel = [from CYMEM_CM55_0_m55_code_INTERNAL_START size CYMEM_CM55_0_m55_code_SIZE]; +define region user_nvm_C = [from CYMEM_CM55_0_user_nvm_C_START size CYMEM_CM55_0_user_nvm_SIZE]; +define region user_nvm_sel = [from CYMEM_CM55_0_user_nvm_C_START size CYMEM_CM55_0_user_nvm_SIZE]; +define region m55_nvm = [from CYMEM_CM55_0_m55_nvm_START size CYMEM_CM55_0_m55_nvm_SIZE]; +define region m55_nvm_sel = [from CYMEM_CM55_0_m55_nvm_START size CYMEM_CM55_0_m55_nvm_SIZE]; +define region m55_trailer = [from CYMEM_CM55_0_m55_trailer_START size CYMEM_CM55_0_m55_trailer_SIZE]; +define region m55_trailer_sel = [from CYMEM_CM55_0_m55_trailer_START size CYMEM_CM55_0_m55_trailer_SIZE]; +define region m55_code_secondary = [from CYMEM_CM55_0_m55_code_secondary_START size CYMEM_CM55_0_m55_code_secondary_SIZE]; +define region m55_code_secondary_sel = [from CYMEM_CM55_0_m55_code_secondary_START size CYMEM_CM55_0_m55_code_secondary_SIZE]; +define region m55_data_secondary = [from CYMEM_CM55_0_m55_data_secondary_START size CYMEM_CM55_0_m55_data_secondary_SIZE]; +define region m55_data_secondary_sel = [from CYMEM_CM55_0_m55_data_secondary_START size CYMEM_CM55_0_m55_data_secondary_SIZE]; +define region m33_m55_shared = [from CYMEM_CM55_0_m33_m55_shared_START size CYMEM_CM55_0_m33_m55_shared_SIZE]; +define region m33_m55_shared_sel = [from CYMEM_CM55_0_m33_m55_shared_START size CYMEM_CM55_0_m33_m55_shared_SIZE]; +define region gfx_mem = [from CYMEM_CM55_0_gfx_mem_START size CYMEM_CM55_0_gfx_mem_SIZE]; +define region gfx_mem_sel = [from CYMEM_CM55_0_gfx_mem_START size CYMEM_CM55_0_gfx_mem_SIZE]; +define region m33_data = [from CYMEM_CM55_0_m33_data_START size CYMEM_CM55_0_m33_data_SIZE]; +define region m33_data_sel = [from CYMEM_CM55_0_m33_data_START size CYMEM_CM55_0_m33_data_SIZE]; +define region m33s_allocatable_shared = [from CYMEM_CM55_0_m33s_allocatable_shared_START size CYMEM_CM55_0_m33s_allocatable_shared_SIZE]; +define region m33s_allocatable_shared_sel = [from CYMEM_CM55_0_m33s_allocatable_shared_START size CYMEM_CM55_0_m33s_allocatable_shared_SIZE]; +define region m33_allocatable_shared = [from CYMEM_CM55_0_m33_allocatable_shared_START size CYMEM_CM55_0_m33_allocatable_shared_SIZE]; +define region m33_allocatable_shared_sel = [from CYMEM_CM55_0_m33_allocatable_shared_START size CYMEM_CM55_0_m33_allocatable_shared_SIZE]; +define region m55_allocatable_shared = [from CYMEM_CM55_0_m55_allocatable_shared_START size CYMEM_CM55_0_m55_allocatable_shared_SIZE]; +define region m55_allocatable_shared_sel = [from CYMEM_CM55_0_m55_allocatable_shared_START size CYMEM_CM55_0_m55_allocatable_shared_SIZE]; diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_memory_locations.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_memory_locations.h new file mode 100644 index 00000000000..98968fda7cc --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_memory_locations.h @@ -0,0 +1,65 @@ +/* This file is automatically generated. */ +#if !defined(CYMEM_MEMORY_LOCATIONS_H) +#define CYMEM_MEMORY_LOCATIONS_H + +#include "cymem_memory_types.h" + +#define CYMEM_CM33_0_S_m55_data_LOCATION IFX_MEMORY_TYPE_CM55_DTCM_INTERNAL +#define CYMEM_CM33_0_S_m55_code_LOCATION IFX_MEMORY_TYPE_CM55_ITCM_INTERNAL +#define CYMEM_CM33_0_S_user_programmable_LOCATION IFX_MEMORY_TYPE_RRAM +#define CYMEM_CM33_0_S_user_nvm_LOCATION IFX_MEMORY_TYPE_RRAM +#define CYMEM_CM33_0_S_m33s_nvm_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_S_m33s_trailer_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_S_m33_nvm_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_S_m33_trailer_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_S_m55_nvm_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_S_m55_trailer_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_S_m55_code_secondary_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM33_0_S_m55_data_secondary_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM33_0_S_m33_m55_shared_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM33_0_S_gfx_mem_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM33_0_S_m33s_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_S_m33s_code_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_S_m33s_data_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_S_m33_code_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_S_m33_data_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_S_m33s_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_S_m33_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_S_m55_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_m55_data_LOCATION IFX_MEMORY_TYPE_CM55_DTCM_INTERNAL +#define CYMEM_CM33_0_m55_code_LOCATION IFX_MEMORY_TYPE_CM55_ITCM_INTERNAL +#define CYMEM_CM33_0_user_programmable_LOCATION IFX_MEMORY_TYPE_RRAM +#define CYMEM_CM33_0_user_nvm_LOCATION IFX_MEMORY_TYPE_RRAM +#define CYMEM_CM33_0_m33s_nvm_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_m33s_trailer_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_m33_nvm_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_m33_trailer_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_m55_nvm_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_m55_trailer_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM33_0_m55_code_secondary_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM33_0_m55_data_secondary_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM33_0_m33_m55_shared_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM33_0_gfx_mem_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM33_0_m33s_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_m33s_code_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_m33s_data_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_m33_code_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_m33_data_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_m33s_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_m33_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM33_0_m55_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM55_0_m55_data_LOCATION IFX_MEMORY_TYPE_CM55_DTCM_INTERNAL +#define CYMEM_CM55_0_m55_code_LOCATION IFX_MEMORY_TYPE_CM55_ITCM_INTERNAL +#define CYMEM_CM55_0_user_nvm_LOCATION IFX_MEMORY_TYPE_RRAM +#define CYMEM_CM55_0_m55_nvm_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM55_0_m55_trailer_LOCATION IFX_MEMORY_TYPE_SMIF0MEM1 +#define CYMEM_CM55_0_m55_code_secondary_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM55_0_m55_data_secondary_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM55_0_m33_m55_shared_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM55_0_gfx_mem_LOCATION IFX_MEMORY_TYPE_SOCMEM_RAM +#define CYMEM_CM55_0_m33_data_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM55_0_m33s_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM55_0_m33_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM +#define CYMEM_CM55_0_m55_allocatable_shared_LOCATION IFX_MEMORY_TYPE_SRAM + +#endif /* CYMEM_MEMORY_LOCATIONS_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_memory_types.h b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_memory_types.h new file mode 100644 index 00000000000..4ce5bace422 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/cymem_memory_types.h @@ -0,0 +1,17 @@ +/* This file is automatically generated. */ +#if !defined(CYMEM_MEMORY_TYPES_H) +#define CYMEM_MEMORY_TYPES_H + +#define IFX_MEMORY_TYPE_CM55_DTCM_INTERNAL (0) +#define IFX_MEMORY_TYPE_CM55_ITCM_INTERNAL (1) +#define IFX_MEMORY_TYPE_RRAM (2) +#define IFX_MEMORY_TYPE_SMIF0MEM1 (3) +#define IFX_MEMORY_TYPE_SOCMEM_RAM (4) +#define IFX_MEMORY_TYPE_SRAM (5) + +#define IS_SMIF_MEMORY(mem) ( \ + (mem == IFX_MEMORY_TYPE_SMIF0MEM1) ? 1 : \ + 0 \ + ) + +#endif /* CYMEM_MEMORY_TYPES_H */ diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/design.cyqspi.memory-export b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/design.cyqspi.memory-export new file mode 100644 index 00000000000..f01aa8338b1 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/design.cyqspi.memory-export @@ -0,0 +1,13 @@ + + + + + + Executable + Readable + Programmable + Nonvolatile + + + + diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/device_mem.json b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/device_mem.json new file mode 100644 index 00000000000..04b3036c628 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/device_mem.json @@ -0,0 +1,43 @@ +{ + "version" : 1.0, + "memoryData" : + { + "physical" : + [ + { "name" : "CM55_DTCM_INTERNAL", "size" : "0x00040000", "start" : [ "0x48040000", "0x58040000", "0x20000000" ] }, + { "name" : "CM55_ITCM_INTERNAL", "size" : "0x00040000", "start" : [ "0x48000000", "0x58000000", "0x00000000" ] }, + { "name" : "RRAM", "size" : "0x00080000", "start" : [ "0x22000000", "0x02000000", "0x12000000", "0x32000000" ] }, + { "name" : "SMIF0MEM1", "size" : "0x04000000", "start" : [ "0x60000000", "0x08000000", "0x18000000", "0x70000000" ] }, + { "name" : "SOCMEM_RAM", "size" : "0x00500000", "start" : [ "0x26000000", "0x06000000", "0x16000000", "0x36000000" ] }, + { "name" : "SRAM", "size" : "0x00100000", "start" : [ "0x24000000", "0x04000000", "0x14000000", "0x34000000" ] } + ], + "region" : + [ + { "name" : "m55_data", "size" : "0x00040000", "start" : [ "0x48040000", "0x58040000", "0x20000000" ] }, + { "name" : "m55_code", "size" : "0x00040000", "start" : [ "0x48000000", "0x58000000", "0x00000000" ] }, + { "name" : "extended_boot_reserved", "size" : "0x00011000", "start" : [ "0x22000000", "0x02000000", "0x12000000", "0x32000000" ], "reserved" : true }, + { "name" : "user_programmable", "size" : "0x0004A000", "start" : [ "0x22011000", "0x02011000", "0x12011000", "0x32011000" ] }, + { "name" : "user_nvm", "size" : "0x00008000", "start" : [ "0x2205B000", "0x0205B000", "0x1205B000", "0x3205B000" ] }, + { "name" : "reserved_region", "size" : "0x00016000", "start" : [ "0x2206A000", "0x0206A000", "0x1206A000", "0x3206A000" ], "reserved" : true }, + { "name" : "m33s_nvm", "size" : "0x00200000", "start" : [ "0x60100000", "0x08100000", "0x18100000", "0x70100000" ] }, + { "name" : "m33s_trailer", "size" : "0x00040000", "start" : [ "0x60300000", "0x08300000", "0x18300000", "0x70300000" ] }, + { "name" : "m33_nvm", "size" : "0x00200000", "start" : [ "0x60340000", "0x08340000", "0x18340000", "0x70340000" ] }, + { "name" : "m33_trailer", "size" : "0x00040000", "start" : [ "0x60540000", "0x08540000", "0x18540000", "0x70540000" ] }, + { "name" : "m55_nvm", "size" : "0x002C0000", "start" : [ "0x60580000", "0x08580000", "0x18580000", "0x70580000" ] }, + { "name" : "m55_trailer", "size" : "0x00040000", "start" : [ "0x60840000", "0x08840000", "0x18840000", "0x70840000" ] }, + { "name" : "m55_code_secondary", "size" : "0x00040000", "start" : [ "0x26000000", "0x06000000", "0x16000000", "0x36000000" ] }, + { "name" : "m55_data_secondary", "size" : "0x002BC000", "start" : [ "0x26040000", "0x06040000", "0x16040000", "0x36040000" ] }, + { "name" : "m33_m55_shared", "size" : "0x00040000", "start" : [ "0x262FC000", "0x062FC000", "0x162FC000", "0x362FC000" ] }, + { "name" : "gfx_mem", "size" : "0x001C4000", "start" : [ "0x2633C000", "0x0633C000", "0x1633C000", "0x3633C000" ] }, + { "name" : "extended_boot_sram_reserved", "size" : "0x00001000", "start" : [ "0x24000000", "0x04000000", "0x14000000", "0x34000000" ], "reserved" : true }, + { "name" : "m33s_shared", "size" : "0x00001000", "start" : [ "0x24001000", "0x04001000", "0x14001000", "0x34001000" ] }, + { "name" : "m33s_code", "size" : "0x00035000", "start" : [ "0x24002000", "0x04002000", "0x14002000", "0x34002000" ] }, + { "name" : "m33s_data", "size" : "0x00021000", "start" : [ "0x24037000", "0x04037000", "0x14037000", "0x34037000" ] }, + { "name" : "m33_code", "size" : "0x00065000", "start" : [ "0x24058000", "0x04058000", "0x14058000", "0x34058000" ] }, + { "name" : "m33_data", "size" : "0x00040000", "start" : [ "0x240BD000", "0x040BD000", "0x140BD000", "0x340BD000" ] }, + { "name" : "m33s_allocatable_shared", "size" : "0x00001000", "start" : [ "0x240FD000", "0x040FD000", "0x140FD000", "0x340FD000" ] }, + { "name" : "m33_allocatable_shared", "size" : "0x00001000", "start" : [ "0x240FE000", "0x040FE000", "0x140FE000", "0x340FE000" ] }, + { "name" : "m55_allocatable_shared", "size" : "0x00001000", "start" : [ "0x240FF000", "0x040FF000", "0x140FF000", "0x340FF000" ] } + ] + } +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/edgeproctectsymbols.json b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/edgeproctectsymbols.json new file mode 100644 index 00000000000..0bfd11cb140 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/edgeproctectsymbols.json @@ -0,0 +1,273 @@ +{ + "symbolInformation" : + [ + { "name" : "CYMEM_CM33_0_S_m55_data_START", "value" : "0x48040000" }, + { "name" : "CYMEM_CM33_0_S_m55_data_S_START", "value" : "0x58040000" }, + { "name" : "CYMEM_CM33_0_S_m55_data_SIZE", "value" : "0x00040000" }, + { "name" : "CYMEM_CM33_0_S_m55_data_OFFSET", "value" : "0x00000000" }, + { "name" : "CYMEM_CM33_0_S_m55_code_START", "value" : "0x48000000" }, + { "name" : "CYMEM_CM33_0_S_m55_code_S_START", "value" : "0x58000000" }, + { "name" : "CYMEM_CM33_0_S_m55_code_SIZE", "value" : "0x00040000" }, + { "name" : "CYMEM_CM33_0_S_m55_code_OFFSET", "value" : "0x00000000" }, + { "name" : "CYMEM_CM33_0_S_user_programmable_START", "value" : "0x22011000" }, + { "name" : "CYMEM_CM33_0_S_user_programmable_C_START", "value" : "0x02011000" }, + { "name" : "CYMEM_CM33_0_S_user_programmable_C_S_START", "value" : "0x12011000" }, + { "name" : "CYMEM_CM33_0_S_user_programmable_S_START", "value" : "0x32011000" }, + { "name" : "CYMEM_CM33_0_S_user_programmable_SIZE", "value" : "0x0004A000" }, + { "name" : "CYMEM_CM33_0_S_user_programmable_OFFSET", "value" : "0x00011000" }, + { "name" : "CYMEM_CM33_0_S_user_nvm_START", "value" : "0x2205B000" }, + { "name" : "CYMEM_CM33_0_S_user_nvm_C_START", "value" : "0x0205B000" }, + { "name" : "CYMEM_CM33_0_S_user_nvm_C_S_START", "value" : "0x1205B000" }, + { "name" : "CYMEM_CM33_0_S_user_nvm_S_START", "value" : "0x3205B000" }, + { "name" : "CYMEM_CM33_0_S_user_nvm_SIZE", "value" : "0x00008000" }, + { "name" : "CYMEM_CM33_0_S_user_nvm_OFFSET", "value" : "0x0005B000" }, + { "name" : "CYMEM_CM33_0_S_m33s_nvm_START", "value" : "0x60100000" }, + { "name" : "CYMEM_CM33_0_S_m33s_nvm_C_START", "value" : "0x08100000" }, + { "name" : "CYMEM_CM33_0_S_m33s_nvm_C_S_START", "value" : "0x18100000" }, + { "name" : "CYMEM_CM33_0_S_m33s_nvm_S_START", "value" : "0x70100000" }, + { "name" : "CYMEM_CM33_0_S_m33s_nvm_SIZE", "value" : "0x00200000" }, + { "name" : "CYMEM_CM33_0_S_m33s_nvm_OFFSET", "value" : "0x00100000" }, + { "name" : "CYMEM_CM33_0_S_m33s_trailer_START", "value" : "0x60300000" }, + { "name" : "CYMEM_CM33_0_S_m33s_trailer_C_START", "value" : "0x08300000" }, + { "name" : "CYMEM_CM33_0_S_m33s_trailer_C_S_START", "value" : "0x18300000" }, + { "name" : "CYMEM_CM33_0_S_m33s_trailer_S_START", "value" : "0x70300000" }, + { "name" : "CYMEM_CM33_0_S_m33s_trailer_SIZE", "value" : "0x00040000" }, + { "name" : "CYMEM_CM33_0_S_m33s_trailer_OFFSET", "value" : "0x00300000" }, + { "name" : "CYMEM_CM33_0_S_m33_nvm_START", "value" : "0x60340000" }, + { "name" : "CYMEM_CM33_0_S_m33_nvm_C_START", "value" : "0x08340000" }, + { "name" : "CYMEM_CM33_0_S_m33_nvm_C_S_START", "value" : "0x18340000" }, + { "name" : "CYMEM_CM33_0_S_m33_nvm_S_START", "value" : "0x70340000" }, + { "name" : "CYMEM_CM33_0_S_m33_nvm_SIZE", "value" : "0x00200000" }, + { "name" : "CYMEM_CM33_0_S_m33_nvm_OFFSET", "value" : "0x00340000" }, + { "name" : "CYMEM_CM33_0_S_m33_trailer_START", "value" : "0x60540000" }, + { "name" : "CYMEM_CM33_0_S_m33_trailer_C_START", "value" : "0x08540000" }, + { "name" : "CYMEM_CM33_0_S_m33_trailer_C_S_START", "value" : "0x18540000" }, + { "name" : "CYMEM_CM33_0_S_m33_trailer_S_START", "value" : "0x70540000" }, + { "name" : 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: "0x18000000", "size" : "0x04000000", "dest" : "0x70000000" } + ] + } + ], + "version" : 1 +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/qspi_config.cfg b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/qspi_config.cfg new file mode 100644 index 00000000000..3e847866237 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/bsp-cfg/qspi_config.cfg @@ -0,0 +1,29 @@ +################################################################################ +# File Name: qspi_config.cfg +# +# Description: +# This file contains a SMIF Bank layout for use with OpenOCD. +# This file was automatically generated and should not be modified. +# QSPI Configurator: 4.60.0.2742 +# +################################################################################ +# Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +set SMIF_BANKS { + 1 {addr 0x60000000 size 0x4000000 psize 0x0000100 esize 0x0040000} +} diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/mpconfigboard.h b/ports/psoc-edge/boards/KIT_PSE84_AI/mpconfigboard.h new file mode 100644 index 00000000000..11a7adbad73 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/mpconfigboard.h @@ -0,0 +1,61 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022-2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// Board and hardware specific configuration +#define MICROPY_HW_MCU_NAME "PSOCE84" +#define MICROPY_HW_BOARD_NAME "KIT_PSE84_AI" + +#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "KIT_PSE84_AI" + +// External QSPI Flash Configuration +// These sizes are determined by the physical flash chip specifications +// and memory map layout for the KIT_PSE84_AI board +#define MICROPY_PY_EXT_FLASH (1) + +// Flash memory map: Total 64MB (0x04000000) QSPI flash (S25HS512T hybrid flash) +// S25HS512T Memory Map: +// Region 0: 0x000000-0x01FFFF (32 x 4KB sectors) +// Region 1: 0x020000-0x03FFFF (1 x 128KB sector) +// Region 2: 0x040000-0x3FFFFFF (255 x 256KB sectors) <- We use this region +// CRITICAL: Base address MUST be aligned to 256KB (0x40000) sector boundary! +#define EXT_FLASH_BASE (0x00900000) // Aligned to sector 36 + +// Usable filesystem space: 64MB - 9MB = 55MB (0x03700000 bytes) +#define EXT_FLASH_SIZE (0x04000000 - EXT_FLASH_BASE) + +// erase sector size : 256KB, fixed by flash chip hardware in Region 2. +#define EXT_FLASH_SECTOR_SIZE (0x40000) /** 256KB*/ + +// Block device block size: Must match erase sector size for proper filesystem operation +#define EXT_FLASH_BLOCK_SIZE_BYTES (EXT_FLASH_SECTOR_SIZE) + +// Program page size: Fixed by flash chip hardware (minimum writable unit). Matches LittleFS write_size. +#define EXT_FLASH_PAGE_SIZE (0x200) /** 512 Bytes */ + +// REPL UART configuration +#define MICROPYTHON_REPL_UART_RX_PIN (pin_P6_5) +#define MICROPYTHON_REPL_UART_TX_PIN (pin_P6_7) +#define MICROPYTHON_REPL_RINGBUF_SIZE (1024) diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/mpconfigboard.mk b/ports/psoc-edge/boards/KIT_PSE84_AI/mpconfigboard.mk new file mode 100644 index 00000000000..dfac06ea188 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/mpconfigboard.mk @@ -0,0 +1,3 @@ +BOARD_VERSION=release-v1.1.0 + +MICROPY_PY_EXT_FLASH = 1 \ No newline at end of file diff --git a/ports/psoc-edge/boards/KIT_PSE84_AI/pins.csv b/ports/psoc-edge/boards/KIT_PSE84_AI/pins.csv new file mode 100644 index 00000000000..4fe9b195572 --- /dev/null +++ b/ports/psoc-edge/boards/KIT_PSE84_AI/pins.csv @@ -0,0 +1,243 @@ +# QSPI flash +,-P0_0 +,-P0_1 +,-P1_0 +,-P1_1 +,-P1_2 +,-P1_3 + +# Not connected +#,-P1_4 +#,-P1_5 +#,-P1_6 +#,-P1_7 + +# QSPI flash +,-P2_0 + +# I3C bus +I3C_SCL,P3_0 +I3C_SDA,P3_1 + +# PSRAM +,-P4_0 +,-P4_1 +,-P4_2 +,-P4_3 +,-P4_4 +,-P4_5 +,-P4_6 +,-P4_7 + +# Not connected +#,-P5_0 + +# JTAG Debug I/O +,-P6_0 +,-P6_1 +,-P6_2 +,-P6_3 + +# Int magnetometer +MAG_INT,P6_4 + +# KitProg UART RX +,-P6_5 + +# Int IMU +IMU0_INT,P6_6 + +# KitProg UART TX +,-P6_7 + +# User button +USER_BUTTON,P7_0 + +# USB ID OGT +,-P7_1 + +# Not connected +#,-P7_2 + +# USB direction +,-P7_3 + +# External clock input +,-P7_4 + +# USB OUT1 DRP +,-P7_5 + +# USB OUT2 DRP +,-P7_6 + +# Int IMU1 +IMU1_INT,P7_7 + +# I2C 1.8V +I2C_SCL_1V8,P8_0 +I2C_SDA_1V8,P8_1 + +# Not connected +#,-P8_2 + +# USB fault signal DRP +,-P8_3 + +# Not connected +#,-P8_4 + +# PDM +PDM_CLK,P8_5 +PDM_DATA,P8_6 + +# Not connected +#,-P8_7 + +# J5 connector +SERIAL_INT0,P9_0 +SERIAL_INT1,P9_1 +SERIAL_INT2,P9_2 +SERIAL_INT3,P9_3 + +# Bluetooth +,-P10_0 +,-P10_1 +,-P10_2 +,-P10_3 +,-P10_4 + +# User LED2 +USER_LED2,P10_5 + +# Bluetooth +,-P10_6 + +# User LED1 +USER_LED1,P10_7 + +# Bluetooth +,-P11_0 + +# PCKL level translator +,-P11_1 + +# Bluetooth +,-P11_2 + +# Int pressure sensor +PRESS_SENS_INT,P11_3 + +# Wifi +,-P11_4 + +# Not connected +#,-P11_5 + +# Wifi +,-P11_6 + +# Not connected +#,-P11_7 + +# Wifi +,-P12_0 +,-P12_1 +,-P12_2 + +# I2S FYSYNC +I2S_TX_FYSYNC,P12_3 + +# Wifi +,-P12_4 +,-P12_5 + +# J17 expansion connector +,P13_0 +,P13_1 +,P13_2 +,P13_3 +,P13_4 +,P13_5 +,P13_6 +,P13_7 + +# Analog microphones +AMIC1_CTB_INP,P14_0 +AMIC1_CTB_INN,P14_1 +AMIC1_CTB_OUT,P14_2 +AMIC2_CTB_OUT,P14_3 +AMIC2_CTB_INP,P14_4 +AMIC2_CTB_INN,P14_5 +AMIC1_CTB_REF,P14_6 +AMIC2_CTB_REF,P14_7 + +# J17 expansion connector +,P15_0 +,P15_1 +,P15_2 +,P15_3 +,P15_4 +,P15_5 +,P15_6 +,P15_7 + +# J14 connector +,P16_0 +,P16_1 +,P16_2 +,P16_3 +,P16_4 +,P16_5 +,P16_6 +,P16_7 +I2C_SCL_3V3,P17_0 +I2C_SDA_3V3,P17_1 +,P17_2 +,P17_3 +,P17_4 +,P17_5 + +# Boot +,-P17_6 + +# J14 connector +,P17_7 + +# Oscillators +,-P18_0 +,-P18_1 +,-P19_0 +,-P19_1 + +,-P20_0 +# Serial Int config +,-P20_1 +,-P20_2 + +# Int Radar +RADAR_INT,P20_3 + +# USER LED RGB G +USER_LED_G,P20_4 +# USER LED RGB B +USER_LED_B,P20_5 +# USER LED RGB R +USER_LED_R,P20_6 + +# Radar reset +RADAR_RESET,P20_7 + +# Wifi +,-P21_0 + +# I2S +I2S_TX_SD,P21_1 +I2S_TX_SCK,P21_2 +I2S_TX_MCK,P21_3 + +# Radar SPI +RADAR_SPI_MISO,P21_4 +RADAR_SPI_MOSI,P21_5 +RADAR_SPI_CLK,P21_6 +RADAR_SPI_CS,P21_7 \ No newline at end of file diff --git a/ports/psoc-edge/boards/deploy.md b/ports/psoc-edge/boards/deploy.md new file mode 100644 index 00000000000..800311487b1 --- /dev/null +++ b/ports/psoc-edge/boards/deploy.md @@ -0,0 +1,44 @@ +### Prerequisites + +To facilitate the installation of the MicroPython PSOC™ Edge port, the `mp-ifx-flash.py` Python script is +provided. It is compatible with Windows, Linux, and macOS. + +Before downloading and running the script, it is recommended to create a new folder to keep all the +related files together. For example: + +```bash +mkdir mp-install +cd mp-install +``` + +You can easily download the script from the terminal using the following command: + +```bash +curl -s -L https://raw.githubusercontent.com/micropython/micropython/master/ports/psoc-edge/tools/mp-ifx-flash.py > mp-ifx-flash.py +``` + +Ensure you have a recent version of [Python 3.x](https://www.python.org/downloads/) and the +[pip](https://pip.pypa.io/en/stable/installation/) package installer installed. Then install the following packages: + +```bash +pip install requests +``` + +### Flashing + +Flashing can be done using the `from-package` command. Specify the board using the `--board` flag, and the path to the downloaded `.zip` package using the `--zip-package` flag, as shown below: + +```bash +python mp-ifx-flash.py from-package --board KIT_PSE84_AI --zip-package pathtodir/psoc-edge-package.zip +``` + +#### Multiple connected devices + +If you have multiple PSOC™ Edge boards connected to your computer, you can identify them by their +serial number and flash each one individually. To do so, use the `-n` flag to provide the serial number of +the target board as shown below: + +```bash +python mp-ifx-flash.py from-package --board KIT_PSE84_AI --zip-package pathtodir/psoc-edge-package.zip -n 181F0D5A01212300 +``` + diff --git a/ports/psoc-edge/boards/make-pins.py b/ports/psoc-edge/boards/make-pins.py new file mode 100644 index 00000000000..3456e0b30e0 --- /dev/null +++ b/ports/psoc-edge/boards/make-pins.py @@ -0,0 +1,330 @@ +from operator import add +import os +import sys +from collections import defaultdict, namedtuple + +sys.path.insert(0, os.path.join(os.path.dirname(__file__), "../../../tools")) +import boardgen + +SUPPORTED_AF = { + "I2C": ["SDA", "SCL"], + "UART": ["TX", "RX", "CTS", "RTS"], + "SPI": ["CLK", "MOSI", "MISO", "SELECT0", "SELECT1"], + "PDM": ["CLK", "DATA"], + # TODO: Other active functionalities that we need to figure out: + # - TDM + # - TCPWM + # - SMIF + # - CANFD + # - PERIx_TR_IO + # - SDHC + # - ETH + # - GFXSS + # - DEBUG + # - I3C + # - M33SYSCPUSS + # - SRSS_EXT_CLK +} + +# Contains the result of parsing an cell from af.csv. +PinAf = namedtuple( + "PinAf", + [ + "af_idx", # int, 0-15 + "af_fn", # e.g. "I2C" + "af_unit", # int, e.g. 1 (for I2C1) or None (for OTG_HS_ULPI_CK) + "af_signal", # e.g. "SDA" + "af_supported", # bool, see table above + "af_name", # e.g. "ACT_x" + "af_ptr", # SCBx or + ], +) + + +class PSE84Pin(boardgen.Pin): + def __init__(self, cpu_pin_name): + super().__init__(cpu_pin_name) + + # The pins are name like PX_Y, where X is the port number and Y is the pin number. + # Each of the numbers can be multiple digits. + # The port are the characters after 'P' and before '_' + self._port = int(cpu_pin_name[1 : cpu_pin_name.index("_")]) + # The pin number is the characters after '_' + self._pin = int(cpu_pin_name[cpu_pin_name.index("_") + 1 :]) + + # List of PinAF instances + self._afs = [] + + def definition(self): + return f"PIN({self._port}, {self._pin}, pin_{self.name()}_af)" + + def add_af_scb(self, af_idx, af_name, af): + # The SCB alternate function follow the + # convention: + # SCB__ + + # The peripheral pointer is the first prefix including + # number, e.g. SCB0 + af_ptr = af.split("_")[0] + # The unit is the number after "SCB" and before "_". + # For example for SCB0 -> 0. + af_unit = af.split("_")[0][3:] # After 'SCB' + # The second token is the function. + # For example I2C, SPI, UART + af_fn = af.split("_")[1] + # The last token is the signal signal type for the + # given function, e.g. SDA, SCL, MOSI + af_signal = af.split("_")[2] + + af_supported = af_fn in SUPPORTED_AF and af_signal in SUPPORTED_AF[af_fn] + + pin_af = PinAf(af_idx, af_fn, af_unit, af_signal, af_supported, af_name, af_ptr) + self._afs.append(pin_af) + + def add_af_pdm(self, af_idx, af_name, af): + # The PDM alternate function follow + # the convention: + # PDM_PDM_ + + af_ptr = ( + af.split("_")[0] + "0" + ) # The peripheral is PDM0 (this index is missing in .csv definition) + af_fn = af.split("_")[1] + + # Split the signal+channel part into alphabetic (signal) and numeric (unit) parts + signal_channel = af.split("_")[2] + + # Find where the numeric part starts + import re + + match = re.match(r"^([A-Za-z]+)(\d+)$", signal_channel) + + if match: + af_signal = match.group(1) # Alphabetic part (e.g., "CLK", "DATA") + af_unit = match.group(2) # Numeric part (e.g., "3", "15", "123") + else: + # Fallback for unexpected format + af_signal = signal_channel + af_unit = None + + af_supported = af_fn in SUPPORTED_AF and af_signal in SUPPORTED_AF[af_fn] + + pin_af = PinAf(af_idx, af_fn, af_unit, af_signal, af_supported, af_name, af_ptr) + self._afs.append(pin_af) + + def add_af(self, af_idx, af_name, af): + # The AF index matches the column index for the ACTx functions 0-15 + # while for DSx functions the columns 16-19 are mapped to DS2-DS5 respectively. + af_act_max_idx = 15 + af_ds_num = 4 + + if af_idx > af_act_max_idx + af_ds_num: + return + + if af_idx <= af_act_max_idx: + if af_name != "ACT_{:d}".format(af_idx): + raise boardgen.PinGeneratorError( + "Invalid AF column name '{:s}' for AF index {:d}.".format(af_name, af_idx) + ) + + if af_idx > af_act_max_idx: + format_idx = ( + af_idx - af_act_max_idx + 1 + ) # The starting index is 2, so we need to subtract + # the max ACTx index and add 1 to get the correct DS index. + if af_name != "DS_{:d}".format(format_idx): + raise boardgen.PinGeneratorError( + "Invalid AF column name '{:s}' for AF index {:d}.".format(af_name, af_idx) + ) + # TODO: Review implementation. + # The names have the following patterns: + # + # __ + # + # As this is not very consistent we will handle each case + # separately and as we improve our understanding we will update + # this code accordingly. + # Currently we are using the definition in the GPIO_PSE84_BGA_220 + # file which has manually added to the boards/pse84x_af.csv. + # But ideally this could be also automatically generated if more + # PSE devices need to be supported in the future. + + # If the prefix match the format SBCx + if af.startswith("SCB"): + self.add_af_scb(af_idx, af_name, af) + elif af.startswith("PDM"): + self.add_af_pdm(af_idx, af_name, af) + else: + # TODO: Extend the parsing to other peripherals. + pass + + # This will be called at the start of the output (after the prefix). Use + # it to emit the af objects (via the AF() macro). + def print_source(self, out_source): + print(file=out_source) + print("const machine_pin_af_obj_t pin_{:s}_af[] = {{".format(self.name()), file=out_source) + for af in self._afs: + if af.af_supported: + print(" ", end="", file=out_source) + else: + print(" // ", end="", file=out_source) + # AF(af_name_idx, af_fn, af_unit, af_signal, af_ptr) + print( + "AF({:s}, {:s}, {:s}, {:s}, {:s}), // {:s}_{:s}{:s}_{:s}".format( + af.af_name, + af.af_fn, + af.af_unit or 0, + af.af_signal or "NONE", + af.af_ptr, + af.af_ptr, + af.af_fn, + af.af_unit, + af.af_signal, + ), + file=out_source, + ) + print("};", file=out_source) + + +class PSE84PinGenerator(boardgen.PinGenerator): + def __init__(self): + super().__init__(pin_type=PSE84Pin, enable_af=True) + self._unhidden_ports = [] + self._port_max_index = 0 + + self._unhidden_scb = [] + self._scb_max_index = 0 + + self._unhidden_i2c = [] + self._unhidden_spi = [] + self._unhidden_uart = [] + + # Collect all unhidden ports from the available + # pins. + # This function can be only used after parse_board_csv() + # has run, as the available_pin generator is constructed + # there. + def add_ports(self): + for pin in self.available_pins(): + if pin._port > self._port_max_index: + self._port_max_index = pin._port + if pin._port not in self._unhidden_ports and not pin._hidden: + self._unhidden_ports.append(pin._port) + + # Collect all unhidden SCB units from the available pins. + # And the each of the potential available I2C, SPI and UART units + # It will not verify that all signals are available for a given unit. + # Therefore, the actual amount of available units for each protocol + # may be lower than the one collected here. + def add_scbs(self): + for pin in self.available_pins(): + if not pin._hidden: + for af in pin._afs: + if af.af_ptr.startswith("SCB"): + if af.af_unit not in self._unhidden_scb: + self._unhidden_scb.append(af.af_unit) + if int(af.af_unit) > self._scb_max_index: + self._scb_max_index = int(af.af_unit) + + if af.af_fn == "I2C": + if af.af_unit not in self._unhidden_i2c: + self._unhidden_i2c.append(af.af_unit) + elif af.af_fn == "SPI": + if af.af_unit not in self._unhidden_spi: + self._unhidden_spi.append(af.af_unit) + elif af.af_fn == "UART": + if af.af_unit not in self._unhidden_uart: + self._unhidden_uart.append(af.af_unit) + + self._unhidden_scb.sort(key=int) + self._unhidden_i2c.sort(key=int) + self._unhidden_spi.sort(key=int) + self._unhidden_uart.sort(key=int) + + # Override the parse_board_csv to add + # the unhidden ports after parsing the board CSV. + def parse_board_csv(self, filename): + super().parse_board_csv(filename) + self.add_ports() + self.add_scbs() + + # Override the default implementation just to change the default arguments + # (extra header row, skip first column). + def parse_af_csv(self, filename): + return super().parse_af_csv(filename, header_rows=1, pin_col=1, af_col=2) + + def print_port_defines(self, out_header): + print(file=out_header) + print( + f"#define MICROPY_PY_MACHINE_PIN_PORT_NUM_ENTRIES ({self._port_max_index + 1})", + file=out_header, + ) + + print(file=out_header) + print("// The MICROPY_PY_MACHINE_PIN_FOR_ALL_PORTS(DO) macro will", file=out_header) + print("// apply the DO macro to all user available ports.", file=out_header) + print("// The DO macro takes the port as argument: DO(port).", file=out_header) + print("#define MICROPY_PY_MACHINE_PIN_FOR_ALL_PORTS(DO) \\", file=out_header) + + lines = [f"DO({port})" for port in self._unhidden_ports] + macro_body = " \\\n".join(lines) + print(macro_body, file=out_header) + + print(file=out_header) + + def print_scb_defines(self, out_header): + print(file=out_header) + print( + f"#define MICROPY_PY_MACHINE_SCB_NUM_ENTRIES ({self._scb_max_index + 1})", + file=out_header, + ) + + print( + f"#define MICROPY_PY_MACHINE_I2C_NUM_ENTRIES ({len(self._unhidden_i2c)})", + file=out_header, + ) + + print( + f"#define MICROPY_PY_MACHINE_SPI_NUM_ENTRIES ({len(self._unhidden_spi)})", + file=out_header, + ) + + print( + f"#define MICROPY_PY_MACHINE_UART_NUM_ENTRIES ({len(self._unhidden_uart)})", + file=out_header, + ) + + print(file=out_header) + print("// The MICROPY_PY_MACHINE_FOR_ALL_SCB(DO) macro will", file=out_header) + print("// apply the DO macro to all user available SCB units.", file=out_header) + print("// The DO macro takes the SCB unit as argument: DO(unit).", file=out_header) + print("#define MICROPY_PY_MACHINE_FOR_ALL_SCB(DO) \\", file=out_header) + + lines = [f"DO({scb})" for scb in self._unhidden_scb] + macro_body = " \\\n".join(lines) + print(macro_body, file=out_header) + + print(file=out_header) + + # Overwrite print_header to extend the print header base class + # function with the pin port defines + def print_header(self, out_header): + super().print_header(out_header) + self.print_port_defines(out_header) + + def print_af_header(self, out_af_header): + self.print_scb_defines(out_af_header) + + # Add additional header file for AF defines and constants + def extra_args(self, parser): + parser.add_argument("--output-af-header") + + # Called in main() after everything else is done to write additional files. + def generate_extra_files(self): + if self.args.output_af_header: + with open(self.args.output_af_header, "w") as out_af_header: + self.print_af_header(out_af_header) + + +if __name__ == "__main__": + PSE84PinGenerator().main() diff --git a/ports/psoc-edge/boards/manifest.py b/ports/psoc-edge/boards/manifest.py new file mode 100644 index 00000000000..c80309cf675 --- /dev/null +++ b/ports/psoc-edge/boards/manifest.py @@ -0,0 +1 @@ +freeze("$(PORT_DIR)/modules") diff --git a/ports/psoc-edge/boards/pse84_prefix.c b/ports/psoc-edge/boards/pse84_prefix.c new file mode 100644 index 00000000000..99c79d2eeff --- /dev/null +++ b/ports/psoc-edge/boards/pse84_prefix.c @@ -0,0 +1,24 @@ +#include "py/obj.h" +#include "py/mphal.h" +#include "machine_pin.h" +#include "machine_pin_af.h" +#include "cy_device_headers_ns.h" + +#define AF(af_name_idx, af_fn, af_unit, af_signal, af_ptr) \ + { \ + .idx = HSIOM_SEL_##af_name_idx, \ + .fn = MACHINE_PIN_AF_FN_##af_fn, \ + .unit = (af_unit), \ + .signal = MACHINE_PIN_AF_SIGNAL_##af_fn##_##af_signal, \ + .periph = (af_ptr) \ + } + +#define PIN(p_port, p_pin, p_af) \ + { \ + { &machine_pin_type }, \ + .name = MP_QSTR_P##p_port##_##p_pin, \ + .port = (p_port), \ + .pin = (p_pin), \ + .af_num = (sizeof(p_af) / sizeof(machine_pin_af_obj_t)), \ + .af = (p_af) \ + } diff --git a/ports/psoc-edge/boards/pse8x_af.csv b/ports/psoc-edge/boards/pse8x_af.csv new file mode 100644 index 00000000000..1e6f16de85b --- /dev/null +++ b/ports/psoc-edge/boards/pse8x_af.csv @@ -0,0 +1,133 @@ +Port ,Pin ,ACT_0 ,ACT_1 ,ACT_2 ,ACT_3 ,ACT_4 ,ACT_5 ,ACT_6 ,ACT_7 ,ACT_8 ,ACT_9 ,ACT_10 ,ACT_11 ,ACT_12,ACT_13 ,ACT_14 ,ACT_15 ,DS_2 ,DS_3 ,DS_4 ,DS_5 +Port0 ,P0_0 ,SMIF1_SMIF0_SPIHB_SELECT1,TCPWM0_LINE0 ,TCPWM0_LINE256 , ,SCB3_SPI_SELECT0, , , , , , , , , , , , , , , +Port0 ,P0_1 ,SMIF1_SMIF0_SPIHB_SELECT2,TCPWM0_LINE_COMPL0 ,TCPWM0_LINE_COMPL256 , , , , , , , , , , , , , , , , , +Port1 ,P1_0 , ,SMIF0_SPIHB_DATA0_TCPWM0_LINE1 ,SMIF0_SPIHB_DATA0_TCPWM0_LINE257 , , , , , , , , , , , , , , , , , +Port1 ,P1_1 , ,SMIF0_SPIHB_DATA1_TCPWM0_LINE_COMPL1,SMIF0_SPIHB_DATA1_TCPWM0_LINE_COMPL257, , , , , , , , , , , , , , , , , +Port1 ,P1_2 , ,SMIF0_SPIHB_DATA2_TCPWM0_LINE2 ,SMIF0_SPIHB_DATA2_TCPWM0_LINE258 , , , , , , , , , , , , , , , , , +Port1 ,P1_3 , ,SMIF0_SPIHB_DATA3_TCPWM0_LINE_COMPL2,SMIF0_SPIHB_DATA3_TCPWM0_LINE_COMPL258, , , , , , , , , , , , , , , , , +Port1 ,P1_4 , ,SMIF0_SPIHB_DATA4_TCPWM0_LINE3 ,SMIF0_SPIHB_DATA4_TCPWM0_LINE259 , , , , , , , , , , , , , , , , , +Port1 ,P1_5 , ,SMIF0_SPIHB_DATA5_TCPWM0_LINE_COMPL3,SMIF0_SPIHB_DATA5_TCPWM0_LINE_COMPL259, , , , , , , , , , , , , , , , , +Port1 ,P1_6 , ,SMIF0_SPIHB_DATA6_TCPWM0_LINE4 ,SMIF0_SPIHB_DATA6_TCPWM0_LINE260 , , , , , , , , , , , , , , , , , +Port1 ,P1_7 , ,SMIF0_SPIHB_DATA7_TCPWM0_LINE_COMPL4,SMIF0_SPIHB_DATA7_TCPWM0_LINE_COMPL260, , , , , , , , , , , , , , , , , +Port2 ,P2_0 ,SMIF0_SMIF0_SPIHB_SELECT1,TCPWM0_LINE5 ,TCPWM0_LINE261 , , , , , , , , , , , , , , , , , +Port3 ,P3_0 , ,TCPWM0_LINE_COMPL5 ,TCPWM0_LINE_COMPL261 , , , , , , , , , , , ,SDHC1_CARD_MECH_WRITE_PROT,I3C_I3C_SCL , , , , +Port3 ,P3_1 , ,TCPWM0_LINE6 ,TCPWM0_LINE262 , , , , , , , , , , , , ,I3C_I3C_SDA , , , , +Port4 ,P4_0 , ,SMIF1_SPIHB_DATA0_TCPWM0_LINE_COMPL6,SMIF1_SPIHB_DATA0_TCPWM0_LINE_COMPL262, , , , , , , , , , , , , , , , , +Port4 ,P4_1 , ,SMIF1_SPIHB_DATA1_TCPWM0_LINE7 ,SMIF1_SPIHB_DATA1_TCPWM0_LINE263 , , , , , , , , , , , , , , , , , +Port4 ,P4_2 , ,SMIF1_SPIHB_DATA2_TCPWM0_LINE_COMPL7,SMIF1_SPIHB_DATA2_TCPWM0_LINE_COMPL263, , , , , , , , , , , , , , , , , +Port4 ,P4_3 , ,SMIF1_SPIHB_DATA3_TCPWM0_LINE0 ,SMIF1_SPIHB_DATA3_TCPWM0_LINE264 , , , , , , , , , , , , ,SMIF1_SPIHB_DATA3_DEBUG600_TRACE_CLOCK, , , , +Port4 ,P4_4 , ,SMIF1_SPIHB_DATA4_TCPWM0_LINE_COMPL0,SMIF1_SPIHB_DATA4_TCPWM0_LINE_COMPL264, , , , , , , , , , , , ,SMIF1_SPIHB_DATA4_DEBUG600_TRACE_DATA0, , , , +Port4 ,P4_5 , ,SMIF1_SPIHB_DATA5_TCPWM0_LINE1 ,SMIF1_SPIHB_DATA5_TCPWM0_LINE265 , , , , , , , , , , , , ,SMIF1_SPIHB_DATA5_DEBUG600_TRACE_DATA1, , , , +Port4 ,P4_6 , ,SMIF1_SPIHB_DATA6_TCPWM0_LINE_COMPL1,SMIF1_SPIHB_DATA6_TCPWM0_LINE_COMPL265, , , , , , , , , , , , ,SMIF1_SPIHB_DATA6_DEBUG600_TRACE_DATA2, , , , +Port4 ,P4_7 , ,SMIF1_SPIHB_DATA7_TCPWM0_LINE2 ,SMIF1_SPIHB_DATA7_TCPWM0_LINE266 , , , , , , , , , , , , ,SMIF1_SPIHB_DATA7_DEBUG600_TRACE_DATA3, , , , +Port5 ,P5_0 ,SMIF0_SMIF0_SPIHB_SELECT0,TCPWM0_LINE_COMPL2 ,TCPWM0_LINE_COMPL266 , , , , , , , , , , , , , , , , , +Port6 ,P6_0 , ,TCPWM0_LINE3 ,TCPWM0_LINE267 , , , , , , , , , , , ,SDHC1_CARD_MECH_WRITE_PROT, , , , ,DEBUG600_SWJ_SWO_TDO +Port6 ,P6_1 , ,TCPWM0_LINE_COMPL3 ,TCPWM0_LINE_COMPL267 , , , , , , , , , , , , ,SDHC1_LED_CTRL , , , ,DEBUG600_SWJ_SWDOE_TDI +Port6 ,P6_2 , ,TCPWM0_LINE4 ,TCPWM0_LINE268 , , , , , , , , , , , , ,SDHC1_CARD_IF_PWR_EN , , , ,DEBUG600_SWJ_SWDIO_TMS +Port6 ,P6_3 , ,TCPWM0_LINE_COMPL4 ,TCPWM0_LINE_COMPL268 , , , ,SCB2_SPI_SELECT1 , , , , , , , , , , , , ,DEBUG600_CLK_SWJ_SWCLK_TCLK +Port6 ,P6_4 , ,TCPWM0_LINE5 ,TCPWM0_LINE269 , , , ,SCB2_SPI_MISO , ,SCB2_UART_CTS , , , , , , ,SDHC1_CARD_DAT_7TO40 , , , , +Port6 ,P6_5 , ,TCPWM0_LINE_COMPL5 ,TCPWM0_LINE_COMPL269 , , , ,SCB2_SPI_CLK ,SCB2_I2C_SCL ,SCB2_UART_RX , , , , , , ,SDHC1_CARD_DAT_7TO41 , , , , +Port6 ,P6_6 , ,TCPWM0_LINE6 ,TCPWM0_LINE270 , , , ,SCB2_SPI_SELECT0 , ,SCB2_UART_RTS , , , , , , ,SDHC1_CARD_DAT_7TO42 , , , , +Port6 ,P6_7 ,SMIF0_SMIF0_SPIHB_SELECT2,TCPWM0_LINE_COMPL6 ,TCPWM0_LINE_COMPL270 , , , ,SCB2_SPI_MOSI ,SCB2_I2C_SDA ,SCB2_UART_TX , , , , , , ,SDHC1_CARD_DAT_7TO43 , , , , +Port7 ,P7_0 ,SMIF0_SMIF0_SPIHB_SELECT3,TCPWM0_LINE7 ,TCPWM0_LINE271 ,M33SYSCPUSS_FAULT0, , , , , , ,PERI0_TR_IO_OUTPUT0,PERI1_TR_IO_OUTPUT0, , , ,SDHC1_CARD_CMD , , , , +Port7 ,P7_1 , ,TCPWM0_LINE_COMPL7 ,TCPWM0_LINE_COMPL271 ,M33SYSCPUSS_FAULT1, , , , , , ,PERI0_TR_IO_OUTPUT1,PERI1_TR_IO_OUTPUT1, , , ,SDHC1_CLK_CARD , , , , +Port7 ,P7_2 , ,TCPWM0_LINE0 ,TCPWM0_LINE272 , , , , , , , , , , , , ,SDHC1_CARD_EMMC_RESET_N , , , ,DEBUG600_RST_SWJ_TRSTN +Port7 ,P7_3 , ,TCPWM0_LINE_COMPL0 ,TCPWM0_LINE_COMPL272 , , , , , , , , , , , , ,SDHC1_CARD_DAT_3TO00 , , , , +Port7 ,P7_4 , ,TCPWM0_LINE1 ,TCPWM0_LINE273 , ,SRSS_EXT_CLK , , , , , , , , , , ,SDHC1_CARD_DETECT_N , , , , +Port7 ,P7_5 , ,TCPWM0_LINE_COMPL1 ,TCPWM0_LINE_COMPL273 , , , , , , , ,PERI0_TR_IO_INPUT4 ,PERI1_TR_IO_INPUT4 , , , ,SDHC1_CARD_DAT_3TO01 , , , , +Port7 ,P7_6 , ,TCPWM0_LINE2 ,TCPWM0_LINE274 , , , , , , , ,PERI0_TR_IO_INPUT5 ,PERI1_TR_IO_INPUT5 , , , ,SDHC1_CARD_DAT_3TO02 , , , , +Port7 ,P7_7 , ,TCPWM0_LINE_COMPL2 ,TCPWM0_LINE_COMPL274 , , , , , , , ,PERI0_TR_IO_INPUT6 ,PERI1_TR_IO_INPUT6 , , , ,SDHC1_CARD_DAT_3TO03 , , , , +Port8 ,P8_0 , ,TCPWM0_LINE3 ,TCPWM0_LINE275 , , , , , , , ,PERI0_TR_IO_INPUT7 ,PERI1_TR_IO_INPUT7 , , , , ,SCB0_SPI_CLK ,SCB0_I2C_SCL , ,M0SECCPUSS_M0SEC_SWD +Port8 ,P8_1 , ,TCPWM0_LINE_COMPL3 ,TCPWM0_LINE_COMPL275 , , , , , , ,PDM_PDM_CLK2 , , , , , , ,SCB0_SPI_MOSI ,SCB0_I2C_SDA , ,M0SECCPUSS_CLK_M0SEC_SWD +Port8 ,P8_2 , ,TCPWM0_LINE4 ,TCPWM0_LINE276 , , , , , , , , , , , , , ,SCB0_SPI_SELECT0, , , +Port8 ,P8_3 , ,TCPWM0_LINE_COMPL4 ,TCPWM0_LINE_COMPL276 , , , , , , , , , , , , , ,SCB0_SPI_SELECT1, , , +Port8 ,P8_4 , ,TCPWM0_LINE5 ,TCPWM0_LINE277 , , , , , , ,PDM_PDM_DATA2, , , , , , ,SCB0_SPI_MISO ,SRSS_CAL_WAVE , , +Port8 ,P8_5 , ,TCPWM0_LINE_COMPL5 ,TCPWM0_LINE_COMPL277 , , , , , , ,PDM_PDM_CLK3 , , , , , , , , , , +Port8 ,P8_6 , ,TCPWM0_LINE6 ,TCPWM0_LINE278 , , , , , , ,PDM_PDM_DATA3, , , , , , , , , , +Port8 ,P8_7 , ,TCPWM0_LINE_COMPL6 ,TCPWM0_LINE_COMPL278 , , , , , , , , , , , , , , , , , +Port9 ,P9_0 , ,TCPWM0_LINE7 ,TCPWM0_LINE_COMPL279 , , , ,SCB1_SPI_SELECT0 , , ,PDM_PDM_CLK5 , , , , , , , , , , +Port9 ,P9_1 , ,TCPWM0_LINE0 ,TCPWM0_LINE_COMPL256 , , , ,SCB1_SPI_MISO , ,SCB1_UART_CTS ,PDM_PDM_DATA5, , , , , , , , , , +Port9 ,P9_2 , ,TCPWM0_LINE_COMPL7 ,TCPWM0_LINE279 , , , ,SCB1_SPI_MOSI ,SCB1_I2C_SDA ,SCB1_UART_TX ,PDM_PDM_CLK4 , , , , , , , , , , +Port9 ,P9_3 , ,TCPWM0_LINE_COMPL0 ,TCPWM0_LINE256 , , , ,SCB1_SPI_CLK ,SCB1_I2C_SCL ,SCB1_UART_RX ,PDM_PDM_DATA4, , , , , , , , , , +Port10,P10_0, ,TCPWM0_LINE1 ,TCPWM0_LINE257 ,M33SYSCPUSS_FAULT0, , , ,SCB4_I2C_SCL ,SCB4_UART_RX , , , , , , ,ETH_TXD3 , , , , +Port10,P10_1, ,TCPWM0_LINE_COMPL1 ,TCPWM0_LINE_COMPL257 ,M33SYSCPUSS_FAULT1, , ,SCB4_SPI_CLK ,SCB4_I2C_SDA ,SCB4_UART_TX , , , , , , ,ETH_RX_CLK , , , , +Port10,P10_2, ,TCPWM0_LINE2 ,TCPWM0_LINE258 , , , ,SCB4_SPI_MOSI , ,SCB4_UART_CTS , , , , , , ,ETH_TX_ER , ,LPCOMP_DSI_COMP1, , +Port10,P10_3, ,TCPWM0_LINE_COMPL2 ,TCPWM0_LINE_COMPL258 , , , ,SCB4_SPI_MISO , ,SCB4_UART_RTS , , , , , , ,ETH_ETH_TSU_TIMER_CMP_VAL , ,LPCOMP_DSI_COMP0, , +Port10,P10_4, ,TCPWM0_LINE3 ,TCPWM0_LINE259 , , , ,SCB4_SPI_SELECT0 , , , , , , , , ,ETH_RXD3 , , , , +Port10,P10_5, ,TCPWM0_LINE_COMPL3 ,TCPWM0_LINE_COMPL259 , , , ,SCB4_SPI_SELECT1 , , , , , , , , ,ETH_RX_CTL , , , , +Port10,P10_6, ,TCPWM0_LINE4 ,TCPWM0_LINE260 , , , , , , , , , , , , ,ETH_RXD0 , , , , +Port10,P10_7, ,TCPWM0_LINE_COMPL4 ,TCPWM0_LINE_COMPL260 , , , , , , , , , , , , ,ETH_RXD1 , , , , +Port10,P11_0, ,TCPWM0_LINE5 ,TCPWM0_LINE261 , , ,TDM_TDM_TX_SCK1 , ,SCB6_I2C_SCL , , , , , , , ,ETH_RXD2 , , , , +Port11,P11_1, ,TCPWM0_LINE_COMPL5 ,TCPWM0_LINE_COMPL261 , , ,TDM_TDM_TX_FSYNC1,SCB6_SPI_MOSI ,SCB6_I2C_SDA ,SCB6_UART_TX , ,PERI0_TR_IO_INPUT1 ,PERI1_TR_IO_INPUT1 , , , ,ETH_RX_ER , , , , +Port11,P11_2, ,TCPWM0_LINE6 ,TCPWM0_LINE262 , , ,TDM_TDM_TX_SD1 ,SCB6_SPI_MISO , ,SCB6_UART_CTS , ,PERI0_TR_IO_INPUT2 ,PERI1_TR_IO_INPUT2 , , , ,ETH_TXD0 , , , , +Port11,P11_3, ,TCPWM0_LINE_COMPL6 ,TCPWM0_LINE_COMPL262 , , ,TDM_TDM_RX_MCK1 ,SCB6_SPI_SELECT0 , ,SCB6_UART_RTS , ,PERI0_TR_IO_INPUT3 ,PERI1_TR_IO_INPUT3 , , , ,ETH_TXD1 , , , , +Port11,P11_4, ,TCPWM0_LINE7 ,TCPWM0_LINE263 , , ,TDM_TDM_RX_SCK1 ,SCB6_SPI_SELECT1 , , , , , , , , ,ETH_TX_CTL , , , , +Port11,P11_5, ,TCPWM0_LINE_COMPL7 ,TCPWM0_LINE_COMPL263 , , ,TDM_TDM_RX_FSYNC1, , , , , , , , , ,ETH_TX_CLK , , , , +Port11,P11_6, ,TCPWM0_LINE0 ,TCPWM0_LINE264 , , ,TDM_TDM_RX_SD1 , , , , , , , , , ,ETH_TXD2 , , , , +Port11,P11_7, ,TCPWM0_LINE_COMPL0 ,TCPWM0_LINE_COMPL264 , , ,TDM_TDM_TX_MCK1 , , , , , , , , , ,ETH_REF_CLK , , , , +Port12,P12_0, ,TCPWM0_LINE1 ,TCPWM0_LINE265 , , , , , , , , , , , , ,SDHC0_CLK_CARD , , , , +Port12,P12_1, ,TCPWM0_LINE_COMPL1 ,TCPWM0_LINE_COMPL265 , , , , , , , , , , , , ,SDHC0_CARD_DAT_3TO00 , , , , +Port12,P12_2, ,TCPWM0_LINE2 ,TCPWM0_LINE266 , , , , , , , , , , , , ,SDHC0_CARD_DAT_3TO01 , , , , +Port12,P12_3,SMIF1_SMIF0_SPIHB_SELECT3,TCPWM0_LINE_COMPL2 ,TCPWM0_LINE_COMPL266 , , , , ,TDM_TDM_TX_FSYNC0, , , , , , , , , , , , +Port12,P12_4, ,TCPWM0_LINE3 ,TCPWM0_LINE267 , , , , , , , , , , , , ,SDHC0_CARD_DAT_3TO02 , , , , +Port12,P12_5, ,TCPWM0_LINE_COMPL3 ,TCPWM0_LINE_COMPL267 , , , , , , , , , , , , ,SDHC0_CARD_DAT_3TO03 , , , , +Port13,P13_0, , , , , , , , , , , , , , , , , , , , +Port13,P13_1, ,TCPWM0_LINE4 ,TCPWM0_LINE268 , , , ,SCB7_SPI_CLK ,SCB7_I2C_SCL ,SCB7_UART_RX , , , , , , ,ETH_MDC , , , , +Port13,P13_2, ,TCPWM0_LINE_COMPL4 ,TCPWM0_LINE_COMPL268 , , , ,SCB7_SPI_MOSI ,SCB7_I2C_SDA ,SCB7_UART_TX ,PDM_PDM_CLK1 , , , , , , , , , , +Port13,P13_3, ,TCPWM0_LINE5 ,TCPWM0_LINE269 , , , ,SCB7_SPI_MISO , ,SCB7_UART_CTS ,PDM_PDM_DATA1, , , , , , , , , , +Port13,P13_4, ,TCPWM0_LINE_COMPL5 ,TCPWM0_LINE_COMPL269 , , , ,SCB7_SPI_SELECT0 , ,SCB7_UART_RTS , , , , , , , , , , , +Port13,P13_5, , , , , , , , , , , , , , , , , , , , +Port13,P13_6, ,TCPWM0_LINE6 ,TCPWM0_LINE270 , , , ,SCB7_SPI_SELECT1 , , , , , , , , ,ETH_MDIO , , , , +Port13,P13_7, ,TCPWM0_LINE_COMPL6 ,TCPWM0_LINE_COMPL270 , , , ,SCB8_SPI_MISO , ,SCB8_UART_CTS , , , , , , , , , , , +Port14,P14_0, , , , , , , , , , , , , , , , , , , , +Port14,P14_1, ,TCPWM0_LINE7 ,TCPWM0_LINE271 , , , , , , ,PDM_PDM_CLK0 , , , , , , , , , , +Port14,P14_2, ,TCPWM0_LINE_COMPL7 ,TCPWM0_LINE_COMPL271 , , , , , , , , , , , , , , , , , +Port14,P14_3, ,TCPWM0_LINE0 ,TCPWM0_LINE272 , , , ,SCB8_SPI_MOSI ,SCB8_I2C_SDA ,SCB8_UART_TX , , , , , , , , , , , +Port14,P14_4, ,TCPWM0_LINE_COMPL0 ,TCPWM0_LINE_COMPL272 , , , ,SCB8_SPI_CLK ,SCB8_I2C_SCL ,SCB8_UART_RX ,PDM_PDM_DATA0, , , , , , , , , , +Port14,P14_5, , , , , , , , , , , , , , , , , , , , +Port14,P14_6, ,TCPWM0_LINE1 ,TCPWM0_LINE273 , , , ,SCB8_SPI_SELECT1 , , , , , , , , , , , , , +Port14,P14_7, ,TCPWM0_LINE_COMPL1 ,TCPWM0_LINE_COMPL273 , , , ,SCB8_SPI_SELECT0 , ,SCB8_UART_RTS , , , , , , , , , , , +Port15,P15_0, ,TCPWM0_LINE2 ,TCPWM0_LINE274 , , , ,SCB9_SPI_CLK ,SCB9_I2C_SCL ,SCB9_UART_RX , , , , , , , , , , , +Port15,P15_1, ,TCPWM0_LINE_COMPL2 ,TCPWM0_LINE_COMPL274 , , , ,SCB9_SPI_MOSI ,SCB9_I2C_SDA ,SCB9_UART_TX , , , , , , , , , , , +Port15,P15_2, ,TCPWM0_LINE3 ,TCPWM0_LINE275 , , , ,SCB9_SPI_MISO , ,SCB9_UART_CTS , , , , , , , , , , , +Port15,P15_3, ,TCPWM0_LINE_COMPL3 ,TCPWM0_LINE_COMPL275 , , , ,SCB9_SPI_SELECT0 , ,SCB9_UART_RTS , , , , , , , , , , , +Port15,P15_4, ,TCPWM0_LINE4 ,TCPWM0_LINE276 , , , ,SCB9_SPI_SELECT1 , , , , , , , , , , , , , +Port15,P15_5, ,TCPWM0_LINE_COMPL4 ,TCPWM0_LINE_COMPL276 , , , , , , , , , , , , , , , , , +Port15,P15_6, ,TCPWM0_LINE5 ,TCPWM0_LINE277 , , , , , , , , , , , , , , , , , +Port15,P15_7, ,TCPWM0_LINE_COMPL5 ,TCPWM0_LINE_COMPL277 , , , , , , , , , , , , , , , , , +Port16,P16_0, ,TCPWM0_LINE0 ,TCPWM0_LINE256 , ,CANFD0_TTCAN_RX0, ,SCB10_SPI_CLK ,SCB10_I2C_SCL ,SCB10_UART_RX , , , , , ,GFXSS_DBI_CSX ,GFXSS_SPI_CSX , , , , +Port16,P16_1, ,TCPWM0_LINE1 ,TCPWM0_LINE257 , ,CANFD0_TTCAN_TX0, ,SCB10_SPI_MOSI ,SCB10_I2C_SDA ,SCB10_UART_TX , , , , ,GFXSS_DBI_WRX,GFXSS_DBI_E ,GFXSS_SPI_SCL , , , , +Port16,P16_2, ,TCPWM0_LINE2 ,TCPWM0_LINE258 , ,CANFD0_TTCAN_RX1, ,SCB10_SPI_MISO , ,SCB10_UART_CTS, , , , , ,GFXSS_DBI_DCX ,GFXSS_SPI_DOUT , , , , +Port16,P16_3, ,TCPWM0_LINE3 ,TCPWM0_LINE259 , , , ,SCB10_SPI_SELECT0, ,SCB10_UART_RTS, , , , , ,GFXSS_DBI_D0 ,GFXSS_SPI_DCX , , , , +Port16,P16_4, ,TCPWM0_LINE4 ,TCPWM0_LINE260 , , , ,SCB10_SPI_SELECT1, , , , , , , ,GFXSS_DBI_D1 , , , , , +Port16,P16_5, ,TCPWM0_LINE5 ,TCPWM0_LINE261 , , , ,SCB5_SPI_MISO , ,SCB5_UART_CTS , , , , , ,GFXSS_DBI_D2 , , , , , +Port16,P16_6, ,TCPWM0_LINE6 ,TCPWM0_LINE278 , , , ,SCB5_SPI_SELECT0 , ,SCB5_UART_RTS , , , , , ,GFXSS_DBI_D3 , , , , , +Port16,P16_7, ,TCPWM0_LINE7 ,TCPWM0_LINE279 , , , ,SCB5_SPI_SELECT1 , , , , , , , ,GFXSS_DBI_D4 , , , , , +Port17,P17_0, ,TCPWM0_LINE_COMPL0 ,TCPWM0_LINE_COMPL256 , , , ,SCB5_SPI_CLK ,SCB5_I2C_SCL ,SCB5_UART_RX , , , , , ,GFXSS_DBI_D5 , , , , , +Port17,P17_1, ,TCPWM0_LINE_COMPL1 ,TCPWM0_LINE_COMPL257 , , , ,SCB5_SPI_MOSI ,SCB5_I2C_SDA ,SCB5_UART_TX , , , , , ,GFXSS_DBI_D6 , , , , , +Port17,P17_2, ,TCPWM0_LINE_COMPL2 ,TCPWM0_LINE_COMPL258 , , , ,SCB11_SPI_CLK ,SCB11_I2C_SCL ,SCB11_UART_RX , , , , , ,GFXSS_DBI_D7 , , , , , +Port17,P17_3, ,TCPWM0_LINE_COMPL3 ,TCPWM0_LINE_COMPL259 , , , ,SCB11_SPI_MOSI ,SCB11_I2C_SDA ,SCB11_UART_TX , , , , , , , , , , , +Port17,P17_4, ,TCPWM0_LINE_COMPL4 ,TCPWM0_LINE_COMPL260 , , , , , , , , , , , , , , , ,PASS_LPPASS_DOUT0 , +Port17,P17_5, ,TCPWM0_LINE_COMPL5 ,TCPWM0_LINE_COMPL261 , , , ,SCB11_SPI_MISO , ,SCB11_UART_CTS, , , , , , , , , ,PASS_LPPASS_DOUT1 , +Port17,P17_6, ,TCPWM0_LINE_COMPL6 ,TCPWM0_LINE_COMPL278 , , , ,SCB11_SPI_SELECT0, ,SCB11_UART_RTS, , , , , , , , , ,PASS_LPPASS_DOUT2 , +Port17,P17_7, ,TCPWM0_LINE_COMPL7 ,TCPWM0_LINE_COMPL279 , , , ,SCB11_SPI_SELECT1, , , , , , , , , , , ,PASS_LPPASS_DOUT3 , +Port18,P18_0, , , , , , , , , , , , , , , , , , , , +Port18,P18_1, , , , , , , , , , , , , , , , , , , , +Port19,P19_0, , , , , , , , , , , , , , , , , , , , +Port19,P19_1, , , , , , , , , , , , , , , , , , , , +Port20,P20_0, ,TCPWM0_LINE7 ,TCPWM0_LINE_COMPL263 , , , ,SCB1_SPI_SELECT1 , , , , , , , , ,DEBUG600_TRACE_CLOCK , , , , +Port20,P20_1, ,TCPWM0_LINE0 ,TCPWM0_LINE_COMPL264 , , , , , , , , , , , , ,DEBUG600_TRACE_DATA3 , , , , +Port20,P20_2, ,TCPWM0_LINE1 ,TCPWM0_LINE_COMPL265 , , , , , , , , , , , , ,DEBUG600_TRACE_DATA2 , , , , +Port20,P20_3, ,TCPWM0_LINE2 ,TCPWM0_LINE_COMPL266 , , , , , , , , , , , , ,DEBUG600_TRACE_DATA1 , , , , +Port20,P20_4, ,TCPWM0_LINE_COMPL7 ,TCPWM0_LINE263 , ,CANFD0_TTCAN_RX0, , , , , , , , , , ,DEBUG600_TRACE_DATA0 , , ,PASS_LPPASS_OBSRV0, +Port20,P20_5, ,TCPWM0_LINE_COMPL0 ,TCPWM0_LINE264 , ,CANFD0_TTCAN_TX0, , , , , , , , , , , , , ,PASS_LPPASS_OBSRV1, +Port20,P20_6, ,TCPWM0_LINE_COMPL1 ,TCPWM0_LINE265 , ,CANFD0_TTCAN_RX1, , , , , , , , , , , , , ,PASS_LPPASS_OBSRV2, +Port20,P20_7, ,TCPWM0_LINE_COMPL2 ,TCPWM0_LINE266 , ,CANFD0_TTCAN_TX1, , , , , , , , , , , , , ,PASS_LPPASS_OBSRV3, +Port21,P21_0, ,TCPWM0_LINE3 ,TCPWM0_LINE267 , , , , , , , , , , , , ,SDHC0_CARD_CMD , , , , +Port21,P21_1, ,TCPWM0_LINE_COMPL3 ,TCPWM0_LINE_COMPL267 , , , , ,TDM_TDM_TX_SD0 , , , , , , , ,SDHC0_CARD_DETECT_N , , , , +Port21,P21_2, ,TCPWM0_LINE4 ,TCPWM0_LINE268 , , , , ,TDM_TDM_TX_SCK0 , , , , , , , ,SDHC0_CARD_MECH_WRITE_PROT , , , , +Port21,P21_3, ,TCPWM0_LINE_COMPL4 ,TCPWM0_LINE_COMPL268 , , , , ,TDM_TDM_TX_MCK0 , , , , , , , ,SDHC0_IO_VOLT_SEL , , , , +Port21,P21_4, ,TCPWM0_LINE5 ,TCPWM0_LINE269 , ,SCB3_SPI_MISO , ,SCB3_UART_CTS ,TDM_TDM_RX_SD0 , , , , , , , ,SDHC0_CARD_IF_PWR_EN , , , , +Port21,P21_5, ,TCPWM0_LINE_COMPL5 ,TCPWM0_LINE_COMPL269 , ,SCB3_SPI_MOSI ,SCB3_I2C_SDA ,SCB3_UART_TX ,TDM_TDM_RX_FSYNC0, , , , , , , , , , , , +Port21,P21_6, ,TCPWM0_LINE6 ,TCPWM0_LINE270 , ,SCB3_SPI_CLK ,SCB3_I2C_SCL ,SCB3_UART_RX ,TDM_TDM_RX_SCK0 , , , , , , , , , , , , +Port21,P21_7,SMIF1_SMIF0_SPIHB_SELECT0,TCPWM0_LINE_COMPL6 ,TCPWM0_LINE_COMPL270 , ,SCB3_SPI_SELECT1, ,SCB3_UART_RTS ,TDM_TDM_RX_MCK0 , , , , , , , , , , , , diff --git a/ports/psoc-edge/clk.c b/ports/psoc-edge/clk.c new file mode 100644 index 00000000000..51907043c18 --- /dev/null +++ b/ports/psoc-edge/clk.c @@ -0,0 +1,314 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "pse84_config.h" +#include "cy_device.h" +#include "cy_sysclk.h" +#include "py/misc.h" +#include "py/runtime.h" + +#include "clk.h" + +#define DEBUG_printf(...) // printf(__VA_ARGS__) +#define clk_assert_raise_val(msg, ret) if (ret != CY_SYSCLK_SUCCESS) { \ + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT(msg), ret); \ +} + +/** + * Value extracted from TRM. + */ + #define PERI_PCLK_DIVIDER_MAX_NUM 26 + +#define CLK_DEST_PERI(clk_dest) ((clk_dest) & PERI_PCLK_PERI_NUM_Msk) +#define CLK_DEST_GROUP(clk_dest) (((clk_dest) & PERI_PCLK_GR_NUM_Msk) >> PERI_PCLK_GR_NUM_Pos) +#define CLK_DEST_INST(clk_dest) (((clk_dest) & PERI_PCLK_INST_NUM_Msk) >> PERI_PCLK_INST_NUM_Pos) + +#define PCLK_DIV_NO_FREE_DIVIDER 0xFF + +typedef struct _pclk_div_obj_t { + uint32_t peri_inst; + uint32_t group; + cy_en_divider_types_t type; + uint32_t number; + uint32_t value; + uint8_t value_frac; + uint8_t owner_count; +} pclk_div_obj_t; + +static pclk_div_obj_t *pclk_div_obj[PERI_PCLK_DIVIDER_MAX_NUM] = {NULL}; + +static pclk_div_obj_t *pclk_div_obj_alloc(void) { + pclk_div_obj_t *clk = NULL; + for (int i = 0; i < PERI_PCLK_DIVIDER_MAX_NUM; i++) { + if (pclk_div_obj[i] == NULL) { + clk = m_new_obj(pclk_div_obj_t); + pclk_div_obj[i] = clk; + break; + } + } + return clk; +} + +static void pclk_div_obj_free(pclk_div_obj_t *clk) { + for (int i = 0; i < PERI_PCLK_DIVIDER_MAX_NUM; i++) { + if (pclk_div_obj[i] == clk) { + m_del_obj(pclk_div_obj_t, clk); + pclk_div_obj[i] = NULL; + break; + } + } +} + +static pclk_div_obj_t *pclk_div_find(en_clk_dst_t clk_dst, uint32_t divider_value, uint8_t divider_value_frac) { + pclk_div_obj_t *clk = NULL; + for (int i = 0; i < PERI_PCLK_DIVIDER_MAX_NUM; i++) { + if (pclk_div_obj[i] != NULL) { + if (pclk_div_obj[i]->value == divider_value && + pclk_div_obj[i]->value_frac == divider_value_frac && + pclk_div_obj[i]->peri_inst == CLK_DEST_INST(clk_dst) && + pclk_div_obj[i]->group == CLK_DEST_GROUP(clk_dst)) { + DEBUG_printf("DEBUG: pclk_div_obj found for peri_inst=%u, group=%u, number=%u, divider=%u, divider_frac=%u\n", CLK_DEST_INST(clk_dst), CLK_DEST_GROUP(clk_dst), pclk_div_obj[i]->number, divider_value, divider_value_frac); + return pclk_div_obj[i]; + } + } + } + return clk; +} + +static void pclk_div_share(en_clk_dst_t clk_dst, pclk_div_obj_t *clk) { + cy_en_sysclk_status_t ret = Cy_SysClk_PeriphAssignDivider(clk_dst, clk->type, clk->number); + clk_assert_raise_val("failed to share divider (PDL err: %lu)", ret); + DEBUG_printf("DEBUG: pclk_div_obj shared for dest = %u\n", clk_dst); + clk->owner_count++; +} + +static pclk_div_obj_t *pclk_div_new_assign_set_enable(en_clk_dst_t clk_dst, cy_en_divider_types_t div_type, uint32_t div_num, uint32_t divider, uint8_t divider_frac) { + uint32_t peri_inst = CLK_DEST_INST(clk_dst); + uint32_t group = CLK_DEST_GROUP(clk_dst); + + pclk_div_obj_t *pclk = pclk_div_obj_alloc(); + if (pclk == NULL) { + return NULL; + } + + pclk->peri_inst = peri_inst; + pclk->group = group; + pclk->type = div_type; + pclk->number = div_num; + pclk->value = divider; + pclk->value_frac = divider_frac; + pclk->owner_count = 1; + + DEBUG_printf("DEBUG: pclk_div_obj(peri_inst=%u, group=%u, div_type=%u, div_num=%u, divider=%u, divider_frac=%u)\n", + peri_inst, group, div_type, div_num, divider, divider_frac); + + cy_en_sysclk_status_t ret = Cy_SysClk_PeriphAssignDivider(clk_dst, div_type, div_num); + clk_assert_raise_val("failed to assign divider (PDL err: %lu)", ret); + + if (div_type == CY_SYSCLK_DIV_16_5_BIT || div_type == CY_SYSCLK_DIV_24_5_BIT) { + ret = Cy_SysClk_PeriPclkSetFracDivider(clk_dst, div_type, div_num, divider, divider_frac); + clk_assert_raise_val("failed to set fractional divider (PDL err: %lu)", ret); + } else { + ret = Cy_SysClk_PeriPclkSetDivider(clk_dst, div_type, div_num, divider); + clk_assert_raise_val("failed to set divider (PDL err: %lu)", ret); + } + ret = Cy_SysClk_PeriPclkEnableDivider(clk_dst, div_type, div_num); + clk_assert_raise_val("failed to enable divider (PDL err: %lu)", ret); + + DEBUG_printf("DEBUG: pclk_div_obj assigned, set, enabled on dest=%u.\n", clk_dst); + + return pclk; +} + +static cy_en_divider_types_t pclk_div_get_type(uint32_t divider, uint8_t divider_frac) { + /* If fractional part is needed, use fractional divider types */ + if (divider_frac != 0) { + if (divider <= 0xFFFFU) { + return CY_SYSCLK_DIV_16_5_BIT; + } else { + return CY_SYSCLK_DIV_24_5_BIT; + } + } + + /* No fractional part needed, use integer dividers */ + if (divider <= 0xFFU) { + return CY_SYSCLK_DIV_8_BIT; + } else if (divider <= 0xFFFFU) { + return CY_SYSCLK_DIV_16_BIT; + } else { + return CY_SYSCLK_DIV_24_5_BIT; + } +} + +static uint8_t pclk_div_get_max_num_for_peri_group(en_clk_dst_t clk_dst, cy_en_divider_types_t div_type) { + uint32_t peri_inst = CLK_DEST_INST(clk_dst); + uint32_t group_num = CLK_DEST_GROUP(clk_dst); + uint8_t max_num = 0; + + if (div_type == CY_SYSCLK_DIV_8_BIT) { + max_num = PERI_PCLK_GR_DIV_8_NR(peri_inst, group_num); + } else if (div_type == CY_SYSCLK_DIV_16_BIT) { + max_num = PERI_PCLK_GR_DIV_16_NR(peri_inst, group_num); + } else if (div_type == CY_SYSCLK_DIV_16_5_BIT) { + max_num = PERI_PCLK_GR_DIV_16_5_NR(peri_inst, group_num); + } else if (div_type == CY_SYSCLK_DIV_24_5_BIT) { + max_num = PERI_PCLK_GR_DIV_24_5_NR(peri_inst, group_num); + } + + return max_num; +} + +static uint8_t pclk_div_get_free_num(en_clk_dst_t clk_dst, cy_en_divider_types_t div_type) { + uint8_t peri_gr_div_max_num = pclk_div_get_max_num_for_peri_group(clk_dst, div_type); + + for (uint8_t i = 0; i < peri_gr_div_max_num; i++) { + bool used = false; + for (uint8_t j = 0; j < PERI_PCLK_DIVIDER_MAX_NUM; j++) { + if (pclk_div_obj[j] != NULL) { + if (pclk_div_obj[j]->peri_inst == CLK_DEST_INST(clk_dst) && + pclk_div_obj[j]->group == CLK_DEST_GROUP(clk_dst) && + pclk_div_obj[j]->type == div_type && + pclk_div_obj[j]->number == i) { + used = true; + break; + } + } + } + if (!used) { + return i; + } + } + + return PCLK_DIV_NO_FREE_DIVIDER; +} + +/******************************************************************************/ +/** -- Peripheral Clock Divider API -- **/ + +void pclk_div_slave_init(en_clk_dst_t clk_dst, pclk_mmio_slave_num_t clk_slave_num) { + uint32_t peri_inst = CLK_DEST_INST(clk_dst); + uint32_t group = CLK_DEST_GROUP(clk_dst); + if (!Cy_SysClk_IsPeriGroupSlaveEnabled(peri_inst, group, clk_slave_num)) { + Cy_SysClk_PeriGroupSlaveInit(peri_inst, group, clk_slave_num, Cy_Sysclk_PeriPclkGetClkHfNum(clk_dst)); + } +} + +void pclk_div_slave_deinit(en_clk_dst_t clk_dst, pclk_mmio_slave_num_t clk_slave_num) { + uint32_t peri_inst = CLK_DEST_INST(clk_dst); + uint32_t group = CLK_DEST_GROUP(clk_dst); + if (Cy_SysClk_IsPeriGroupSlaveEnabled(peri_inst, group, clk_slave_num)) { + Cy_SysClk_PeriGroupSlaveDeinit(peri_inst, group, clk_slave_num); + } +} + +uint32_t pclk_div_get_input_freq(en_clk_dst_t clk_dst) { + uint32_t hf_clk_source = Cy_Sysclk_PeriPclkGetClkHfNum(clk_dst); + + if (!Cy_SysClk_ClkHfIsEnabled(hf_clk_source)) { + /** + * TODO: + * Currently all this is initialized in "cycfg_clocks.c". + * Therefore, we assume that this is initialized and enabled. + * In the future, maybe the clock management is exposed to + * the user. + */ + return 0; + } + + return Cy_SysClk_ClkHfGetFrequency(hf_clk_source); +} + +pclk_div_obj_t *pclk_div_init(en_clk_dst_t clk_dst, uint32_t divider, uint8_t divider_frac) { + pclk_div_obj_t *pclk = NULL; + + /** + * Look for an existing peripheral clock divider + * which could be reused. + * If found, share it with the caller. + */ + pclk = pclk_div_find(clk_dst, divider, divider_frac); + if (pclk != NULL) { + pclk_div_share(clk_dst, pclk); + return pclk; + } + + /* Get the required divider type base on its value + fractional value */ + cy_en_divider_types_t div_type = pclk_div_get_type(divider, divider_frac); + + /* Get the a free peri-group divider number*/ + uint8_t div_num = pclk_div_get_free_num(clk_dst, div_type); + if (div_num == PCLK_DIV_NO_FREE_DIVIDER) { + return NULL; + } + + return pclk_div_new_assign_set_enable(clk_dst, div_type, div_num, divider, divider_frac); +} + +void pclk_div_deinit(pclk_div_obj_t *clk) { + if (clk == NULL) { + return; + } + + clk->owner_count--; + + /* Still in use by other peripherals */ + if (clk->owner_count > 0) { + return; + } + + uint32_t ip_block = (clk->peri_inst << PERI_PCLK_INST_NUM_Pos) | (clk->group << PERI_PCLK_GR_NUM_Pos); + cy_en_sysclk_status_t ret = Cy_SysClk_PeriPclkDisableDivider(ip_block, clk->type, clk->number); + clk_assert_raise_val("failed to disable divider (PDL err: %lu)", ret); + DEBUG_printf("DEBUG: pclk_div_obj disabled for peri_inst=%u, group=%u, div_type=%u, div_num=%u\n", clk->peri_inst, clk->group, clk->type, clk->number); + + pclk_div_obj_free(clk); +} + + +/******************************************************************************/ +/** -- Static PCLK Divider instance enablement for REPL UART-- **/ + + +static pclk_div_obj_t pclk_div_obj_uart_repl; +void pclk_div_uart_repl_init(void) { + pclk_div_obj_t *pclk = &pclk_div_obj_uart_repl; + pclk->group = CLK_DEST_GROUP(PCLK_SCB2_CLOCK_SCB_EN); + pclk->peri_inst = CLK_DEST_INST(PCLK_SCB2_CLOCK_SCB_EN); + pclk->type = CY_SYSCLK_DIV_8_BIT; + pclk->number = 0; + pclk->value = 72U; // From retarget-io: floor(100000000/(115200*12)) = 72 + pclk->value_frac = 0; + pclk->owner_count = 1; + + pclk_div_obj[0] = pclk; + + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB2_PERI_NR, CY_MMIO_SCB2_GROUP_NR, CY_MMIO_SCB2_SLAVE_NR, CY_MMIO_SCB2_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB2_CLOCK_SCB_EN, CY_SYSCLK_DIV_8_BIT, 0U); + + uint32_t ip_block = (pclk->peri_inst << PERI_PCLK_INST_NUM_Pos) | (pclk->group << PERI_PCLK_GR_NUM_Pos); + Cy_SysClk_PeriPclkSetDivider(ip_block, CY_SYSCLK_DIV_8_BIT, 0U, 72U); + Cy_SysClk_PeriPclkEnableDivider(ip_block, CY_SYSCLK_DIV_8_BIT, 0U); +} diff --git a/ports/psoc-edge/clk.h b/ports/psoc-edge/clk.h new file mode 100644 index 00000000000..b2ec44c05af --- /dev/null +++ b/ports/psoc-edge/clk.h @@ -0,0 +1,42 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_PSOC_EDGE_CLK_H +#define MICROPY_INCLUDED_PSOC_EDGE_CLK_H + +/* Forward declare pclk_div_obj_t */ +typedef struct _pclk_div_obj_t pclk_div_obj_t; + +typedef uint32_t pclk_mmio_slave_num_t; + +void pclk_div_slave_init(en_clk_dst_t clk_dst, pclk_mmio_slave_num_t clk_slave_num); +void pclk_div_slave_deinit(en_clk_dst_t clk_dst, pclk_mmio_slave_num_t clk_slave_num); + +uint32_t pclk_div_get_input_freq(en_clk_dst_t clk_dst); +pclk_div_obj_t *pclk_div_init(en_clk_dst_t clk_dst, uint32_t divider, uint8_t divider_frac); +void pclk_div_deinit(pclk_div_obj_t *clk); + +#endif // MICROPY_INCLUDED_PSOC_EDGE_CLK_H diff --git a/ports/psoc-edge/config/shift_ns.json b/ports/psoc-edge/config/shift_ns.json new file mode 100644 index 00000000000..4d67c395f23 --- /dev/null +++ b/ports/psoc-edge/config/shift_ns.json @@ -0,0 +1,29 @@ +{ + "schema-version": 1.0, + "content": + [ + { + "name": "relocate_non_secure_hex", + "enabled" : true, + "commands" : + [ + { + "command" : "hex-relocate", + "inputs" : + [ + { + "file" : "{{ ns_hex }}", + "regions" : "{{RelocationTable}}" + } + ], + "outputs": + [ + { + "file" : "{{ ns_shifted_hex }}" + } + ] + } + ] + } + ] +} diff --git a/ports/psoc-edge/config/sign_s.json b/ports/psoc-edge/config/sign_s.json new file mode 100644 index 00000000000..db27012d5e4 --- /dev/null +++ b/ports/psoc-edge/config/sign_s.json @@ -0,0 +1,33 @@ +{ + "schema-version": 1.0, + "content": + [ + { + "name": "sign_secboot_hex", + "enabled" : true, + "commands" : + [ + { + "command" : "sign", + "inputs" : + [ + { + "file" : "{{ s_hex }}", + "header-size": "0x400", + "fill-value" : "0xff", + "slot-size" : "0x240000", + "hex-address" : "{{CYMEM_CM33_0_S_m33s_nvm_S_START}}" + } + ], + "outputs": + [ + { + "file" : "{{ s_signed_hex }}", + "format": "ihex" + } + ] + } + ] + } + ] +} \ No newline at end of file diff --git a/ports/psoc-edge/config/sign_shift_merge.json b/ports/psoc-edge/config/sign_shift_merge.json new file mode 100644 index 00000000000..1a654b3b9f6 --- /dev/null +++ b/ports/psoc-edge/config/sign_shift_merge.json @@ -0,0 +1,83 @@ +{ + "schema-version": 1.0, + "content": + [ + { + "name": "sign_secboot_hex", + "enabled" : true, + "commands" : + [ + { + "command" : "sign", + "inputs" : + [ + { + "file" : "{{ s_hex }}", + "header-size": "0x400", + "fill-value" : "0xff", + "slot-size" : "0x240000", + "hex-address" : "{{CYMEM_CM33_0_S_m33s_nvm_S_START}}" + } + ], + "outputs": + [ + { + "file" : "{{ s_signed_hex }}", + "format": "ihex" + } + ] + } + ] + }, + { + "name": "relocate_non_secure_hex", + "enabled" : true, + "commands" : + [ + { + "command" : "hex-relocate", + "inputs" : + [ + { + "file" : "{{ ns_hex }}", + "regions" : "{{RelocationTable}}" + } + ], + "outputs": + [ + { + "file" : "{{ ns_shifted_hex }}" + } + ] + } + ] + }, + { + "name": "merge_sec_non_secure_hex", + "enabled": true, + "commands" : + [ + { + "command" : "merge", + "inputs" : + [ + { + "file" : "{{ s_signed_hex }}" + }, + { + "file" : "{{ ns_shifted_hex }}" + } + ], + "outputs" : + [ + { + "file" : "{{ signed_merged_hex }}", + "format" : "ihex", + "overlap" : "error" + } + ] + } + ] + } + ] +} diff --git a/ports/psoc-edge/help.c b/ports/psoc-edge/help.c new file mode 100644 index 00000000000..716d08150b7 --- /dev/null +++ b/ports/psoc-edge/help.c @@ -0,0 +1,42 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022-2024 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +const char psoc_edge_help_text[] = + "Welcome to MicroPython!\n" + "\n" + "For online help please visit https://micropython.org/help/.\n" + "\n" + "For access to the hardware use the 'machine' module.\n" + "PSOC™ Edge specific commands are in the 'psoc-edge' module.\n" + "\n" + "Useful control commands:\n" + " CTRL-C -- interrupt a running program\n" + " CTRL-D -- on a blank line, do a soft reset of the board\n" + " CTRL-E -- on a blank line, enter paste mode\n" + "\n" + "For further help on a specific object, type help(obj)\n" + "For a list of available modules, type help('modules')\n" +; diff --git a/ports/psoc-edge/machine_pin.c b/ports/psoc-edge/machine_pin.c new file mode 100644 index 00000000000..cc7b0e3a426 --- /dev/null +++ b/ports/psoc-edge/machine_pin.c @@ -0,0 +1,558 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "cy_gpio.h" + +#include "extmod/modmachine.h" +#include "extmod/virtpin.h" +#include "machine_pin.h" + +#define pin_assert_raise_val(msg, ret) if (ret != CY_RSLT_SUCCESS) { \ + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT(msg), ret); \ +} + +#define MACHINE_PIN_OUT_VAL_UNDEF 0xFFU + +uint8_t pin_get_mode(const machine_pin_obj_t *self) { + uint32_t drive_mode = Cy_GPIO_GetDrivemode(Cy_GPIO_PortToAddr(self->port), self->pin); + + switch (drive_mode) { + case CY_GPIO_DM_HIGHZ: + case CY_GPIO_DM_PULLUP_DOWN: + return GPIO_MODE_IN; + + case CY_GPIO_DM_STRONG: + return GPIO_MODE_OUT; + + case CY_GPIO_DM_OD_DRIVESLOW: + case CY_GPIO_DM_PULLUP: + return GPIO_MODE_OPEN_DRAIN; + + default: + return GPIO_MODE_NONE; + } +} + +static inline uint8_t pin_get_out_value(const machine_pin_obj_t *self) { + return Cy_GPIO_ReadOut(Cy_GPIO_PortToAddr(self->port), self->pin); +} + +static uint8_t pin_get_pull(const machine_pin_obj_t *self) { + uint32_t drive_mode = Cy_GPIO_GetDrivemode(Cy_GPIO_PortToAddr(self->port), self->pin); + + switch (drive_mode) { + case CY_GPIO_DM_PULLUP: + return GPIO_PULL_UP; + + case CY_GPIO_DM_PULLUP_DOWN: + return (pin_get_out_value(self) == 1) ? GPIO_PULL_UP : GPIO_PULL_DOWN; + + default: + return GPIO_PULL_NONE; + } +} + +static inline uint32_t pin_get_drive(const machine_pin_obj_t *self) { + return Cy_GPIO_GetDriveSel(Cy_GPIO_PortToAddr(self->port), self->pin); +} + +static inline void pin_set_drive(const machine_pin_obj_t *self, uint32_t drive) { + Cy_GPIO_SetDriveSel(Cy_GPIO_PortToAddr(self->port), self->pin, drive); +} + +static inline void pin_init_default(const machine_pin_obj_t *self) { + Cy_GPIO_Pin_FastInit(Cy_GPIO_PortToAddr(self->port), self->pin, CY_GPIO_DM_HIGHZ, 0, HSIOM_SEL_GPIO); +} + +qstr get_mode_str(uint8_t mode) { + switch (mode) { + case GPIO_MODE_IN: + return MP_QSTR_IN; + case GPIO_MODE_OUT: + return MP_QSTR_OUT; + case GPIO_MODE_OPEN_DRAIN: + return MP_QSTR_OPEN_DRAIN; + default: + return MP_QSTR_None; + } +} + +qstr get_pull_str(uint8_t pull) { + switch (pull) { + case GPIO_PULL_UP: + return MP_QSTR_PULL_UP; + case GPIO_PULL_DOWN: + return MP_QSTR_PULL_DOWN; + default: + return MP_QSTR_None; + } +} + +/** + * Get the PDL drive mode configuration for the given pin mode + * and pull configuration. + * The initial value is also validated and set to a coherent + * value with the pull configuration if not defined by the user. + */ +uint32_t get_drive_mode(uint8_t mode, uint8_t pull, uint8_t *value) { + uint32_t drive_mode = CY_GPIO_DM_INVALID; + + /* -- Pin.IN -- */ + if (mode == GPIO_MODE_IN) { + if (*value != MACHINE_PIN_OUT_VAL_UNDEF) { + mp_printf(&mp_plat_print, "machine.Pin warning: initial value is ignored for Pin.IN mode\n"); + } + if (pull == GPIO_PULL_NONE) { + drive_mode = CY_GPIO_DM_HIGHZ; + } else if (pull == GPIO_PULL_UP) { + drive_mode = CY_GPIO_DM_PULLUP_DOWN; + *value = 1; + } else if (pull == GPIO_PULL_DOWN) { + drive_mode = CY_GPIO_DM_PULLUP_DOWN; + *value = 0; + } else { + drive_mode = CY_GPIO_DM_INVALID; + } + /* -- Pin.OUT -- */ + } else if (mode == GPIO_MODE_OUT) { + if (*value == MACHINE_PIN_OUT_VAL_UNDEF) { + *value = 0; // Default to low + } + if (pull == GPIO_PULL_NONE) { + drive_mode = CY_GPIO_DM_STRONG; + } else { + drive_mode = CY_GPIO_DM_INVALID; + } + /** + * Pull resistors not configurable for output mode + */ + /* -- Pin.OPEN_DRAIN -- */ + } else if (mode == GPIO_MODE_OPEN_DRAIN) { + if (*value == MACHINE_PIN_OUT_VAL_UNDEF) { + *value = 1; // Default to high + } + if (pull == GPIO_PULL_NONE) { + drive_mode = CY_GPIO_DM_OD_DRIVESLOW; + } else if (pull == GPIO_PULL_UP) { + drive_mode = CY_GPIO_DM_PULLUP; + } else { + drive_mode = CY_GPIO_DM_INVALID; + } + /* -- Pin.None (invalid) -- */ + } else if (mode == GPIO_MODE_NONE) { + drive_mode = CY_GPIO_DM_INVALID; + } + + if (drive_mode == CY_GPIO_DM_INVALID) { + qstr mode_qstr = get_mode_str(mode); + qstr pull_qstr = get_pull_str(pull); + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("machine.Pin with mode=Pin.%q + pull=Pin.%q is not supported"), mode_qstr, pull_qstr); + } + + return drive_mode; +} + +static inline void assert_mode(uint8_t mode) { + if (mode != GPIO_MODE_IN && mode != GPIO_MODE_OUT && mode != GPIO_MODE_OPEN_DRAIN) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("machine.Pin invalid mode %d. Valid modes are: Pin.IN, Pin.OUT, Pin.OPEN_DRAIN"), mode); + } +} + +static inline void assert_pull(uint8_t pull) { + if (pull != GPIO_PULL_NONE && pull != GPIO_PULL_UP && pull != GPIO_PULL_DOWN) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("machine.Pin invalid pull %d. Valid pulls are: Pin.PULL_NONE, Pin.PULL_UP, Pin.PULL_DOWN"), pull); + } +} + +static inline void assert_drive(uint32_t drive) { + if (drive > CY_GPIO_DRIVE_SEL_7) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("machine.Pin invalid drive %d. Valid drives are: 0-7"), drive); + } +} + +static inline void assert_value(uint8_t value) { + if (value != 0 && value != 1) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("machine.Pin invalid value %d. Valid values are: 0, 1"), value); + } +} + +const machine_pin_obj_t *machine_pin_get_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name) { + const mp_map_t *named_map = &named_pins->map; + mp_map_elem_t *named_elem = mp_map_lookup((mp_map_t *)named_map, name, MP_MAP_LOOKUP); + if (named_elem != NULL && named_elem->value != MP_OBJ_NULL) { + return MP_OBJ_TO_PTR(named_elem->value); + } + return NULL; +} + +const machine_pin_obj_t *machine_pin_get_af_pin(machine_pin_af_unit_t af_unit, machine_pin_af_signal_t af_signal) { + const mp_map_t *cpu_map = &machine_pin_cpu_pins_locals_dict.map; + + for (size_t i = 0; i < cpu_map->alloc; i++) { + const mp_map_elem_t *elem = &cpu_map->table[i]; + if (elem->value == MP_OBJ_NULL) { + continue; + } + + const machine_pin_obj_t *pin = MP_OBJ_TO_PTR(elem->value); + for (uint8_t j = 0; j < pin->af_num; j++) { + const machine_pin_af_obj_t *af = &pin->af[j]; + if (af->unit == af_unit && af->signal == af_signal) { + return pin; + } + } + } + + return NULL; +} + +const machine_pin_obj_t *machine_pin_get_pin_obj(mp_obj_t obj) { + const machine_pin_obj_t *pin_obj; + + // pin can a pin object already + if (mp_obj_is_type(obj, &machine_pin_type)) { + return MP_OBJ_TO_PTR(obj); + } + + // pin can be a board named pin + pin_obj = machine_pin_get_named_pin(&machine_pin_board_pins_locals_dict, obj); + if (pin_obj) { + return pin_obj; + } + + // pin can be a cpu named pin + pin_obj = machine_pin_get_named_pin(&machine_pin_cpu_pins_locals_dict, obj); + if (pin_obj) { + return pin_obj; + } + + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin(%s) doesn't exist"), mp_obj_str_get_str(obj)); +} + +/******************************************************************************/ +// MicroPython bindings + +static mp_obj_t machine_pin_obj_init_helper(const machine_pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + enum { + ARG_mode, ARG_pull, ARG_drive, ARG_value + }; + static const mp_arg_t allowed_args[] = { + {MP_QSTR_mode, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE}}, + {MP_QSTR_pull, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_INT(-1)}}, + {MP_QSTR_drive, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE}}, + {MP_QSTR_value, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE}} + }; + + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + uint8_t mode = pin_get_mode(self); + if (args[ARG_mode].u_obj != mp_const_none) { + mode = mp_obj_get_uint(args[ARG_mode].u_obj); + assert_mode(mode); + } + + uint8_t pull; + if (args[ARG_pull].u_obj == mp_const_none) { + pull = GPIO_PULL_NONE; + } else { + mp_int_t p = mp_obj_get_int(args[ARG_pull].u_obj); + if (p == -1) { + pull = pin_get_pull(self); + } else { + pull = p; + } + } + assert_pull(pull); + + uint8_t value = MACHINE_PIN_OUT_VAL_UNDEF; + if (args[ARG_value].u_obj != mp_const_none) { + value = mp_obj_is_true(args[ARG_value].u_obj); + assert_value(value); + } + + uint32_t drive = pin_get_drive(self); + if (args[ARG_drive].u_obj != mp_const_none) { + drive = mp_obj_get_uint(args[ARG_drive].u_obj); + assert_drive(drive); + } + + mp_hal_pin_config(self, mode, pull, value); + pin_set_drive(self, drive); + + return mp_const_none; +} + +mp_obj_t mp_pin_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 1, 6, true); + + const machine_pin_obj_t *self = machine_pin_get_pin_obj(args[0]); + pin_init_default(self); + + if (n_args > 1 || n_kw > 0) { + // pin mode given, so configure this GPIO + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + machine_pin_obj_init_helper(self, n_args - 1, args + 1, &kw_args); // skipping "id" as an arg as it is a part of self*. + } + + return MP_OBJ_FROM_PTR(self); +} + +static mp_obj_t machine_pin_obj_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { + return machine_pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args); +} +MP_DEFINE_CONST_FUN_OBJ_KW(machine_pin_obj_init_obj, 1, machine_pin_obj_init); + +static void machine_pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "Pin(Pin.cpu.%q", self->name); + + uint8_t mode = pin_get_mode(self); + qstr mode_qst = get_mode_str(mode); + if (mode_qst != MP_QSTR_None) { + mp_printf(print, ", mode=Pin.%q", mode_qst); + } + + uint8_t pull = pin_get_pull(self); + qstr pull_qst = get_pull_str(pull); + if (pull_qst != MP_QSTR_None) { + mp_printf(print, ", pull=Pin.%q", pull_qst); + } + mp_print_str(print, ")"); +} + +static mp_obj_t machine_pin_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, 1, false); + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (n_args == 0) { + // get pin + return MP_OBJ_NEW_SMALL_INT(mp_hal_pin_read(self)); + } else { + // set pin + mp_hal_pin_write(self, mp_obj_is_true(args[0])); + return mp_const_none; + } +} + +static mp_obj_t machine_pin_value(size_t n_args, const mp_obj_t *args) { + return machine_pin_call(args[0], n_args - 1, 0, args + 1); +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_pin_value_obj, 1, 2, machine_pin_value); + +static mp_obj_t machine_pin_off(mp_obj_t self_in) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_hal_pin_low(self); + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_off_obj, machine_pin_off); + +static mp_obj_t machine_pin_on(mp_obj_t self_in) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_hal_pin_high(self); + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_on_obj, machine_pin_on); + +static mp_obj_t machine_pin_toggle(mp_obj_t self_in) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (mp_hal_pin_read(self)) { + mp_hal_pin_low(self); + } else { + mp_hal_pin_high(self); + } + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_toggle_obj, machine_pin_toggle); + +static mp_obj_t machine_pin_mode(size_t n_args, const mp_obj_t *args) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(args[0]); + if (n_args == 1) { + return MP_OBJ_NEW_SMALL_INT(pin_get_mode(self)); + } else { + uint8_t mode = mp_obj_get_uint(args[1]); + assert_mode(mode); + mp_hal_pin_config(self, mode, GPIO_PULL_NONE, MACHINE_PIN_OUT_VAL_UNDEF); + return mp_const_none; + } +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_pin_mode_obj, 1, 2, machine_pin_mode); + +static mp_obj_t machine_pin_pull(size_t n_args, const mp_obj_t *args) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(args[0]); + if (n_args == 1) { + uint8_t pull = pin_get_pull(self); + if (pull == GPIO_PULL_NONE) { + return mp_const_none; + } else { + return MP_OBJ_NEW_SMALL_INT(pull); + } + } else { + uint8_t pull = (args[1] == mp_const_none) ? GPIO_PULL_NONE : mp_obj_get_uint(args[1]); + assert_pull(pull); + mp_hal_pin_config(self, pin_get_mode(self), pull, MACHINE_PIN_OUT_VAL_UNDEF); + return mp_const_none; + } +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_pin_pull_obj, 1, 2, machine_pin_pull); + + +static mp_obj_t machine_pin_drive(size_t n_args, const mp_obj_t *args) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(args[0]); + if (n_args == 1) { + return MP_OBJ_NEW_SMALL_INT(pin_get_drive(self)); + } else { + uint32_t drive = mp_obj_get_uint(args[1]); + assert_drive(drive); + pin_set_drive(self, drive); + return mp_const_none; + } +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_pin_drive_obj, 1, 2, machine_pin_drive); + +extern mp_obj_t machine_pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args); +static MP_DEFINE_CONST_FUN_OBJ_KW(machine_pin_irq_obj, 1, machine_pin_irq); + +/** + * void machine_pin_deinit_all(void) { + * Not implemented. + * + * Rationale: + * There is no PDL API to deinitialize a single pin, only at the port level via + * void Cy_GPIO_Port_Deinit(GPIO_PRT_Type *base). + * If we deinitialize an entire port, we will end up deinitializing other + * pins that are used by MicroPython but not defined at the user level, + * such as the REPL UART interface pins. Thus, breaking basic core functionalities. + * + * This means that after a soft reset, pins will retain their + * configuration, which is not ideal since the system is not starting in + * the same state. + * This should not be a problem since pins can be reconfigured if reused, + * and if not reused, they won't be in scope after reset. + * The pin itself is not deinitialized, but its IRQ (if enabled) will be cleared, + * disabled, and deinitialized upon soft reset. That should be sufficient to + * prevent unexpected behavior. + * + * Discarded solutions: + * We could reset pins to default values, but we don't know if there is + * a single valid default configuration for all pins. Other initial + * value tracking mechanisms would also overcomplicate the code. + * Therefore, at the moment, such solutions don't seem worth it. + * } + */ + +static mp_uint_t pin_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) { + (void)errcode; + machine_pin_obj_t *self = self_in; + + switch (request) { + case MP_PIN_READ: { + return mp_hal_pin_read(self); + } + case MP_PIN_WRITE: { + mp_hal_pin_write(self, arg); + return 0; + } + } + return -1; +} + +static const mp_pin_p_t pin_pin_p = { + .ioctl = pin_ioctl, +}; + +MP_DEFINE_CONST_OBJ_TYPE( + pin_cpu_pins_obj_type, + MP_QSTR_cpu, + MP_TYPE_FLAG_NONE, + locals_dict, &machine_pin_cpu_pins_locals_dict + ); + +MP_DEFINE_CONST_OBJ_TYPE( + pin_board_pins_obj_type, + MP_QSTR_board, + MP_TYPE_FLAG_NONE, + locals_dict, &machine_pin_board_pins_locals_dict + ); + +static const mp_rom_map_elem_t machine_pin_locals_dict_table[] = { + // Instance methods + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pin_obj_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&machine_pin_value_obj) }, + { MP_ROM_QSTR(MP_QSTR_off), MP_ROM_PTR(&machine_pin_off_obj) }, + { MP_ROM_QSTR(MP_QSTR_on), MP_ROM_PTR(&machine_pin_on_obj) }, + { MP_ROM_QSTR(MP_QSTR_low), MP_ROM_PTR(&machine_pin_off_obj) }, + { MP_ROM_QSTR(MP_QSTR_high), MP_ROM_PTR(&machine_pin_on_obj) }, + { MP_ROM_QSTR(MP_QSTR_toggle), MP_ROM_PTR(&machine_pin_toggle_obj) }, + { MP_ROM_QSTR(MP_QSTR_mode), MP_ROM_PTR(&machine_pin_mode_obj) }, + { MP_ROM_QSTR(MP_QSTR_pull), MP_ROM_PTR(&machine_pin_pull_obj) }, + { MP_ROM_QSTR(MP_QSTR_drive), MP_ROM_PTR(&machine_pin_drive_obj) }, + { MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&machine_pin_irq_obj) }, + + // class attributes + #if MICROPY_PY_MACHINE_PIN_BOARD_NUM_ENTRIES > 0 + { MP_ROM_QSTR(MP_QSTR_board), MP_ROM_PTR(&pin_board_pins_obj_type) }, + #endif + #if MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES > 0 + { MP_ROM_QSTR(MP_QSTR_cpu), MP_ROM_PTR(&pin_cpu_pins_obj_type) }, + #endif + + // Const + { MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(GPIO_MODE_IN) }, + { MP_ROM_QSTR(MP_QSTR_OUT), MP_ROM_INT(GPIO_MODE_OUT) }, + { MP_ROM_QSTR(MP_QSTR_OPEN_DRAIN), MP_ROM_INT(GPIO_MODE_OPEN_DRAIN) }, + + { MP_ROM_QSTR(MP_QSTR_PULL_UP), MP_ROM_INT(GPIO_PULL_UP) }, + { MP_ROM_QSTR(MP_QSTR_PULL_DOWN), MP_ROM_INT(GPIO_PULL_DOWN) }, + + { MP_ROM_QSTR(MP_QSTR_DRIVE_0), MP_ROM_INT(CY_GPIO_DRIVE_SEL_0) }, + { MP_ROM_QSTR(MP_QSTR_DRIVE_1), MP_ROM_INT(CY_GPIO_DRIVE_SEL_1) }, + { MP_ROM_QSTR(MP_QSTR_DRIVE_2), MP_ROM_INT(CY_GPIO_DRIVE_SEL_2) }, + { MP_ROM_QSTR(MP_QSTR_DRIVE_3), MP_ROM_INT(CY_GPIO_DRIVE_SEL_3) }, + { MP_ROM_QSTR(MP_QSTR_DRIVE_4), MP_ROM_INT(CY_GPIO_DRIVE_SEL_4) }, + { MP_ROM_QSTR(MP_QSTR_DRIVE_5), MP_ROM_INT(CY_GPIO_DRIVE_SEL_5) }, + { MP_ROM_QSTR(MP_QSTR_DRIVE_6), MP_ROM_INT(CY_GPIO_DRIVE_SEL_6) }, + { MP_ROM_QSTR(MP_QSTR_DRIVE_7), MP_ROM_INT(CY_GPIO_DRIVE_SEL_7) }, + + { MP_ROM_QSTR(MP_QSTR_IRQ_FALLING), MP_ROM_INT(CY_GPIO_INTR_FALLING)}, + { MP_ROM_QSTR(MP_QSTR_IRQ_RISING), MP_ROM_INT(CY_GPIO_INTR_RISING)}, +}; + +static MP_DEFINE_CONST_DICT(machine_pin_locals_dict, machine_pin_locals_dict_table); + +MP_DEFINE_CONST_OBJ_TYPE( + machine_pin_type, + MP_QSTR_Pin, + MP_TYPE_FLAG_NONE, + make_new, mp_pin_make_new, + print, machine_pin_print, + call, machine_pin_call, + protocol, &pin_pin_p, + locals_dict, &machine_pin_locals_dict + ); diff --git a/ports/psoc-edge/machine_pin.h b/ports/psoc-edge/machine_pin.h new file mode 100644 index 00000000000..538a35f4e56 --- /dev/null +++ b/ports/psoc-edge/machine_pin.h @@ -0,0 +1,56 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_PSOC_EDGE_MACHINE_PIN_H +#define MICROPY_INCLUDED_PSOC_EDGE_MACHINE_PIN_H + +#include "py/obj.h" +#include "machine_pin_af.h" + +enum {GPIO_MODE_NONE = 0, GPIO_MODE_IN, GPIO_MODE_OUT, GPIO_MODE_OPEN_DRAIN}; + +enum {GPIO_PULL_NONE = 0, GPIO_PULL_UP, GPIO_PULL_DOWN}; + +typedef struct _machine_pin_obj_t { + mp_obj_base_t base; + qstr name; + uint8_t port; + uint8_t pin; + uint8_t af_num; + const machine_pin_af_obj_t *af; +} machine_pin_obj_t; + +extern const mp_obj_type_t machine_pin_type; + +#include "genhdr/pins.h" + +extern const mp_obj_dict_t machine_pin_cpu_pins_locals_dict; +extern const mp_obj_dict_t machine_pin_board_pins_locals_dict; + +const machine_pin_obj_t *machine_pin_get_pin_obj(mp_obj_t obj); +const machine_pin_obj_t *machine_pin_get_af_pin(machine_pin_af_unit_t af_unit, machine_pin_af_signal_t af_signal); + +#endif // MICROPY_INCLUDED_PSOC_EDGE_MACHINE_PIN_H diff --git a/ports/psoc-edge/machine_pin_af.c b/ports/psoc-edge/machine_pin_af.c new file mode 100644 index 00000000000..cc78ec205f5 --- /dev/null +++ b/ports/psoc-edge/machine_pin_af.c @@ -0,0 +1,56 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "machine_pin_af.h" + +const char *machine_pin_af_fn_str[] = { + [MACHINE_PIN_AF_FN_I2C] = "I2C", + [MACHINE_PIN_AF_FN_SPI] = "SPI", + [MACHINE_PIN_AF_FN_UART] = "UART", + [MACHINE_PIN_AF_FN_PDM] = "PDM", + /* TODO: Add additional functionalities */ +}; + +const char *machine_pin_af_signal_str[] = { + [MACHINE_PIN_AF_SIGNAL_I2C_SDA] = "I2C_SDA", + [MACHINE_PIN_AF_SIGNAL_I2C_SCL] = "I2C_SCL", + + [MACHINE_PIN_AF_SIGNAL_SPI_MOSI] = "SPI_MOSI", + [MACHINE_PIN_AF_SIGNAL_SPI_MISO] = "SPI_MISO", + [MACHINE_PIN_AF_SIGNAL_SPI_CLK] = "SPI_CLK", + [MACHINE_PIN_AF_SIGNAL_SPI_SELECT0] = "SPI_SELECT0", + [MACHINE_PIN_AF_SIGNAL_SPI_SELECT1] = "SPI_SELECT1", + + [MACHINE_PIN_AF_SIGNAL_UART_TX] = "UART_TX", + [MACHINE_PIN_AF_SIGNAL_UART_RX] = "UART_RX", + [MACHINE_PIN_AF_SIGNAL_UART_CTS] = "UART_CTS", + [MACHINE_PIN_AF_SIGNAL_UART_RTS] = "UART_RTS", + + [MACHINE_PIN_AF_SIGNAL_PDM_CLK] = "PDM_CLK", + [MACHINE_PIN_AF_SIGNAL_PDM_DATA] = "PDM_DATA", + + /* TODO: Add additional types */ +}; diff --git a/ports/psoc-edge/machine_pin_af.h b/ports/psoc-edge/machine_pin_af.h new file mode 100644 index 00000000000..3027bb4b75a --- /dev/null +++ b/ports/psoc-edge/machine_pin_af.h @@ -0,0 +1,83 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_PSOC_EDGE_MACHINE_PIN_AF_H +#define MICROPY_INCLUDED_PSOC_EDGE_MACHINE_PIN_AF_H + +#include "py/obj.h" +#include "gpio_pse84_bga_220.h" + +typedef enum { + MACHINE_PIN_AF_FN_I2C, + MACHINE_PIN_AF_FN_SPI, + MACHINE_PIN_AF_FN_UART, + + MACHINE_PIN_AF_FN_PDM, + /* TODO: Add additional functionalities */ + + MACHINE_PIN_AF_FN_NONE = 0xFF +} machine_pin_af_fn_t; + +extern const char *machine_pin_af_fn_str[]; + +typedef enum { + MACHINE_PIN_AF_SIGNAL_I2C_SDA, + MACHINE_PIN_AF_SIGNAL_I2C_SCL, + + MACHINE_PIN_AF_SIGNAL_SPI_MOSI, + MACHINE_PIN_AF_SIGNAL_SPI_MISO, + MACHINE_PIN_AF_SIGNAL_SPI_CLK, + MACHINE_PIN_AF_SIGNAL_SPI_SELECT0, + MACHINE_PIN_AF_SIGNAL_SPI_SELECT1, + + MACHINE_PIN_AF_SIGNAL_UART_TX, + MACHINE_PIN_AF_SIGNAL_UART_RX, + MACHINE_PIN_AF_SIGNAL_UART_CTS, + MACHINE_PIN_AF_SIGNAL_UART_RTS, + + MACHINE_PIN_AF_SIGNAL_PDM_CLK, + MACHINE_PIN_AF_SIGNAL_PDM_DATA, + + /* TODO: Add additional types */ +} machine_pin_af_signal_t; + +extern const char *machine_pin_af_signal_str[]; + +#define MACHINE_PIN_AF_UNIT_NONE 0xFF +typedef uint16_t machine_pin_af_unit_t; +typedef void *machine_pin_af_periph_t; + +typedef struct { + en_hsiom_sel_t idx; + machine_pin_af_fn_t fn; + machine_pin_af_unit_t unit; + machine_pin_af_signal_t signal; + machine_pin_af_periph_t periph; +} machine_pin_af_obj_t; + +extern const mp_obj_type_t machine_pin_af_type; + +#endif // MICROPY_INCLUDED_PSOC_EDGE_MACHINE_PIN_AF_H diff --git a/ports/psoc-edge/machine_pin_irq.c b/ports/psoc-edge/machine_pin_irq.c new file mode 100644 index 00000000000..582d5d55bce --- /dev/null +++ b/ports/psoc-edge/machine_pin_irq.c @@ -0,0 +1,333 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "cy_gpio.h" +#include "sys_int.h" + +#include "py/misc.h" +#include "py/runtime.h" +#include "shared/runtime/mpirq.h" +#include "machine_pin.h" + +/* ======================================================================================================================== */ + + +/* Forward declaration */ +static void machine_pin_irq_port_handler(uint8_t port); +/** + * All the pins of one port share the same IRQ handler. + * Therefore, we can replicate the handlers based on the + * available CPU GPIO ports that are exposed to the users. + * + * Alternatively, a single handler could have been used + * for all ports and pins, but that would require sweeping + * all ports and pins, which could be too much for an ISR. + */ +#define DEFINE_GPIO_PORT_IRQ_HANDLER(port) \ + void PORT##port##_IRQ_Handler(void) { \ + machine_pin_irq_port_handler(port); \ + } + +/** + * The file build-/genhdr/pins.h contains the macro + * + * MICROPY_PY_MACHINE_PIN_FOR_ALL_PORTS(DO) + * + * which uses the X-macro (as argument) pattern to pass a worker + * macro DO(port) for the list of all user available ports. + * + * The available (not hidden) user ports are those defined in the + * boards//pins.csv file, which are not prefixed + * with a hyphen(-). + * See tools/boardgen.py and psoc-edge/boards/make-pins.py + * for more information. + */ + +/* Define all GPIO port IRQ handlers */ +MICROPY_PY_MACHINE_PIN_FOR_ALL_PORTS(DEFINE_GPIO_PORT_IRQ_HANDLER) + +/** + * Array of GPIO port IRQ configuration struct look up table. + * + * The IRQ number values are defined in cy_device_headers_ns.h + * files for non-secure core. + * The IRQn_Type value naming are different for the + * secure core as they include "_sec_" in the names. + * TODO: Review if secure core needs to be supported. + * We can add conditional compilation using the macro CY_DEVICE_SECURE. + */ +static sys_int_cfg_t port_irq_cfg[MICROPY_PY_MACHINE_PIN_PORT_NUM_ENTRIES] = { + #define MAP_GPIO_PORT_IRQ_CONFIG(port) [port] = { ioss_interrupts_gpio_##port##_IRQn, SYS_INT_IRQ_LOWEST_PRIORITY, PORT##port##_IRQ_Handler}, + MICROPY_PY_MACHINE_PIN_FOR_ALL_PORTS(MAP_GPIO_PORT_IRQ_CONFIG) +}; + +/* ======================================================================================================================== */ +/* machine_pin_irq struct and API functions */ + +typedef struct _machine_pin_irq_obj_t { + mp_irq_obj_t base; + uint32_t flags; + uint32_t trigger; + sys_int_cfg_t *port_cfg; +} machine_pin_irq_obj_t; + +machine_pin_irq_obj_t *machine_pin_irq_obj[MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES]; + +static machine_pin_irq_obj_t *machine_pin_get_irq_obj(machine_pin_obj_t *pin_obj) { + uint32_t idx = 0; + for (idx = 0; idx < MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES; idx++) { + machine_pin_irq_obj_t *irq = machine_pin_irq_obj[idx]; + if (irq != NULL) { + machine_pin_obj_t *irq_parent = MP_OBJ_TO_PTR(irq->base.parent); + if (irq_parent == pin_obj) { + return irq; + } + } + } + return NULL; +} + +static machine_pin_irq_obj_t *machine_pin_irq_obj_allocate(void) { + for (uint32_t idx = 0; idx < MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES; idx++) { + machine_pin_irq_obj_t *irq = machine_pin_irq_obj[idx]; + if (irq == NULL) { + irq = m_new_obj(machine_pin_irq_obj_t); + machine_pin_irq_obj[idx] = irq; + return irq; + } + } + + mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("no more Pin IRQ objects available")); +} + +static void machine_pin_irq_obj_dealloc(machine_pin_irq_obj_t *irq) { + for (uint32_t idx = 0; idx < MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES; idx++) { + if (machine_pin_irq_obj[idx] == irq) { + m_del_obj(machine_pin_irq_obj_t, irq); + machine_pin_irq_obj[idx] = NULL; + return; + } + } +} + +static machine_pin_irq_obj_t *machine_pin_irq_find(uint8_t port, uint8_t pin) { + for (uint32_t idx = 0; idx < MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES; idx++) { + machine_pin_irq_obj_t *irq = machine_pin_irq_obj[idx]; + if (irq != NULL) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(irq->base.parent); + if (self->port == port && self->pin == pin) { + return irq; + } + } + } + return NULL; +} + +static void machine_pin_irq_port_handler(uint8_t port) { + /** + * All pins in the same port will run the same handler. + * Therefore we iterate over all the pins and check if their interrupt + * status are active. + */ + for (uint8_t pin = 0; pin < CY_GPIO_PINS_MAX; pin++) { + if (Cy_GPIO_GetInterruptStatus(Cy_GPIO_PortToAddr(port), pin)) { + /* Clear the GPIO source first so back-to-back edges can re-latch. */ + Cy_GPIO_ClearInterrupt(Cy_GPIO_PortToAddr(port), pin); + + machine_pin_irq_obj_t *irq = machine_pin_irq_find(port, pin); + + /** + * Update the flags with the current trigger that caused the IRQ. + * There is not a PDL function to get the current trigger, + * so we use the configured trigger as the source of truth. + * This means that if both edges are enabled, the flags will + * indicate both edges even if only one of them caused the IRQ. + */ + irq->flags = irq->trigger; + if (irq->base.handler != mp_const_none) { + mp_irq_handler(&irq->base); + } + } + } +} + +/** + * Returns true if more than one pin irq objects are registered for the same port. + * False otherwise. + */ +static bool machine_pin_irq_are_multiple_pin_irqs_registered_in_port(uint32_t port) { + uint32_t pin_irq_registered_in_port = 0; + for (uint32_t idx = 0; idx < MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES; idx++) { + machine_pin_irq_obj_t *irq = machine_pin_irq_obj[idx]; + if (irq != NULL) { + machine_pin_obj_t *pin_obj = MP_OBJ_TO_PTR(irq->base.parent); + if (pin_obj->port == port) { + if (++pin_irq_registered_in_port > 1) { + return true; + } + } + } + } + return false; +} + +/** + * Set the priority of the port interrupt. + * + * As all port pins share the same interrupt source, if multiple pins have an IRQ + * registered, the desired new priority cannot be lower than the current configured priority. + * This mechanism upgrades the priority of all pin port interrupts to ensure that higher priority + * interrupts are not inadvertently masked by lower priority ones. + */ +static void machine_pin_irq_set_priority(sys_int_cfg_t *port_cfg, uint32_t port, uint32_t priority) { + bool multiple_pin_irq_registered_in_port = machine_pin_irq_are_multiple_pin_irqs_registered_in_port(port); + if (!multiple_pin_irq_registered_in_port) { + port_cfg->priority = priority; + } else { + #define GPIO_PORT_HIGHER_PRIORITY(prio1, prio2) MIN(prio1, prio2) /* A smaller number means higher priority. */ + port_cfg->priority = GPIO_PORT_HIGHER_PRIORITY(port_cfg->priority, priority); + } +} + +#define MP_PIN_IRQ_TRIGGER_DISABLE 0x00UL +#define MP_PIN_IRQ_ALLOWED_FLAGS (CY_GPIO_INTR_RISING | CY_GPIO_INTR_FALLING) + +static void machine_pin_irq_config(machine_pin_irq_obj_t *irq, uint32_t trigger) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(irq->base.parent); + if (trigger == MP_PIN_IRQ_TRIGGER_DISABLE) { + sys_int_deinit(irq->port_cfg); + Cy_GPIO_ClearInterrupt(Cy_GPIO_PortToAddr(self->port), self->pin); + Cy_GPIO_SetInterruptMask(Cy_GPIO_PortToAddr(self->port), self->pin, 0u); + return; + } else { + Cy_GPIO_ClearInterrupt(Cy_GPIO_PortToAddr(self->port), self->pin); + Cy_GPIO_SetInterruptEdge(Cy_GPIO_PortToAddr(self->port), self->pin, trigger); + Cy_GPIO_SetInterruptMask(Cy_GPIO_PortToAddr(self->port), self->pin, 1u); + sys_int_init(irq->port_cfg); + } +} + +static mp_uint_t machine_pin_irq_trigger(mp_obj_t self_in, mp_uint_t trigger) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + machine_pin_irq_obj_t *irq = machine_pin_get_irq_obj(self); + + /* Check the trigger */ + mp_uint_t not_supported = trigger & ~MP_PIN_IRQ_ALLOWED_FLAGS; + if (trigger != 0 && not_supported) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("trigger 0x%08x unsupported"), not_supported); + } + + irq->flags = 0; + irq->trigger = trigger; + + machine_pin_irq_config(irq, trigger); + + return 0; +} + +static mp_uint_t machine_pin_irq_info(mp_obj_t self_in, mp_uint_t info_type) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + machine_pin_irq_obj_t *irq = machine_pin_get_irq_obj(self); + + if (info_type == MP_IRQ_INFO_FLAGS) { + return irq->flags; + } else if (info_type == MP_IRQ_INFO_TRIGGERS) { + return irq->trigger; + } + return 0; +} + +static const mp_irq_methods_t machine_pin_irq_methods = { + .trigger = machine_pin_irq_trigger, + .info = machine_pin_irq_info, +}; + +static void machine_pin_irq_obj_init(machine_pin_irq_obj_t *irq, machine_pin_obj_t *parent_pin) { + mp_irq_init(&irq->base, &machine_pin_irq_methods, MP_OBJ_FROM_PTR(parent_pin)); + irq->flags = 0; + irq->trigger = 0; + irq->port_cfg = &port_irq_cfg[parent_pin->port]; +} + +static void machine_pin_irq_obj_deinit(machine_pin_irq_obj_t *irq) { + irq->base.handler = mp_const_none; + irq->base.ishard = false; + irq->trigger = 0; + irq->flags = 0; + irq->port_cfg = NULL; +} + +mp_obj_t machine_pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + enum { ARG_handler, ARG_trigger, ARG_hard, ARG_priority }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_handler, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_trigger, MP_ARG_INT, {.u_int = CY_GPIO_INTR_RISING | CY_GPIO_INTR_FALLING} }, + { MP_QSTR_hard, MP_ARG_BOOL, {.u_bool = false} }, + { MP_QSTR_priority, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = SYS_INT_IRQ_LOWEST_PRIORITY }}, + }; + + machine_pin_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + machine_pin_irq_obj_t *irq = machine_pin_get_irq_obj(self); + if (irq == NULL) { + irq = machine_pin_irq_obj_allocate(); + machine_pin_irq_obj_init(irq, self); + } + + if (n_args > 1 || kw_args->used != 0) { + /* Check the handler */ + mp_obj_t handler = args[ARG_handler].u_obj; + if (handler != mp_const_none && !mp_obj_is_callable(handler)) { + mp_raise_ValueError(MP_ERROR_TEXT("handler must be None or callable")); + /* If handler is None, disable the IRQ */ + } else if (handler == mp_const_none) { + machine_pin_irq_trigger(self, MP_PIN_IRQ_TRIGGER_DISABLE); + return MP_OBJ_FROM_PTR(irq); + } + irq->base.handler = args[ARG_handler].u_obj; + irq->base.ishard = args[ARG_hard].u_bool; + machine_pin_irq_set_priority(irq->port_cfg, self->port, args[ARG_priority].u_int); + machine_pin_irq_trigger(self, args[ARG_trigger].u_int); + } + + return MP_OBJ_FROM_PTR(irq); +} + +void machine_pin_irq_deinit_all(void) { + for (uint32_t i = 0; i < MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES; i++) { + machine_pin_irq_obj_t *irq = machine_pin_irq_obj[i]; + if (irq != NULL) { + machine_pin_irq_config(irq, MP_PIN_IRQ_TRIGGER_DISABLE); + machine_pin_irq_obj_deinit(irq); + machine_pin_irq_obj_dealloc(irq); + } + } +} + +// Register pin IRQ objects as roots so they are retained by the GC. +MP_REGISTER_ROOT_POINTER(struct _machine_pin_irq_obj_t *machine_pin_irq_obj[MICROPY_PY_MACHINE_PIN_CPU_NUM_ENTRIES]); diff --git a/ports/psoc-edge/machine_rtc.c b/ports/psoc-edge/machine_rtc.c new file mode 100644 index 00000000000..5cd33c2b874 --- /dev/null +++ b/ports/psoc-edge/machine_rtc.c @@ -0,0 +1,592 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2021 "Krzysztof Adamski" + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +// std includes +#include +#include +#include +#include +#include +#include + + +// micropython includes +#include "py/nlr.h" +#include "py/obj.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "py/mperrno.h" +#include "shared/timeutils/timeutils.h" +#include "py/misc.h" + +// port-specific includes +#include "modmachine.h" + +#include "cy_rtc.h" +#include "cybsp.h" + +#define RTC_INIT_YEAR 15 /* 2015 = 2000 + 15 (RTC hardware stores 0-99) */ +#define RTC_INIT_MONTH 1 /* January */ +#define RTC_INIT_MDAY 1 +#define RTC_INIT_WDAY 4 /* Thursday */ +#define RTC_INIT_HOUR 0 +#define RTC_INIT_MINUTE 0 +#define RTC_INIT_SECOND 0 +#define RTC_INIT_DST 0 + +#define RTC_CENTURY (2000u) /* RTC hardware supports years 0-99 = 2000-2099 */ +#define RTC_ACCESS_RETRY_COUNT (500U) +#define RTC_RETRY_DELAY_MS (5U) + +#define RTC_BREG_WORDS (8U) +#define RTC_BREG_META_INDEX (RTC_BREG_WORDS - 1U) +#define RTC_BREG_DATA_WORDS (RTC_BREG_WORDS - 1U) +#define RTC_BREG_MAGIC (0x5254U) + +#ifndef MICROPY_HW_RTC_USER_MEM_MAX +#define MICROPY_HW_RTC_USER_MEM_MAX (RTC_BREG_DATA_WORDS * 4U) +#endif + +#define rtc_assert_raise(msg, ret) if (ret != CY_RSLT_SUCCESS) { \ + mp_raise_ValueError(MP_ERROR_TEXT(msg)); \ +} + +typedef struct _machine_rtc_obj_t { + mp_obj_base_t base; + mp_obj_t callback; + uint64_t alarm_period_s; + uint64_t alarm_elapse_time_s; + bool alarmset; + bool repeat; + volatile bool time_updated; +} machine_rtc_obj_t; + +void srss_interrupt_rtc_IRQHandler(void); + +// singleton RTC object +static machine_rtc_obj_t machine_rtc_obj = { + .base = {&machine_rtc_type}, + .callback = NULL, + .alarm_period_s = 0, + .alarm_elapse_time_s = 0, + .alarmset = false, + .repeat = false, + .time_updated = true, +}; + +static bool rtc_irq_initialized = false; + +static inline void machine_rtc_mark_time_updated(void) { + machine_rtc_obj.time_updated = true; +} + +bool machine_rtc_read_and_clear_time_updated(void) { + bool updated = machine_rtc_obj.time_updated; + machine_rtc_obj.time_updated = false; + return updated; +} + +static inline uint32_t rtc_breg_read(uint32_t index) { + return BACKUP_BREG_SET2[index]; +} + +static inline void rtc_breg_write(uint32_t index, uint32_t value) { + BACKUP_BREG_SET2[index] = value; +} + +static void rtc_interrupt_init(void) { + if (rtc_irq_initialized) { + return; + } + + cy_stc_sysint_t intr_cfg = { + srss_interrupt_rtc_IRQn, + 3, + }; + + cy_en_sysint_status_t rslt = Cy_SysInt_Init(&intr_cfg, srss_interrupt_rtc_IRQHandler); + if (rslt != CY_SYSINT_SUCCESS) { + mp_raise_ValueError(MP_ERROR_TEXT("RTC IRQ init failed")); + } + + rtc_irq_initialized = true; +} + +static bool rtc_validate_date_time(int sec, int min, int hour, int mday, int month, int year_full) { + if (year_full < RTC_CENTURY || year_full > RTC_CENTURY + 99) { + return false; + } + if (month < 1 || month > 12) { + return false; + } + if (mday < 1) { + return false; + } + if (hour < 0 || hour > 23) { + return false; + } + if (min < 0 || min > 59) { + return false; + } + if (sec < 0 || sec > 59) { + return false; + } + + static const uint8_t days_in_month_table[12] = { + 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, + }; + uint8_t days_in_month = days_in_month_table[month - 1]; + if (month == 2 && Cy_RTC_IsLeapYear((uint32_t)year_full)) { + days_in_month++; + } + + return mday <= days_in_month; +} + +void machine_rtc_get_datetime(timeutils_struct_time_t *time) { + cy_stc_rtc_config_t current_date_time = {0}; + Cy_RTC_GetDateAndTime(¤t_date_time); + + time->tm_year = current_date_time.year + RTC_CENTURY; + time->tm_mon = current_date_time.month; + time->tm_mday = current_date_time.date; + time->tm_hour = current_date_time.hour; + time->tm_min = current_date_time.min; + time->tm_sec = current_date_time.sec; + time->tm_wday = current_date_time.dayOfWeek - 1u; + time->tm_yday = timeutils_year_day(current_date_time.year + RTC_CENTURY, current_date_time.month, current_date_time.date); +} + +void machine_rtc_init_all(void) { + /* Variable used to store return status of RTC API */ + cy_en_rtc_status_t rtc_status; + uint32_t rtc_access_retry = RTC_ACCESS_RETRY_COUNT; + + /* RTC block doesn't allow to access, when synchronizing the user registers + * and the internal actual RTC registers. It will return RTC_BUSY value, if + * it is not available to update the configuration values. Needs to retry, + * if it doesn't return CY_RTC_SUCCESS. */ + + do + { + rtc_status = Cy_RTC_Init(&CYBSP_RTC_config); + rtc_access_retry--; + Cy_SysLib_Delay(RTC_RETRY_DELAY_MS); + } while ((rtc_status != CY_RTC_SUCCESS) && (rtc_access_retry != 0)); + + if (rtc_status == CY_RTC_SUCCESS) { + machine_rtc_mark_time_updated(); + } +} + +// Helper function to set/get datetime +// Note: The weekday field is always auto-calculated by the RTC hardware based on the date. +// Even if an invalid weekday is provided in the input tuple, it will be recalculated and +// overwritten with the correct value. datetime() does not raise an error for incorrect +// weekday values - the hardware ensures weekday always matches the actual calendar date. +static mp_obj_t machine_rtc_datetime_helper(mp_uint_t n_args, const mp_obj_t *args) { + if (n_args == 1) { + /* Get the current date and time */ + timeutils_struct_time_t time; + machine_rtc_get_datetime(&time); + mp_obj_t tuple[8] = { + mp_obj_new_int(time.tm_year), + mp_obj_new_int(time.tm_mon), + mp_obj_new_int(time.tm_mday), + mp_obj_new_int(time.tm_wday + 1u), + mp_obj_new_int(time.tm_hour), + mp_obj_new_int(time.tm_min), + mp_obj_new_int(time.tm_sec), + mp_obj_new_int(0), + }; + return mp_obj_new_tuple(8, tuple); + } else { + // Set date and time using direct API + mp_obj_t *items; + mp_obj_get_array_fixed_n(args[1], 8, &items); + + int year_full = mp_obj_get_int(items[0]); + int month = mp_obj_get_int(items[1]); + int date = mp_obj_get_int(items[2]); + // items[3] is dayOfWeek - ignored and auto-calculated by RTC hardware + // The hardware will compute the correct weekday from the year/month/date + int hour = mp_obj_get_int(items[4]); + int min = mp_obj_get_int(items[5]); + int sec = mp_obj_get_int(items[6]); + + if (!rtc_validate_date_time(sec, min, hour, date, month, year_full)) { + mp_raise_ValueError(MP_ERROR_TEXT("invalid date/time")); + } + + uint32_t year = year_full - RTC_CENTURY; + Cy_RTC_SetDateAndTimeDirect(sec, min, hour, date, month, year); + machine_rtc_mark_time_updated(); + } + return mp_const_none; +} + +// Helper to convert datetime tuple to seconds since epoch +static inline uint64_t rtc_get_datetime_in_sec(mp_obj_t datetime) { + size_t len; + mp_obj_t *elem; + mp_obj_get_array(datetime, &len, &elem); + + // Expect tuple of length 8 + if (len < 8 || len > 9) { + mp_raise_TypeError(MP_ERROR_TEXT("datetime tuple needs length 8 or 9")); + } + + // Format: (year, month, day, weekday, hour, minute, second, subseconds) + return timeutils_mktime(mp_obj_get_int(elem[0]), + mp_obj_get_int(elem[1]), mp_obj_get_int(elem[2]), + mp_obj_get_int(elem[4]), mp_obj_get_int(elem[5]), mp_obj_get_int(elem[6])); +} + +// Helper to get current time as seconds since epoch +static inline uint64_t rtc_get_current_time_in_sec() { + mp_obj_t datetime = machine_rtc_datetime_helper(1, NULL); + + size_t len; + mp_obj_t *elem; + mp_obj_get_array(datetime, &len, &elem); + + // Expect tuple of length 8 + if (len < 8 || len > 9) { + mp_raise_TypeError(MP_ERROR_TEXT("datetime tuple needs length 8 or 9")); + } + + // Format: (year, month, day, weekday, hour, minute, second, subseconds) + // Note: elem[0] is already full year (2000-2099), not year since 1900 + return timeutils_mktime(mp_obj_get_int(elem[0]), + mp_obj_get_int(elem[1]), mp_obj_get_int(elem[2]), + mp_obj_get_int(elem[4]), mp_obj_get_int(elem[5]), mp_obj_get_int(elem[6])); +} + + +/* Forward declarations */ +static void rtc_irq_handler(void *self_in, uint32_t event); +static void rtc_alarm_setup(machine_rtc_obj_t *self); + +/* Override weak PDL alarm interrupt handler */ +void Cy_RTC_Alarm1Interrupt(void) { + /* Call our MicroPython callback handler */ + rtc_irq_handler(&machine_rtc_obj, 0); +} + +/* Hardware RTC interrupt handler (called by NVIC) - must match IRQn naming */ +void srss_interrupt_rtc_IRQHandler(void) { + /* Use PDL middleware to dispatch to specific alarm/DST handlers */ + Cy_RTC_Interrupt(NULL, false); /* NULL = no DST, false = normal mode */ +} + +/* Setup alarm hardware to trigger at the specified time */ +static void rtc_alarm_setup(machine_rtc_obj_t *self) { + if (!self->alarmset) { + return; + } + + /* Get the alarm time in seconds since epoch */ + uint64_t alarm_time_s = self->alarm_elapse_time_s; + + /* Convert seconds since epoch to datetime components */ + timeutils_struct_time_t tm; + timeutils_seconds_since_epoch_to_struct_time(alarm_time_s, &tm); + + /* Set the alarm using PDL direct API (no year field in alarm, matches recurring time) */ + cy_en_rtc_status_t status = Cy_RTC_SetAlarmDateAndTimeDirect( + tm.tm_sec, tm.tm_min, tm.tm_hour, + tm.tm_mday, tm.tm_mon, CY_RTC_ALARM_1); + + if (status != CY_RTC_SUCCESS) { + mp_raise_ValueError(MP_ERROR_TEXT("failed to set alarm")); + } + + /* Enable RTC ALARM1 interrupt */ + Cy_RTC_ClearInterrupt(CY_RTC_INTR_MASK); + Cy_RTC_SetInterruptMask(CY_RTC_INTR_ALARM1); + + /* Initialize and enable NVIC interrupt for RTC */ + rtc_interrupt_init(); + NVIC_ClearPendingIRQ(srss_interrupt_rtc_IRQn); + NVIC_EnableIRQ(srss_interrupt_rtc_IRQn); +} + +/* Software IRQ handler callback */ +void rtc_irq_handler(void *self_in, uint32_t event) { + machine_rtc_obj_t *self = (machine_rtc_obj_t *)self_in; + + if (self->alarmset && self->repeat) { + self->alarm_elapse_time_s += self->alarm_period_s; + rtc_alarm_setup(self); + } else { + self->alarmset = false; + Cy_RTC_SetInterruptMask(0); + Cy_RTC_ClearInterrupt(CY_RTC_INTR_MASK); + NVIC_ClearPendingIRQ(srss_interrupt_rtc_IRQn); + } + + if (self->callback != NULL) { + mp_sched_schedule(self->callback, MP_OBJ_FROM_PTR(self)); + } +} + + +// MicroPython bindings for RTC class +static mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, 0, false); + return (mp_obj_t)&machine_rtc_obj; +} + +static mp_obj_t machine_rtc_init(mp_obj_t self_in, mp_obj_t datetime) { + machine_rtc_obj_t *self = (machine_rtc_obj_t *)self_in; + self->alarm_elapse_time_s = 0; + self->alarm_period_s = 0; + self->alarmset = false; + self->callback = NULL; + self->repeat = false; + + mp_obj_t args[2] = {self_in, datetime}; + machine_rtc_datetime_helper(2, args); + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_2(machine_rtc_init_obj, machine_rtc_init); + +static mp_obj_t machine_rtc_deinit(mp_obj_t self_in) { + /* Resets RTC to 1st Jan' 2015 as mentioned in MPY guide*/ + Cy_RTC_SetDateAndTimeDirect(RTC_INIT_SECOND, RTC_INIT_MINUTE, RTC_INIT_HOUR, + RTC_INIT_MDAY, RTC_INIT_MONTH, RTC_INIT_YEAR); + machine_rtc_mark_time_updated(); + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_deinit_obj, machine_rtc_deinit); + +static mp_obj_t machine_rtc_datetime(mp_uint_t n_args, const mp_obj_t *datetime) { + return machine_rtc_datetime_helper(n_args, datetime); +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_rtc_datetime_obj, 1, 2, machine_rtc_datetime); + +static mp_obj_t machine_rtc_now(mp_obj_t self_in) { + return machine_rtc_datetime_helper(1, NULL); +} +static MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_now_obj, machine_rtc_now); + +static mp_obj_t machine_rtc_alarm(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_time, MP_ARG_OBJ, {.u_obj = mp_const_none} }, + { MP_QSTR_repeat, MP_ARG_KW_ONLY | MP_ARG_BOOL, {.u_bool = false} }, + }; + + // Parse args + uint64_t dtime_sec; + machine_rtc_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + uint64_t alarm_set_time_s = rtc_get_current_time_in_sec(); + + self->repeat = args[1].u_bool; + + if (args[0].u_obj == mp_const_none) { + mp_raise_ValueError(MP_ERROR_TEXT("missing alarm time")); + } + + if (mp_obj_is_type(args[0].u_obj, &mp_type_tuple)) { // datetime tuple given + // repeat cannot be used with a datetime tuple + if (self->repeat) { + mp_raise_ValueError(MP_ERROR_TEXT("invalid argument(s) value")); + } + dtime_sec = rtc_get_datetime_in_sec(args[0].u_obj); + if (dtime_sec < alarm_set_time_s) { + mp_raise_ValueError(MP_ERROR_TEXT("alarm time in past")); + } + self->alarm_period_s = dtime_sec - alarm_set_time_s; + } else { // then it must be an integer + int64_t delay_ms = mp_obj_get_int(args[0].u_obj); + if (delay_ms <= 0) { + mp_raise_ValueError(MP_ERROR_TEXT("time must be > 0")); + } + self->alarm_period_s = ((uint64_t)delay_ms + 999) / 1000; + } + self->alarm_elapse_time_s = alarm_set_time_s + self->alarm_period_s; + self->alarmset = true; + + /* Configure hardware alarm */ + rtc_alarm_setup(self); + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_KW(machine_rtc_alarm_obj, 1, machine_rtc_alarm); + +static mp_obj_t machine_rtc_alarm_left(size_t n_args, const mp_obj_t *args) { + machine_rtc_obj_t *self = MP_OBJ_TO_PTR(args[0]); + // only alarm id 0 is available + if (n_args > 1 && mp_obj_get_int(args[1]) != 0) { + mp_raise_OSError(MP_ENODEV); + } + if (self->alarmset) { + uint64_t curr_time = rtc_get_current_time_in_sec(); + uint64_t alarm_time = self->alarm_elapse_time_s; + return mp_obj_new_int_from_uint((alarm_time >= curr_time) ? ((alarm_time - curr_time) * 1000) : 0); + } + mp_raise_ValueError(MP_ERROR_TEXT("alarm not set")); +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_rtc_alarm_left_obj, 1, 2, machine_rtc_alarm_left); + +static mp_obj_t machine_rtc_alarm_cancel(size_t n_args, const mp_obj_t *args) { + machine_rtc_obj_t *self = MP_OBJ_TO_PTR(args[0]); + // only alarm id 0 is available + if (n_args > 1 && mp_obj_get_int(args[1]) != 0) { + mp_raise_OSError(MP_ENODEV); + } + + /* Disable the hardware alarm */ + Cy_RTC_SetInterruptMask(0); /* Disable all RTC interrupts */ + Cy_RTC_ClearInterrupt(CY_RTC_INTR_ALARM1); /* Clear any pending */ + NVIC_DisableIRQ(srss_interrupt_rtc_IRQn); + + /* Clear software alarm state */ + self->alarmset = false; + self->repeat = false; + self->alarm_period_s = 0; + self->alarm_elapse_time_s = 0; + + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_rtc_alarm_cancel_obj, 1, 2, machine_rtc_alarm_cancel); + +static mp_obj_t machine_rtc_memory(size_t n_args, const mp_obj_t *args) { + if (n_args == 1) { + Cy_RTC_SyncFromRtc(); + + uint32_t meta = rtc_breg_read(RTC_BREG_META_INDEX); + uint32_t magic = (meta >> 16) & 0xFFFFU; + uint32_t stored_len = meta & 0xFFFFU; + + if ((magic != RTC_BREG_MAGIC) || (stored_len > MICROPY_HW_RTC_USER_MEM_MAX)) { + return mp_obj_new_bytes((const uint8_t *)"", 0); + } + + uint8_t data[MICROPY_HW_RTC_USER_MEM_MAX] = {0}; + for (uint32_t index = 0; index < RTC_BREG_DATA_WORDS; ++index) { + uint32_t value = rtc_breg_read(index); + data[index * 4U + 0U] = (uint8_t)((value >> 0U) & 0xFFU); + data[index * 4U + 1U] = (uint8_t)((value >> 8U) & 0xFFU); + data[index * 4U + 2U] = (uint8_t)((value >> 16U) & 0xFFU); + data[index * 4U + 3U] = (uint8_t)((value >> 24U) & 0xFFU); + } + + return mp_obj_new_bytes(data, stored_len); + } + + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_READ); + + if (bufinfo.len > MICROPY_HW_RTC_USER_MEM_MAX) { + mp_raise_ValueError(MP_ERROR_TEXT("buffer too long")); + } + + cy_en_rtc_status_t write_status = Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED); + if (write_status != CY_RTC_SUCCESS) { + mp_raise_ValueError(MP_ERROR_TEXT("RTC memory write unavailable")); + } + + uint8_t data[MICROPY_HW_RTC_USER_MEM_MAX] = {0}; + memcpy(data, bufinfo.buf, bufinfo.len); + + for (uint32_t index = 0; index < RTC_BREG_DATA_WORDS; ++index) { + uint32_t value = ((uint32_t)data[index * 4U + 0U] << 0U) + | ((uint32_t)data[index * 4U + 1U] << 8U) + | ((uint32_t)data[index * 4U + 2U] << 16U) + | ((uint32_t)data[index * 4U + 3U] << 24U); + rtc_breg_write(index, value); + } + + uint32_t meta = (RTC_BREG_MAGIC << 16) | ((uint32_t)bufinfo.len & 0xFFFFU); + rtc_breg_write(RTC_BREG_META_INDEX, meta); + + write_status = Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED); + if (write_status != CY_RTC_SUCCESS) { + mp_raise_ValueError(MP_ERROR_TEXT("RTC memory write finalize failed")); + } + + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_rtc_memory_obj, 1, 2, machine_rtc_memory); + +static mp_obj_t machine_rtc_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + enum { ARG_trigger, ARG_handler, ARG_wake }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_trigger, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_handler, MP_ARG_REQUIRED | MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_wake, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} } + }; + + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + machine_rtc_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + + self->callback = args[ARG_handler].u_obj; + if (args[ARG_handler].u_obj == mp_const_none) { + self->callback = NULL; + } + + if (args[ARG_trigger].u_int != 0) { + mp_raise_OSError(MP_ENODEV); + } + + if (args[ARG_wake].u_int != -1) { + mp_raise_NotImplementedError(MP_ERROR_TEXT("wake not implemented")); + } + + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_KW(machine_rtc_irq_obj, 1, machine_rtc_irq); + +static const mp_rom_map_elem_t machine_rtc_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&machine_rtc_deinit_obj) }, + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_rtc_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_rtc_deinit_obj) }, + { MP_ROM_QSTR(MP_QSTR_datetime), MP_ROM_PTR(&machine_rtc_datetime_obj) }, + { MP_ROM_QSTR(MP_QSTR_now), MP_ROM_PTR(&machine_rtc_now_obj) }, + { MP_ROM_QSTR(MP_QSTR_alarm), MP_ROM_PTR(&machine_rtc_alarm_obj) }, + { MP_ROM_QSTR(MP_QSTR_alarm_left), MP_ROM_PTR(&machine_rtc_alarm_left_obj) }, + { MP_ROM_QSTR(MP_QSTR_alarm_cancel), MP_ROM_PTR(&machine_rtc_alarm_cancel_obj) }, + { MP_ROM_QSTR(MP_QSTR_cancel), MP_ROM_PTR(&machine_rtc_alarm_cancel_obj) }, + { MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&machine_rtc_irq_obj) }, + { MP_ROM_QSTR(MP_QSTR_memory), MP_ROM_PTR(&machine_rtc_memory_obj)}, + { MP_ROM_QSTR(MP_QSTR_ALARM0), MP_ROM_INT(0) }, + +}; +static MP_DEFINE_CONST_DICT(machine_rtc_locals_dict, machine_rtc_locals_dict_table); + +MP_DEFINE_CONST_OBJ_TYPE( + machine_rtc_type, + MP_QSTR_RTC, + MP_TYPE_FLAG_NONE, + make_new, machine_rtc_make_new, + locals_dict, &machine_rtc_locals_dict + ); diff --git a/ports/psoc-edge/machine_scb.c b/ports/psoc-edge/machine_scb.c new file mode 100644 index 00000000000..1d0e92c47ec --- /dev/null +++ b/ports/psoc-edge/machine_scb.c @@ -0,0 +1,108 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mpconfigport.h" + +#if MICROPY_PY_MACHINE_I2C || MICROPY_PY_MACHINE_I2C_TARGET || MICROPY_PY_MACHINE_SPI || MICROPY_PY_MACHINE_UART + +#include "py/runtime.h" +#include "genhdr/pins_af.h" +#include "machine_scb.h" + +/* Forward declaration */ +static void machine_scb_irq_handler(uint8_t scb); + +#define DEFINE_SCB_IRQ_HANDLER(scb) \ + void SCB##scb##_IRQ_Handler(void) { \ + machine_scb_irq_handler(scb); \ + } + +/** + * The file build-/genhdr/pins_af.h contains the macro + * + * MICROPY_PY_MACHINE_FOR_ALL_SCB(DO) + * + * which uses the X-macro (as argument) pattern to pass a worker + * macro DO(port) for the list of all user available ports. + * + * The available (not hidden) user SCBs are those alternate + * functions defined in the boards/pse8x_af.csv file, for which + * the corresponding pin are available for the user. + * The available pins are those defined in the + * boards//pins.csv file, which are not prefixed + * with a hyphen(-). + * See tools/boardgen.py and psoc-edge/boards/make-pins.py + * for more information. + */ + +MICROPY_PY_MACHINE_FOR_ALL_SCB(DEFINE_SCB_IRQ_HANDLER) + +#define MAP_SCB_IRQ_CONFIG(scb) \ + [scb] = { \ + scb, \ + SCB##scb, \ + { \ + scb_##scb##_interrupt_IRQn, \ + SYS_INT_IRQ_LOWEST_PRIORITY, \ + SCB##scb##_IRQ_Handler \ + }, \ + PCLK_SCB##scb##_CLOCK_SCB_EN, \ + CY_MMIO_SCB##scb##_SLAVE_NR, \ + NULL, \ + NULL, \ + }, + +static machine_scb_obj_t machine_scb_obj[MICROPY_PY_MACHINE_SCB_NUM_ENTRIES] = { + MICROPY_PY_MACHINE_FOR_ALL_SCB(MAP_SCB_IRQ_CONFIG) +}; + +static void machine_scb_irq_handler(uint8_t scb) { + machine_scb_obj_t *scb_obj = &machine_scb_obj[scb]; + if (scb_obj->parent != NULL && scb_obj->parent_handler != NULL) { + scb_obj->parent_handler(scb_obj->parent); + } +} + +machine_scb_obj_t *machine_scb_obj_alloc(uint8_t scb, mp_obj_t parent, machine_scb_parent_irq_handler_t handler) { + machine_scb_obj_t *obj = &machine_scb_obj[scb]; + if (obj->parent != NULL) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("SCB %u is already in use by another I2C, SPI or UART instance."), scb); + } + obj->parent = parent; + obj->parent_handler = handler; + return &machine_scb_obj[scb]; +} + +void machine_scb_obj_free(machine_scb_obj_t *scb) { + scb->parent = NULL; + scb->parent_handler = NULL; +} + +bool machine_scb_is_free(uint8_t scb) { + return machine_scb_obj[scb].parent == NULL; +} + +#endif // MICROPY_PY_MACHINE_I2C || MICROPY_PY_MACHINE_I2C_TARGET || MICROPY_PY_MACHINE_SPI || MICROPY_PY_MACHINE_UART diff --git a/ports/psoc-edge/machine_scb.h b/ports/psoc-edge/machine_scb.h new file mode 100644 index 00000000000..16ea4f5ac33 --- /dev/null +++ b/ports/psoc-edge/machine_scb.h @@ -0,0 +1,49 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_PSOC_EDGE_MACHINE_SCB_H +#define MICROPY_INCLUDED_PSOC_EDGE_MACHINE_SCB_H + +#include "sys_int.h" +#include "py/obj.h" + +typedef void (*machine_scb_parent_irq_handler_t)(mp_obj_t scb_obj); + +typedef struct _machine_scb_obj_t { + int8_t id; + CySCB_Type *scb; + sys_int_cfg_t irq; + en_clk_dst_t clk; + uint8_t mmio_slave_nr; + mp_obj_t parent; + machine_scb_parent_irq_handler_t parent_handler; +} machine_scb_obj_t; + +machine_scb_obj_t *machine_scb_obj_alloc(uint8_t scb, mp_obj_t parent, machine_scb_parent_irq_handler_t handler); +void machine_scb_obj_free(machine_scb_obj_t *scb); +bool machine_scb_is_free(uint8_t scb); + +#endif // MICROPY_INCLUDED_PSOC_EDGE_MACHINE_SCB_H diff --git a/ports/psoc-edge/machine_uart.c b/ports/psoc-edge/machine_uart.c new file mode 100644 index 00000000000..9e41b7c5760 --- /dev/null +++ b/ports/psoc-edge/machine_uart.c @@ -0,0 +1,1034 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file is never compiled standalone, it's included directly from +// extmod/machine_uart.c via MICROPY_PY_MACHINE_UART_INCLUDEFILE. + +// std includes +#include + +// MTB / PDL includes +#include "cybsp.h" +#include "cy_scb_uart.h" +#include "cy_scb_common.h" + +// MicroPython includes +#include "py/ringbuf.h" +#include "py/mphal.h" +#include "py/mperrno.h" +#include "py/nlr.h" +#include "py/stream.h" +#include "py/misc.h" + +// Port-specific includes +#include "genhdr/pins_af.h" +#include "modmachine.h" +#include "mphalport.h" +#include "machine_scb.h" +#include "sys_int.h" +#include "clk.h" + +/******************************************************************************/ +// Defaults and constants + +#define uart_assert_raise_val(msg, ret) if (ret != CY_SCB_UART_SUCCESS) { \ + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT(msg), ret); \ +} + +/** + * Integer ceil conversion from microseconds to milliseconds. + * (us + 999) / 1000 == ceil(us / 1000), so sub-ms durations do not become 0 ms. + */ +#define us_to_ms_ceil(us) (((us) + 999ULL) / 1000ULL) + +// Flow control macros not part of PSOC Edge PDL +#define UART_FLOW_CONTROL_NONE (0) +#define UART_FLOW_CONTROL_RTS (1) +#define UART_FLOW_CONTROL_CTS (2) +#define UART_IRQ_RXIDLE (CY_SCB_RX_INTR_NOT_EMPTY) + +// Class-level constants exposed to Python +#define MICROPY_PY_MACHINE_UART_CLASS_CONSTANTS \ + { MP_ROM_QSTR(MP_QSTR_IRQ_RXIDLE), MP_ROM_INT(UART_IRQ_RXIDLE) }, \ + { MP_ROM_QSTR(MP_QSTR_IRQ_BREAK), MP_ROM_INT(CY_SCB_RX_INTR_UART_BREAK_DETECT) }, \ + { MP_ROM_QSTR(MP_QSTR_IRQ_TXIDLE), MP_ROM_INT(CY_SCB_TX_INTR_UART_DONE) }, \ + { MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_INT(UART_FLOW_CONTROL_RTS) }, \ + { MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_INT(UART_FLOW_CONTROL_CTS) }, \ + +/******************************************************************************/ + +typedef struct _machine_uart_obj_t { + mp_obj_base_t base; + int id; // id matches the SCB id. + machine_scb_obj_t *scb_obj; + pclk_div_obj_t *pclk_div; + mp_hal_pin_obj_t tx; + mp_hal_pin_obj_t rx; + mp_hal_pin_obj_t rts; + mp_hal_pin_obj_t cts; + uint32_t baudrate; + uint32_t flow; + uint8_t bits; + mp_obj_t parity; + uint8_t stop; + uint32_t timeout_ms; + uint32_t timeout_char_ms; + cy_stc_scb_uart_context_t ctx; + ringbuf_t rx_ringbuf; + #if MICROPY_PY_MACHINE_UART_IRQ + uint32_t mp_irq_trigger; + uint32_t mp_irq_flags; + mp_irq_obj_t *mp_irq_obj; + bool rx_idle_irq_pending; + uint32_t rx_idle_timeout; + #endif +} machine_uart_obj_t; + +static machine_uart_obj_t *mp_machine_uart_obj_get(uint8_t id) { + for (uint8_t i = 0; i < MICROPY_PY_MACHINE_UART_NUM_ENTRIES; i++) { + if (MP_STATE_PORT(machine_uart_obj[i]) != NULL) { + if (MP_STATE_PORT(machine_uart_obj[i])->id == id) { + return MP_STATE_PORT(machine_uart_obj[i]); + } + } + } + return NULL; +} + +static machine_uart_obj_t *mp_machine_uart_obj_alloc(void) { + machine_uart_obj_t *self = NULL; + for (uint8_t i = 0; i < MICROPY_PY_MACHINE_UART_NUM_ENTRIES; i++) { + if (MP_STATE_PORT(machine_uart_obj[i]) == NULL) { + self = mp_obj_malloc(machine_uart_obj_t, &machine_uart_type); + MP_STATE_PORT(machine_uart_obj[i]) = self; + break; + } + } + + if (self == NULL) { + mp_raise_ValueError(MP_ERROR_TEXT("all available UART instances are allocated")); + } + + return self; +} + +static void mp_machine_uart_obj_free(machine_uart_obj_t *self) { + for (uint8_t i = 0; i < MICROPY_PY_MACHINE_UART_NUM_ENTRIES; i++) { + if (MP_STATE_PORT(machine_uart_obj[i]) == self) { + MP_STATE_PORT(machine_uart_obj[i]) = NULL; + break; + } + } +} + +MP_REGISTER_ROOT_POINTER(struct _machine_uart_obj_t *machine_uart_obj[MICROPY_PY_MACHINE_UART_NUM_ENTRIES]); + +#if MICROPY_PY_MACHINE_UART_IRQ +static void machine_uart_irq_rx_idle(machine_uart_obj_t *self); +static void machine_uart_irq_rx_break(machine_uart_obj_t *self); +static void machine_uart_irq_tx_idle(machine_uart_obj_t *self); +#endif + +static void machine_uart_fill_rx_ring_buff(machine_uart_obj_t *self) { + uint32_t available_rx_frames = Cy_SCB_UART_GetNumInRxFifo(self->scb_obj->scb); + for (uint32_t i = 0; i < available_rx_frames; i++) { + if (!ringbuf_put(&self->rx_ringbuf, (uint8_t)Cy_SCB_UART_Get(self->scb_obj->scb))) { + /** + * No overflow handling. + * Just return and wait for next interrupt + * to read the remaining data. + */ + return; + } + } +} + +static void machine_uart_scb_isr(mp_obj_t hw_uart_obj) { + machine_uart_obj_t *self = MP_OBJ_TO_PTR(hw_uart_obj); + + if (0UL != (CY_SCB_RX_INTR & Cy_SCB_GetInterruptCause(self->scb_obj->scb))) { + if (0UL != (CY_SCB_RX_INTR_NOT_EMPTY & Cy_SCB_GetRxInterruptStatusMasked(self->scb_obj->scb))) { + machine_uart_fill_rx_ring_buff(self); + + #if MICROPY_PY_MACHINE_UART_IRQ + machine_uart_irq_rx_idle(self); + #endif + + Cy_SCB_ClearRxInterrupt(self->scb_obj->scb, CY_SCB_RX_INTR_NOT_EMPTY); + } + + #if MICROPY_PY_MACHINE_UART_IRQ + if (0UL != (CY_SCB_RX_INTR_UART_BREAK_DETECT & Cy_SCB_GetRxInterruptStatusMasked(self->scb_obj->scb))) { + machine_uart_irq_rx_break(self); + Cy_SCB_ClearRxInterrupt(self->scb_obj->scb, CY_SCB_RX_INTR_UART_BREAK_DETECT); + } + #endif + } + + #if MICROPY_PY_MACHINE_UART_IRQ + if ((0UL != (CY_SCB_TX_INTR & Cy_SCB_GetInterruptCause(self->scb_obj->scb))) && + (0UL != (CY_SCB_TX_INTR_UART_DONE & Cy_SCB_GetTxInterruptStatusMasked(self->scb_obj->scb)))) { + machine_uart_irq_tx_idle(self); + Cy_SCB_ClearTxInterrupt(self->scb_obj->scb, CY_SCB_TX_INTR_UART_DONE); + } + #endif +} + +static void machine_uart_obj_make_or_reuse(machine_uart_obj_t **self_ptr, uint8_t id, bool *is_new) { + /** + * UART() constructor path: + * + * Create or reuse and object based on the id. + * If the object for the given id already exists, + * reuse it and reinit the hardware with the new params. + * If the object is being created for the first time, + * allocate it and the associated SCB object. + */ + + /* Use object if it already exists */ + (*self_ptr) = mp_machine_uart_obj_get(id); + (*is_new) = false; + + if (*self_ptr == NULL) { + /* Create a new object and allocate the scb instance if free.*/ + if (machine_scb_is_free(id)) { + (*self_ptr) = mp_machine_uart_obj_alloc(); + (*self_ptr)->id = id; + (*self_ptr)->pclk_div = NULL; + (*self_ptr)->scb_obj = machine_scb_obj_alloc(id, *self_ptr, machine_uart_scb_isr); + pclk_div_slave_init((*self_ptr)->scb_obj->clk, (*self_ptr)->scb_obj->mmio_slave_nr); + } else { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("SCB %u is already in use by a machine.I2C or machine.SPI instance."), id); + } + (*is_new) = true; + } +} + +#define MACHINE_UART_OVERSAMPLING (12UL) + +static inline uint8_t machine_uart_break_width(machine_uart_obj_t *self) { + return 1 + // Start bit + self->bits + + (self->parity != mp_const_none ? 1 : 0) + + (self->stop) + + 1; // Extra bit, make the frame longer +} + +static inline uint32_t machine_uart_frame_time_us(machine_uart_obj_t *self) { + /** + * Integer ceil division: + * (num + den - 1) / den == ceil(num / den). + * Here it computes ceil((bits_per_frame * 1e6) / baudrate), so frame time does + * not round down too aggressively when baudrate is high. + */ + uint32_t bits_per_frame = machine_uart_break_width(self) - 1; + uint64_t num = (uint64_t)bits_per_frame * 1000000ULL; + return (uint32_t)((num + self->baudrate - 1) / self->baudrate); +} + +static inline uint32_t machine_uart_baudrate_get_divider(machine_uart_obj_t *self) { + uint32_t clock_freq = pclk_div_get_input_freq(self->scb_obj->clk); + if (clock_freq == 0) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("failed to get clock frequency for UART(%u)"), self->id); + } + + uint32_t divider = (uint32_t)(clock_freq / (self->baudrate * MACHINE_UART_OVERSAMPLING)); + /* + * No fractional divider should be required: + * Experimentally: + * - baud rates 2400, 4800, 9600, 19200 bps: + * The error between the actual baud rate + * and the requested is < 1% for 16 bits divider + * - baud rates 115200, 230400, 460800 bps: + * The error between the actual baud rate and + * the requested is < 1% for 8 bits divider + * + */ + + return divider; +} + +static inline cy_en_scb_uart_parity_t machine_uart_get_pdl_parity(mp_obj_t parity) { + if (parity == mp_const_none) { + return CY_SCB_UART_PARITY_NONE; + } + switch (mp_obj_get_int(parity)) { + case 0: + return CY_SCB_UART_PARITY_EVEN; + case 1: + return CY_SCB_UART_PARITY_ODD; + } + + return CY_SCB_UART_PARITY_NONE; +} + +static inline char *machine_uart_get_parity_str(mp_obj_t parity) { + static char *parity_str[] = { + "0", + "1", + "None" + }; + + if (parity == mp_const_none) { + return parity_str[2]; + } + switch (mp_obj_get_int(parity)) { + case 0: + return parity_str[0]; + case 1: + return parity_str[1]; + } + + return parity_str[2]; +} + +static inline cy_en_scb_uart_stop_bits_t machine_uart_get_pdl_stop(uint8_t stop) { + switch (stop) { + case 1: + return CY_SCB_UART_STOP_BITS_1; + case 2: + return CY_SCB_UART_STOP_BITS_2; + } + + return CY_SCB_UART_STOP_BITS_1; +} + +static void machine_uart_hw_init(machine_uart_obj_t *self) { + cy_stc_scb_uart_config_t config = + { + .uartMode = CY_SCB_UART_STANDARD, + .enableMultiProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + + .oversample = MACHINE_UART_OVERSAMPLING, + + .enableMsbFirst = false, + .dataWidth = self->bits, + .parity = machine_uart_get_pdl_parity(self->parity), + .stopBits = machine_uart_get_pdl_stop(self->stop), + .enableInputFilter = false, + .breakWidth = machine_uart_break_width(self), + .dropOnFrameError = false, + .dropOnParityError = false, + + .receiverAddress = 0UL, + .receiverAddressMask = 0UL, + .acceptAddrInFifo = false, + + /** + * TODO: Enable CTS/RTS based on user config. + */ + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + + .rxFifoTriggerLevel = 0UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 0UL, + .txFifoIntEnableMask = 0UL, + }; + + uint32_t divider = machine_uart_baudrate_get_divider(self); + self->pclk_div = pclk_div_init(self->scb_obj->clk, divider, 0); + if (self->pclk_div == NULL) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("failed to initialize clock divider for UART(%u)"), self->id); + } + + cy_en_scb_uart_status_t rslt = Cy_SCB_UART_Init(self->scb_obj->scb, &config, &self->ctx); + uart_assert_raise_val("failed to initialize UART hardware, error code: %d", rslt); + + sys_int_init(&(self->scb_obj->irq)); + Cy_SCB_SetRxInterruptMask(self->scb_obj->scb, CY_SCB_RX_INTR_NOT_EMPTY); + + Cy_SCB_UART_Enable(self->scb_obj->scb); +} + +static void machine_uart_hw_deinit(machine_uart_obj_t *self) { + Cy_SCB_UART_Disable(self->scb_obj->scb, &self->ctx); + sys_int_deinit(&self->scb_obj->irq); + pclk_div_deinit(self->pclk_div); + self->pclk_div = NULL; +} + +static bool machine_uart_rx_wait(machine_uart_obj_t *self, uint32_t timeout_ms) { + uint32_t timeout_time_ms = mp_hal_ticks_ms() + timeout_ms; + + while (ringbuf_avail(&self->rx_ringbuf) == 0) { + if (mp_hal_ticks_ms() > timeout_time_ms) { + return false; + } + mp_event_handle_nowait(); + } + + return true; +} + +static bool machine_uart_tx_wait(machine_uart_obj_t *self, uint32_t timeout_ms) { + uint32_t timeout_time_ms = mp_hal_ticks_ms() + timeout_ms; + while ((Cy_SCB_UART_GetTxFifoStatus(self->scb_obj->scb) & CY_SCB_UART_TX_NOT_FULL) == 0) { + if (mp_hal_ticks_ms() > timeout_time_ms) { + return false; + } + mp_event_handle_nowait(); + } + + return true; +} + +/******************************************************************************/ +// MicroPython bindings + +static void mp_machine_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "UART(id=%u, " + "tx="MP_HAL_PIN_FMT ", " + "rx="MP_HAL_PIN_FMT ", " + "baudrate=%ld, " + "bits=%u, " + "parity=%s, " + "stop=%u, ", + self->id, + mp_hal_pin_name(self->tx), + mp_hal_pin_name(self->rx), + self->baudrate, + self->bits, + machine_uart_get_parity_str(self->parity), + self->stop + ); + + if (self->rts != NULL) { + mp_printf(print, "rts="MP_HAL_PIN_FMT ", ", mp_hal_pin_name(self->rts)); + } + + if (self->cts != NULL) { + mp_printf(print, "cts="MP_HAL_PIN_FMT ", ", mp_hal_pin_name(self->cts)); + } + + mp_printf(print, "flow=%u, " + "timeout=%ld, " + "timeout_char=%ld, " + "rxbuf=%d)", + self->flow, + self->timeout_ms, + self->timeout_char_ms, + self->rx_ringbuf.size + ); +} + +#define DEFAULT_UART_BAUDRATE (115200) +#define DEFAULT_UART_BITS (8) +#define DEFAULT_UART_STOP (1) +#define DEFAULT_UART_RXBUF_SIZE (256) + +enum { + ARG_tx, ARG_rx, + ARG_baudrate, ARG_bits, ARG_parity, ARG_stop, + ARG_rts, ARG_cts, ARG_flow, + ARG_timeout, ARG_timeout_char, ARG_rxbuf +}; + +static const mp_arg_t allowed_args[] = { + { MP_QSTR_tx, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_rx, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_baudrate, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_UART_BAUDRATE} }, + { MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_UART_BITS} }, + { MP_QSTR_parity, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_stop, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_UART_STOP} }, + { MP_QSTR_rts, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_cts, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UART_FLOW_CONTROL_NONE} }, + { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_rxbuf, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_UART_RXBUF_SIZE} }, +}; + +/** + * Core init implementation. Accepts a pointer-to-pointer for self so it can + * allocate a new object when *self_ptr is NULL (constructor path). When called + * from init() the object is already allocated so *self_ptr is non-NULL. + */ +static void machine_uart_init_impl(machine_uart_obj_t **self_ptr, int uart_id, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + /* -- TX / RX pins -- */ + uint8_t pin_num = 2U; + #define MAX_MACHINE_UART_OBJ_AF_PINS 4 + mp_hal_pin_af_config_t uart_pins_af_config[MAX_MACHINE_UART_OBJ_AF_PINS] = { + /* TX */ MP_HAL_PIN_AF_CONF_INIT_GPIO_SIGNAL(CY_GPIO_DM_STRONG_IN_OFF, 1, MACHINE_PIN_AF_SIGNAL_UART_TX), + /* RX */ MP_HAL_PIN_AF_CONF_INIT_GPIO_SIGNAL(CY_GPIO_DM_HIGHZ, 0, MACHINE_PIN_AF_SIGNAL_UART_RX), + }; + + if (args[ARG_tx].u_obj != mp_const_none) { + mp_hal_pin_obj_t tx_pin = mp_hal_get_pin_obj(args[ARG_tx].u_obj); + MP_HAL_PIN_AF_CONF_SET_PIN_AF(uart_pins_af_config[0], tx_pin); + } + + if (args[ARG_rx].u_obj != mp_const_none) { + mp_hal_pin_obj_t rx_pin = mp_hal_get_pin_obj(args[ARG_rx].u_obj); + MP_HAL_PIN_AF_CONF_SET_PIN_AF(uart_pins_af_config[1], rx_pin); + } + + /* -- Flow control pins -- */ + uint32_t flow = (uint32_t)args[ARG_flow].u_int; + + /** TODO: Currently throw error if flow is not NONE. + * This needs to be implemented + * { + */ + if (flow != UART_FLOW_CONTROL_NONE) { + mp_raise_ValueError(MP_ERROR_TEXT("flow control not supported yet. Keep flow=0")); + } + /** } */ + + #define PIN_AF_CONFIG_INDEX_NONE (0xFF) + uint8_t pin_af_conf_rts_index = PIN_AF_CONFIG_INDEX_NONE; + if (flow & UART_FLOW_CONTROL_RTS) { + pin_af_conf_rts_index = pin_num; + pin_num++; + uart_pins_af_config[pin_af_conf_rts_index] = MP_HAL_PIN_AF_CONF_INIT_GPIO_SIGNAL(CY_GPIO_DM_STRONG_IN_OFF, 1, MACHINE_PIN_AF_SIGNAL_UART_RTS); + if (args[ARG_rts].u_obj != mp_const_none) { + mp_hal_pin_obj_t rts_pin = mp_hal_get_pin_obj(args[ARG_rts].u_obj); + MP_HAL_PIN_AF_CONF_SET_PIN_AF(uart_pins_af_config[pin_af_conf_rts_index], rts_pin); + } + } + + uint8_t pin_af_conf_cts_index = PIN_AF_CONFIG_INDEX_NONE; + if (flow & UART_FLOW_CONTROL_CTS) { + pin_af_conf_cts_index = pin_num; + pin_num++; + uart_pins_af_config[pin_af_conf_cts_index] = MP_HAL_PIN_AF_CONF_INIT_GPIO_SIGNAL(CY_GPIO_DM_HIGHZ, 0, MACHINE_PIN_AF_SIGNAL_UART_CTS); + if (args[ARG_cts].u_obj != mp_const_none) { + mp_hal_pin_obj_t cts_pin = mp_hal_get_pin_obj(args[ARG_cts].u_obj); + MP_HAL_PIN_AF_CONF_SET_PIN_AF(uart_pins_af_config[pin_af_conf_cts_index], cts_pin); + } + } + + /* -- Resolve ID - pin match -- */ + machine_pin_af_unit_t fn_unit = (machine_pin_af_unit_t)uart_id; + mp_hal_periph_pins_af_resolve_fn_unit(uart_pins_af_config, pin_num, MACHINE_PIN_AF_FN_UART, &fn_unit); + + /* -- Resolve not provided AF pins -- */ + mp_hal_periph_pins_af_resolve_pin_af(uart_pins_af_config, pin_num, fn_unit); + + /* -- Baudrate -- */ + uint32_t baudrate = (uint32_t)args[ARG_baudrate].u_int; + if (baudrate == 0U) { + mp_raise_ValueError(MP_ERROR_TEXT("baudrate must be non-zero")); + } + + /* -- Data bits -- */ + uint8_t bits = args[ARG_bits].u_int; + /** + * TODO: Add support for 7 (or below <8 bits) and 9 bits. + */ + if (bits != 8) { + mp_raise_ValueError(MP_ERROR_TEXT("bits must be 8")); + } + + /* -- Parity -- */ + mp_obj_t parity = args[ARG_parity].u_obj; + if (parity != mp_const_none) { + int p = mp_obj_get_int(parity); + if (p != 0 && p != 1) { + mp_raise_ValueError(MP_ERROR_TEXT("parity must be None, 0 (even) or 1 (odd)")); + } + } + + /* -- Stop bits -- */ + uint8_t stop = args[ARG_stop].u_int; + if (stop != 1 && stop != 2) { + mp_raise_ValueError(MP_ERROR_TEXT("stop bits must be 1 or 2")); + } + + /* -- Timeouts -- */ + if (args[ARG_timeout].u_int < 0) { + mp_raise_ValueError(MP_ERROR_TEXT("timeout must be non-negative")); + } + uint32_t timeout_ms = args[ARG_timeout].u_int; + + if (args[ARG_timeout_char].u_int < 0) { + mp_raise_ValueError(MP_ERROR_TEXT("timeout_char must be non-negative")); + } + uint32_t timeout_char_ms = args[ARG_timeout_char].u_int; + /* Make sure timeout_char is at least as long as a whole character (13 bits to be safe). */ + uint32_t min_timeout_char = 13000 / baudrate + 1; + if (timeout_char_ms < min_timeout_char) { + timeout_char_ms = min_timeout_char; + } + + machine_uart_obj_t *self = *self_ptr; + + /* -- Object allocation -- */ + bool is_new = false; + bool is_make_obj_required = (*self_ptr == NULL) ? true : false; + if (is_make_obj_required) { + machine_uart_obj_make_or_reuse(self_ptr, fn_unit, &is_new); + self = *self_ptr; + } + + /* -- Reinitialization reset -- */ + /* For reused UART() object or init() path */ + if (!is_new) { + machine_uart_hw_deinit(self); + m_del(uint8_t, self->rx_ringbuf.buf, self->rx_ringbuf.size); + } + + /* -- UART params init -- */ + self->tx = uart_pins_af_config[0].pin; + self->rx = uart_pins_af_config[1].pin; + self->rts = (pin_af_conf_rts_index != PIN_AF_CONFIG_INDEX_NONE) ? uart_pins_af_config[pin_af_conf_rts_index].pin : MP_OBJ_NULL; + self->cts = (pin_af_conf_cts_index != PIN_AF_CONFIG_INDEX_NONE) ? uart_pins_af_config[pin_af_conf_cts_index].pin : MP_OBJ_NULL; + self->flow = flow; + self->baudrate = baudrate; + self->bits = bits; + self->parity = parity; + self->stop = stop; + self->timeout_ms = timeout_ms; + self->timeout_char_ms = timeout_char_ms; + + /* -- IRQ init -- */ + #if MICROPY_PY_MACHINE_UART_IRQ + self->mp_irq_obj = NULL; + self->mp_irq_trigger = 0; + self->mp_irq_flags = 0; + self->rx_idle_irq_pending = false; + self->rx_idle_timeout = 0; + #endif + + /* -- Initialise hardware -- */ + nlr_buf_t nlr; + if (nlr_push(&nlr) == 0) { + ringbuf_alloc(&self->rx_ringbuf, args[ARG_rxbuf].u_int); + mp_hal_periph_pins_af_init(uart_pins_af_config, pin_num); + machine_uart_hw_init(self); + nlr_pop(); + } else { + // Ensure partially-initialized instances are fully released on init failure. + machine_uart_hw_deinit(self); + m_del(uint8_t, self->rx_ringbuf.buf, self->rx_ringbuf.size); + nlr_raise(nlr.ret_val); + } +} + +static mp_obj_t mp_machine_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, MP_OBJ_FUN_ARGS_MAX, true); + + /** + * Only the constructor takes the id. + * Its validation together with the rest of the arguments is + * delegated to machine_uart_init_implt() which also allocates + * the object self = NULL. + */ + int uart_id = MACHINE_PIN_AF_UNIT_NONE; + size_t init_n_args = n_args; + const mp_obj_t *init_args = args; + if (n_args > 0 && mp_obj_is_int(args[0])) { + uart_id = mp_obj_get_int(args[0]); + if (uart_id < 0 || uart_id >= MICROPY_PY_MACHINE_SCB_NUM_ENTRIES) { + mp_raise_ValueError(MP_ERROR_TEXT("UART id out of range")); + } + init_n_args = n_args - 1; + init_args = args + 1; + } else if (n_args > 0) { + mp_raise_TypeError(MP_ERROR_TEXT("UART id must be an integer")); + } + + machine_uart_obj_t *self = NULL; + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + machine_uart_init_impl(&self, uart_id, init_n_args, init_args, &kw_args); + return MP_OBJ_FROM_PTR(self); +} + +static void mp_machine_uart_deinit(machine_uart_obj_t *self) { + machine_uart_hw_deinit(self); + m_del(uint8_t, self->rx_ringbuf.buf, self->rx_ringbuf.size); + pclk_div_slave_deinit(self->scb_obj->clk, self->scb_obj->mmio_slave_nr); + machine_scb_obj_free(self->scb_obj); + mp_machine_uart_obj_free(self); +} + +static void mp_machine_uart_init_helper(machine_uart_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + machine_uart_init_impl(&self, self->id, n_args, pos_args, kw_args); +} + +static mp_int_t mp_machine_uart_any(machine_uart_obj_t *self) { + return ringbuf_avail(&self->rx_ringbuf); +} + +static bool mp_machine_uart_txdone(machine_uart_obj_t *self) { + return Cy_SCB_UART_IsTxComplete(self->scb_obj->scb); +} + +#if MICROPY_PY_MACHINE_UART_SENDBREAK +static void mp_machine_uart_sendbreak(machine_uart_obj_t *self) { + Cy_SCB_UART_SendBreakBlocking(self->scb_obj->scb, machine_uart_break_width(self)); +} +#endif + +#if MICROPY_PY_MACHINE_UART_READCHAR_WRITECHAR +static mp_int_t mp_machine_uart_readchar(machine_uart_obj_t *self) { + if (machine_uart_rx_wait(self, self->timeout_ms)) { + return (uint8_t)ringbuf_get(&self->rx_ringbuf); + } + + return MP_STREAM_ERROR; +} + +static void mp_machine_uart_writechar(machine_uart_obj_t *self, uint16_t data) { + if (machine_uart_tx_wait(self, self->timeout_ms)) { + Cy_SCB_UART_Put(self->scb_obj->scb, (uint32_t)data); + } else { + mp_raise_OSError(MP_ETIMEDOUT); + } +} +#endif + +static mp_uint_t mp_machine_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) { + machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (size == 0) { + return 0; + } + + /* wait for first char to become available */ + if (!machine_uart_rx_wait(self, self->timeout_ms)) { + /* return EAGAIN error to indicate non-blocking (then read() method returns None) */ + *errcode = MP_EAGAIN; + return MP_STREAM_ERROR; + } + + uint32_t read_count = 0; + uint32_t to_read; + do { + to_read = (size < ringbuf_avail(&self->rx_ringbuf)) ? size : ringbuf_avail(&self->rx_ringbuf); + ringbuf_memcpy_get_internal(&self->rx_ringbuf, (uint8_t *)buf_in + read_count, to_read); + read_count += to_read; + size -= to_read; + } while (size > 0 && machine_uart_rx_wait(self, self->timeout_char_ms)); + + return read_count; +} + +static mp_uint_t mp_machine_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) { + machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + + /* wait to be able to write the first character. */ + if (!machine_uart_tx_wait(self, self->timeout_ms)) { + /* EAGAIN causes write to return None */ + *errcode = MP_EAGAIN; + return MP_STREAM_ERROR; + } + + uint32_t write_count = 0; + do { + uint32_t written = Cy_SCB_UART_PutArray(self->scb_obj->scb, (void *)buf_in, size); + buf_in = (const uint8_t *)buf_in + written; + size -= written; + write_count += written; + } while (size > 0 && machine_uart_tx_wait(self, self->timeout_char_ms)); + + return write_count; +} + +static mp_uint_t mp_machine_uart_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) { + machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_uint_t ret; + if (request == MP_STREAM_POLL) { + uintptr_t flags = arg; + ret = 0; + if ((flags & MP_STREAM_POLL_RD) && ringbuf_avail(&self->rx_ringbuf) > 0) { + ret |= MP_STREAM_POLL_RD; + } + if ((flags & MP_STREAM_POLL_WR) && (Cy_SCB_UART_GetTxFifoStatus(self->scb_obj->scb) & CY_SCB_UART_TX_NOT_FULL)) { + ret |= MP_STREAM_POLL_WR; + } + } else if (request == MP_STREAM_FLUSH) { + /** + * Calculate the timeout based on the number of TX FIFO frame + * left (+ some margin) and the frame time. + * This is to avoid waiting too long for the flush to complete. + */ + #define MACHINE_UART_FLUSH_EXTRA_FRAMES_MARGIN 10 + uint64_t flush_time_us = (uint64_t)(MACHINE_UART_FLUSH_EXTRA_FRAMES_MARGIN + Cy_SCB_UART_GetNumInTxFifo(self->scb_obj->scb)) * machine_uart_frame_time_us(self); + uint32_t flush_time_ms = us_to_ms_ceil(flush_time_us); + uint32_t timeout = mp_hal_ticks_ms() + flush_time_ms; + do { + if (mp_machine_uart_txdone(self)) { + return 0; + } + mp_event_handle_nowait(); + } while (mp_hal_ticks_ms() < timeout); + *errcode = MP_ETIMEDOUT; + ret = MP_STREAM_ERROR; + } else { + *errcode = MP_EINVAL; + ret = MP_STREAM_ERROR; + } + return ret; +} + +void machine_uart_deinit_all() { + for (uint8_t i = 0; i < MICROPY_PY_MACHINE_UART_NUM_ENTRIES; i++) { + machine_uart_obj_t *self = MP_STATE_PORT(machine_uart_obj[i]); + if (self != NULL) { + mp_machine_uart_deinit(self); + } + } +} + +#if MICROPY_PY_MACHINE_UART_IRQ + +#define MP_UART_ALLOWED_FLAGS (UART_IRQ_RXIDLE | \ + CY_SCB_RX_INTR_UART_BREAK_DETECT | \ + CY_SCB_TX_INTR_UART_DONE) + +static mp_obj_t machine_uart_rx_idle_soft(mp_obj_t self_in); +static MP_DEFINE_CONST_FUN_OBJ_1(machine_uart_rx_idle_soft_obj, machine_uart_rx_idle_soft); + + +static mp_obj_t machine_uart_rx_idle_soft(mp_obj_t self_in) { + /** + * The irq handle is only scheduled when no bytes + * have been received within the frame time. + * This avoid calling the irq handler for every NOT_EMPTY + * interrupt when a burst of bytes is received. + * */ + machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->rx_idle_irq_pending) { + if (mp_hal_ticks_ms() >= self->rx_idle_timeout) { + if (ringbuf_avail(&self->rx_ringbuf) > 0) { + mp_irq_handler(self->mp_irq_obj); + } + self->rx_idle_irq_pending = false; + } else { + mp_sched_schedule(MP_OBJ_FROM_PTR(&machine_uart_rx_idle_soft_obj), MP_OBJ_FROM_PTR(self)); + } + } + + return mp_const_none; +} + +static void machine_uart_irq_rx_idle(machine_uart_obj_t *self) { + /** + * If an IRQ_IDLE is pending, the timeout is just updated + * after a NOT_EMPTY interrupt has triggered a RX FIFO buffer + * read. + * Otherwise, the soft irq handler is scheduled. The + * soft irq handler checks if the timeout is expired, and + * if so, calls the user irq handler. If not, it reschedules itself + * to check again after the timeout. + */ + if ((self->mp_irq_obj != NULL) && + (self->mp_irq_obj->handler != NULL) && + (self->mp_irq_trigger & UART_IRQ_RXIDLE)) { + self->mp_irq_flags |= UART_IRQ_RXIDLE; + + /* Number of frame times to wait before triggering RX idle IRQ */ + #define RX_IDLE_NUM_OF_FRAMES_MARGIN 5 + uint32_t frame_time_ms = us_to_ms_ceil(machine_uart_frame_time_us(self)); + self->rx_idle_timeout = mp_hal_ticks_ms() + frame_time_ms * RX_IDLE_NUM_OF_FRAMES_MARGIN; + if (!self->rx_idle_irq_pending) { + self->rx_idle_irq_pending = true; + mp_sched_schedule(MP_OBJ_FROM_PTR(&machine_uart_rx_idle_soft_obj), MP_OBJ_FROM_PTR(self)); + } + } +} + +static void machine_uart_irq_rx_break(machine_uart_obj_t *self) { + if ((self->mp_irq_obj != NULL) && + (self->mp_irq_obj->handler != NULL) && + (self->mp_irq_trigger & CY_SCB_RX_INTR_UART_BREAK_DETECT)) { + self->mp_irq_flags |= CY_SCB_RX_INTR_UART_BREAK_DETECT; + mp_irq_handler(self->mp_irq_obj); + } +} + +static void machine_uart_irq_tx_idle(machine_uart_obj_t *self) { + if ((self->mp_irq_obj != NULL) && + (self->mp_irq_obj->handler != NULL) && + (self->mp_irq_trigger & CY_SCB_TX_INTR_UART_DONE)) { + self->mp_irq_flags |= CY_SCB_TX_INTR_UART_DONE; + mp_irq_handler(self->mp_irq_obj); + } +} + +static void machine_uart_irq_scb_config(machine_uart_obj_t *self, bool enable) { + if (enable) { + /** + * CY_SCB_RX_INTR_NOT_EMPTY is always enabled. + */ + if (self->mp_irq_trigger & CY_SCB_RX_INTR_UART_BREAK_DETECT) { + /** + * Clear any stale sticky status before unmasking to prevent a + * spurious ISR from a break that occurred before this irq() call. + */ + Cy_SCB_ClearRxInterrupt(self->scb_obj->scb, CY_SCB_RX_INTR_UART_BREAK_DETECT | CY_SCB_RX_INTR_NOT_EMPTY); + Cy_SCB_SetRxInterruptMask(self->scb_obj->scb, CY_SCB_RX_INTR_UART_BREAK_DETECT | CY_SCB_RX_INTR_NOT_EMPTY); + } + if (self->mp_irq_trigger & CY_SCB_TX_INTR_UART_DONE) { + /** + * Clear any stale sticky status before unmasking to prevent a + * spurious ISR from a TX done that occurred before this irq() call. + */ + Cy_SCB_ClearTxInterrupt(self->scb_obj->scb, CY_SCB_TX_INTR_UART_DONE); + Cy_SCB_SetTxInterruptMask(self->scb_obj->scb, CY_SCB_TX_INTR_UART_DONE); + } + } else { + /** + * If disabling, we want to keep the CY_SCB_RX_INTR_NOT_EMPTY + * enabled to be able to fill the RX ring buffer and avoid data loss. + */ + Cy_SCB_SetRxInterruptMask(self->scb_obj->scb, CY_SCB_RX_INTR_NOT_EMPTY); + Cy_SCB_SetTxInterruptMask(self->scb_obj->scb, 0); + } +} + +static mp_uint_t uart_irq_trigger(mp_obj_t self_in, mp_uint_t new_trigger) { + machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + machine_uart_irq_scb_config(self, false); + self->mp_irq_trigger = new_trigger; + machine_uart_irq_scb_config(self, true); + return 0; +} + +static mp_uint_t uart_irq_info(mp_obj_t self_in, mp_uint_t info_type) { + machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (info_type == MP_IRQ_INFO_FLAGS) { + mp_uint_t flags = self->mp_irq_flags; + self->mp_irq_flags = 0; + return flags; + } else if (info_type == MP_IRQ_INFO_TRIGGERS) { + return self->mp_irq_trigger; + } + return 0; +} + +const mp_irq_methods_t uart_irq_methods = { + .trigger = uart_irq_trigger, + .info = uart_irq_info, +}; + +static mp_irq_obj_t *mp_machine_uart_irq(machine_uart_obj_t *self, bool any_args, mp_arg_val_t *args) { + if (self->mp_irq_obj == NULL) { + self->mp_irq_trigger = 0; + self->mp_irq_obj = mp_irq_new(&uart_irq_methods, MP_OBJ_FROM_PTR(self)); + } + + if (any_args) { + /* Check the handler */ + mp_obj_t handler = args[MP_IRQ_ARG_INIT_handler].u_obj; + if (handler != mp_const_none && !mp_obj_is_callable(handler)) { + mp_raise_ValueError(MP_ERROR_TEXT("handler must be None or callable")); + } + + /* Check the trigger */ + mp_uint_t trigger = args[MP_IRQ_ARG_INIT_trigger].u_int; + mp_uint_t not_supported = trigger & ~MP_UART_ALLOWED_FLAGS; + if (trigger != 0 && not_supported) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("trigger 0x%08x unsupported"), not_supported); + } + + /* Reconfigure user IRQs */ + machine_uart_irq_scb_config(self, false); + self->mp_irq_obj->handler = handler; + self->mp_irq_obj->ishard = args[MP_IRQ_ARG_INIT_hard].u_bool; + self->mp_irq_trigger = trigger; + machine_uart_irq_scb_config(self, true); + } + + return self->mp_irq_obj; +} +#endif + +/******************************************************************************/ +// Static REPL UART instance enablement + +extern void pclk_div_uart_repl_init(void); +machine_uart_obj_t repl_uart_obj; +static uint8_t repl_uart_buf[MICROPYTHON_REPL_RINGBUF_SIZE]; + +void machine_uart_repl_init() { + repl_uart_obj.tx = MICROPYTHON_REPL_UART_TX_PIN; + repl_uart_obj.rx = MICROPYTHON_REPL_UART_RX_PIN; + + mp_hal_pin_af_config_t uart_pins_config[2] = { + MP_HAL_PIN_AF_CONF_INIT(repl_uart_obj.tx, CY_GPIO_DM_STRONG_IN_OFF, 1, MACHINE_PIN_AF_SIGNAL_UART_TX), + MP_HAL_PIN_AF_CONF_INIT(repl_uart_obj.rx, CY_GPIO_DM_HIGHZ, 0, MACHINE_PIN_AF_SIGNAL_UART_RX), + }; + + uint8_t scb_unit = uart_pins_config[0].af->unit; + + repl_uart_obj.scb_obj = machine_scb_obj_alloc(scb_unit, &repl_uart_obj, machine_uart_scb_isr); + repl_uart_obj.id = scb_unit; + mp_hal_periph_pins_af_init(uart_pins_config, 2); + + repl_uart_obj.baudrate = DEFAULT_UART_BAUDRATE; + + pclk_div_uart_repl_init(); + + repl_uart_obj.bits = DEFAULT_UART_BITS; + repl_uart_obj.parity = mp_const_none; + repl_uart_obj.stop = 1; + repl_uart_obj.timeout_ms = 0; + repl_uart_obj.timeout_char_ms = 13000 / repl_uart_obj.baudrate + 1; + + repl_uart_obj.rx_ringbuf.buf = repl_uart_buf; + repl_uart_obj.rx_ringbuf.size = sizeof(repl_uart_buf); + + #if MICROPY_PY_MACHINE_UART_IRQ + repl_uart_obj.mp_irq_obj = NULL; + repl_uart_obj.mp_irq_trigger = 0; + repl_uart_obj.mp_irq_flags = 0; + #endif + + machine_uart_hw_init(&repl_uart_obj); +} + +int machine_uart_repl_readchar(void) { + for (;;) { + int c = ringbuf_get(&repl_uart_obj.rx_ringbuf); + if (c != -1) { + return c; + } + mp_event_handle_nowait(); + } +} + +void machine_uart_repl_write(const void *buf_in, mp_uint_t size) { + int errcode; + mp_machine_uart_write(&repl_uart_obj, buf_in, size, &errcode); +} + +uintptr_t machine_uart_repl_ioctl(uintptr_t arg) { + int errcode; + return mp_machine_uart_ioctl(&repl_uart_obj, MP_STREAM_POLL, arg, &errcode); +} diff --git a/ports/psoc-edge/main.c b/ports/psoc-edge/main.c new file mode 100644 index 00000000000..86f9eb74161 --- /dev/null +++ b/ports/psoc-edge/main.c @@ -0,0 +1,189 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022-2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// std includes +#include +#include +#include + + +// MTB includes +#include "cybsp.h" + +// micropython includes +#include "py/builtin.h" +#include "py/compile.h" +#include "py/gc.h" +#include "py/mperrno.h" +#include "py/stackctrl.h" +#include "py/runtime.h" +#include "shared/runtime/gchelper.h" +#include "shared/runtime/pyexec.h" +#include "shared/readline/readline.h" + +// port-specific includes +#include "mphalport.h" + +typedef enum { + BOOT_MODE_NORMAL, + BOOT_MODE_SAFE +} boot_mode_t; + + +#if MICROPY_ENABLE_GC +extern uint8_t __StackTop, __StackSize; +extern uint8_t __HeapBase, __HeapLimit; +#endif + +extern void machine_rtc_init_all(void); +extern void machine_pin_irq_deinit_all(void); +extern void machine_uart_deinit_all(void); +extern void mp_hal_ticks_init(void); + +boot_mode_t check_boot_mode(void) { + boot_mode_t boot_mode; + + // Initialize user LED + Cy_GPIO_Pin_FastInit(CYBSP_USER_LED_PORT, CYBSP_USER_LED_NUM, CY_GPIO_DM_STRONG, 0, HSIOM_SEL_GPIO); + + // Initialize user button + Cy_GPIO_Pin_FastInit(CYBSP_USER_BTN1_PORT, CYBSP_USER_BTN1_NUM, CY_GPIO_DM_PULLUP, 1, HSIOM_SEL_GPIO); + + // Added 5ms delay to allow bypass capacitor connected to the user button without external pull-up to charge. + Cy_SysLib_Delay(5); + + if (Cy_GPIO_Read(CYBSP_USER_BTN1_PORT, CYBSP_USER_BTN1_NUM) == CYBSP_BTN_PRESSED) { + // Blink LED twice to indicate safe boot mode was entered + for (int i = 0; i < 4; i++) { + Cy_GPIO_Inv(CYBSP_USER_LED_PORT, CYBSP_USER_LED_NUM); + Cy_SysLib_Delay(500); // delay in milliseconds + } + boot_mode = BOOT_MODE_SAFE; + mp_printf(&mp_plat_print, "- DEVICE IS IN SAFE BOOT MODE -\n"); + } else { + boot_mode = BOOT_MODE_NORMAL; + } + + // Turn off LED after boot mode check + Cy_GPIO_Clr(CYBSP_USER_LED_PORT, CYBSP_USER_LED_NUM); + + return boot_mode; +} + +int main(void) { + cy_rslt_t result = CY_RSLT_SUCCESS; + + /* Initialize the device and board peripherals. */ + result = cybsp_init(); + if (result != CY_RSLT_SUCCESS) { + mp_raise_ValueError(MP_ERROR_TEXT("cybsp_init failed !\n")); + } + + /* Enable global interrupts */ + __enable_irq(); + + /* Initialize stdio interface */ + mp_hal_stdio_init(); + + // Initialise the MicroPython runtime. + #if MICROPY_ENABLE_GC + gc_init(&__HeapBase, &__HeapLimit); + mp_cstack_init_with_top((void *)&__StackTop, (size_t)&__StackSize); + #endif + + mp_hal_ticks_init(); + +soft_reset: + machine_rtc_init_all(); + mp_init(); + + readline_init0(); + + #if MICROPY_VFS + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_)); + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_lib)); + + + #if MICROPY_VFS_LFS2 + pyexec_frozen_module("_boot.py", false); + #endif + #endif + + if (check_boot_mode() == BOOT_MODE_NORMAL) { + // Execute user scripts. + int ret = pyexec_file_if_exists("/boot.py"); + + if (ret & PYEXEC_FORCED_EXIT) { + goto soft_reset; + } + + if (pyexec_mode_kind == PYEXEC_MODE_FRIENDLY_REPL) { + ret = pyexec_file_if_exists("/main.py"); + + if (ret & PYEXEC_FORCED_EXIT) { + goto soft_reset; + } + } + } + + for (;;) { + if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) { + if (pyexec_raw_repl() != 0) { + break; + } + } else { + if (pyexec_friendly_repl() != 0) { + break; + } + } + } + + mp_printf(&mp_plat_print, "MPY: soft reboot\n"); + + machine_pin_irq_deinit_all(); + machine_uart_deinit_all(); + + #if MICROPY_ENABLE_GC + gc_sweep_all(); + #endif + mp_deinit(); + + goto soft_reset; +} + +#if MICROPY_ENABLE_GC +void gc_collect(void) { + gc_collect_start(); + gc_helper_collect_regs_and_stack(); + gc_collect_end(); +} +#endif + +// Handle uncaught exceptions (should never be reached in a correct C implementation). +void nlr_jump_fail(void *val) { + for (;;) { + } +} diff --git a/ports/psoc-edge/modmachine.c b/ports/psoc-edge/modmachine.c new file mode 100644 index 00000000000..e0ec7a3ccc1 --- /dev/null +++ b/ports/psoc-edge/modmachine.c @@ -0,0 +1,78 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022-2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// std includes +#include +#include + +// mpy includes +#include "py/obj.h" +#include "py/gc.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "shared/runtime/pyexec.h" +#include "extmod/modnetwork.h" + +// port-specific includes +#include "cybsp.h" +#include "modmachine.h" +#include "modpsocedge.h" + +enum clock_freq_type PLL0_freq = AUDIO_SYS_CLOCK_73_728_000_HZ; +enum clock_freq_type freq_peri; + +#if MICROPY_PY_MACHINE + +// machine.idle() +// This executies a wfi machine instruction which reduces power consumption +// of the MCU until an interrupt occurs, at which point execution continues. +static void mp_machine_idle(void) { + __WFI(); // standard ARM instruction +} +/* TODO: currently unused +static void mp_machine_set_freq(size_t n_args, const mp_obj_t *args) { + freq_peri = mp_obj_get_int(args[0]); // Assuming the enum values are used as integers + switch (freq_peri) { + case AUDIO_SYS_CLOCK_73_728_000_HZ: + PLL0_freq = AUDIO_SYS_CLOCK_73_728_000_HZ; + break; + case AUDIO_SYS_CLOCK_169_344_000_HZ: + PLL0_freq = AUDIO_SYS_CLOCK_169_344_000_HZ; + break; + default: + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid frequency type %lu"), freq_peri); + break; + } +} +*/ + +#define MICROPY_PY_MACHINE_EXTRA_GLOBALS \ + /* Modules */ \ + { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&machine_pin_type) }, \ + { MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&machine_rtc_type) }, \ + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&machine_uart_type) }, \ + +#endif // MICROPY_PY_MACHINE diff --git a/ports/psoc-edge/modmachine.h b/ports/psoc-edge/modmachine.h new file mode 100644 index 00000000000..cc3cfb5da5b --- /dev/null +++ b/ports/psoc-edge/modmachine.h @@ -0,0 +1,46 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022-2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_PSOCEDGE_MODMACHINE_H +#define MICROPY_INCLUDED_PSOCEDGE_MODMACHINE_H + + +// micropython includes +#include "py/obj.h" + +enum clock_freq_type { + AUDIO_SYS_CLOCK_73_728_000_HZ = 73728000UL /* (Ideally 73.728 MHz) For sample rates: 8 KHz / 16 KHz / 48 KHz */, + AUDIO_SYS_CLOCK_169_344_000_HZ = 169344000UL /* (Ideally 169.344 MHz) For sample rates: 22.05 KHz / 44.1 KHz */, + CM4, + CM4_FLL +}; + +extern enum clock_freq_type PLL0_freq; +extern const mp_obj_type_t machine_uart_type; +extern const mp_obj_type_t machine_pdm_pcm_type; +extern const mp_obj_type_t machine_rtc_type; + +#endif // MICROPY_INCLUDED_PSOCEDGE_MODMACHINE_H diff --git a/ports/psoc-edge/modpsocedge.c b/ports/psoc-edge/modpsocedge.c new file mode 100644 index 00000000000..156253572ec --- /dev/null +++ b/ports/psoc-edge/modpsocedge.c @@ -0,0 +1,50 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020-2021 Damien P. George + * Copyright (c) 2022-2024 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// micropython includes +#include "py/runtime.h" + + +// port-specific includes +#include "modpsocedge.h" + +static const mp_rom_map_elem_t psoc_edge_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_psoc_edge) }, + #if MICROPY_ENABLE_EXT_QSPI_FLASH + { MP_ROM_QSTR(MP_QSTR_QSPI_Flash), MP_ROM_PTR(&psoc_edge_qspi_flash_type) }, + #endif +}; +static MP_DEFINE_CONST_DICT(psoc_edge_module_globals, psoc_edge_module_globals_table); + + +const mp_obj_module_t mp_module_psoc_edge = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t *)&psoc_edge_module_globals, +}; + + +MP_REGISTER_MODULE(MP_QSTR_psoc_edge, mp_module_psoc_edge); diff --git a/ports/psoc-edge/modpsocedge.h b/ports/psoc-edge/modpsocedge.h new file mode 100644 index 00000000000..004dcecf920 --- /dev/null +++ b/ports/psoc-edge/modpsocedge.h @@ -0,0 +1,36 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020-2021 Damien P. George + * Copyright (c) 2022-2024 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_PSOCEDGE_MODPSOCEDGE_H +#define MICROPY_INCLUDED_PSOCEDGE_MODPSOCEDGE_H + + +// micropython includes +#include "py/obj.h" + +extern const mp_obj_type_t psoc_edge_qspi_flash_type; + +#endif // MICROPY_INCLUDED_PSOCEDGE_MODPSOCEDGE_H diff --git a/ports/psoc-edge/modtime.c b/ports/psoc-edge/modtime.c new file mode 100644 index 00000000000..3229198f5d3 --- /dev/null +++ b/ports/psoc-edge/modtime.c @@ -0,0 +1,54 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2021 Damien P. George + * Copyright (c) 2023-2024 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// std includes +#include "stdio.h" +#include + +// micropython includes +#include "extmod/modtime.h" +#include "modmachine.h" +#include "py/runtime.h" +#include "shared/timeutils/timeutils.h" + +extern void machine_rtc_get_datetime(timeutils_struct_time_t *time); + +static void mp_time_localtime_get(timeutils_struct_time_t *time) { + machine_rtc_get_datetime(time); +} + +uint64_t mp_hal_time_get_epoch_seconds(void) { + timeutils_struct_time_t current_date_time; + machine_rtc_get_datetime(¤t_date_time); + + return timeutils_seconds_since_epoch(current_date_time.tm_year, current_date_time.tm_mon, current_date_time.tm_mday, + current_date_time.tm_hour, current_date_time.tm_min, current_date_time.tm_sec); +} + +static mp_obj_t mp_time_time_get(void) { + return timeutils_obj_from_timestamp(mp_hal_time_get_epoch_seconds()); +} diff --git a/ports/psoc-edge/modules/_boot.py b/ports/psoc-edge/modules/_boot.py new file mode 100644 index 00000000000..780652b2773 --- /dev/null +++ b/ports/psoc-edge/modules/_boot.py @@ -0,0 +1,23 @@ +def boot(): + import os, machine, psoc_edge as psocedge + + # Create block device instance from external flash + bdev = psocedge.QSPI_Flash() + + # sector size 4 KB for external flash + read_size = 0x1000 + # page size 256 B + write_size = 0x200 + + try: + vfs = os.VfsLfs2(bdev, progsize=write_size, readsize=read_size) + os.mount(vfs, "/") + except: + # Format flash if filesystem not found + os.VfsLfs2.mkfs(bdev, progsize=write_size, readsize=read_size) + vfs = os.VfsLfs2(bdev, progsize=write_size, readsize=read_size) + os.mount(vfs, "/") + + +boot() +del boot diff --git a/ports/psoc-edge/mpconfigport.h b/ports/psoc-edge/mpconfigport.h new file mode 100644 index 00000000000..bfc1c20580d --- /dev/null +++ b/ports/psoc-edge/mpconfigport.h @@ -0,0 +1,85 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2022-2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// Options controlling how MicroPython is built, overriding defaults in py/mpconfig.h +#include +#include "mpconfigboard.h" + +// Use core features for Thonny compatibility (larger firmware) +#define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_EXTRA_FEATURES) + +// MicroPython emitters +#define MICROPY_PERSISTENT_CODE_LOAD (1) +#define MICROPY_EMIT_THUMB (1) +#define MICROPY_EMIT_INLINE_THUMB (1) +#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void *)((mp_uint_t)(p) | 1)) + +// Python internal features +#define MICROPY_READER_VFS (1) +#define MICROPY_ENABLE_GC (1) +#define MICROPY_STACK_CHECK_MARGIN (1024) +#define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) +#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ) +#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT) +#define MICROPY_SCHEDULER_DEPTH (8) +#define MICROPY_SCHEDULER_STATIC_NODES (1) +#define MICROPY_USE_INTERNAL_ERRNO (1) +#define MICROPY_ALLOC_PARSE_CHUNK_INIT (16) +#define MICROPY_PY_MATH_GAMMA_FIX_NEGINF (1) + +// Fine control over Python builtins, classes, modules, etc +#define MICROPY_PY_SYS_PLATFORM "psoc-edge" +#define MICROPY_PY_BUILTINS_HELP_TEXT psoc_edge_help_text +#define MICROPY_REPL_INFO (1) + +// Extended modules +#define MICROPY_PY_TIME_GMTIME_LOCALTIME_MKTIME (1) +#define MICROPY_PY_TIME_TIME_TIME_NS (1) +#define MICROPY_PY_TIME_INCLUDEFILE "ports/psoc-edge/modtime.c" +#define MICROPY_TIME_SUPPORT_Y1969_AND_BEFORE (1) +#define MICROPY_EPOCH_IS_1970 (1) +#define MICROPY_VFS (1) +#define MICROPY_ALLOC_PATH_MAX (256) + +// Machine module +#define MICROPY_PY_MACHINE (1) +#define MICROPY_PY_MACHINE_INCLUDEFILE "ports/psoc-edge/modmachine.c" + +#define MICROPY_PY_MACHINE_PIN_MAKE_NEW mp_pin_make_new + +#define MICROPY_PY_MACHINE_UART (1) +#define MICROPY_PY_MACHINE_UART_INCLUDEFILE "ports/psoc-edge/machine_uart.c" +#define MICROPY_PY_MACHINE_UART_SENDBREAK (1) +#define MICROPY_PY_MACHINE_UART_READCHAR_WRITECHAR (1) +#define MICROPY_PY_MACHINE_UART_IRQ (1) +#define MICROPY_STREAMS_NON_BLOCK (1) + +// type definitions for the specific machine +#define MP_SSIZE_MAX (0x7fffffff) + +typedef long mp_off_t; + +#define MP_STATE_PORT MP_STATE_VM diff --git a/ports/psoc-edge/mpconfigport.mk b/ports/psoc-edge/mpconfigport.mk new file mode 100644 index 00000000000..902dafd8bca --- /dev/null +++ b/ports/psoc-edge/mpconfigport.mk @@ -0,0 +1 @@ +MICROPY_VFS_LFS2=1 \ No newline at end of file diff --git a/ports/psoc-edge/mphalport.c b/ports/psoc-edge/mphalport.c new file mode 100644 index 00000000000..154f2a87cf8 --- /dev/null +++ b/ports/psoc-edge/mphalport.c @@ -0,0 +1,183 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// std includes +#include "stdio.h" + +// MTB includes +#include "mtb_hal_system.h" + +// micropython includes +#include "mpconfigport.h" +#include "mphalport.h" + +#include "py/runtime.h" + +extern void machine_uart_repl_init(void); +extern int machine_uart_repl_readchar(void); +extern void machine_uart_repl_write(const void *buf_in, mp_uint_t size); +extern uintptr_t machine_uart_repl_ioctl(uintptr_t arg); + +void mp_hal_stdio_init(void) { + machine_uart_repl_init(); +} + +uintptr_t mp_hal_stdio_poll(uintptr_t poll_flags) { + return machine_uart_repl_ioctl(poll_flags); +} + +void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) { + machine_uart_repl_write(str, len); +} + +int mp_hal_stdin_rx_chr(void) { + return machine_uart_repl_readchar(); +} + +extern uint32_t get_drive_mode(uint8_t mode, uint8_t pull, uint8_t *value); + +void mp_hal_pin_config(mp_hal_pin_obj_t pin, uint32_t mode, uint32_t pull, uint32_t value) { + uint8_t validated_value = (uint8_t)value; + uint32_t drive_mode = get_drive_mode(mode, pull, &validated_value); + Cy_GPIO_Pin_FastInit(Cy_GPIO_PortToAddr(pin->port), pin->pin, drive_mode, validated_value, HSIOM_SEL_GPIO); +} + +extern uint8_t pin_get_mode(const machine_pin_obj_t *self); + +uint32_t mp_hal_pin_read(mp_hal_pin_obj_t pin) { + return Cy_GPIO_Read(Cy_GPIO_PortToAddr(pin->port), pin->pin); +} + +void mp_hal_pin_write(mp_hal_pin_obj_t pin, uint8_t polarity) { + Cy_GPIO_Write(Cy_GPIO_PortToAddr(pin->port), pin->pin, polarity); +} + +mp_hal_pin_af_obj_t mp_hal_pin_af_find(mp_hal_pin_obj_t pin, machine_pin_af_signal_t af_signal) { + for (uint8_t i = 0; i < pin->af_num; i++) { + const machine_pin_af_obj_t *af = &pin->af[i]; + if (af->signal == af_signal) { + return af; + } + } + + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin '%q' does not support '%s'."), pin->name, machine_pin_af_signal_str[af_signal]); +} + +machine_pin_af_unit_t mp_hal_periph_pins_af_get_af_unit(const mp_hal_pin_af_config_t *periph_pins_config, uint8_t num_pins, machine_pin_af_fn_t fn) { + bool found_first_valid_pin = false; + machine_pin_af_periph_t periph_ptr = NULL; + uint32_t unit = MACHINE_PIN_AF_UNIT_NONE; + for (uint8_t i = 0; i < num_pins; i++) { + const mp_hal_pin_af_config_t *pin_cfg = &periph_pins_config[i]; + if (pin_cfg->pin == NULL || pin_cfg->af == NULL) { + continue; + } + if (!found_first_valid_pin) { + periph_ptr = pin_cfg->af->periph; + unit = pin_cfg->af->unit; + found_first_valid_pin = true; + } else { + if (pin_cfg->af->fn != fn) { + mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("all pins must belong to the same function.")); + } + if (pin_cfg->af->periph != periph_ptr) { + mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("all pins must belong to the same peripheral.")); + } + if (pin_cfg->af->unit != unit) { + mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("all pins must belong to the same unit.")); + } + } + } + + return unit; +} + +void mp_hal_periph_pins_af_resolve_fn_unit(const mp_hal_pin_af_config_t *periph_pins_config, uint8_t pin_num, machine_pin_af_fn_t fn, machine_pin_af_unit_t *fn_unit) { + uint8_t resolved_fn_unit; + uint8_t suggested_fn_unit = *fn_unit; + + /** + * Resolve the AF unit for the provided pins. + * It can be that the configuration still don't have + * any pin AF assigned. + * Therefore, its AF unit is not yet determined. + */ + machine_pin_af_unit_t pin_af_unit = mp_hal_periph_pins_af_get_af_unit(periph_pins_config, pin_num, fn); + + /* No pins have been defined. */ + if (pin_af_unit == MACHINE_PIN_AF_UNIT_NONE) { + /* The suggested AF unit candidate is chosen if defined. */ + if (suggested_fn_unit != MACHINE_PIN_AF_UNIT_NONE) { + resolved_fn_unit = (uint8_t)suggested_fn_unit; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("no id or pins have been provided. At least one of them must be specified.")); + } + } else { + /* The pins have been defined. */ + /* The suggested AF unit has been also defined.*/ + if (suggested_fn_unit != MACHINE_PIN_AF_UNIT_NONE) { + if (suggested_fn_unit == pin_af_unit) { + /* The suggested AF unit matches the AF unit discovered from the passed pins */ + resolved_fn_unit = (uint8_t)suggested_fn_unit; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("the id does not match the discovered id from the provided pins.")); + } + } else { + /* No suggested AF unit has been passed */ + resolved_fn_unit = pin_af_unit; + } + } + + (*fn_unit) = resolved_fn_unit; +} + +void mp_hal_periph_pins_af_resolve_pin_af(mp_hal_pin_af_config_t *periph_pins_config, uint8_t pin_num, machine_pin_af_unit_t fn_unit) { + for (uint8_t i = 0; i < pin_num; i++) { + if (periph_pins_config[i].af == NULL && periph_pins_config[i].pin == NULL) { + periph_pins_config[i].pin = machine_pin_get_af_pin(fn_unit, periph_pins_config[i].signal); + if (periph_pins_config[i].pin == NULL) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("no signal '%s' available for id %d."), machine_pin_af_signal_str[periph_pins_config[i].signal], fn_unit); + } + periph_pins_config[i].af = mp_hal_pin_af_find(periph_pins_config[i].pin, periph_pins_config[i].signal); + } else { + /** + * It should not enter here. As this function should + * be only called after pin - AF unit matching */ + if (periph_pins_config[i].af->unit != fn_unit && periph_pins_config[i].pin != NULL) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("the pin '%q' does not match the AF unit %d."), periph_pins_config[i].pin->name, fn_unit); + } + } + } +} + +machine_pin_af_periph_t mp_hal_periph_pins_af_init(const mp_hal_pin_af_config_t *periph_pins_config, uint8_t num_pins) { + for (uint8_t i = 0; i < num_pins; i++) { + const mp_hal_pin_af_config_t *pin_cfg = &periph_pins_config[i]; + Cy_GPIO_Pin_FastInit(Cy_GPIO_PortToAddr(pin_cfg->pin->port), pin_cfg->pin->pin, pin_cfg->cy_drive_mode, pin_cfg->init_value, pin_cfg->af->idx); + } + + return periph_pins_config[0].af->periph; +} diff --git a/ports/psoc-edge/mphalport.h b/ports/psoc-edge/mphalport.h new file mode 100644 index 00000000000..cab18f4564b --- /dev/null +++ b/ports/psoc-edge/mphalport.h @@ -0,0 +1,126 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_PSOC_EDGE_HALPORT_H +#define MICROPY_INCLUDED_PSOC_EDGE_HALPORT_H + +// std includes +#include +#include + + +// micropython includes +#include "py/mpconfig.h" +#include "py/runtime.h" +#include "machine_pin.h" + +#include "cybsp.h" + +static inline void enable_irq(mp_uint_t state) { + if (state == 0) { + __enable_irq(); + } +} + +static inline mp_uint_t disable_irq(void) { + mp_uint_t state = __get_PRIMASK(); + __disable_irq(); + return state; +} + +#define MICROPY_BEGIN_ATOMIC_SECTION() disable_irq() +#define MICROPY_END_ATOMIC_SECTION(state) enable_irq(state) + +#define mp_hal_delay_us_fast mp_hal_delay_us + +void mp_hal_delay_us(mp_uint_t us); +void mp_hal_delay_us_fast(mp_uint_t us); +void mp_hal_delay_ms(mp_uint_t ms); + +void mp_hal_stdio_init(void); +uintptr_t mp_hal_stdio_poll(uintptr_t poll_flags); +int mp_hal_stdin_rx_chr(void); +void mp_hal_set_interrupt_char(int c); // -1 to disable + + +#define MP_HAL_PIN_FMT "\'%q\'" +#define mp_hal_pin_obj_t const machine_pin_obj_t * +#define mp_hal_get_pin_obj(o) machine_pin_get_pin_obj(o) +#define mp_hal_pin_name(p) ((p)->name) +#define mp_hal_pin_input(p) mp_hal_pin_config((p), GPIO_MODE_IN, GPIO_PULL_NONE, 0) +#define mp_hal_pin_output(p) mp_hal_pin_config((p), GPIO_MODE_OUT, GPIO_PULL_NONE, 0) +#define mp_hal_pin_open_drain(p) mp_hal_pin_config((p), GPIO_MODE_OPEN_DRAIN, GPIO_PULL_NONE, 0) +#define mp_hal_pin_high(p) mp_hal_pin_write((p), 1) +#define mp_hal_pin_low(p) mp_hal_pin_write((p), 0) +#define mp_hal_pin_od_low(p) mp_hal_pin_low(p) +#define mp_hal_pin_od_high(p) mp_hal_pin_high(p) + +void mp_hal_pin_config(mp_hal_pin_obj_t pin, uint32_t mode, uint32_t pull, uint32_t value); +void mp_hal_pin_write(mp_hal_pin_obj_t pin, uint8_t polarity); +uint32_t mp_hal_pin_read(mp_hal_pin_obj_t pin); + +/** + * HAL Pin AF helper functions and types + */ + +#define mp_hal_pin_af_obj_t const machine_pin_af_obj_t * + +typedef struct { + mp_hal_pin_obj_t pin; + machine_pin_af_signal_t signal; + uint32_t cy_drive_mode; + uint32_t init_value; + mp_hal_pin_af_obj_t af; +}mp_hal_pin_af_config_t; + +#define MP_HAL_PIN_AF_CONF_INIT(_pin, _cy_drive_mode, _init_value, _af_signal) (mp_hal_pin_af_config_t) { \ + .pin = _pin, \ + .signal = _af_signal, \ + .cy_drive_mode = _cy_drive_mode, \ + .init_value = _init_value, \ + .af = mp_hal_pin_af_find(_pin, _af_signal) \ +} + +#define MP_HAL_PIN_AF_CONF_INIT_GPIO_SIGNAL(_cy_drive_mode, _init_value, _af_signal) (mp_hal_pin_af_config_t) { \ + .pin = NULL, \ + .signal = _af_signal, \ + .cy_drive_mode = _cy_drive_mode, \ + .init_value = _init_value, \ + .af = NULL \ +} + +#define MP_HAL_PIN_AF_CONF_SET_PIN_AF(conf_obj, _pin) \ + conf_obj.pin = _pin; \ + conf_obj.af = mp_hal_pin_af_find(_pin, conf_obj.signal); + + +mp_hal_pin_af_obj_t mp_hal_pin_af_find(mp_hal_pin_obj_t pin, machine_pin_af_signal_t af_signal); + +void mp_hal_periph_pins_af_resolve_fn_unit(const mp_hal_pin_af_config_t *periph_pins_config, uint8_t pin_num, machine_pin_af_fn_t fn, machine_pin_af_unit_t *fn_unit); +void mp_hal_periph_pins_af_resolve_pin_af(mp_hal_pin_af_config_t *periph_pins_config, uint8_t pin_num, machine_pin_af_unit_t fn_unit); +machine_pin_af_periph_t mp_hal_periph_pins_af_init(const mp_hal_pin_af_config_t *periph_pins_config, uint8_t num_pins); + +#endif // MICROPY_INCLUDED_PSOC_EDGE_HALPORT_H diff --git a/ports/psoc-edge/psoc_edge_qspi_flash.c b/ports/psoc-edge/psoc_edge_qspi_flash.c new file mode 100644 index 00000000000..ae661fedfb3 --- /dev/null +++ b/ports/psoc-edge/psoc_edge_qspi_flash.c @@ -0,0 +1,252 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020-2021 Damien P. George + * Copyright (c) 2022-2024 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// std includes +#include +#include + +// micropython includes +#include "py/runtime.h" +#include "extmod/vfs.h" +#include "modpsocedge.h" +#include "py/misc.h" + +// MTB includes +#include "cybsp.h" +#include "cy_pdl.h" +#include "mphalport.h" +#include "cycfg_qspi_memslot.h" +#include "mtb_serial_memory.h" + +#define DEBUG_printf(...) // printf(__VA_ARGS__) + +#ifndef MICROPY_HW_FLASH_STORAGE_BYTES +#define MICROPY_HW_FLASH_STORAGE_BYTES (EXT_FLASH_SIZE) +#endif +static_assert(MICROPY_HW_FLASH_STORAGE_BYTES % EXT_FLASH_SECTOR_SIZE == 0, "Flash storage size must be a multiple of sector size"); + +#ifndef MICROPY_HW_FLASH_STORAGE_BASE +#define MICROPY_HW_FLASH_STORAGE_BASE (EXT_FLASH_BASE) +#endif + +/* Slot number of the memory to use */ +#define MEM_SLOT_NUM (0U) +#define MEM_SLOT_DIVIDER (2U) +#define MEM_SLOT_MULTIPLIER (2U) + +/* 100 MHz interface clock frequency */ +#define QSPI_BUS_FREQUENCY_HZ (100000000Ul) + +uint8_t qspi_flash_init = 0; + +mtb_serial_memory_t serial_memory_obj; +cy_stc_smif_mem_context_t smif_mem_context; +cy_stc_smif_mem_info_t smif_mem_info; + +typedef struct _psoc_edge_qspi_flash_obj_t { + mp_obj_base_t base; + uint32_t flash_base; + uint32_t flash_size; +} psoc_edge_qspi_flash_obj_t; + +// Static singleton object for default flash access +static psoc_edge_qspi_flash_obj_t psoc_edge_qspi_flash_obj = { + .base = { &psoc_edge_qspi_flash_type }, + .flash_base = EXT_FLASH_BASE, + .flash_size = EXT_FLASH_SIZE, +}; + +static mp_obj_t psoc_edge_qspi_flash_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + /* Set-up serial memory. */ + cy_rslt_t result = CY_RSLT_SUCCESS; + + if (!qspi_flash_init) { + result = mtb_serial_memory_setup(&serial_memory_obj, + MTB_SERIAL_MEMORY_CHIP_SELECT_1, + CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_config.base, + CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_config.clock, + &smif_mem_context, + &smif_mem_info, + &smif0BlockConfig); + + if (result == CY_RSLT_SUCCESS) { + qspi_flash_init = true; + } else { + DEBUG_printf("psoc_edge_qspi_flash_make_new() failed with error code: 0x%08lx\n", result); + mp_raise_msg(&mp_type_Exception, MP_ERROR_TEXT("psoc_edge_qspi_flash_make_new() - QSPI flash init failed!\n")); + } + } + + // Parse arguments + enum { ARG_start, ARG_len }; + + static const mp_arg_t allowed_args[] = { + { MP_QSTR_start, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_len, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + }; + + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (args[ARG_start].u_int == -1 && args[ARG_len].u_int == -1) { + // Default singleton object that accesses entire flash + return MP_OBJ_FROM_PTR(&psoc_edge_qspi_flash_obj); + } + + // Create new object with custom start/len + psoc_edge_qspi_flash_obj_t *self = mp_obj_malloc(psoc_edge_qspi_flash_obj_t, &psoc_edge_qspi_flash_type); + + mp_int_t start = args[ARG_start].u_int; + + if (start == -1) { + start = 0; + } else if (!(0 <= start && start < MICROPY_HW_FLASH_STORAGE_BYTES && start % EXT_FLASH_SECTOR_SIZE == 0)) { + mp_raise_ValueError(MP_ERROR_TEXT("invalid 'start' value")); + } + + mp_int_t len = args[ARG_len].u_int; + + if (len == -1) { + len = MICROPY_HW_FLASH_STORAGE_BYTES - start; + } else if (!(0 < len && start + len <= MICROPY_HW_FLASH_STORAGE_BYTES && len % EXT_FLASH_SECTOR_SIZE == 0)) { + mp_raise_ValueError(MP_ERROR_TEXT("invalid 'len' value")); + } + + self->flash_base = MICROPY_HW_FLASH_STORAGE_BASE + start; + self->flash_size = len; + + return MP_OBJ_FROM_PTR(self); +} + +static mp_obj_t psoc_edge_qspi_flash_readblocks(size_t n_args, const mp_obj_t *args) { + psoc_edge_qspi_flash_obj_t *self = MP_OBJ_TO_PTR(args[0]); + uint32_t offset = mp_obj_get_int(args[1]) * EXT_FLASH_BLOCK_SIZE_BYTES; + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[2], &bufinfo, MP_BUFFER_WRITE); + + if (n_args == 4) { + offset += mp_obj_get_int(args[3]); + } + cy_rslt_t result = mtb_serial_memory_read(&serial_memory_obj, self->flash_base + offset, bufinfo.len, bufinfo.buf); + + if (result != CY_RSLT_SUCCESS) { + mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("read failed: 0x%08lx"), result); + } + + return mp_const_none; +} + +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(psoc_edge_qspi_flash_readblocks_obj, 3, 4, psoc_edge_qspi_flash_readblocks); + +static mp_obj_t psoc_edge_qspi_flash_writeblocks(size_t n_args, const mp_obj_t *args) { + psoc_edge_qspi_flash_obj_t *self = MP_OBJ_TO_PTR(args[0]); + uint32_t offset = mp_obj_get_int(args[1]) * EXT_FLASH_BLOCK_SIZE_BYTES; + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[2], &bufinfo, MP_BUFFER_READ); + + if (n_args == 3) { + // Round up to ensure we erase all sectors that will be written to + uint32_t numSectors = (bufinfo.len + EXT_FLASH_SECTOR_SIZE - 1) / EXT_FLASH_SECTOR_SIZE; + + for (uint32_t i = 0; i < numSectors; ++i) { + cy_rslt_t result = mtb_serial_memory_erase(&serial_memory_obj, self->flash_base + offset + i * EXT_FLASH_SECTOR_SIZE, mtb_serial_memory_get_erase_size(&serial_memory_obj, self->flash_base + offset + i * EXT_FLASH_SECTOR_SIZE)); + // the mtb_serial_memory_get_erase_size() function call is necessary to keep the erase at sector boundary, else it throws errors. + + if (CY_RSLT_SUCCESS != result) { + mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("erase before write failed: 0x%08lx"), result); + } + } + } else { + offset += mp_obj_get_int(args[3]); + } + + cy_rslt_t result = mtb_serial_memory_write(&serial_memory_obj, self->flash_base + offset, bufinfo.len, bufinfo.buf); + + if (result != CY_RSLT_SUCCESS) { + mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("write failed: 0x%08lx"), result); + } + + return mp_const_none; +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(psoc_edge_qspi_flash_writeblocks_obj, 3, 4, psoc_edge_qspi_flash_writeblocks); + +static mp_obj_t psoc_edge_qspi_flash_ioctl(mp_obj_t self_in, mp_obj_t cmd_in, mp_obj_t arg_in) { + psoc_edge_qspi_flash_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_int_t cmd = mp_obj_get_int(cmd_in); + + switch (cmd) { + case MP_BLOCKDEV_IOCTL_INIT: + if (!qspi_flash_init) { + mtb_serial_memory_setup(&serial_memory_obj, + MTB_SERIAL_MEMORY_CHIP_SELECT_1, + CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_config.base, + CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_config.clock, + &smif_mem_context, + &smif_mem_info, + &smif0BlockConfig); + qspi_flash_init = true; + } + return MP_OBJ_NEW_SMALL_INT(0); + case MP_BLOCKDEV_IOCTL_DEINIT: + if (qspi_flash_init) { + qspi_flash_init = false; + } + return MP_OBJ_NEW_SMALL_INT(0); + case MP_BLOCKDEV_IOCTL_SYNC: + return MP_OBJ_NEW_SMALL_INT(0); + case MP_BLOCKDEV_IOCTL_BLOCK_COUNT: + return MP_OBJ_NEW_SMALL_INT(self->flash_size / EXT_FLASH_SECTOR_SIZE); + case MP_BLOCKDEV_IOCTL_BLOCK_SIZE: + return MP_OBJ_NEW_SMALL_INT(EXT_FLASH_SECTOR_SIZE); + case MP_BLOCKDEV_IOCTL_BLOCK_ERASE: { + uint32_t offset = mp_obj_get_int(arg_in) * EXT_FLASH_BLOCK_SIZE_BYTES; + cy_rslt_t result = mtb_serial_memory_erase(&serial_memory_obj, self->flash_base + offset, mtb_serial_memory_get_erase_size(&serial_memory_obj, self->flash_base + offset)); + if (result != CY_RSLT_SUCCESS) { + mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("erase failed: 0x%08lx"), result); + } + return MP_OBJ_NEW_SMALL_INT(0); + } + default: + return mp_const_none; + } +} +static MP_DEFINE_CONST_FUN_OBJ_3(psoc_edge_qspi_flash_ioctl_obj, psoc_edge_qspi_flash_ioctl); + +static const mp_rom_map_elem_t psoc_edge_qspi_flash_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_readblocks), MP_ROM_PTR(&psoc_edge_qspi_flash_readblocks_obj) }, + { MP_ROM_QSTR(MP_QSTR_writeblocks), MP_ROM_PTR(&psoc_edge_qspi_flash_writeblocks_obj) }, + { MP_ROM_QSTR(MP_QSTR_ioctl), MP_ROM_PTR(&psoc_edge_qspi_flash_ioctl_obj) }, +}; +static MP_DEFINE_CONST_DICT(psoc_edge_qspi_flash_locals_dict, psoc_edge_qspi_flash_locals_dict_table); + +MP_DEFINE_CONST_OBJ_TYPE( + psoc_edge_qspi_flash_type, + MP_QSTR_QSPI_Flash, + MP_TYPE_FLAG_NONE, + make_new, psoc_edge_qspi_flash_make_new, + locals_dict, &psoc_edge_qspi_flash_locals_dict + ); diff --git a/ports/psoc-edge/qstrdefsport.h b/ports/psoc-edge/qstrdefsport.h new file mode 100644 index 00000000000..17a09fbb646 --- /dev/null +++ b/ports/psoc-edge/qstrdefsport.h @@ -0,0 +1,5 @@ +// qstrs specific to this port +// *FORMAT-OFF* +Q(/) +Q(/flash) +Q(/lib) diff --git a/ports/psoc-edge/secboot/Makefile b/ports/psoc-edge/secboot/Makefile new file mode 100644 index 00000000000..a51cd60182c --- /dev/null +++ b/ports/psoc-edge/secboot/Makefile @@ -0,0 +1,204 @@ +################################################################################# +# CM33 secure project + +BOARD ?= KIT_PSE84_AI +BOARD_DIR ?= ../boards/$(BOARD) +BUILD ?= ../build-$(BOARD)/secboot + +# Include the core environment definitions; this will set $(TOP). +include ../../../py/mkenv.mk + +CROSS_COMPILE ?= arm-none-eabi- + +PSE_LIB_TOP_DIR ?= lib/psoc-edge +PSE_LIB_DIR ?= $(TOP)/$(PSE_LIB_TOP_DIR) +BOARD_TOP_DIR = ports/psoc-edge/boards/$(BOARD) + +INC += $(addprefix -I$(TOP)/lib/,\ + CMSIS_6/CMSIS/Core/Include \ + CMSIS_6/CMSIS/Core/Include/a-profile \ + CMSIS_6/CMSIS/Core/Include/m-profile \ + CMSIS_6/CMSIS/Core/Include/r-profile \ +) + +DEFINES = \ + -DCOMPONENT_CM33 \ + -DCORE_NAME_CM33_0=1 \ + -DCOMPONENT_MTB_HAL \ + -DCOMPONENT_MW_ASYNC_TRANSFER \ + -DCOMPONENT_MW_MTB_IPC \ + -DCOMPONENT_MW_MTB_SRF \ + -DCOMPONENT_SECURE_DEVICE \ + -DCYBSP_MCUBOOT_HEADER_SIZE=0x400 \ + +INC += $(addprefix -I$(PSE_LIB_DIR)/,\ + async-transfer/include \ + \ + core-lib/include \ + \ + mtb-dsl-pse8xxgp/device-utils/syspm/hobto/pdm_pcm/audioss_pdm \ + mtb-dsl-pse8xxgp/device-utils/syspm/hobto/pdm_pcm/mxpdm \ + mtb-dsl-pse8xxgp/device-utils/syspm/include \ + \ + mtb-dsl-pse8xxgp/hal/include \ + \ + mtb-dsl-pse8xxgp/nnkernel/COMPONENT_CM33/include \ + \ + mtb-dsl-pse8xxgp/pdl/devices/include \ + mtb-dsl-pse8xxgp/pdl/devices/include/ip \ + mtb-dsl-pse8xxgp/pdl/drivers/include \ + mtb-dsl-pse8xxgp/pdl/drivers/third_party/ethernet/include \ + \ + mtb-ipc/include \ + \ + mtb-srf/include \ + \ + se-rt-services-utils \ + \ + TARGET_$(BOARD) \ + TARGET_$(BOARD)/bluetooth \ + TARGET_$(BOARD)/COMPONENT_CM33/COMPONENT_SECURE_DEVICE \ + ) + +INC += \ + -I$(BOARD_DIR) \ + -I$(BOARD_DIR)/bsp-cfg \ + +MACHINE_FLAGS = \ + -mcpu=cortex-m33 \ + --specs=nano.specs \ + --specs=nosys.specs \ + -mfloat-abi=hard \ + -mfpu=fpv5-sp-d16 \ + -mthumb + +CFLAGS += -c $(MACHINE_FLAGS) \ + -ffat-lto-objects \ + -g \ + -Wall \ + -pipe \ + -mcmse \ + $(INC) \ + $(DEFINES) \ + +ifeq ($(DEBUG), 1) +CFLAGS += -Og +else +CFLAGS += -Os -DNDEBUG +CFLAGS += -fdata-sections -ffunction-sections +endif + +# If the nsc_veneer.o is not present, it is +# generated without reference. +NSC_VENEER = nsc_veneer.o +NSC_VENEER_TEMP = $(BUILD)/$(NSC_VENEER).tmp +ifneq ($(wildcard $(NSC_VENEER)),) +IN_IMPLIB_FLAG = -Wl,--in-implib -Wl,$(NSC_VENEER) +endif + +LDFLAGS = $(MACHINE_FLAGS) \ + -Wl,--gc-sections \ + -Wl,--cmse-implib $(IN_IMPLIB_FLAG) -Wl,--out-implib -Wl,$(NSC_VENEER_TEMP) \ + -Wl,--print-memory-usage \ + -Wl,--no-warn-rwx-segments \ + -Xlinker -L $(PSE_LIB_DIR)/TARGET_$(BOARD)/COMPONENT_CM33/TOOLCHAIN_GCC_ARM \ + -Xlinker -L $(BOARD_DIR)/bsp-cfg \ + -T$(PSE_LIB_DIR)/TARGET_$(BOARD)/COMPONENT_CM33/TOOLCHAIN_GCC_ARM/pse84_s_cm33.ld \ + -Wl,-Map,$(BUILD)/secboot.map + +SRC_C = \ + main.c \ + +PSE_BSP_CFG_C += $(addprefix $(BOARD_TOP_DIR)/bsp-cfg/,\ + cycfg.c \ + cycfg_clocks.c \ + cycfg_peripheral_clocks.c \ + cycfg_peripherals.c \ + cycfg_pins.c \ + cycfg_protection.c \ + cycfg_routing.c \ + cycfg_system.c \ + ) + +PSE_LIB_SRC_C += $(addprefix $(PSE_LIB_TOP_DIR)/, \ + mtb-dsl-pse8xxgp/pdl/devices/source/cy_device.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_gpio.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_mpc.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_pdl_srf.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_ppc.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_smif.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_sysclk_v2.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_syslib.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_syspm_pdcm.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_syspm_ppu.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_syspm_v4.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_trigmux.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/cy_wdt.c \ + mtb-dsl-pse8xxgp/pdl/drivers/source/ppu_v1.c \ + \ + mtb-dsl-pse8xxgp/support/source/mtb_stdlib_stubs.c \ + \ + mtb-srf/source/mtb_srf.c \ + \ + se-rt-services-utils/ifx_se_crc32.c \ + se-rt-services-utils/ifx_se_fih.c \ + se-rt-services-utils/ifx_se_platform.c \ + se-rt-services-utils/ifx_se_syscall.c \ + se-rt-services-utils/ifx_se_syscall_builtin.c \ + \ + TARGET_$(BOARD)/cybsp.c \ + TARGET_$(BOARD)/system_edge.c \ + TARGET_$(BOARD)/COMPONENT_CM33/COMPONENT_SECURE_DEVICE/s_start_pse84.c \ + TARGET_$(BOARD)/COMPONENT_CM33/COMPONENT_SECURE_DEVICE/s_system_init.c \ + TARGET_$(BOARD)/COMPONENT_CM33/COMPONENT_SECURE_DEVICE/s_system_pse84.c \ + ) + +PSE_SRC_ASM = $(PSE_LIB_TOP_DIR)/mtb-dsl-pse8xxgp/pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S \ + +OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(PSE_BSP_CFG_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(PSE_LIB_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(PSE_SRC_ASM:.S=.o)) + +# Main targets + +all: $(BUILD)/secboot.hex cmse_post_build_update + +# Generate elf file +$(BUILD)/secboot.elf: $(OBJ) + @echo "Linking... $@" + @$(CC) $(OBJ) $(LDFLAGS) -o $@ + @$(SIZE) $@ + +# Compile C files +vpath %.c . $(TOP) | $(BUILD) +$(BUILD)/%.o: %.c | $(BUILD) + @mkdir -p $(dir $@) + @echo "Compiling $<" + @$(CC) $(CFLAGS) -c -MD -MF $(@:.o=.d) -o $@ $< + +# Compile S files +vpath %.S . $(TOP) | $(BUILD) +$(BUILD)/%.o: %.S | $(BUILD) + @mkdir -p $(dir $@) + @echo "Assembling $<" + @$(CC) $(CFLAGS) -c -MD -MF $(@:.o=.d) -o $@ $< + +# Generate hex file +$(BUILD)/secboot.hex: $(BUILD)/secboot.elf + @$(OBJCOPY) -O ihex $< $@ + +# Create build directory +$(BUILD): + @mkdir -p $(BUILD) + +# Replace the original veneer with the generated temp veneer after build. +cmse_post_build_update: + @$(Q)[ ! -f $(NSC_VENEER_TEMP) ] || cmp -s $(NSC_VENEER_TEMP) $(NSC_VENEER) || cp -f $(NSC_VENEER_TEMP) $(NSC_VENEER);\ + rm -f $(NSC_VENEER_TEMP) + +# Clean +clean: + @rm -rf $(BUILD) + +.PHONY: all clean cmse_post_build_update diff --git a/ports/psoc-edge/secboot/main.c b/ports/psoc-edge/secboot/main.c new file mode 100644 index 00000000000..1b735055530 --- /dev/null +++ b/ports/psoc-edge/secboot/main.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* File Name: main.c +* +* Description: This is the source code for CM33 Secure Project. +* +* Related Document: See README.md +* +* +******************************************************************************* +* Copyright 2023-2025, Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. All rights reserved. +* +* This software, including source code, documentation and related +* materials ("Software") is owned by Cypress Semiconductor Corporation +* or one of its affiliates ("Cypress") and is protected by and subject to +* worldwide patent protection (United States and foreign), +* United States copyright laws and international treaty provisions. +* Therefore, you may use this Software only as provided in the license +* agreement accompanying the software package from which you +* obtained this Software ("EULA"). +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, +* non-transferable license to copy, modify, and compile the Software +* source code solely for use in connection with Cypress's +* integrated circuit products. Any reproduction, modification, translation, +* compilation, or representation of this Software except as specified +* above is prohibited without the express written permission of Cypress. +* +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress +* reserves the right to make changes to the Software without notice. Cypress +* does not assume any liability arising out of the application or use of the +* Software or any product or circuit described in the Software. Cypress does +* not authorize its products for use in any products where a malfunction or +* failure of the Cypress product may reasonably be expected to result in +* significant property damage, injury or death ("High Risk Product"). By +* including Cypress's product in a High Risk Product, the manufacturer +* of such system or application assumes all risk of such use and in doing +* so agrees to indemnify Cypress against all liability. +*******************************************************************************/ + +/******************************************************************************* +* Header Files +*******************************************************************************/ + +#include "cy_pdl.h" +#include "cybsp.h" + +/***************************************************************************** +* Macros +******************************************************************************/ +#define CM33_NS_APP_BOOT_ADDR (CYMEM_CM33_0_m33_nvm_START + CYBSP_MCUBOOT_HEADER_SIZE) +/***************************************************************************** +* Function Name: main +****************************************************************************** +* This is the main function for Cortex M33 CPU secure application +* NOTE: CM33 secure project assumes that certain memory and peripheral regions +* will be accessed from non-secure environment by the CM33 NS /CM55 code, +* For such regions MPC and PPC configurations are applied by cybsp_init to make +* it non-secure. Any access to these regions from the secure side is recommended +* to be done before the MPC/PPC configuration is applied.Once a memory or +* peripheral region is marked as non secure it cannot be accessed from the secure +* side using secure aliased address but may be accessed using non secure aliased +* address +*****************************************************************************/ +int main(void) { + uint32_t ns_stack; + cy_cmse_funcptr NonSecure_ResetHandler; + cy_rslt_t result; + + /* Set up internal routing, pins, and clock-to-peripheral connections */ + result = cybsp_init(); + + /* Board initialization failed. Stop program execution */ + if (CY_RSLT_SUCCESS != result) { + /* Disable all interrupts. */ + __disable_irq(); + + CY_ASSERT(0); + + /* Infinite loop */ + while (true) { + ; + } + + } + + /* Enable global interrupts */ + __enable_irq(); + + ns_stack = (uint32_t)(*((uint32_t *)CM33_NS_APP_BOOT_ADDR)); + __TZ_set_MSP_NS(ns_stack); + + NonSecure_ResetHandler = (cy_cmse_funcptr)(*((uint32_t *)(CM33_NS_APP_BOOT_ADDR + 4))); + + /* Start non-secure application */ + NonSecure_ResetHandler(); + + for (;;) + { + } +} + +/* [] END OF FILE */ diff --git a/ports/psoc-edge/secboot/nsc_veneer.o b/ports/psoc-edge/secboot/nsc_veneer.o new file mode 100644 index 0000000000000000000000000000000000000000..44c10e981495b69df9df4afdb6e1d8ec75fba869 GIT binary patch literal 296 zcmb<-^>JflWMqH=Mg|QA1doBC10=!1z-j_kpaEnu!<52lka|T90SOKuEyVEgKSORw zQhaeyT6|GzVQFe{Nqli>Qf_7m1A|_1Wo}7g5|Az_g3uXI7ThdC43J$+NQyx2Qhirq_num); + NVIC_DisableIRQ(int_cfg->irq_num); + + cy_stc_sysint_t intr_cfg = { + int_cfg->irq_num, + int_cfg->priority + }; + + cy_en_sysint_status_t rslt = Cy_SysInt_Init(&intr_cfg, int_cfg->handler); + sys_int_assert_raise_val("system interrupt init failed (PSE PDL error code: %lx)", rslt); + + NVIC_EnableIRQ(int_cfg->irq_num); +} + +void sys_int_deinit(sys_int_cfg_t *int_cfg) { + NVIC_ClearPendingIRQ(int_cfg->irq_num); + NVIC_DisableIRQ(int_cfg->irq_num); + int_cfg->priority = SYS_INT_IRQ_LOWEST_PRIORITY; +} + +void sys_int_enable(sys_int_cfg_t *int_cfg) { + NVIC_EnableIRQ(int_cfg->irq_num); +} + +void sys_int_disable(sys_int_cfg_t *int_cfg) { + NVIC_DisableIRQ(int_cfg->irq_num); +} + +void sys_int_clear(sys_int_cfg_t *int_cfg) { + NVIC_ClearPendingIRQ(int_cfg->irq_num); +} diff --git a/ports/psoc-edge/sys_int.h b/ports/psoc-edge/sys_int.h new file mode 100644 index 00000000000..1dad6e6acff --- /dev/null +++ b/ports/psoc-edge/sys_int.h @@ -0,0 +1,56 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_PSOC_EDGE_SYS_INT_H +#define MICROPY_INCLUDED_PSOC_EDGE_SYS_INT_H + +#include "cy_sysint.h" +#include "cy_device_headers.h" + +/** + * Define the lowest interrupt priority. + * The cy_device_headers_ns.h file might + * define the interrupt priority levels. + */ +#if defined(__NVIC_PRIO_BITS) + #define SYS_INT_IRQ_LOWEST_PRIORITY ((1 << __NVIC_PRIO_BITS) - 1) +#else + #define SYS_INT_IRQ_LOWEST_PRIORITY 7 +#endif + +typedef struct _sys_int_cfg_t { + IRQn_Type irq_num; + uint32_t priority; + cy_israddress handler; +} sys_int_cfg_t; + +void sys_int_init(sys_int_cfg_t *int_cfg); +void sys_int_deinit(sys_int_cfg_t *int_cfg); +void sys_int_enable(sys_int_cfg_t *int_cfg); +void sys_int_disable(sys_int_cfg_t *int_cfg); +void sys_int_clear(sys_int_cfg_t *int_cfg); + +#endif // MICROPY_INCLUDED_PSOC_EDGE_SYS_INT_H diff --git a/ports/psoc-edge/systick.c b/ports/psoc-edge/systick.c new file mode 100644 index 00000000000..4c22d22783c --- /dev/null +++ b/ports/psoc-edge/systick.c @@ -0,0 +1,159 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Infineon Technologies AG + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "cybsp.h" +#include "cy_systick.h" + +#include "mphalport.h" + +#include "py/runtime.h" + +volatile uint64_t psoc_edge_systick_ms_count; +uint32_t psoc_edge_systick_cpu_hz; + +// Use the SysTick pending-interrupt state as rollover evidence. This matches our +// callback-based ms counter model ("ISR increment still outstanding") and avoids +// Cy_SysTick_GetCountFlag()'s read-to-clear side effect. +#define MP_HAL_SYSTICK_WRAP_PENDING() (((SCB->ICSR) & SCB_ICSR_PENDSTSET_Msk) != 0u) + +typedef struct { + uint64_t ms_count; + uint32_t systick_reload; + uint32_t systick_val; + uint32_t cpu_hz; +} mp_hal_systick_snapshot_t; + +static void psoc_edge_systick_callback(void) { + psoc_edge_systick_ms_count += 1; +} + +void mp_hal_ticks_init(void) { + psoc_edge_systick_cpu_hz = SystemCoreClock; + if (psoc_edge_systick_cpu_hz < 1000) { + mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("invalid SystemCoreClock (< 1000 Hz).")); + } + + // Configure SysTick for 1ms period and count overflows in software. + uint32_t systick_interval = psoc_edge_systick_cpu_hz / 1000; + + psoc_edge_systick_ms_count = 0; + Cy_SysTick_Init(CY_SYSTICK_CLOCK_SOURCE_CLK_CPU, systick_interval - 1); + Cy_SysTick_SetCallback(0, psoc_edge_systick_callback); +} + +static mp_hal_systick_snapshot_t mp_hal_systick_snapshot(void) { + mp_hal_systick_snapshot_t snap; + + mp_uint_t irq_state = MICROPY_BEGIN_ATOMIC_SECTION(); + snap.ms_count = psoc_edge_systick_ms_count; + snap.systick_reload = Cy_SysTick_GetReload(); + snap.systick_val = Cy_SysTick_GetValue(); + // SysTick may have wrapped but its ISR not run yet; account for that pending rollover + // so software time does not momentarily go backwards across the wrap boundary. + if (MP_HAL_SYSTICK_WRAP_PENDING()) { + snap.ms_count += 1; + } + snap.cpu_hz = psoc_edge_systick_cpu_hz; + MICROPY_END_ATOMIC_SECTION(irq_state); + + if (snap.cpu_hz == 0) { + mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("invalid systick CPU clock.")); + } + + return snap; +} + +uint64_t mp_hal_systick_ticks_us64(void) { + mp_hal_systick_snapshot_t snap = mp_hal_systick_snapshot(); + + uint32_t elapsed_cycles = snap.systick_reload - snap.systick_val; + return snap.ms_count * 1000ULL + ((uint64_t)elapsed_cycles * 1000000ULL) / snap.cpu_hz; +} + +mp_uint_t mp_hal_ticks_ms(void) { + return mp_hal_systick_ticks_us64() / 1000ULL; +} + +mp_uint_t mp_hal_ticks_us(void) { + return mp_hal_systick_ticks_us64(); +} + +mp_uint_t mp_hal_ticks_cpu(void) { + mp_hal_systick_snapshot_t snap = mp_hal_systick_snapshot(); + return snap.ms_count * snap.cpu_hz + (snap.systick_reload - snap.systick_val); +} + +void mp_hal_delay_ms(mp_uint_t ms) { + mp_uint_t start = mp_hal_ticks_ms(); + mp_event_handle_nowait(); + while (mp_hal_ticks_ms() - start < ms) { + mp_event_handle_nowait(); + } +} + +void mp_hal_delay_us(mp_uint_t us) { + mp_uint_t start = mp_hal_ticks_us(); + mp_event_handle_nowait(); + while (mp_hal_ticks_us() - start < us) { + mp_event_handle_nowait(); + } +} + +extern uint64_t mp_hal_time_get_epoch_seconds(void); +extern bool machine_rtc_read_and_clear_time_updated(void); + +uint64_t mp_hal_time_ns(void) { + static uint64_t time_us_offset_from_epoch = 0; + // Resync whenever RTC time was updated (set/deinit/init path marks this). + bool need_resync = machine_rtc_read_and_clear_time_updated(); + + while (need_resync) { + // Wait until RTC second changes so we can anchor the monotonic timer + // to a known wall-clock second boundary. + uint64_t prev_seconds = mp_hal_time_get_epoch_seconds(); + uint64_t edge_ticks_us; + uint64_t edge_seconds; + + do { + edge_seconds = mp_hal_time_get_epoch_seconds(); + } while (edge_seconds == prev_seconds); + + // Capture the monotonic timestamp immediately after observing the RTC + // second rollover so the fixed offset stays aligned to wall-clock time. + // `edge_seconds` is the first observed second after the rollover. + edge_ticks_us = mp_hal_systick_ticks_us64(); + time_us_offset_from_epoch = edge_seconds * 1000000ULL - edge_ticks_us; + + // If RTC was updated during calibration, repeat once more to align with + // the latest RTC second boundary. + need_resync = machine_rtc_read_and_clear_time_updated(); + } + + return (time_us_offset_from_epoch + mp_hal_systick_ticks_us64()) * 1000ULL; +} diff --git a/ports/psoc-edge/tools/mp-ifx-flash.py b/ports/psoc-edge/tools/mp-ifx-flash.py new file mode 100644 index 00000000000..2ffa2cdac7b --- /dev/null +++ b/ports/psoc-edge/tools/mp-ifx-flash.py @@ -0,0 +1,378 @@ +import argparse, os, sys, shlex, shutil, subprocess, requests, tempfile, zipfile, tarfile + +boards = [ + {"name": "KIT_PSE84_AI", "ocd_cfg_file": "pse84xgxs2.cfg"}, +] + +opsys = "" +version = "0.1.0" + + +# Decorator to flush every print +def flush_print(func): + printer = func + + def wrapped(*args): + printer(*args, flush=True) + + return wrapped + + +print_f = flush_print(print) + + +def colour_str_success(msg): + green_str_start = "\x1b[1;32;40m" + str_color_end = "\x1b[0m" + return green_str_start + msg + str_color_end + + +def colour_str_error(msg): + red_str_start = "\x1b[1;31;40m" + str_color_end = "\x1b[0m" + return red_str_start + msg + str_color_end + + +def colour_str_highlight(msg): + purple_str_start = "\x1b[1;35;40m" + str_color_end = "\x1b[0m" + return purple_str_start + msg + str_color_end + + +def colour_str_warn(msg): + yellow_str_start = "\x1b[1;33;40m" + str_color_end = "\x1b[0m" + return yellow_str_start + msg + str_color_end + + +def set_environment(): + global opsys + if sys.platform == "linux" or sys.platform == "linux2": + opsys = "linux" + elif sys.platform == "win32" or sys.platform == "cygwin": + opsys = "win" + os.system("color") # Enable colouring in cmd and powershell + elif sys.platform == "darwin": + opsys = "mac" + + +####################################################################### +# OpenOCD download, install, flash and cleanup functions + + +def openocd_download_install(): + if opsys == "linux": + file_os_suffix = "linux" + file_extension = ".tar.gz" + openocd_exe = "openocd" + elif opsys == "win": + file_os_suffix = "windows" + file_extension = ".zip" + openocd_exe = "openocd.exe" + elif opsys == "mac": + file_os_suffix = "macos" + file_extension = ".zip" + openocd_exe = "openocd" + + openocd_compressed = "openocd" + file_extension + + def is_openocd_already_downloaded(): + if os.path.exists(os.path.join("openocd", "bin", openocd_exe)): + # Add openocd to path + os.environ["PATH"] = os.path.join("openocd", "bin") + os.pathsep + os.environ["PATH"] + valid_openocd_version = is_openocd_already_in_sys_path() + if not valid_openocd_version: + clean_openocd() + + return valid_openocd_version + + return False + + def is_openocd_already_in_sys_path(): + try: + ocd_proc = subprocess.Popen( + [openocd_exe, "--version"], stderr=subprocess.PIPE, stdout=subprocess.PIPE + ) + out, err = ocd_proc.communicate(timeout=10) + + if err: + return False + out_str = out.decode() + supported_versions = [ + "0.12.0+dev-5.8.0.3960", + "0.12.0+dev-5.11.0.4042", + "0.12.0+dev-5.12.0.4170", + ] + for ver in supported_versions: + if ver in out_str: + print_f(f"openocd found in system path : {shutil.which('openocd')}") + return True + except: + return False + + return False + + def get_openocd_file_url_name(): + filename_base = "openocd-5.11.0.4042-" + url_base = "https://github.com/Infineon/openocd/releases/download/release-v5.11.0/" + + file_name = filename_base + file_os_suffix + file_extension + file_url = url_base + file_name + + return file_url, file_name + + def clean_openocd(file_name): + if os.path.exists(file_name): + os.remove(file_name) + + def download_openocd(file_url, file_name): + res = requests.get(file_url) + open(file_name, "wb").write(res.content) + os.replace(file_name, openocd_compressed) + + def extract_openocd(): + if opsys == "linux": + compress_file = tarfile.open(openocd_compressed) + compress_file.extractall(".") + compress_file.close() + elif opsys == "win" or opsys == "mac": + compress_file = zipfile.ZipFile(openocd_compressed) + compress_file.extractall(".") + compress_file.close() + + def openocd_setup(): + # Add openocd to path + os.environ["PATH"] = os.path.join("openocd", "bin") + os.pathsep + os.environ["PATH"] + + if opsys == "linux": + # Install udev rules + sh_args = ["sh", "openocd/udev_rules/install_rules.sh"] + try: + sh_proc = subprocess.Popen(sh_args) + sh_proc.wait() + except: + sys.exit(colour_str_error("bash error")) + + if opsys == "mac": + os.chmod(os.path.join("openocd", "bin", "openocd"), 0o755) + + if not is_openocd_already_in_sys_path(): + if not is_openocd_already_downloaded(): + print_f("Downloading openocd...") + file_url, file_name = get_openocd_file_url_name() + clean_openocd(file_name) + download_openocd(file_url, file_name) + print_f("Extracting openocd...") + extract_openocd() + else: + print_f("openocd already available. Download skipped") + + openocd_setup() + + +def openocd_program(board, hex_file, cfg_dir, flm_file, serial_adapter_sn=None): + # Find tool path cross-platform + openocd = shutil.which("openocd") + if not openocd: + sys.exit(colour_str_error("error: openocd not found in PATH")) + + # Convert to forward slashes for cross-platform compatibility + openocd = openocd.replace("\\", "/") + + # Get the root openocd path. + # It is two level up from the openocd executable + openocd_root_dir = os.path.dirname(os.path.dirname(openocd)) + + for brd in boards: + if board == brd["name"]: + ocd_cfg_file = brd["ocd_cfg_file"] + + serial_adapter_opt = "" + if serial_adapter_sn is not None: + serial_adapter_opt = "adapter serial " + str(serial_adapter_sn) + + openocd_cmd = ( + openocd + + " -s " + + str(openocd_root_dir) + + "/scripts" + + " -s " + + str(cfg_dir) + + ' -c "set QSPI_FLASHLOADER ' + + str(flm_file) + + '"' + + ' -c "source [find interface/kitprog3.cfg]; ' + + str(serial_adapter_opt) + + ";" + + " transport select swd;" + + " source [find target/infineon/" + + str(ocd_cfg_file) + + "];" + + " init; reset init; adapter speed 12000;" + + " flash write_image erase " + + str(hex_file) + + ";" + + " verify_image " + + str(hex_file) + + ";" + + ' reset run; shutdown;"' + ) + + openocd_args = shlex.split(openocd_cmd) + + ocd_proc = subprocess.Popen(openocd_args, stderr=subprocess.PIPE, stdout=subprocess.PIPE) + try: + out, err = ocd_proc.communicate(timeout=30) + except: + ocd_proc.kill() + sys.exit(colour_str_error("openocd error.")) + if err: + sys.exit(colour_str_error(err.decode() + "Are you sure the board is connected?")) + + +def openocd_remove(): + if opsys == "linux": + file_extension = ".tar.gz" + elif opsys == "win" or opsys == "mac": + file_extension = ".zip" + + openocd_compressed = "openocd" + file_extension + if os.path.exists(openocd_compressed): + os.remove(openocd_compressed) + + if os.path.exists("openocd"): + shutil.rmtree("openocd") + + +#################################################################################################### + + +def validate_board_name(board_name): + board_supported = False + for brd in boards: + if board_name == brd["name"]: + board_supported = True + break + + if not board_supported: + sys.exit(colour_str_error("error: board is not supported")) + + +def flash_from_files(board, hex_file, cfg_file, flm_file, serial_adapter_sn): + cfg_dir = os.path.dirname(cfg_file) + print(f"Flashing board '{board}' with hex file '{os.path.basename(hex_file)}'...") + openocd_program(board, hex_file, cfg_dir, flm_file, serial_adapter_sn) + print(colour_str_success("Device setup completed :)")) + + +def flash_from_package(board, zip_package, serial_adapter_sn): + def get_files_from_package(zip_package): + hex_file = None + cfg_file = None + flm_file = None + + if not os.path.exists(zip_package): + sys.exit(colour_str_error("error: zip package not found")) + + tmpdirname = tempfile.mkdtemp() + with zipfile.ZipFile(zip_package, "r") as zip_ref: + zip_ref.extractall(tmpdirname) + for root, dirs, files in os.walk(tmpdirname): + for file in files: + if file.endswith(".hex"): + hex_file = os.path.join(root, file) + elif file.endswith(".cfg"): + cfg_file = os.path.join(root, file) + elif file.endswith(".FLM"): + flm_file = os.path.join(root, file) + + # If any of the files is missing, raise an error + if not hex_file or not cfg_file or not flm_file: + shutil.rmtree(tmpdirname) + sys.exit(colour_str_error("error: zip package must contain .hex, .cfg and .FLM files")) + + return hex_file, cfg_file, flm_file, tmpdirname + + hex_file, cfg_file, flm_file, tmpdirname = get_files_from_package(zip_package) + try: + flash_from_files(board, hex_file, cfg_file, flm_file, serial_adapter_sn) + finally: + shutil.rmtree(tmpdirname) + + +def flash_command_args(args): + # TODO: if no command (None) implement interactive mode to gather the values. + validate_board_name(args.board) + + if args.command == "from-package": + flash_from_package(args.board, args.zip_package, args.serial_num) + + +def parser(): + class ver_action(argparse.Action): + def __init__(self, option_strings, dest, **kwargs): + return super().__init__( + option_strings, dest, nargs=0, default=argparse.SUPPRESS, **kwargs + ) + + def __call__(self, parser, namespace, values, option_string, **kwargs): + print_f("mp-ifx-flash version: " + version) + parser.exit() + + p = argparse.ArgumentParser( + formatter_class=argparse.RawTextHelpFormatter, + description="MicroPython Infineon Flash Utility", + ) + p.add_argument("-v", "--version", action=ver_action, help="mp-ifx-flash version") + + subparsers = p.add_subparsers(dest="command") + + # Shared parent parser for common arguments (board, serial-num) + common = argparse.ArgumentParser(add_help=False) + common.add_argument("-b", "--board", required=True, type=str, help="Infineon board name") + common.add_argument( + "-n", + "--serial-num", + default=None, + type=str, + help="Serial number of the board serial adapter", + ) + + # Subcommand: from-package + sp_zip = subparsers.add_parser( + "from-package", + parents=[common], + formatter_class=argparse.RawTextHelpFormatter, + help="Flash from a compressed package", + description="Flash from a compressed package containing .hex, .cfg and .FLM files.", + ) + sp_zip.add_argument( + "-z", + "--zip-package", + required=True, + type=str, + help="Firmware zip package containing .hex, .cfg and .FLM files", + ) + + # TODO: Subcommand: from-files (pass directly the .hex, .cfg and .FLM files) + # TODO: Subcommand: from-remote (just pass the board and optionally the version, and the tool will fetch the latest firmware from Infineon fork and flash it) + + args = p.parse_args() + + # Print help if no command is provided + # TODO: Future interactive mode. + if args.command is None: + p.print_help(sys.stderr) + sys.exit(1) + + return args + + +if __name__ == "__main__": + try: + set_environment() + args = parser() + flash_command_args(args) + except KeyboardInterrupt: + print_f(colour_str_error("error: keyboard interrupt")) + openocd_remove() From 58b2e3cfe32f22ed00e3eb06ba94f27b0b592a52 Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:13:04 +0200 Subject: [PATCH 497/635] tools/ci: Add ci setup and build for psoc-edge. Signed-off-by: jaenrig-ifx --- tools/ci.sh | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tools/ci.sh b/tools/ci.sh index 63b574424e6..f7d1dc88883 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -348,6 +348,21 @@ function ci_nrf_build { make ${MAKEOPTS} -C ports/nrf BOARD=PCA10090 } +######################################################################################## +# ports/psoc-edge + +function ci_psoc_edge_setup { + ci_gcc_arm_setup + sudo apt remove python3-packaging python3-jsonschema python3-cryptography + sudo pip3 install edgeprotecttools +} + +function ci_psoc_edge_build { + make ${MAKEOPTS} -C mpy-cross + make ${MAKEOPTS} -C ports/psoc-edge submodules + make ${MAKEOPTS} -C ports/psoc-edge +} + ######################################################################################## # ports/qemu From 5b7c207e3577a83c575cb8f80c6eb6dfd39c5099 Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:14:31 +0200 Subject: [PATCH 498/635] tools/autobuild: Add psoc-edge port to autobuild. Signed-off-by: jaenrig-ifx --- tools/autobuild/autobuild.sh | 2 ++ tools/autobuild/build-boards.sh | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/tools/autobuild/autobuild.sh b/tools/autobuild/autobuild.sh index ed748fc01e1..c240d112497 100755 --- a/tools/autobuild/autobuild.sh +++ b/tools/autobuild/autobuild.sh @@ -92,6 +92,8 @@ cd ../mimxrt build_mimxrt_boards ${FW_TAG} ${LOCAL_FIRMWARE} cd ../nrf build_nrf_boards ${FW_TAG} ${LOCAL_FIRMWARE} +cd ../psoc-edge +build_psoc_edge_boards ${FW_TAG} ${LOCAL_FIRMWARE} cd ../renesas-ra build_renesas_ra_boards ${FW_TAG} ${LOCAL_FIRMWARE} cd ../rp2 diff --git a/tools/autobuild/build-boards.sh b/tools/autobuild/build-boards.sh index db309bf0001..a0699256d62 100755 --- a/tools/autobuild/build-boards.sh +++ b/tools/autobuild/build-boards.sh @@ -119,6 +119,10 @@ function build_nrf_boards { build_boards nrfx_glue.h $1 $2 bin hex uf2 } +function build_psoc_edge_boards { + build_boards modpsocedge.c $1 $2 zip +} + function build_renesas_ra_boards { build_boards ra_it.c $1 $2 bin hex } From 767097ab5233e2bb931fbd4bfab005c96555cb88 Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:15:05 +0200 Subject: [PATCH 499/635] tests/extmod/machine_uart_irq_txidle: Add variable timing window. Signed-off-by: jaenrig-ifx --- tests/extmod/machine_uart_irq_txidle.py | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tests/extmod/machine_uart_irq_txidle.py b/tests/extmod/machine_uart_irq_txidle.py index a56f6e3cf85..6c20503d45f 100644 --- a/tests/extmod/machine_uart_irq_txidle.py +++ b/tests/extmod/machine_uart_irq_txidle.py @@ -19,6 +19,11 @@ def irq(u): text = "Hello World" * 20 +char_margin = 10 # number of characters to wait before and after the expected IRQ firing + +if "psoc-edge" in sys.platform: + char_margin = 100 + # Test that the IRQ is called after the write has completed. for bits_per_s in (2400, 9600, 115200): uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs) @@ -27,12 +32,12 @@ def irq(u): # The IRQ_TXIDLE shall trigger after the message has been sent. Thus # the test marks a time window close to the expected of the sending # and the time at which the IRQ should have been fired. - # It is just a rough estimation of 10 characters before and - # 20 characters after the data's end. + # It is just a rough estimation of 'char_margin' characters before and + # '2 x char_margin' characters after the data's end. bits_per_char = 10 # 1(startbit) + 8(bits) + 1(stopbit) + 0(parity) - start_time_us = (len(text) - 10) * bits_per_char * 1_000_000 // bits_per_s - window_ms = 20 * bits_per_char * 1_000 // bits_per_s + 1 + start_time_us = (len(text) - char_margin) * bits_per_char * 1_000_000 // bits_per_s + window_ms = (2 * char_margin) * bits_per_char * 1_000 // bits_per_s + 1 print("write", bits_per_s) uart.write(text) From 6d177de18f2758155ebd8842ed5c00505e53756c Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:15:35 +0200 Subject: [PATCH 500/635] tests/extmod/machine_uart_tx: Add timing margin for psoc-edge. Signed-off-by: jaenrig-ifx --- tests/extmod/machine_uart_tx.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/extmod/machine_uart_tx.py b/tests/extmod/machine_uart_tx.py index 4e0ff37a8b1..90afd069fec 100644 --- a/tests/extmod/machine_uart_tx.py +++ b/tests/extmod/machine_uart_tx.py @@ -26,6 +26,8 @@ bit_margin = 1 elif "nrf" in sys.platform: timing_margin_us = 130 +elif "psoc-edge" in sys.platform: + timing_margin_us = 190 elif "pyboard" in sys.platform: initial_delay_ms = 50 # UART sends idle frame after init, so wait for that bit_margin = 1 # first start-bit must wait to sync with the UART clock From 5cd1a7ebe359d44b40353f7984a2a3dce9067843 Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:16:01 +0200 Subject: [PATCH 501/635] tests/extmod_hardware/machine_uart_irq_break: Add psoc-edge support. Signed-off-by: jaenrig-ifx --- tests/extmod_hardware/machine_uart_irq_break.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/extmod_hardware/machine_uart_irq_break.py b/tests/extmod_hardware/machine_uart_irq_break.py index 1832d9883ba..8906df36155 100644 --- a/tests/extmod_hardware/machine_uart_irq_break.py +++ b/tests/extmod_hardware/machine_uart_irq_break.py @@ -31,7 +31,7 @@ def irq(u): time.sleep_ms(10) uart.sendbreak() time.sleep_ms(10) - if "esp32" in sys.platform: - # On esp32 a read is needed to read in the break byte. + if sys.platform in ("esp32", "psoc-edge"): + # On these platforms a read is needed to read in the break byte. uart.read() print("done") From 71a0ae8c6d9964a4515e194e082e7016e921870e Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:16:28 +0200 Subject: [PATCH 502/635] tests/target_wiring: Add KIT_PSE84_AI with UART loopback. Signed-off-by: jaenrig-ifx --- tests/target_wiring/KIT_PSE84_AI.py | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 tests/target_wiring/KIT_PSE84_AI.py diff --git a/tests/target_wiring/KIT_PSE84_AI.py b/tests/target_wiring/KIT_PSE84_AI.py new file mode 100644 index 00000000000..8ef3f08385d --- /dev/null +++ b/tests/target_wiring/KIT_PSE84_AI.py @@ -0,0 +1,5 @@ +# Target wiring for KIT_PSE84_AI. + +# UART(5) is on P17_1/P17_0. +uart_loopback_args = () +uart_loopback_kwargs = {"tx": "P17_1", "rx": "P17_0"} From 49fe1749a02ed0e339148608c439f1c53c8cf69d Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Mon, 13 Jul 2026 21:16:52 +0200 Subject: [PATCH 503/635] github/workflows/ports_psoc-edge.yml: Add psoc edge build ci check. Signed-off-by: jaenrig-ifx --- .github/workflows/ports_psoc-edge.yml | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 .github/workflows/ports_psoc-edge.yml diff --git a/.github/workflows/ports_psoc-edge.yml b/.github/workflows/ports_psoc-edge.yml new file mode 100644 index 00000000000..f0f37e94939 --- /dev/null +++ b/.github/workflows/ports_psoc-edge.yml @@ -0,0 +1,28 @@ +name: psoc-edge port + +on: + push: + pull_request: + paths: + - '.github/workflows/*.yml' + - 'tools/**' + - 'py/**' + - 'extmod/**' + - 'shared/**' + - 'lib/**' + - 'drivers/**' + - 'ports/psoc-edge/**' + +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + +jobs: + build_psoc_edge: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v7 + - name: Install packages + run: tools/ci.sh psoc_edge_setup + - name: Build + run: tools/ci.sh psoc_edge_build From 1a4df82620265ac7273d91952a7ffb91464b24ac Mon Sep 17 00:00:00 2001 From: Owen Date: Tue, 21 Jul 2026 18:24:28 +0200 Subject: [PATCH 504/635] esp32/machine_sdcard: Expose SDMMC host bus slot width in board config. This commit changes the default ESP32-P4 bus width from 1 to 4. MICROPY_HW_SDMMC_DEFAULT_WIDTH can be used for esp32 chips that support SDMMC host buses; it defaults to 1 except for the esp32-p4, where it defaults to 4. Signed-off-by: Owen --- ports/esp32/machine_sdcard.c | 12 ++++++------ ports/esp32/mpconfigport.h | 7 +++++++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/ports/esp32/machine_sdcard.c b/ports/esp32/machine_sdcard.c index 1b1582a0913..3a7174ae3aa 100644 --- a/ports/esp32/machine_sdcard.c +++ b/ports/esp32/machine_sdcard.c @@ -208,14 +208,14 @@ static mp_obj_t machine_sdcard_make_new(const mp_obj_type_t *type, size_t n_args #endif ARG_freq, }; - #if SOC_SDMMC_HOST_SUPPORTED - static const int DEFAULT_SLOT = MICROPY_HW_SDMMC_DEFAULT_SLOT; - #else - static const int DEFAULT_SLOT = SD_SLOT_MAX; - #endif static const mp_arg_t allowed_args[] = { - { MP_QSTR_slot, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_SLOT} }, + #if SOC_SDMMC_HOST_SUPPORTED + { MP_QSTR_slot, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = MICROPY_HW_SDMMC_DEFAULT_SLOT} }, + { MP_QSTR_width, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = MICROPY_HW_SDMMC_DEFAULT_WIDTH} }, + #else + { MP_QSTR_slot, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = SD_SLOT_MAX} }, { MP_QSTR_width, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} }, + #endif { MP_QSTR_cd, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, { MP_QSTR_wp, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} }, // These are only needed if using SPI mode diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index 4074a9f51c9..45d789f469b 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -231,6 +231,13 @@ #define MICROPY_HW_SDMMC_DEFAULT_SLOT (1) #endif #endif +#ifndef MICROPY_HW_SDMMC_DEFAULT_WIDTH +#if CONFIG_IDF_TARGET_ESP32P4 +#define MICROPY_HW_SDMMC_DEFAULT_WIDTH (4) +#else +#define MICROPY_HW_SDMMC_DEFAULT_WIDTH (1) +#endif +#endif #define MICROPY_HW_SOFTSPI_MIN_DELAY (0) #define MICROPY_HW_SOFTSPI_MAX_BAUDRATE (esp_rom_get_cpu_ticks_per_us() * 1000000 / 200) // roughly #define MICROPY_PY_SSL (MICROPY_PY_NETWORK) From 8026c32e1d4d6be1ee536d5001277587787b079d Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 19 Jun 2026 23:58:17 +1000 Subject: [PATCH 505/635] tools/mpy_ld.py: Automatically provide memset/memmove/memcpy if needed. Native modules sometimes need memset/memmove/memcpy. This is currently handled by explicitly providing wrapper functions for these that call into the provided native glue API, namely `mp_fun_table.memset_` etc. This commit improves the situation by automatically providing wrapper/ trampoline functions when they are needed by the native code, using a direct pointer to `mp_fun_table.memset_` etc. Most architectures use a small trampoline function linked into the native .mpy file which calls through to mem*. The absolute address of mem* will be written during the .mpy relocation process. For xtensa, calls to mem* are made via the GOT so they are already indirect. Therefore the value put in the GOT can be the actual pointer to th mem* function (rather than a pointer to a trampoline). Signed-off-by: Damien George --- tools/mpy_ld.py | 117 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 116 insertions(+), 1 deletion(-) diff --git a/tools/mpy_ld.py b/tools/mpy_ld.py index 4fd85484c7d..65c8e8c4d7d 100755 --- a/tools/mpy_ld.py +++ b/tools/mpy_ld.py @@ -29,7 +29,7 @@ """ import sys, os, struct, re -from elftools.elf import elffile +from elftools.elf import elffile, relocation import ar_util sys.path.append(os.path.dirname(__file__) + "/../py") @@ -217,6 +217,65 @@ def asm_jump_riscv(entry): raise LinkError("jumps larger than 2GiB are not supported") +def asm_jump_abs_word_x86(): + # Emits the following (must be 4-byte-aligned): + # nop * 3 + # mov PTR, eax + # jmp *eax + nop = 0x90 + mov = 0xB8 + jmp = 0xE0FF + return struct.pack("<3BBIH", nop, nop, nop, mov, 0, jmp), 4 + + +def asm_jump_abs_word_x64(): + # Emits the following (must be 8-byte-aligned): + # nop * 6 + # mov PTR, rax + # jmp *rax + nop = 0x90 + mov = 0xB848 + jmp = 0xE0FF + return struct.pack("<6BHQH", nop, nop, nop, nop, nop, nop, mov, 0, jmp), 8 + + +def asm_jump_abs_word_thumb(): + # Emits the following (must be 4-byte-aligned): + # ldr r3, [pc, #0] + # bx r3 + # PTR + r3 = 3 + ldr = 0x4800 | r3 << 8 + bx = 0x4700 | r3 << 3 + return struct.pack("") + env.sections.insert(1, section) + r = relocation.Relocation({}, None) + r.index = get_memx_function_index(n) + r.offset = reloc + section.reloc.append(r) + section.reloc_name = "unknown" + sym.section = section else: undef_errors.append("{}: undefined symbol: {}".format(sym.filename, sym.name)) @@ -1380,6 +1478,8 @@ def link_objects(env, native_qstr_vals_len): do_relocation_text(env, sec.addr, r) elif sec.name.startswith(".data.rel.ro"): do_relocation_data(env, sec.addr, r) + elif sec.name.startswith(".internal"): + env.mpy_relocs.append((".text", sec.addr + r.offset, r.index)) else: assert 0, sec.name @@ -1387,6 +1487,15 @@ def link_objects(env, native_qstr_vals_len): ################################################################################ # .mpy output +MP_FUN_TABLE_MEMSET = 50 +MP_FUN_TABLE_MEMMOVE = 51 + + +def get_memx_function_index(f): + if f == "memset": + return MP_FUN_TABLE_MEMSET + return MP_FUN_TABLE_MEMMOVE + class MPYOutput: def open(self, fname): @@ -1419,6 +1528,12 @@ def write_qstr(self, s): self.write_bytes(b"\x00") def write_reloc(self, base, offset, dest, n): + if dest > 2 and n > 1: + # dest>2 cannot encode n, so do it manually. + for _ in range(n): + self.write_reloc(base, offset, dest, 1) + offset += 1 + return need_offset = not (base == self.prev_base and offset == self.prev_offset + 1) self.prev_offset = offset + n - 1 if dest <= 2: From 8fcd1868716993e5b18f00e0667d364bb55d7d4b Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 19 Jun 2026 23:59:42 +1000 Subject: [PATCH 506/635] examples/natmod: Remove explicit memset/memmove/memcpy wrappers. They are now provided by `mpy_ld.py`. Signed-off-by: Damien George --- examples/natmod/btree/btree_c.c | 13 ------------- examples/natmod/deflate/deflate.c | 9 --------- examples/natmod/framebuf/framebuf.c | 9 --------- examples/natmod/re/re.c | 13 ------------- 4 files changed, 44 deletions(-) diff --git a/examples/natmod/btree/btree_c.c b/examples/natmod/btree/btree_c.c index 7eb3d908513..c26dbcc8478 100644 --- a/examples/natmod/btree/btree_c.c +++ b/examples/natmod/btree/btree_c.c @@ -4,19 +4,6 @@ #include -#if !defined(__linux__) || (defined(__clang__) && (defined(__x86_64__) || defined(__i386__) || __ARM_ARCH == 7)) -void *memcpy(void *dst, const void *src, size_t n) { - return mp_fun_table.memmove_(dst, src, n); -} -void *memset(void *s, int c, size_t n) { - return mp_fun_table.memset_(s, c, n); -} -#endif - -void *memmove(void *dest, const void *src, size_t n) { - return mp_fun_table.memmove_(dest, src, n); -} - void *malloc(size_t n) { void *ptr = m_malloc(n); return ptr; diff --git a/examples/natmod/deflate/deflate.c b/examples/natmod/deflate/deflate.c index dc948c3d1d1..3c470aca9f0 100644 --- a/examples/natmod/deflate/deflate.c +++ b/examples/natmod/deflate/deflate.c @@ -3,15 +3,6 @@ #include "py/dynruntime.h" -#if !defined(__linux__) || (defined(__clang__) && (defined(__x86_64__) || defined(__i386__) || __ARM_ARCH == 7)) -void *memcpy(void *dst, const void *src, size_t n) { - return mp_fun_table.memmove_(dst, src, n); -} -void *memset(void *s, int c, size_t n) { - return mp_fun_table.memset_(s, c, n); -} -#endif - mp_obj_full_type_t deflateio_type; #include "extmod/moddeflate.c" diff --git a/examples/natmod/framebuf/framebuf.c b/examples/natmod/framebuf/framebuf.c index 3a981772745..6e672439fe9 100644 --- a/examples/natmod/framebuf/framebuf.c +++ b/examples/natmod/framebuf/framebuf.c @@ -3,15 +3,6 @@ #include "py/dynruntime.h" -#if !defined(__linux__) || (defined(__clang__) && (defined(__x86_64__) || defined(__i386__) || __ARM_ARCH == 7)) -void *memcpy(void *dst, const void *src, size_t n) { - return mp_fun_table.memmove_(dst, src, n); -} -void *memset(void *s, int c, size_t n) { - return mp_fun_table.memset_(s, c, n); -} -#endif - mp_obj_full_type_t mp_type_framebuf; #include "extmod/modframebuf.c" diff --git a/examples/natmod/re/re.c b/examples/natmod/re/re.c index db2b6754d18..6c5c65842d6 100644 --- a/examples/natmod/re/re.c +++ b/examples/natmod/re/re.c @@ -32,19 +32,6 @@ void mp_cstack_check(void) { } } -#if !defined(__linux__) || (defined(__clang__) && (defined(__x86_64__) || defined(__i386__) || __ARM_ARCH == 7)) -void *memcpy(void *dst, const void *src, size_t n) { - return mp_fun_table.memmove_(dst, src, n); -} -void *memset(void *s, int c, size_t n) { - return mp_fun_table.memset_(s, c, n); -} -#endif - -void *memmove(void *dest, const void *src, size_t n) { - return mp_fun_table.memmove_(dest, src, n); -} - mp_obj_full_type_t match_type; mp_obj_full_type_t re_type; From 228d96df6176e52498c73e4863cd517efa6b706a Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 10 Jul 2026 23:16:11 +1000 Subject: [PATCH 507/635] tools/ci.sh: Test building and running natmods using clang. Using the existing "float clang" unix CI job. Signed-off-by: Damien George --- .github/workflows/ports_unix.yml | 4 ++++ tools/ci.sh | 23 +++++++++++++++++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ports_unix.yml b/.github/workflows/ports_unix.yml index f70e52eb7f8..c9048687db0 100644 --- a/.github/workflows/ports_unix.yml +++ b/.github/workflows/ports_unix.yml @@ -255,6 +255,10 @@ jobs: run: tools/ci.sh unix_float_clang_build - name: Run main test suite run: tools/ci.sh unix_float_clang_run_tests + - name: Build native mpy modules + run: tools/ci.sh native_mpy_modules_clang_build + - name: Test importing .mpy generated by mpy_ld.py + run: tools/ci.sh unix_standard_run_native_mpy_tests - name: Print failures if: failure() run: tests/run-tests.py --print-failures diff --git a/tools/ci.sh b/tools/ci.sh index f7d1dc88883..08af9f3f796 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -702,6 +702,13 @@ function ci_unix_run_tests_full_helper { ci_unix_run_tests_full_extra $micropython } +function ci_unix_run_native_mpy_tests_helper { + variant=$1 + shift + MICROPYPATH=examples/natmod/features2 ./ports/unix/build-$variant/micropython -m features2 + (cd tests && MICROPY_MICROPYTHON=../ports/unix/build-$variant/micropython ./run-natmodtests.py "$@" extmod/*.py) +} + function ci_native_mpy_modules_build { if [ "$1" = "" ]; then arch=x64 @@ -727,6 +734,14 @@ function ci_native_mpy_modules_32bit_build { ci_native_mpy_modules_build x86 } +function ci_native_mpy_modules_clang_build { + # This currently only supports the host architecture (assumed to be x64). + for natmod in btree deflate features1 features2 features3 features4 framebuf heapq random re + do + make -C examples/natmod/$natmod CC=clang + done +} + function ci_unix_minimal_build { make ${MAKEOPTS} -C ports/unix VARIANT=minimal } @@ -744,6 +759,10 @@ function ci_unix_standard_run_tests { ci_unix_run_tests_full_helper standard } +function ci_unix_standard_run_native_mpy_tests { + ci_unix_run_native_mpy_tests_helper standard "$@" +} + function ci_unix_standard_v2_build { ci_unix_build_helper VARIANT=standard MICROPY_PREVIEW_VERSION_2=1 ci_unix_build_ffi_lib_helper gcc @@ -818,8 +837,7 @@ function ci_unix_coverage_run_mpy_merge_tests { } function ci_unix_coverage_run_native_mpy_tests { - MICROPYPATH=examples/natmod/features2 ./ports/unix/build-coverage/micropython -m features2 - (cd tests && ./run-natmodtests.py "$@" extmod/*.py) + ci_unix_run_native_mpy_tests_helper coverage "$@" } function ci_unix_32bit_setup { @@ -885,6 +903,7 @@ function ci_unix_gil_enabled_run_tests { function ci_unix_clang_setup { sudo apt-get update sudo apt-get install clang + pip3 install ar pyelftools clang --version } From b9cceaa6fd61d9620e96296730156c8a82c6802f Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 20 Jul 2026 12:05:27 +1000 Subject: [PATCH 508/635] py/makeqstrdefs.py: Propagate out errors from parallel pp step. Commit e6380fa15a4ddea6a80aeb557c159bc89c9507b1 changed the pp step from `subprocess.check_output()` to use `subprocess.Popen()`, but did not check the return code of the process. That means any process errors (eg compiler error) are swallowed and do not stop the build. This commit fixes that by explicitly checking `proc.returncode` once the process is complete, and raising an exception. Signed-off-by: Damien George --- py/makeqstrdefs.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/py/makeqstrdefs.py b/py/makeqstrdefs.py index 6998d1ea2bd..e1046fa2b19 100644 --- a/py/makeqstrdefs.py +++ b/py/makeqstrdefs.py @@ -68,7 +68,8 @@ def pp(flags): def run(files): try: filtered_lines = [] - with subprocess.Popen(args.pp + flags + files, stdout=subprocess.PIPE) as proc: + cmd = args.pp + flags + files + with subprocess.Popen(cmd, stdout=subprocess.PIPE) as proc: recent_file = None for line in proc.stdout: if line.isspace(): @@ -80,6 +81,9 @@ def run(files): filtered_lines.append(recent_file) recent_file = None filtered_lines.append(line) + proc.wait() + if proc.returncode: + raise PreprocessorError("command failed: " + " ".join(cmd)) return b"".join(filtered_lines) except subprocess.CalledProcessError as er: raise PreprocessorError(str(er)) From 215081bc37a4df27610e335b1bd5c5495c84801f Mon Sep 17 00:00:00 2001 From: Phil Howard Date: Fri, 3 Jul 2026 19:17:53 +0100 Subject: [PATCH 509/635] rp2: Bring up PSRAM using the SDK's hardware_psram library. Pico SDK 2.3.0 provides a hardware_psram library that detects and initialises PSRAM during runtime_init. Use it instead of the port's hand-written rp2_psram.c. Boards that fit PSRAM set MICROPY_HW_ENABLE_PSRAM (and, where the pico-sdk board header does not already provide it, MICROPY_HW_PSRAM_CS_PIN) in their mpconfigboard.cmake. These gate the hardware_psram link and feed the SDK: where the board header configures a size, its chip-select and size are used as-is; otherwise the size is auto-detected on the configured chip-select. main.c asserts the configured chip-select matches the board header. The GC heap is sized from psram_get_size() and placed using the SDK's __psram_start__/__psram_end__ linker symbols. PSRAM QMI timing is re-tuned after clock changes; flash programming restores it via the SDK's CS1 setup callback. CMakeLists: Reconsile board header config with mpconfigboard.*. rp2/rp2_psram: Redundant, removed. rp2/boards: Config updated. rp2/modmachine: Reconfigure PSRAM on clock change. rp2/rp2_flash: Document that SDK implicitly restores PSRAM. Signed-off-by: Phil Howard --- ports/rp2/CMakeLists.txt | 34 ++- .../mpconfigboard.cmake | 4 + .../ADAFRUIT_FEATHER_RP2350/mpconfigboard.h | 4 +- .../mpconfigboard.cmake | 4 + .../mpconfigboard.h | 3 - .../mpconfigboard.cmake | 4 + .../mpconfigboard.h | 4 +- .../mpconfigboard.cmake | 4 + .../SPARKFUN_PROMICRO_RP2350/mpconfigboard.h | 3 - .../mpconfigboard.cmake | 4 + .../SPARKFUN_THINGPLUS_RP2350/mpconfigboard.h | 3 - .../mpconfigboard.cmake | 4 + .../SPARKFUN_XRP_CONTROLLER/mpconfigboard.h | 3 - .../mpconfigboard.cmake | 4 + .../WAVESHARE_RP2350B_CORE/mpconfigboard.h | 2 - ports/rp2/main.c | 29 ++- ports/rp2/modmachine.c | 10 +- ports/rp2/rp2_flash.c | 8 +- ports/rp2/rp2_psram.c | 201 ------------------ ports/rp2/rp2_psram.h | 44 ---- 20 files changed, 99 insertions(+), 277 deletions(-) delete mode 100644 ports/rp2/rp2_psram.c delete mode 100644 ports/rp2/rp2_psram.h diff --git a/ports/rp2/CMakeLists.txt b/ports/rp2/CMakeLists.txt index a8b999e3d27..e674b19adf7 100644 --- a/ports/rp2/CMakeLists.txt +++ b/ports/rp2/CMakeLists.txt @@ -170,7 +170,6 @@ set(MICROPY_SOURCE_PORT pendsv.c rp2_flash.c rp2_pio.c - rp2_psram.c rp2_dma.c uart.c usbd.c @@ -593,6 +592,39 @@ target_compile_definitions(${MICROPY_TARGET} PRIVATE MICROPY_HW_ROMFS_BYTES=${MICROPY_HW_ROMFS_BYTES} ) +# PSRAM (RP2350 only) is brought up by the SDK's hardware_psram library at boot +# (runtime_init). Boards that fit PSRAM set MICROPY_HW_ENABLE_PSRAM and +# MICROPY_HW_PSRAM_CS_PIN in their mpconfigboard.cmake. +# +# Defer to the pico-sdk board header where it configures PSRAM: if it sets a size +# (PICO_PSRAM_SIZE_BYTES, which the SDK exposes as a CMake variable), use the +# header's chip-select and size as-is. main.c asserts the header chip-select +# matches MICROPY_HW_PSRAM_CS_PIN. Otherwise drive the SDK from the downstream +# config: auto-detect the size on the configured chip-select. +# +# MicroPython re-tunes the QMI timing after clock changes (see main.c and +# modmachine.c); flash programming restores it via the SDK's CS1 setup callback. +if(PICO_RP2350 AND MICROPY_HW_ENABLE_PSRAM) + list(APPEND PICO_SDK_COMPONENTS + hardware_psram + ) + target_compile_definitions(${MICROPY_TARGET} PRIVATE + MICROPY_HW_ENABLE_PSRAM=1 + ) + if(DEFINED MICROPY_HW_PSRAM_CS_PIN) + target_compile_definitions(${MICROPY_TARGET} PRIVATE + MICROPY_HW_PSRAM_CS_PIN=${MICROPY_HW_PSRAM_CS_PIN} + ) + endif() + if(NOT PICO_PSRAM_SIZE_BYTES) + # No size configured upstream: auto-detect on the configured chip-select. + target_compile_definitions(${MICROPY_TARGET} PRIVATE + PICO_PSRAM_CS_PIN=${MICROPY_HW_PSRAM_CS_PIN} + PICO_AUTO_DETECT_PSRAM_SIZE=1 + ) + endif() +endif() + # Apply optimisations to performance-critical source code. set_source_files_properties( ${MICROPY_PY_DIR}/map.c diff --git a/ports/rp2/boards/ADAFRUIT_FEATHER_RP2350/mpconfigboard.cmake b/ports/rp2/boards/ADAFRUIT_FEATHER_RP2350/mpconfigboard.cmake index 26db5db5965..3f5bdec039b 100644 --- a/ports/rp2/boards/ADAFRUIT_FEATHER_RP2350/mpconfigboard.cmake +++ b/ports/rp2/boards/ADAFRUIT_FEATHER_RP2350/mpconfigboard.cmake @@ -11,3 +11,7 @@ endif() # To change the gpio count for QFN-80 # set(PICO_NUM_GPIOS 48) + +# 8MB PSRAM on GPIO8. +set(MICROPY_HW_ENABLE_PSRAM 1) +set(MICROPY_HW_PSRAM_CS_PIN 8) diff --git a/ports/rp2/boards/ADAFRUIT_FEATHER_RP2350/mpconfigboard.h b/ports/rp2/boards/ADAFRUIT_FEATHER_RP2350/mpconfigboard.h index d6f950f8cc4..c31e3bedba8 100644 --- a/ports/rp2/boards/ADAFRUIT_FEATHER_RP2350/mpconfigboard.h +++ b/ports/rp2/boards/ADAFRUIT_FEATHER_RP2350/mpconfigboard.h @@ -10,6 +10,4 @@ // Red user LED GPIO7 -// Optional PSRAM on GPIO8 -#define MICROPY_HW_PSRAM_CS_PIN (8) -#define MICROPY_HW_ENABLE_PSRAM (1) +// Optional PSRAM on GPIO8 (enabled in mpconfigboard.cmake) diff --git a/ports/rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350/mpconfigboard.cmake b/ports/rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350/mpconfigboard.cmake index c9c9b1ab1b9..b611c7efebe 100644 --- a/ports/rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350/mpconfigboard.cmake +++ b/ports/rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350/mpconfigboard.cmake @@ -12,3 +12,7 @@ set(MICROPY_FROZEN_MANIFEST ${MICROPY_BOARD_DIR}/manifest.py) if(NOT DEFINED MICROPY_HW_FLASH_STORAGE_BYTES) set(MICROPY_HW_FLASH_STORAGE_BYTES 14680064) # 14 * 1024 * 1024 endif() + +# 8MB PSRAM on GPIO0. +set(MICROPY_HW_ENABLE_PSRAM 1) +set(MICROPY_HW_PSRAM_CS_PIN 0) diff --git a/ports/rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350/mpconfigboard.h b/ports/rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350/mpconfigboard.h index b55eac5d8fd..8d38b380d4c 100644 --- a/ports/rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350/mpconfigboard.h +++ b/ports/rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350/mpconfigboard.h @@ -27,6 +27,3 @@ #define MICROPY_HW_UART1_RX (5) #define MICROPY_HW_UART1_CTS (6) #define MICROPY_HW_UART1_RTS (7) - -#define MICROPY_HW_PSRAM_CS_PIN (0) -#define MICROPY_HW_ENABLE_PSRAM (1) diff --git a/ports/rp2/boards/SPARKFUN_IOTREDBOARD_RP2350/mpconfigboard.cmake b/ports/rp2/boards/SPARKFUN_IOTREDBOARD_RP2350/mpconfigboard.cmake index f1dd0021176..816fd51b9f6 100644 --- a/ports/rp2/boards/SPARKFUN_IOTREDBOARD_RP2350/mpconfigboard.cmake +++ b/ports/rp2/boards/SPARKFUN_IOTREDBOARD_RP2350/mpconfigboard.cmake @@ -22,3 +22,7 @@ set(MICROPY_FROZEN_MANIFEST ${MICROPY_BOARD_DIR}/manifest.py) if(NOT DEFINED MICROPY_HW_FLASH_STORAGE_BYTES) set(MICROPY_HW_FLASH_STORAGE_BYTES 15204352) # PICO_FLASH_SIZE_BYTES - 1536 * 1024 = 16MB - 1.5MB endif() + +# 8MB PSRAM on GPIO47. +set(MICROPY_HW_ENABLE_PSRAM 1) +set(MICROPY_HW_PSRAM_CS_PIN 47) diff --git a/ports/rp2/boards/SPARKFUN_IOTREDBOARD_RP2350/mpconfigboard.h b/ports/rp2/boards/SPARKFUN_IOTREDBOARD_RP2350/mpconfigboard.h index 767e36c07d0..1818fd626af 100644 --- a/ports/rp2/boards/SPARKFUN_IOTREDBOARD_RP2350/mpconfigboard.h +++ b/ports/rp2/boards/SPARKFUN_IOTREDBOARD_RP2350/mpconfigboard.h @@ -44,9 +44,7 @@ #define MICROPY_HW_SPI1_MOSI (11) #define MICROPY_HW_SPI1_MISO (8) -// PSRAM -#define MICROPY_HW_PSRAM_CS_PIN (47) -#define MICROPY_HW_ENABLE_PSRAM (1) +// PSRAM enabled in mpconfigboard.cmake // #include "enable_cyw43.h" diff --git a/ports/rp2/boards/SPARKFUN_PROMICRO_RP2350/mpconfigboard.cmake b/ports/rp2/boards/SPARKFUN_PROMICRO_RP2350/mpconfigboard.cmake index ab547e9ed93..92b26929ece 100644 --- a/ports/rp2/boards/SPARKFUN_PROMICRO_RP2350/mpconfigboard.cmake +++ b/ports/rp2/boards/SPARKFUN_PROMICRO_RP2350/mpconfigboard.cmake @@ -6,3 +6,7 @@ set(PICO_PLATFORM "rp2350") if(NOT DEFINED MICROPY_HW_FLASH_STORAGE_BYTES) set(MICROPY_HW_FLASH_STORAGE_BYTES 14680064) # 14 * 1024 * 1024 endif() + +# 8MB PSRAM. The chip-select (GPIO19) and size come from the pico-sdk board +# header (sparkfun_promicro_rp2350.h). +set(MICROPY_HW_ENABLE_PSRAM 1) diff --git a/ports/rp2/boards/SPARKFUN_PROMICRO_RP2350/mpconfigboard.h b/ports/rp2/boards/SPARKFUN_PROMICRO_RP2350/mpconfigboard.h index 2ceecfd1cc0..15063782280 100644 --- a/ports/rp2/boards/SPARKFUN_PROMICRO_RP2350/mpconfigboard.h +++ b/ports/rp2/boards/SPARKFUN_PROMICRO_RP2350/mpconfigboard.h @@ -20,6 +20,3 @@ #define MICROPY_HW_SPI0_SCK (22) #define MICROPY_HW_SPI0_MOSI (23) #define MICROPY_HW_SPI0_MISO (20) - -#define MICROPY_HW_PSRAM_CS_PIN (19) -#define MICROPY_HW_ENABLE_PSRAM (1) diff --git a/ports/rp2/boards/SPARKFUN_THINGPLUS_RP2350/mpconfigboard.cmake b/ports/rp2/boards/SPARKFUN_THINGPLUS_RP2350/mpconfigboard.cmake index 1227ff8ac1f..27e9affa374 100644 --- a/ports/rp2/boards/SPARKFUN_THINGPLUS_RP2350/mpconfigboard.cmake +++ b/ports/rp2/boards/SPARKFUN_THINGPLUS_RP2350/mpconfigboard.cmake @@ -17,3 +17,7 @@ set(MICROPY_FROZEN_MANIFEST ${MICROPY_BOARD_DIR}/manifest.py) if(NOT DEFINED MICROPY_HW_FLASH_STORAGE_BYTES) set(MICROPY_HW_FLASH_STORAGE_BYTES 14680064) # 14 * 1024 * 1024 endif() + +# 8MB PSRAM. The chip-select (GPIO8) and size come from the pico-sdk board +# header (sparkfun_thingplus_rp2350.h). +set(MICROPY_HW_ENABLE_PSRAM 1) diff --git a/ports/rp2/boards/SPARKFUN_THINGPLUS_RP2350/mpconfigboard.h b/ports/rp2/boards/SPARKFUN_THINGPLUS_RP2350/mpconfigboard.h index e8456c4d0fd..5461da112fa 100644 --- a/ports/rp2/boards/SPARKFUN_THINGPLUS_RP2350/mpconfigboard.h +++ b/ports/rp2/boards/SPARKFUN_THINGPLUS_RP2350/mpconfigboard.h @@ -42,6 +42,3 @@ int mp_hal_is_pin_reserved(int n); #define MICROPY_HW_UART1_RX (5) #define MICROPY_HW_UART1_CTS (6) #define MICROPY_HW_UART1_RTS (7) - -#define MICROPY_HW_PSRAM_CS_PIN (8) -#define MICROPY_HW_ENABLE_PSRAM (1) diff --git a/ports/rp2/boards/SPARKFUN_XRP_CONTROLLER/mpconfigboard.cmake b/ports/rp2/boards/SPARKFUN_XRP_CONTROLLER/mpconfigboard.cmake index 7d1c06aef83..b65c3db1098 100644 --- a/ports/rp2/boards/SPARKFUN_XRP_CONTROLLER/mpconfigboard.cmake +++ b/ports/rp2/boards/SPARKFUN_XRP_CONTROLLER/mpconfigboard.cmake @@ -22,3 +22,7 @@ set(MICROPY_FROZEN_MANIFEST ${MICROPY_BOARD_DIR}/manifest.py) if(NOT DEFINED MICROPY_HW_FLASH_STORAGE_BYTES) set(MICROPY_HW_FLASH_STORAGE_BYTES 15204352) # PICO_FLASH_SIZE_BYTES - 1536 * 1024 = 16MB - 1.5MB endif() + +# 8MB PSRAM on GPIO47. +set(MICROPY_HW_ENABLE_PSRAM 1) +set(MICROPY_HW_PSRAM_CS_PIN 47) diff --git a/ports/rp2/boards/SPARKFUN_XRP_CONTROLLER/mpconfigboard.h b/ports/rp2/boards/SPARKFUN_XRP_CONTROLLER/mpconfigboard.h index 164824e85d7..289e707f62a 100644 --- a/ports/rp2/boards/SPARKFUN_XRP_CONTROLLER/mpconfigboard.h +++ b/ports/rp2/boards/SPARKFUN_XRP_CONTROLLER/mpconfigboard.h @@ -46,6 +46,3 @@ int mp_hal_is_pin_reserved(int n); #define MICROPY_HW_UART1_RX (9) #define MICROPY_HW_UART1_CTS (10) #define MICROPY_HW_UART1_RTS (11) - -#define MICROPY_HW_PSRAM_CS_PIN (47) -#define MICROPY_HW_ENABLE_PSRAM (1) diff --git a/ports/rp2/boards/WAVESHARE_RP2350B_CORE/mpconfigboard.cmake b/ports/rp2/boards/WAVESHARE_RP2350B_CORE/mpconfigboard.cmake index 920d5b1711c..a071333fb33 100644 --- a/ports/rp2/boards/WAVESHARE_RP2350B_CORE/mpconfigboard.cmake +++ b/ports/rp2/boards/WAVESHARE_RP2350B_CORE/mpconfigboard.cmake @@ -14,3 +14,7 @@ set(PICO_FLASH_SIZE_BYTES 16777216) if(NOT DEFINED MICROPY_HW_FLASH_STORAGE_BYTES) set(MICROPY_HW_FLASH_STORAGE_BYTES 14680064) # 14 * 1024 * 1024 endif() + +# 8MB PSRAM on GPIO47. +set(MICROPY_HW_ENABLE_PSRAM 1) +set(MICROPY_HW_PSRAM_CS_PIN 47) diff --git a/ports/rp2/boards/WAVESHARE_RP2350B_CORE/mpconfigboard.h b/ports/rp2/boards/WAVESHARE_RP2350B_CORE/mpconfigboard.h index 06efbbfd3d7..8c2c54c23c6 100644 --- a/ports/rp2/boards/WAVESHARE_RP2350B_CORE/mpconfigboard.h +++ b/ports/rp2/boards/WAVESHARE_RP2350B_CORE/mpconfigboard.h @@ -2,8 +2,6 @@ #define MICROPY_HW_BOARD_NAME "Waveshare RP2350B Core" #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) -#define MICROPY_HW_PSRAM_CS_PIN (47) -#define MICROPY_HW_ENABLE_PSRAM (1) // Override machine_uart.c definitions. // See waveshare_rp2350b.h and note that the PICO_DEFAULT_UART configuration diff --git a/ports/rp2/main.c b/ports/rp2/main.c index c67f404f61e..f43c85eee50 100644 --- a/ports/rp2/main.c +++ b/ports/rp2/main.c @@ -48,7 +48,6 @@ #include "mpnetworkport.h" #include "genhdr/mpversion.h" #include "mp_usbd.h" -#include "rp2_psram.h" #include "pico/stdlib.h" #include "pico/binary_info.h" @@ -67,9 +66,22 @@ #endif #include "pico/aon_timer.h" #include "shared/timeutils/timeutils.h" +#if MICROPY_HW_ENABLE_PSRAM +#include "hardware/psram.h" +// When the pico-sdk board header configures the PSRAM chip-select, make sure the +// downstream MicroPython config (MICROPY_HW_PSRAM_CS_PIN) agrees with it. +#if defined(PICO_PSRAM_CS_PIN) && defined(MICROPY_HW_PSRAM_CS_PIN) && (PICO_PSRAM_CS_PIN != MICROPY_HW_PSRAM_CS_PIN) +#error "MICROPY_HW_PSRAM_CS_PIN does not match the board header's PICO_PSRAM_CS_PIN" +#endif +#endif extern uint8_t __StackTop, __StackBottom; extern uint8_t __GcHeapStart, __GcHeapEnd; +#if MICROPY_HW_ENABLE_PSRAM +// Provided by the SDK's PSRAM linker sections: __psram_start__ is ORIGIN(PSRAM) +// (the PSRAM base) and __psram_end__ is the end of any __in_psram data. +extern uint8_t __psram_start__, __psram_end__; +#endif // Embed version info in the binary in machine readable form bi_decl(bi_program_version_string(MICROPY_GIT_TAG)); @@ -99,7 +111,12 @@ int main(int argc, char **argv) { rp2_flash_set_timing(); #if MICROPY_HW_ENABLE_PSRAM - size_t psram_size = psram_init(MICROPY_HW_PSRAM_CS_PIN); + // The SDK's runtime_init brought PSRAM up at the boot clock; re-tune the QMI + // timing now that the system clock has been set to its final value. + if (psram_is_available()) { + psram_configure_params(PICO_DEFAULT_PSRAM_MAX_FREQ, PICO_DEFAULT_PSRAM_MAX_SELECT, PICO_DEFAULT_PSRAM_MIN_DESELECT); + psram_reinitialize(); + } #endif #if MICROPY_HW_ENABLE_UART_REPL @@ -131,12 +148,16 @@ int main(int argc, char **argv) { mp_cstack_init_with_top(&__StackTop, &__StackTop - &__StackBottom); #if MICROPY_HW_ENABLE_PSRAM + size_t psram_size = psram_get_size(); // 0 if PSRAM was not brought up if (psram_size) { + // Use PSRAM from the end of any __in_psram data up to the top of the chip. + void *psram_heap_start = &__psram_end__; + void *psram_heap_end = &__psram_start__ + psram_size; #if MICROPY_GC_SPLIT_HEAP gc_init(&__GcHeapStart, &__GcHeapEnd); - gc_add((void *)PSRAM_BASE, (void *)(PSRAM_BASE + psram_size)); + gc_add(psram_heap_start, psram_heap_end); #else - gc_init((void *)PSRAM_BASE, (void *)(PSRAM_BASE + psram_size)); + gc_init(psram_heap_start, psram_heap_end); #endif } else { gc_init(&__GcHeapStart, &__GcHeapEnd); diff --git a/ports/rp2/modmachine.c b/ports/rp2/modmachine.c index dc064cc1a77..fc711770e29 100644 --- a/ports/rp2/modmachine.c +++ b/ports/rp2/modmachine.c @@ -31,8 +31,10 @@ #include "mp_usbd.h" #include "modmachine.h" #include "uart.h" -#include "rp2_psram.h" #include "rp2_flash.h" +#if MICROPY_HW_ENABLE_PSRAM +#include "hardware/psram.h" +#endif #include "clocks_extra.h" #include "hardware/pll.h" #include "hardware/structs/rosc.h" @@ -133,7 +135,11 @@ static void mp_machine_set_freq(size_t n_args, const mp_obj_t *args) { mp_uart_init(); #endif #if MICROPY_HW_ENABLE_PSRAM - psram_init(MICROPY_HW_PSRAM_CS_PIN); + // Re-tune the PSRAM QMI timing for the new system clock. + if (psram_is_available()) { + psram_configure_params(PICO_DEFAULT_PSRAM_MAX_FREQ, PICO_DEFAULT_PSRAM_MAX_SELECT, PICO_DEFAULT_PSRAM_MIN_DESELECT); + psram_reinitialize(); + } #endif } diff --git a/ports/rp2/rp2_flash.c b/ports/rp2/rp2_flash.c index 4d41d45733c..d030b78866a 100644 --- a/ports/rp2/rp2_flash.c +++ b/ports/rp2/rp2_flash.c @@ -33,7 +33,6 @@ #include "modrp2.h" #include "hardware/flash.h" #include "pico/binary_info.h" -#include "rp2_psram.h" #ifdef PICO_RP2350 #include "hardware/structs/ioqspi.h" #include "hardware/structs/qmi.h" @@ -189,11 +188,10 @@ static uint32_t begin_critical_flash_section(void) { } static void end_critical_flash_section(uint32_t state) { - // The ROM function to program flash will have reset flash and PSRAM timings to defaults + // The ROM function to program flash will have reset the flash timing to + // defaults. (PSRAM timing is restored automatically by the SDK's flash + // routines via the QMI CS1 setup callback registered by psram_reinitialize.) rp2_flash_set_timing_internal(clock_get_hz(clk_sys)); - #if MICROPY_HW_ENABLE_PSRAM - psram_init(MICROPY_HW_PSRAM_CS_PIN); - #endif restore_interrupts(state); if (use_multicore_lockout()) { multicore_lockout_end_blocking(); diff --git a/ports/rp2/rp2_psram.c b/ports/rp2/rp2_psram.c deleted file mode 100644 index 3b212680674..00000000000 --- a/ports/rp2/rp2_psram.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2025 Phil Howard - * Mike Bell - * Kirk D. Benell - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/mphal.h" - -#if MICROPY_HW_ENABLE_PSRAM - -#include "hardware/structs/ioqspi.h" -#include "hardware/structs/qmi.h" -#include "hardware/structs/xip_ctrl.h" -#include "hardware/clocks.h" -#include "hardware/sync.h" -#include "rp2_psram.h" - -size_t __no_inline_not_in_flash_func(psram_detect)(void) { - int psram_size = 0; - - // Try and read the PSRAM ID via direct_csr. - qmi_hw->direct_csr = 30 << QMI_DIRECT_CSR_CLKDIV_LSB | QMI_DIRECT_CSR_EN_BITS; - - // Need to poll for the cooldown on the last XIP transfer to expire - // (via direct-mode BUSY flag) before it is safe to perform the first - // direct-mode operation - while ((qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) != 0) { - } - - // Exit out of QMI in case we've inited already - qmi_hw->direct_csr |= QMI_DIRECT_CSR_ASSERT_CS1N_BITS; - - // Transmit as quad. - qmi_hw->direct_tx = QMI_DIRECT_TX_OE_BITS | QMI_DIRECT_TX_IWIDTH_VALUE_Q << QMI_DIRECT_TX_IWIDTH_LSB | 0xf5; - - while ((qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) != 0) { - } - - (void)qmi_hw->direct_rx; - - qmi_hw->direct_csr &= ~(QMI_DIRECT_CSR_ASSERT_CS1N_BITS); - - // Read the id - qmi_hw->direct_csr |= QMI_DIRECT_CSR_ASSERT_CS1N_BITS; - uint8_t kgd = 0; - uint8_t eid = 0; - - for (size_t i = 0; i < 7; i++) { - if (i == 0) { - qmi_hw->direct_tx = 0x9f; - } else { - qmi_hw->direct_tx = 0xff; - } - - while ((qmi_hw->direct_csr & QMI_DIRECT_CSR_TXEMPTY_BITS) == 0) { - } - - while ((qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) != 0) { - } - - if (i == 5) { - kgd = qmi_hw->direct_rx; - } else if (i == 6) { - eid = qmi_hw->direct_rx; - } else { - (void)qmi_hw->direct_rx; - } - } - - // Disable direct csr. - qmi_hw->direct_csr &= ~(QMI_DIRECT_CSR_ASSERT_CS1N_BITS | QMI_DIRECT_CSR_EN_BITS); - - if (kgd == 0x5D) { - psram_size = 1024 * 1024; // 1 MiB - uint8_t size_id = eid >> 5; - if (eid == 0x26 || size_id == 2) { - psram_size *= 8; // 8 MiB - } else if (size_id == 0) { - psram_size *= 2; // 2 MiB - } else if (size_id == 1) { - psram_size *= 4; // 4 MiB - } - } - - return psram_size; -} - -size_t __no_inline_not_in_flash_func(psram_init)(uint cs_pin) { - gpio_set_function(cs_pin, GPIO_FUNC_XIP_CS1); - - uint32_t intr_stash = save_and_disable_interrupts(); - - size_t psram_size = psram_detect(); - - if (!psram_size) { - restore_interrupts(intr_stash); - return 0; - } - - // Read clock speed before entering direct mode (flash access is - // unavailable while QMI direct mode is enabled) - const int max_psram_freq = 133000000; - const int clock_hz = clock_get_hz(clk_sys); - - // Enable direct mode, PSRAM CS, clkdiv of 10. - qmi_hw->direct_csr = 10 << QMI_DIRECT_CSR_CLKDIV_LSB | \ - QMI_DIRECT_CSR_EN_BITS | \ - QMI_DIRECT_CSR_AUTO_CS1N_BITS; - while (qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) { - } - - // Enable QPI mode on the PSRAM - const uint CMD_QPI_EN = 0x35; - qmi_hw->direct_tx = QMI_DIRECT_TX_NOPUSH_BITS | CMD_QPI_EN; - - while (qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) { - } - - // Set PSRAM timing for APS6404 - // - // Using an rxdelay equal to the divisor isn't enough when running the APS6404 close to 133MHz. - // So: don't allow running at divisor 1 above 100MHz (because delay of 2 would be too late), - // and add an extra 1 to the rxdelay if the divided clock is > 100MHz (i.e. sys clock > 200MHz). - int divisor = (clock_hz + max_psram_freq - 1) / max_psram_freq; - if (divisor == 1 && clock_hz > 100000000) { - divisor = 2; - } - int rxdelay = divisor; - if (clock_hz / divisor > 100000000) { - rxdelay += 1; - } - - // - Max select must be <= 8us. The value is given in multiples of 64 system clocks. - // - Min deselect must be >= 18ns. The value is given in system clock cycles - ceil(divisor / 2). - const int clock_period_fs = 1000000000000000ll / clock_hz; - const int max_select = (125 * 1000000) / clock_period_fs; // 125 = 8000ns / 64 - const int min_deselect = (18 * 1000000 + (clock_period_fs - 1)) / clock_period_fs - (divisor + 1) / 2; - - qmi_hw->m[1].timing = 1 << QMI_M1_TIMING_COOLDOWN_LSB | - QMI_M1_TIMING_PAGEBREAK_VALUE_1024 << QMI_M1_TIMING_PAGEBREAK_LSB | - max_select << QMI_M1_TIMING_MAX_SELECT_LSB | - min_deselect << QMI_M1_TIMING_MIN_DESELECT_LSB | - rxdelay << QMI_M1_TIMING_RXDELAY_LSB | - divisor << QMI_M1_TIMING_CLKDIV_LSB; - - // Set PSRAM commands and formats - qmi_hw->m[1].rfmt = - QMI_M0_RFMT_PREFIX_WIDTH_VALUE_Q << QMI_M0_RFMT_PREFIX_WIDTH_LSB | \ - QMI_M0_RFMT_ADDR_WIDTH_VALUE_Q << QMI_M0_RFMT_ADDR_WIDTH_LSB | \ - QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_Q << QMI_M0_RFMT_SUFFIX_WIDTH_LSB | \ - QMI_M0_RFMT_DUMMY_WIDTH_VALUE_Q << QMI_M0_RFMT_DUMMY_WIDTH_LSB | \ - QMI_M0_RFMT_DATA_WIDTH_VALUE_Q << QMI_M0_RFMT_DATA_WIDTH_LSB | \ - QMI_M0_RFMT_PREFIX_LEN_VALUE_8 << QMI_M0_RFMT_PREFIX_LEN_LSB | \ - 6 << QMI_M0_RFMT_DUMMY_LEN_LSB; - - qmi_hw->m[1].rcmd = 0xEB; - - qmi_hw->m[1].wfmt = - QMI_M0_WFMT_PREFIX_WIDTH_VALUE_Q << QMI_M0_WFMT_PREFIX_WIDTH_LSB | \ - QMI_M0_WFMT_ADDR_WIDTH_VALUE_Q << QMI_M0_WFMT_ADDR_WIDTH_LSB | \ - QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_Q << QMI_M0_WFMT_SUFFIX_WIDTH_LSB | \ - QMI_M0_WFMT_DUMMY_WIDTH_VALUE_Q << QMI_M0_WFMT_DUMMY_WIDTH_LSB | \ - QMI_M0_WFMT_DATA_WIDTH_VALUE_Q << QMI_M0_WFMT_DATA_WIDTH_LSB | \ - QMI_M0_WFMT_PREFIX_LEN_VALUE_8 << QMI_M0_WFMT_PREFIX_LEN_LSB; - - qmi_hw->m[1].wcmd = 0x38; - - // Disable direct mode - qmi_hw->direct_csr = 0; - - // Enable writes to PSRAM - hw_set_bits(&xip_ctrl_hw->ctrl, XIP_CTRL_WRITABLE_M1_BITS); - - restore_interrupts(intr_stash); - - return psram_size; -} - -#endif diff --git a/ports/rp2/rp2_psram.h b/ports/rp2/rp2_psram.h deleted file mode 100644 index 0eddf634159..00000000000 --- a/ports/rp2/rp2_psram.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2025 Phil Howard - * Mike Bell - * Kirk D. Benell - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "pico/stdlib.h" - -#ifndef MICROPY_INCLUDED_RP2_RP2_PSRAM_H -#define MICROPY_INCLUDED_RP2_RP2_PSRAM_H - -#if MICROPY_HW_ENABLE_PSRAM -#ifndef MICROPY_HW_PSRAM_CS_PIN -#error "MICROPY_HW_ENABLE_PSRAM requires MICROPY_HW_PSRAM_CS_PIN" -#endif - -#define PSRAM_BASE _u(0x11000000) - -extern size_t psram_init(uint cs_pin); -#endif - -#endif From d569751e4600d899510028f062441e225f612370 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 21 Jul 2026 13:12:42 +1000 Subject: [PATCH 510/635] rp2/boards/SEEED_XIAO_RP2350: Decrease filesystem size to 1408k. This flash size of this board was corrected from 4MiB down to 2MiB in pico-sdk 2.3.0, in commit https://github.com/raspberrypi/pico-sdk/commit/0da73ec045d39f9d9676eb3261f6dbc55d12cc26 So, reduce the filesystem size in order that the firmware fits. The size of 1408k was chosen to match SEEED_XIAO_RP2040. Signed-off-by: Damien George --- ports/rp2/boards/SEEED_XIAO_RP2350/mpconfigboard.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/rp2/boards/SEEED_XIAO_RP2350/mpconfigboard.cmake b/ports/rp2/boards/SEEED_XIAO_RP2350/mpconfigboard.cmake index 95a5ac21c29..38663bbf09d 100644 --- a/ports/rp2/boards/SEEED_XIAO_RP2350/mpconfigboard.cmake +++ b/ports/rp2/boards/SEEED_XIAO_RP2350/mpconfigboard.cmake @@ -5,5 +5,5 @@ set(PICO_BOARD "seeed_xiao_rp2350") # set(PICO_NUM_GPIOS 48) if(NOT DEFINED MICROPY_HW_FLASH_STORAGE_BYTES) - set(MICROPY_HW_FLASH_STORAGE_BYTES 3145728) # PICO_FLASH_SIZE_BYTES - 1024 * 1024 = 4MB - 1MB + set(MICROPY_HW_FLASH_STORAGE_BYTES 1441792) # 1408 * 1024 endif() From 072ff7bd384f0b17865dd4068289165938015b81 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 21 Jul 2026 13:31:54 +1000 Subject: [PATCH 511/635] stm32/boards/B_L072Z_LRWAN1: Enable MICROPY_PY_BUILTINS_MEMORYVIEW. This board is tight on flash and sets the feature level to "core". That excludes `memoryview` which is needed for the new `machine.mem_backup()` feature. Both `memoryview` and `mem_backup` are useful features, so enable the former to get them both working. Signed-off-by: Damien George --- ports/stm32/boards/B_L072Z_LRWAN1/mpconfigboard.h | 1 + 1 file changed, 1 insertion(+) diff --git a/ports/stm32/boards/B_L072Z_LRWAN1/mpconfigboard.h b/ports/stm32/boards/B_L072Z_LRWAN1/mpconfigboard.h index df781a75671..f4bd251f10e 100644 --- a/ports/stm32/boards/B_L072Z_LRWAN1/mpconfigboard.h +++ b/ports/stm32/boards/B_L072Z_LRWAN1/mpconfigboard.h @@ -17,6 +17,7 @@ #define MICROPY_OPT_COMPUTED_GOTO (0) #define MICROPY_PY_BUILTINS_COMPLEX (0) #define MICROPY_PY_GENERATOR_PEND_THROW (0) +#define MICROPY_PY_BUILTINS_MEMORYVIEW (1) #define MICROPY_PY_MATH (0) #define MICROPY_PY_FRAMEBUF (0) #define MICROPY_PY_SOCKET (0) From c82d9ca8f87fe3c4d1045fe675c5623135635e90 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Tue, 21 Jul 2026 20:51:14 +0200 Subject: [PATCH 512/635] tools/mpremote: Properly escape quotes for commands. closes: https://github.com/micropython/micropython/issues/18657 Signed-off-by: Jos Verlinde --- tools/mpremote/mpremote/transport.py | 32 +++++++++++++++++----------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/tools/mpremote/mpremote/transport.py b/tools/mpremote/mpremote/transport.py index e5cb2c479fa..6ef0ea2a0af 100644 --- a/tools/mpremote/mpremote/transport.py +++ b/tools/mpremote/mpremote/transport.py @@ -53,6 +53,14 @@ def __init__(self, status_code, error_output): listdir_result = namedtuple("dir_result", ["name", "st_mode", "st_ino", "st_size"]) +def _quote_path(path: str) -> str: + """ + Properly escape a path string for use in Python code sent to the REPL. + Uses repr() to handle all special characters including quotes, backslashes, and Unicode characters. + """ + return repr(path) + + # Takes a Transport error (containing the text of an OSError traceback) and # raises it as the corresponding OSError-derived exception. def _convert_filesystem_error(e, info): @@ -84,7 +92,7 @@ def repr_consumer(b): buf.extend(b.replace(b"\x04", b"")) cmd = "import os\nfor f in os.ilistdir(%s):\n print(repr(f), end=',')" % ( - ("'%s'" % src) if src else "" + _quote_path(src) if src else "" ) try: buf.extend(b"[") @@ -101,7 +109,7 @@ def repr_consumer(b): def fs_stat(self, src): try: self.exec("import os") - return os.stat_result(self.eval("tuple(os.stat(%s))" % ("'%s'" % src))) + return os.stat_result(self.eval("tuple(os.stat(%s))" % _quote_path(src))) except TransportExecError as e: raise _convert_filesystem_error(e, src) from None @@ -122,8 +130,8 @@ def fs_isdir(self, src): def fs_printfile(self, src, chunk_size=256): cmd = ( - "with open('%s') as f:\n while 1:\n" - " b=f.read(%u)\n if not b:break\n print(b,end='')" % (src, chunk_size) + "with open(%s) as f:\n while 1:\n" + " b=f.read(%u)\n if not b:break\n print(b,end='')" % (_quote_path(src), chunk_size) ) try: self.exec(cmd, data_consumer=stdout_write_bytes) @@ -137,7 +145,7 @@ def fs_readfile(self, src, chunk_size=256, progress_callback=None): contents = bytearray() try: - self.exec("f=open('%s','rb')\nr=f.read" % src) + self.exec("f=open(%s,'rb')\nr=f.read" % _quote_path(src)) while True: chunk = self.eval("r({})".format(chunk_size)) if not chunk: @@ -157,7 +165,7 @@ def fs_writefile(self, dest, data, chunk_size=256, progress_callback=None): written = 0 try: - self.exec("f=open('%s','wb')\nw=f.write" % dest) + self.exec("f=open(%s,'wb')\nw=f.write" % _quote_path(dest)) while data: chunk = data[:chunk_size] self.exec("w(" + repr(chunk) + ")") @@ -171,25 +179,25 @@ def fs_writefile(self, dest, data, chunk_size=256, progress_callback=None): def fs_mkdir(self, path): try: - self.exec("import os\nos.mkdir('%s')" % path) + self.exec("import os\nos.mkdir(%s)" % _quote_path(path)) except TransportExecError as e: raise _convert_filesystem_error(e, path) from None def fs_rmdir(self, path): try: - self.exec("import os\nos.rmdir('%s')" % path) + self.exec("import os\nos.rmdir(%s)" % _quote_path(path)) except TransportExecError as e: raise _convert_filesystem_error(e, path) from None def fs_rmfile(self, path): try: - self.exec("import os\nos.remove('%s')" % path) + self.exec("import os\nos.remove(%s)" % _quote_path(path)) except TransportExecError as e: raise _convert_filesystem_error(e, path) from None def fs_touchfile(self, path): try: - self.exec("f=open('%s','a')\nf.close()" % path) + self.exec("f=open(%s,'a')\nf.close()" % _quote_path(path)) except TransportExecError as e: raise _convert_filesystem_error(e, path) from None @@ -202,8 +210,8 @@ def fs_hashfile(self, path, algo, chunk_size=256): return getattr(hashlib, algo)(data).digest() try: self.exec( - "buf = memoryview(bytearray({chunk_size}))\nwith open('{path}', 'rb') as f:\n while True:\n n = f.readinto(buf)\n if n == 0:\n break\n h.update(buf if n == {chunk_size} else buf[:n])\n".format( - chunk_size=chunk_size, path=path + "buf = memoryview(bytearray({chunk_size}))\nwith open({path}, 'rb') as f:\n while True:\n n = f.readinto(buf)\n if n == 0:\n break\n h.update(buf if n == {chunk_size} else buf[:n])\n".format( + chunk_size=chunk_size, path=_quote_path(path) ) ) return self.eval("h.digest()") From e7c29b965b60a5cfbaa33aa762b71cdadf60bc93 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Tue, 21 Jul 2026 20:51:15 +0200 Subject: [PATCH 513/635] tools/mpremote: Fix command expansion to handle `=`. fixes: https://github.com/micropython/micropython/issues/18658 Signed-off-by: Jos Verlinde --- tools/mpremote/mpremote/main.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/mpremote/mpremote/main.py b/tools/mpremote/mpremote/main.py index b57de0e25fc..123246928ae 100644 --- a/tools/mpremote/mpremote/main.py +++ b/tools/mpremote/mpremote/main.py @@ -492,6 +492,7 @@ def usage_error(cmd, exp_args, msg): last_arg_idx = len(args) pre = [] + exp_args = () # Initialize to empty tuple for commands with no expected args while args and args[0] in _command_expansions: cmd = args.pop(0) exp_args, exp_sub, _ = _command_expansions[cmd] @@ -518,7 +519,7 @@ def usage_error(cmd, exp_args, msg): args[0:0] = exp_sub last_arg_idx = len(exp_sub) - if last_arg_idx < len(args) and "=" in args[last_arg_idx]: + if exp_args and last_arg_idx < len(args) and "=" in args[last_arg_idx]: # Extra unknown arguments given. arg = args[last_arg_idx].split("=", 1)[0] usage_error(cmd, exp_args, f"given unexpected argument {arg}") From 8b3491b4cb610d2c9323913489f3ffd87d09f15a Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Tue, 21 Jul 2026 20:51:15 +0200 Subject: [PATCH 514/635] tools/mpremote: Fix UnicodeEncodeError on Windows consoles. Adds a Modern Windows console implementation that can write raw UTF-8 bytes directly (like POSIX) Improve the Legacy consol to use an incremental decoder to handle split UTF-8 sequences within writes. fixes https://github.com/micropython/micropython/issues/15228 Signed-off-by: Jos Verlinde --- tools/mpremote/mpremote/console.py | 191 ++++++++++++++++++++------- tools/mpremote/mpremote/main.py | 7 + tools/mpremote/mpremote/transport.py | 53 +++++++- 3 files changed, 198 insertions(+), 53 deletions(-) diff --git a/tools/mpremote/mpremote/console.py b/tools/mpremote/mpremote/console.py index e34fd9e2776..2d48304b3a0 100644 --- a/tools/mpremote/mpremote/console.py +++ b/tools/mpremote/mpremote/console.py @@ -1,3 +1,6 @@ +import codecs +import io +import os import sys, time try: @@ -52,6 +55,9 @@ def write(self, buf): class ConsoleWindows: + _USE_RAW_OUTPUT = None + _CONSOLE_CP_UTF8_SET = False + KEY_MAP = { b"H": b"A", # UP b"P": b"B", # DOWN @@ -82,6 +88,19 @@ class ConsoleWindows: def __init__(self): self.ctrl_c = 0 + self._use_raw_output = ConsoleWindows._USE_RAW_OUTPUT + if self._use_raw_output is None: + self._use_raw_output = ConsoleWindows._detect_modern_console(sys.stdout) + if self._use_raw_output: + # Modern console: write raw UTF-8 bytes like POSIX + self.outfile = sys.stdout.buffer + if hasattr(self.outfile, "raw"): + self.outfile = self.outfile.raw + # Ensure console interprets output as UTF-8 + ConsoleWindows._ensure_console_output_utf8() + else: + # Legacy console: use incremental decoder to handle split UTF-8 sequences + self._decoder = codecs.getincrementaldecoder("utf-8")(errors="replace") def _sigint_handler(self, signo, frame): self.ctrl_c += 1 @@ -116,61 +135,135 @@ def readchar(self): return ch def write(self, buf): - buf = buf.decode() if isinstance(buf, bytes) else buf - sys.stdout.write(buf) - sys.stdout.flush() - # for b in buf: - # if isinstance(b, bytes): - # msvcrt.putch(b) - # else: - # msvcrt.putwch(b) + if self._use_raw_output: + # Modern console: write raw UTF-8 bytes directly (like POSIX) + if isinstance(buf, str): + buf = buf.encode("utf-8") + self.outfile.write(buf) + self.outfile.flush() + else: + # Legacy console: use incremental decoder to handle split UTF-8 sequences + if isinstance(buf, bytes): + buf = self._decoder.decode(buf) + if buf: + sys.stdout.write(buf) + sys.stdout.flush() + @staticmethod + def enable_vt_mode(): + # Windows VT mode (>= win10 only) + # https://bugs.python.org/msg291732 + import ctypes + from ctypes import wintypes -if termios: - Console = ConsolePosix - VT_ENABLED = True -else: - Console = ConsoleWindows + kernel32 = ctypes.WinDLL("kernel32", use_last_error=True) + + ENABLE_VIRTUAL_TERMINAL_PROCESSING = 0x0004 + + def _check_bool(result, func, args): + if not result: + raise ctypes.WinError(ctypes.get_last_error()) + return args + + lpdword = ctypes.POINTER(wintypes.DWORD) + kernel32.GetConsoleMode.errcheck = _check_bool + kernel32.GetConsoleMode.argtypes = (wintypes.HANDLE, lpdword) + kernel32.SetConsoleMode.errcheck = _check_bool + kernel32.SetConsoleMode.argtypes = (wintypes.HANDLE, wintypes.DWORD) + + def set_conout_mode(new_mode, mask=0xFFFFFFFF): + # Don't assume StandardOutput is a console. + # Open CONOUT$ instead. + fdout = os.open("CONOUT$", os.O_RDWR) + try: + hout = msvcrt.get_osfhandle(fdout) + old_mode = wintypes.DWORD() + kernel32.GetConsoleMode(hout, ctypes.byref(old_mode)) + mode = (new_mode & mask) | (old_mode.value & ~mask) + kernel32.SetConsoleMode(hout, mode) + return old_mode.value + finally: + os.close(fdout) + + mode = mask = ENABLE_VIRTUAL_TERMINAL_PROCESSING + try: + set_conout_mode(mode, mask) + return True + except WindowsError: + return False - # Windows VT mode ( >= win10 only) - # https://bugs.python.org/msg291732 - import ctypes, os - from ctypes import wintypes + @classmethod + def configure_unicode_output(cls): + """Configure stdout/stderr for Unicode support on Windows legacy consoles.""" + if sys.platform != "win32": + return - kernel32 = ctypes.WinDLL("kernel32", use_last_error=True) + # Cache the modern-console detection result for ConsoleWindows. + if cls._USE_RAW_OUTPUT is None: + cls._USE_RAW_OUTPUT = cls._detect_modern_console(sys.stdout) - ERROR_INVALID_PARAMETER = 0x0057 - ENABLE_VIRTUAL_TERMINAL_PROCESSING = 0x0004 + # Set console output code page to UTF-8 for raw byte output. + cls._ensure_console_output_utf8() - def _check_bool(result, func, args): - if not result: - raise ctypes.WinError(ctypes.get_last_error()) - return args + # Full Unicode encodings that don't need fixing. + unicode_encodings = {"utf-8", "utf-16", "utf-16-le", "utf-16-be", "utf-32"} - LPDWORD = ctypes.POINTER(wintypes.DWORD) - kernel32.GetConsoleMode.errcheck = _check_bool - kernel32.GetConsoleMode.argtypes = (wintypes.HANDLE, LPDWORD) - kernel32.SetConsoleMode.errcheck = _check_bool - kernel32.SetConsoleMode.argtypes = (wintypes.HANDLE, wintypes.DWORD) + for stream_name in ("stdout", "stderr"): + stream = getattr(sys, stream_name, None) + if stream is None or not hasattr(stream, "encoding"): + continue - def set_conout_mode(new_mode, mask=0xFFFFFFFF): - # don't assume StandardOutput is a console. - # open CONOUT$ instead - fdout = os.open("CONOUT$", os.O_RDWR) + encoding = (stream.encoding or "").lower().replace("_", "-") + + # Skip if already a full Unicode encoding. + if encoding in unicode_encodings: + continue + + # Reconfigure with UTF-8 and error handling for limited encodings. + if hasattr(stream, "buffer"): + wrapped = io.TextIOWrapper( + stream.buffer, + encoding="utf-8", + errors="backslashreplace", + ) + setattr(sys, stream_name, wrapped) + + @staticmethod + def _detect_modern_console(stream): + """Detect if running in a modern Windows console that supports raw UTF-8.""" + # Windows Terminal + if os.environ.get("WT_SESSION"): + return True + # VS Code integrated terminal + if os.environ.get("TERM_PROGRAM") == "vscode": + return True + # ConEmu/Cmder + if os.environ.get("ConEmuANSI") == "ON": + return True + + encoding = getattr(stream, "encoding", None) + if encoding: + encoding = encoding.lower().replace("_", "-") + if encoding in ("utf-8", "utf8"): + return True + return False + + @classmethod + def _ensure_console_output_utf8(cls): + if cls._CONSOLE_CP_UTF8_SET: + return try: - hout = msvcrt.get_osfhandle(fdout) - old_mode = wintypes.DWORD() - kernel32.GetConsoleMode(hout, ctypes.byref(old_mode)) - mode = (new_mode & mask) | (old_mode.value & ~mask) - kernel32.SetConsoleMode(hout, mode) - return old_mode.value - finally: - os.close(fdout) - - # def enable_vt_mode(): - mode = mask = ENABLE_VIRTUAL_TERMINAL_PROCESSING - try: - set_conout_mode(mode, mask) - VT_ENABLED = True - except WindowsError: - VT_ENABLED = False + import ctypes + + ctypes.windll.kernel32.SetConsoleOutputCP(65001) + except Exception: + pass + cls._CONSOLE_CP_UTF8_SET = True + + +if termios: + Console = ConsolePosix + VT_ENABLED = True +else: + Console = ConsoleWindows + VT_ENABLED = ConsoleWindows.enable_vt_mode() diff --git a/tools/mpremote/mpremote/main.py b/tools/mpremote/mpremote/main.py index 123246928ae..e0edba69330 100644 --- a/tools/mpremote/mpremote/main.py +++ b/tools/mpremote/mpremote/main.py @@ -559,6 +559,13 @@ def ensure_friendly_repl(self): def main(): + if sys.platform == "win32": + # Configure stdout/stderr before any imports that might print: on some Windows + # consoles the default code page/encoding can't represent all Unicode. + from .console import ConsoleWindows + + ConsoleWindows.configure_unicode_output() + config = load_user_config() prepare_command_expansions(config) diff --git a/tools/mpremote/mpremote/transport.py b/tools/mpremote/mpremote/transport.py index 6ef0ea2a0af..4aa17b1dbfb 100644 --- a/tools/mpremote/mpremote/transport.py +++ b/tools/mpremote/mpremote/transport.py @@ -29,14 +29,59 @@ from .mp_errno import MP_ERRNO_TABLE -def stdout_write_bytes(b): +# Buffer for accumulating bytes that may be split UTF-8 sequences +_stdout_buffer = b"" + + +def stdout_write_bytes(b: bytes): + """Write bytes to stdout, handling UTF-8 encoding and buffering incomplete sequences. + + Strips CTRL-D (0x04) bytes and buffers incomplete UTF-8 sequences across calls. + Uses binary mode with sequence validation when available, otherwise decodes + with replacement characters for invalid sequences. + """ + global _stdout_buffer b = b.replace(b"\x04", b"") + if not b: + return + + _stdout_buffer += b + if hasattr(sys.stdout, "buffer"): - sys.stdout.buffer.write(b) - sys.stdout.buffer.flush() + # Try to decode to find complete UTF-8 sequences + # Write only complete sequences, keep incomplete trailing bytes buffered + try: + # Try to decode the entire buffer + _stdout_buffer.decode("utf-8") + # Success - all bytes form valid UTF-8, write them all + sys.stdout.buffer.write(_stdout_buffer) + sys.stdout.buffer.flush() + _stdout_buffer = b"" + except UnicodeDecodeError as e: + # Check if error is at the end (incomplete sequence) vs middle (invalid) + if e.start == 0 and e.reason == "unexpected end of data": + # Starts with incomplete sequence - keep buffering + pass + elif e.start > 0: + # Write valid prefix, keep incomplete/invalid suffix + valid_bytes = _stdout_buffer[: e.start] + sys.stdout.buffer.write(valid_bytes) + sys.stdout.buffer.flush() + _stdout_buffer = _stdout_buffer[e.start :] + # If remaining is just incomplete trailing bytes, keep them + # If it's invalid, write with replacement + if len(_stdout_buffer) > 4: # Max UTF-8 sequence is 4 bytes + sys.stdout.buffer.write(_stdout_buffer[:1]) + _stdout_buffer = _stdout_buffer[1:] + else: + # Invalid sequence at start - write one byte and continue + sys.stdout.buffer.write(_stdout_buffer[:1]) + sys.stdout.buffer.flush() + _stdout_buffer = _stdout_buffer[1:] else: - text = b.decode(sys.stdout.encoding, "strict") + text = _stdout_buffer.decode(sys.stdout.encoding, "replace") sys.stdout.write(text) + _stdout_buffer = b"" class TransportError(Exception): From a5548fb97b5c6049940c59b7df258b08ae3ce6c1 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Tue, 21 Jul 2026 20:51:15 +0200 Subject: [PATCH 515/635] tools/mpremote: Convert string input to bytes in wr_bytes method. RemoteCommand.wr_bytes(): Now correctly encodes strings to UTF-8 bytes before calculating length. Based on the suggestion by @felixdoer Fixes issue #13055. Signed-off-by: Jos Verlinde --- tools/mpremote/mpremote/transport_serial.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/mpremote/mpremote/transport_serial.py b/tools/mpremote/mpremote/transport_serial.py index ab70982b646..75e1cd6830c 100644 --- a/tools/mpremote/mpremote/transport_serial.py +++ b/tools/mpremote/mpremote/transport_serial.py @@ -552,6 +552,8 @@ def wr_s32(self, i): self.fout.write(self.buf4) def wr_bytes(self, b): + if isinstance(b, str): + b = bytes(b, "utf8") self.wr_s32(self.buffer_nbytes(b)) self.fout.write(b) From be787b8cb7572b0dfd5d58bcbfef98ab72d6bd19 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Tue, 21 Jul 2026 20:51:15 +0200 Subject: [PATCH 516/635] tools/mpremote/tests: Add `-t device` and skip functionality. Signed-off-by: Jos Verlinde --- tools/mpremote/tests/README.md | 27 ++++++++- tools/mpremote/tests/run-mpremote-tests.sh | 70 +++++++++++++++++++++- 2 files changed, 92 insertions(+), 5 deletions(-) diff --git a/tools/mpremote/tests/README.md b/tools/mpremote/tests/README.md index a437e554da8..353f7ad907c 100644 --- a/tools/mpremote/tests/README.md +++ b/tools/mpremote/tests/README.md @@ -25,5 +25,28 @@ To run a single test do: $ ./run-mpremote-tests.sh ./test_filesystem.sh -Each test should print "OK" if it passed. Otherwise it will print "CRASH", or "FAIL" -and a diff of the expected and actual test output. +To run tests against a specific device: + + $ ./run-mpremote-tests.sh -t /dev/ttyACM0 + $ ./run-mpremote-tests.sh -t rfc2217://localhost:2217 + +Device shortcuts are supported: `a0` → `/dev/ttyACM0`, `u0` → `/dev/ttyUSB0`, `c0` → `COM0`. + +Each test should print "OK" if it passed. Otherwise it will print "CRASH", "FAIL" +(with a diff of expected vs actual output), or "skip" if the test was skipped. + +## Skipping Tests + +Tests can skip themselves by outputting `SKIP` on a line by itself and exiting with +code 0. This is useful when a test is not applicable to a particular device or +configuration. + +Example in a test script: +```bash +if [[ "${MPREMOTE_DEVICE}" == rfc2217://* ]]; then + echo "SKIP" + exit 0 +fi +``` + +The `MPREMOTE_DEVICE` environment variable contains the device path passed via `-t`. diff --git a/tools/mpremote/tests/run-mpremote-tests.sh b/tools/mpremote/tests/run-mpremote-tests.sh index b25b5fd7d29..303932b09c5 100755 --- a/tools/mpremote/tests/run-mpremote-tests.sh +++ b/tools/mpremote/tests/run-mpremote-tests.sh @@ -4,20 +4,84 @@ set -e TEST_DIR=$(dirname $0) MPREMOTE=${TEST_DIR}/../mpremote.py +# Parse command line options +DEVICE="" +TESTS="" + +show_help() { + echo "Usage: $(basename $0) [-t ] [test_file.sh ...]" + echo "" + echo "Run mpremote tests against a MicroPython target." + echo "" + echo "Options:" + echo " -t Test instance/device to connect to. Examples:" + echo " -t a0 Connect to /dev/ttyACM0" + echo " -t u0 Connect to /dev/ttyUSB0" + echo " -t c0 Connect to COM0" + echo " -t /dev/ttyACM0 Connect to specified serial port" + echo " -t rfc2217://host:port Connect via RFC2217" + echo " If not specified, uses mpremote's auto-detection." + echo " -h Show this help message" + echo "" + echo "Arguments:" + echo " test_file.sh Specific test file(s) to run. If not specified," + echo " all test_*.sh files in the tests directory are run." + exit 0 +} + +while getopts "t:h" opt; do + case $opt in + t) + DEVICE="$OPTARG" + ;; + h) + show_help + ;; + \?) + echo "Invalid option: -$OPTARG" >&2 + exit 1 + ;; + esac +done +shift $((OPTIND-1)) + +# Convert device shortcuts to full paths (similar to run-tests.py) +if [ -n "$DEVICE" ]; then + case "$DEVICE" in + a[0-9]*) + DEVICE="/dev/ttyACM${DEVICE#a}" + ;; + u[0-9]*) + DEVICE="/dev/ttyUSB${DEVICE#u}" + ;; + c[0-9]*) + DEVICE="COM${DEVICE#c}" + ;; + esac + # Set MPREMOTE_DEVICE for tests to use + export MPREMOTE_DEVICE="$DEVICE" + # Update MPREMOTE to include connect command + MPREMOTE="${MPREMOTE} connect ${DEVICE}" + echo "Using device: $DEVICE" +fi + if [ -z "$1" ]; then # Find tests matching test_*.sh TESTS=${TEST_DIR}/test_*.sh else # Specific test path from the command line. - TESTS="$1" + TESTS="$@" fi for t in $TESTS; do TMP=$(mktemp -d) echo -n "${t}: " # Strip CR and replace the random temp dir with a token. - if env MPREMOTE=${MPREMOTE} TMP="${TMP}" "${t}" 2>&1 | tr -d '\r' | sed "s,${TMP},"'${TMP},g' > "${t}.out"; then - if diff "${t}.out" "${t}.exp" > /dev/null; then + if env MPREMOTE="${MPREMOTE}" TMP="${TMP}" MPREMOTE_DEVICE="${DEVICE}" "${t}" 2>&1 | tr -d '\r' | sed "s,${TMP},"'${TMP},g' > "${t}.out"; then + # Check if test was skipped (matches main test runner convention) + if grep -q "^SKIP$" "${t}.out"; then + echo "skip" + elif diff "${t}.out" "${t}.exp" > /dev/null; then echo "OK" else echo "FAIL" From 9a2ba6c3599a9c6fb0fb1d8f5e74db75a1169e08 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Tue, 21 Jul 2026 20:51:15 +0200 Subject: [PATCH 517/635] tools/mpremote/tests: Use a shared ramdisk script across tests. Reduces code duplication while allowing different configurations. Signed-off-by: Jos Verlinde --- tools/mpremote/tests/README.md | 16 ++++++ tools/mpremote/tests/ramdisk.py | 56 +++++++++++++++++++ tools/mpremote/tests/test_filesystem.sh | 56 +++++-------------- tools/mpremote/tests/test_fs_tree.sh | 33 +---------- .../mpremote/tests/test_mip_local_install.sh | 35 ++---------- 5 files changed, 93 insertions(+), 103 deletions(-) create mode 100644 tools/mpremote/tests/ramdisk.py diff --git a/tools/mpremote/tests/README.md b/tools/mpremote/tests/README.md index 353f7ad907c..ad27b9eec37 100644 --- a/tools/mpremote/tests/README.md +++ b/tools/mpremote/tests/README.md @@ -50,3 +50,19 @@ fi ``` The `MPREMOTE_DEVICE` environment variable contains the device path passed via `-t`. + +## Using the RAM Disk + +Tests that need a writable filesystem can use `ramdisk.py` to create a temporary +FAT filesystem in RAM: + +```bash +TEST_DIR=$(dirname $0) +$MPREMOTE run "${TEST_DIR}/ramdisk.py" +``` +Defaults to: block_size=512, num_blocks=50, mount_path='/ramdisk', do_chdir=True +Custom parameters can be passed via `exec`: + +```bash +$MPREMOTE exec "mount_path='/__ramdisk'; do_chdir=False" run "${TEST_DIR}/ramdisk.py" +``` diff --git a/tools/mpremote/tests/ramdisk.py b/tools/mpremote/tests/ramdisk.py new file mode 100644 index 00000000000..da65da20ab9 --- /dev/null +++ b/tools/mpremote/tests/ramdisk.py @@ -0,0 +1,56 @@ +# Creates a RAM disk for testing. +# Usage: mpremote run ramdisk.py +# Or with custom parameters: +# mpremote exec "block_size=1024; num_blocks=100; mount_path='/myram'" run ramdisk.py +# mpremote exec "mount_path='/__ramdisk'; do_chdir=False" run ramdisk.py +# Defaults: block_size=512, num_blocks=50, mount_path='/ramdisk', do_chdir=True + +import os + + +class RAMBlockDev: + def __init__(self, block_size, num_blocks): + self.block_size = block_size + self.data = bytearray(block_size * num_blocks) + + def readblocks(self, block_num, buf): + for i in range(len(buf)): + buf[i] = self.data[block_num * self.block_size + i] + + def writeblocks(self, block_num, buf): + for i in range(len(buf)): + self.data[block_num * self.block_size + i] = buf[i] + + def ioctl(self, op, arg): + if op == 4: # get number of blocks + return len(self.data) // self.block_size + if op == 5: # get block size + return self.block_size + + +# Use globals if set via exec, otherwise use defaults +try: + block_size +except NameError: + block_size = 512 + +try: + num_blocks +except NameError: + num_blocks = 50 + +try: + mount_path +except NameError: + mount_path = "/ramdisk" + +try: + do_chdir +except NameError: + do_chdir = True + +bdev = RAMBlockDev(block_size, num_blocks) +os.VfsFat.mkfs(bdev) +os.mount(bdev, mount_path) +if do_chdir: + os.chdir(mount_path) diff --git a/tools/mpremote/tests/test_filesystem.sh b/tools/mpremote/tests/test_filesystem.sh index 13c5394f71c..4bd43acf390 100755 --- a/tools/mpremote/tests/test_filesystem.sh +++ b/tools/mpremote/tests/test_filesystem.sh @@ -1,39 +1,11 @@ #!/bin/bash set -e -# Creates a RAM disk big enough to hold two copies of the test directory -# structure. -cat << EOF > "${TMP}/ramdisk.py" -class RAMBlockDev: - def __init__(self, block_size, num_blocks): - self.block_size = block_size - self.data = bytearray(block_size * num_blocks) - - def readblocks(self, block_num, buf): - for i in range(len(buf)): - buf[i] = self.data[block_num * self.block_size + i] - - def writeblocks(self, block_num, buf): - for i in range(len(buf)): - self.data[block_num * self.block_size + i] = buf[i] - - def ioctl(self, op, arg): - if op == 4: # get number of blocks - return len(self.data) // self.block_size - if op == 5: # get block size - return self.block_size - -import os - -bdev = RAMBlockDev(512, 50) -os.VfsFat.mkfs(bdev) -os.mount(bdev, '/ramdisk') -os.chdir('/ramdisk') -EOF - +# Get the test directory (where this script and ramdisk.py are located) +TEST_DIR=$(dirname $0) echo ----- -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume ls echo ----- @@ -108,7 +80,7 @@ cat << EOF > "${TMP}/package/subpackage/y.py" def y(): print("y") EOF -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume cp -r "${TMP}/package" : $MPREMOTE resume ls : :package :package/subpackage $MPREMOTE resume exec "import package; package.x(); package.y()" @@ -116,7 +88,7 @@ $MPREMOTE resume exec "import package; package.x(); package.y()" # Same thing except with a destination directory name. echo ----- -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume cp -r "${TMP}/package" :package2 $MPREMOTE resume ls : :package2 :package2/subpackage $MPREMOTE resume exec "import package2; package2.x(); package2.y()" @@ -124,7 +96,7 @@ $MPREMOTE resume exec "import package2; package2.x(); package2.y()" # Copy to an existing directory, it will be copied inside. echo ----- -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume mkdir :test $MPREMOTE resume cp -r "${TMP}/package" :test $MPREMOTE resume ls :test :test/package :test/package/subpackage @@ -148,14 +120,14 @@ ls "${TMP}/copy" "${TMP}/copy/package2" "${TMP}/copy/package2/subpackage" # Copy from device to another location on the device with destination directory name. echo ----- -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume cp -r "${TMP}/package" : $MPREMOTE resume cp -r :package :package3 $MPREMOTE resume ls : :package3 :package3/subpackage # Copy from device to another location on the device into an existing directory. echo ----- -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume cp -r "${TMP}/package" : $MPREMOTE resume mkdir :package4 $MPREMOTE resume cp -r :package :package4 @@ -175,7 +147,7 @@ echo ----- # Test rm -r functionality # start with a fresh ramdisk before each test # rm -r MCU current working directory -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume touch :a.py $MPREMOTE resume touch :b.py $MPREMOTE resume cp -r "${TMP}/package" : @@ -185,7 +157,7 @@ $MPREMOTE resume ls :/ramdisk echo ----- # rm -r relative subfolder -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume touch :a.py $MPREMOTE resume mkdir :testdir $MPREMOTE resume cp -r "${TMP}/package" :testdir/package @@ -197,14 +169,14 @@ $MPREMOTE resume ls :testdir echo ----- # rm -r non-existent path -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume ls : $MPREMOTE resume rm -r :nonexistent || echo "expect error" echo ----- # rm -r absolute root # no -v to generate same output on stm32 and other ports -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume touch :a.py $MPREMOTE resume touch :b.py $MPREMOTE resume cp -r "${TMP}/package" : @@ -215,7 +187,7 @@ $MPREMOTE resume ls :/ramdisk echo ----- # rm -r relative mountpoint -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume touch :a.py $MPREMOTE resume touch :b.py $MPREMOTE resume cp -r "${TMP}/package" : @@ -225,7 +197,7 @@ $MPREMOTE resume ls :/ramdisk echo ----- # rm -r absolute mountpoint -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume touch :a.py $MPREMOTE resume touch :b.py $MPREMOTE resume cp -r "${TMP}/package" : diff --git a/tools/mpremote/tests/test_fs_tree.sh b/tools/mpremote/tests/test_fs_tree.sh index d7fc433ae6a..925079ddadb 100755 --- a/tools/mpremote/tests/test_fs_tree.sh +++ b/tools/mpremote/tests/test_fs_tree.sh @@ -1,39 +1,12 @@ #!/bin/bash set -e -# Creates a RAM disk big enough to hold two copies of the test directory -# structure. -cat << EOF > "${TMP}/ramdisk.py" -class RAMBlockDev: - def __init__(self, block_size, num_blocks): - self.block_size = block_size - self.data = bytearray(block_size * num_blocks) - - def readblocks(self, block_num, buf): - for i in range(len(buf)): - buf[i] = self.data[block_num * self.block_size + i] - - def writeblocks(self, block_num, buf): - for i in range(len(buf)): - self.data[block_num * self.block_size + i] = buf[i] - - def ioctl(self, op, arg): - if op == 4: # get number of blocks - return len(self.data) // self.block_size - if op == 5: # get block size - return self.block_size - -import os - -bdev = RAMBlockDev(512, 50) -os.VfsFat.mkfs(bdev) -os.mount(bdev, '/ramdisk') -os.chdir('/ramdisk') -EOF +# Get the test directory (where this script and ramdisk.py are located) +TEST_DIR=$(dirname $0) # setup echo ----- -$MPREMOTE run "${TMP}/ramdisk.py" +$MPREMOTE run "${TEST_DIR}/ramdisk.py" $MPREMOTE resume ls echo ----- diff --git a/tools/mpremote/tests/test_mip_local_install.sh b/tools/mpremote/tests/test_mip_local_install.sh index fb8c597bd14..44c29b0f2b6 100755 --- a/tools/mpremote/tests/test_mip_local_install.sh +++ b/tools/mpremote/tests/test_mip_local_install.sh @@ -10,37 +10,10 @@ PACKAGE=mip_example PACKAGE_DIR=${TMP}/example MODULE_DIR=${PACKAGE_DIR}/${PACKAGE} -target=/__ramdisk -block_size=512 -num_blocks=50 - -# Create the smallest permissible ramdisk. -cat << EOF > "${TMP}/ramdisk.py" -class RAMBlockDev: - def __init__(self, block_size, num_blocks): - self.block_size = block_size - self.data = bytearray(block_size * num_blocks) - - def readblocks(self, block_num, buf): - for i in range(len(buf)): - buf[i] = self.data[block_num * self.block_size + i] - - def writeblocks(self, block_num, buf): - for i in range(len(buf)): - self.data[block_num * self.block_size + i] = buf[i] +# Get the test directory (where this script and ramdisk.py are located) +TEST_DIR=$(dirname $0) - def ioctl(self, op, arg): - if op == 4: # get number of blocks - return len(self.data) // self.block_size - if op == 5: # get block size - return self.block_size - -import os - -bdev = RAMBlockDev(${block_size}, ${num_blocks}) -os.VfsFat.mkfs(bdev) -os.mount(bdev, '${target}') -EOF +target=/__ramdisk echo ----- Setup mkdir -p ${MODULE_DIR} @@ -56,7 +29,7 @@ cat > ${PACKAGE_DIR}/package.json < Date: Tue, 21 Jul 2026 20:51:15 +0200 Subject: [PATCH 518/635] tools/mpremote/tests: Add test for unicode fixes. Add regressions tests for utf-8 and unicode. Signed-off-by: Jos Verlinde --- tools/mpremote/tests/test_unicode.sh | 74 ++++++++++++++++++++++++ tools/mpremote/tests/test_unicode.sh.exp | 33 +++++++++++ 2 files changed, 107 insertions(+) create mode 100755 tools/mpremote/tests/test_unicode.sh create mode 100644 tools/mpremote/tests/test_unicode.sh.exp diff --git a/tools/mpremote/tests/test_unicode.sh b/tools/mpremote/tests/test_unicode.sh new file mode 100755 index 00000000000..8bfaadb5dcb --- /dev/null +++ b/tools/mpremote/tests/test_unicode.sh @@ -0,0 +1,74 @@ +#!/bin/bash +set -e + +# Test Unicode and special character handling in mpremote. +# These tests cover: +# - Properly escaping quotes for commands (transport.py) +# - Command expansion handling `=` (main.py) +# - UTF-8 display and encoding fixes (console.py, transport.py) +# - wr_bytes string to bytes conversion (transport_serial.py) + +# Create a RAM disk for testing +# Get the test directory (where this script and ramdisk.py are located) +TEST_DIR=$(dirname $0) + +# Initialize ramdisk for file tests +$MPREMOTE run "${TEST_DIR}/ramdisk.py" + +echo ----- +# Test UTF-8 output via exec (tests stdout_write_bytes UTF-8 handling) +$MPREMOTE resume exec "print('Hello 世界')" +$MPREMOTE resume exec "print('Emoji: 🎉🐍')" +$MPREMOTE resume exec "print('Accents: café, naïve, résumé')" + +echo ----- +# Test Files with single quotes in names (tests _quote_path in transport.py) +$MPREMOTE resume touch ":quote'test.txt" +$MPREMOTE resume ls : +$MPREMOTE resume rm ":quote'test.txt" +$MPREMOTE resume ls : + +echo ----- +# Test Writing and reading UTF-8 content (tests transport and wr_bytes) +cat << EOF > "${TMP}/unicode_content.txt" +Hello 世界 +Emoji: 🎉🐍 +Café résumé naïve +EOF +$MPREMOTE resume cp "${TMP}/unicode_content.txt" : +$MPREMOTE resume cat :unicode_content.txt +$MPREMOTE resume sha256sum :unicode_content.txt +cat "${TMP}/unicode_content.txt" | sha256sum + +echo ----- +# This test writes UTF-8 content via mount and reads it back +# https://github.com/micropython/micropython/issues/13055 +cat << EOF > "${TMP}/write_utf_to_mounted.py" +with open("foo.txt", 'w', encoding='utf-8') as file: + file.write("🔢 Data" + '\n') + file.write("🔢 Data" + '\n') + +with open("foo.txt", 'r', encoding='utf-8') as file: + data = file.read() + print(data) +EOF +$MPREMOTE mount ${TMP} run "${TMP}/write_utf_to_mounted.py" + + +echo ----- +# Test Command expansion with `=` sign (tests main.py fix) +# The `=` in arguments should not cause errors +$MPREMOTE resume exec "x = 'a=b'; print(x)" + +echo ----- +# Test eval with Unicode strings +$MPREMOTE resume eval "'Hello 世界'" +$MPREMOTE resume eval "repr('日本語')" + +echo ----- +# Test UTF-8 display on Windows +# Testing mpremote on windows with bash is not straightforward, +# but we can at least run the command that was problematic. +$MPREMOTE resume exec "print('Hello World'); print('你好'); print('=' * 20)" + +echo ----- diff --git a/tools/mpremote/tests/test_unicode.sh.exp b/tools/mpremote/tests/test_unicode.sh.exp new file mode 100644 index 00000000000..826abf0df5d --- /dev/null +++ b/tools/mpremote/tests/test_unicode.sh.exp @@ -0,0 +1,33 @@ +----- +Hello 世界 +Emoji: 🎉🐍 +Accents: café, naïve, résumé +----- +touch :quote'test.txt +ls : + 0 quote'test.txt +rm :quote'test.txt +ls : +----- +cp ${TMP}/unicode_content.txt : +Hello 世界 +Emoji: 🎉🐍 +Café résumé naïve +sha256sum :unicode_content.txt +8f22a7c6092948ff41897b28dca429cd6a3de87a5bd6e113d24adf91f3cbeeac +8f22a7c6092948ff41897b28dca429cd6a3de87a5bd6e113d24adf91f3cbeeac - +----- +🔢 Data +🔢 Data + +Local directory ${TMP} is mounted at /remote +----- +a=b +----- +Hello 世界 +'日本語' +----- +Hello World +你好 +==================== +----- From 6a689d3e556b8773cdf6e43c8f6993dfed160b2e Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Thu, 23 Jul 2026 14:30:35 +0200 Subject: [PATCH 519/635] shared/runtime/softtimer: Fix undefined behaviour with a NULL heap. When soft_timer_heap is NULL the expression &soft_timer_heap->pairheap is undefined behaviour in both C and C++. This is harmless today only because pairheap is at offset 0, so the expression folds to NULL, but a struct reorder would corrupt the heap. The same pattern occurs in soft_timer_insert(), remove(), handler(), deinit() and gc_mark_all(). This patch fixes the UB by introducing a safe pairheap accessor that avoids the undefined behaviour of &e->pairheap when e is NULL, while guaranteeing that pairheap is always the first member, via static assert. Signed-off-by: iabdalkader --- shared/runtime/softtimer.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/shared/runtime/softtimer.c b/shared/runtime/softtimer.c index b154cd9d7b5..c2bfeef4ccf 100644 --- a/shared/runtime/softtimer.c +++ b/shared/runtime/softtimer.c @@ -25,6 +25,7 @@ */ #include +#include #include "py/gc.h" #include "py/mphal.h" #include "py/runtime.h" @@ -59,6 +60,11 @@ static void soft_timer_schedule_at_ms(uint32_t ticks_ms) { // and is explicitly GC traced by soft_timer_gc_mark_all(). static soft_timer_entry_t *soft_timer_heap; +// Safe pairheap accessor that avoids the undefined behaviour of +// &e->pairheap when e is NULL. Note this is valid only because +// pairheap is the first member (guaranteed by MP_STATIC_ASSERT). +#define SOFT_TIMER_HEAP(e) ((mp_pairheap_t *)(e)) + static int soft_timer_lt(mp_pairheap_t *n1, mp_pairheap_t *n2) { soft_timer_entry_t *e1 = (soft_timer_entry_t *)n1; soft_timer_entry_t *e2 = (soft_timer_entry_t *)n2; @@ -74,7 +80,7 @@ void soft_timer_deinit(void) { soft_timer_entry_t *entry = (soft_timer_entry_t *)mp_pairheap_peek(soft_timer_lt, &heap_from->pairheap); heap_from = (soft_timer_entry_t *)mp_pairheap_pop(soft_timer_lt, &heap_from->pairheap); if (!(entry->flags & SOFT_TIMER_FLAG_GC_ALLOCATED)) { - heap_to = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, &heap_to->pairheap, &entry->pairheap); + heap_to = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, SOFT_TIMER_HEAP(heap_to), &entry->pairheap); } } soft_timer_heap = heap_to; @@ -99,7 +105,7 @@ void soft_timer_handler(void) { } if (entry->mode == SOFT_TIMER_MODE_PERIODIC) { entry->expiry_ms += entry->delta_ms; - heap = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, &heap->pairheap, &entry->pairheap); + heap = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, SOFT_TIMER_HEAP(heap), &entry->pairheap); } } soft_timer_heap = heap; @@ -122,13 +128,17 @@ void soft_timer_gc_mark_all(void) { if (entry->flags & SOFT_TIMER_FLAG_GC_ALLOCATED) { gc_collect_root((void **)&entry, 1); } - heap_to = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, &heap_to->pairheap, &entry->pairheap); + heap_to = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, SOFT_TIMER_HEAP(heap_to), &entry->pairheap); } soft_timer_heap = heap_to; MICROPY_PY_PENDSV_EXIT; } void soft_timer_static_init(soft_timer_entry_t *entry, uint16_t mode, uint32_t delta_ms, void (*cb)(soft_timer_entry_t *)) { + // Ensure that pairheap is always the first member of soft_timer_entry_t + // to allow casting between pointers of soft_timer_entry_t and mp_pairheap_t. + MP_STATIC_ASSERT(offsetof(soft_timer_entry_t, pairheap) == 0); + mp_pairheap_init_node(soft_timer_lt, &entry->pairheap); entry->flags = 0; entry->mode = mode; @@ -140,7 +150,7 @@ void soft_timer_insert(soft_timer_entry_t *entry, uint32_t initial_delta_ms) { mp_pairheap_init_node(soft_timer_lt, &entry->pairheap); entry->expiry_ms = soft_timer_get_ms() + initial_delta_ms; MICROPY_PY_PENDSV_ENTER; - soft_timer_heap = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, &soft_timer_heap->pairheap, &entry->pairheap); + soft_timer_heap = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, SOFT_TIMER_HEAP(soft_timer_heap), &entry->pairheap); if (entry == soft_timer_heap) { // This new timer became the earliest one so schedule a callback. soft_timer_schedule_at_ms(entry->expiry_ms); @@ -150,6 +160,6 @@ void soft_timer_insert(soft_timer_entry_t *entry, uint32_t initial_delta_ms) { void soft_timer_remove(soft_timer_entry_t *entry) { MICROPY_PY_PENDSV_ENTER; - soft_timer_heap = (soft_timer_entry_t *)mp_pairheap_delete(soft_timer_lt, &soft_timer_heap->pairheap, &entry->pairheap); + soft_timer_heap = (soft_timer_entry_t *)mp_pairheap_delete(soft_timer_lt, SOFT_TIMER_HEAP(soft_timer_heap), &entry->pairheap); MICROPY_PY_PENDSV_EXIT; } From a53a0db0d6885057d2eafabc0809c2d9c7accf91 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Fri, 23 Aug 2024 09:30:33 +0200 Subject: [PATCH 520/635] esp32/modmachine: Export machine_bootloader_rtc(). Make the function machine_bootloader_rtc() available to other modules by declaring it in mpconfigport.h, when selected via its #define. This is needed for the Arduino Nano ESP32 board to be able to call this function from the board_init.c file. Signed-off-by: Luca Burelli --- ports/esp32/modmachine.c | 2 +- ports/esp32/modmachine.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/ports/esp32/modmachine.c b/ports/esp32/modmachine.c index 968e64123c0..5fb9bf8f518 100644 --- a/ports/esp32/modmachine.c +++ b/ports/esp32/modmachine.c @@ -272,7 +272,7 @@ static mp_int_t mp_machine_reset_cause(void) { #include "esp32s3/rom/usb/chip_usb_dw_wrapper.h" #endif -MP_NORETURN static void machine_bootloader_rtc(void) { +MP_NORETURN void machine_bootloader_rtc(void) { #if CONFIG_IDF_TARGET_ESP32S3 && MICROPY_HW_USB_CDC usb_usj_mode(); usb_dc_prepare_persist(); diff --git a/ports/esp32/modmachine.h b/ports/esp32/modmachine.h index af58f5f1052..61b6633e349 100644 --- a/ports/esp32/modmachine.h +++ b/ports/esp32/modmachine.h @@ -21,4 +21,8 @@ void machine_pwm_deinit_all(void); void machine_uart_deinit_all(void); void machine_i2s_init0(); +#ifdef MICROPY_ESP32_USE_BOOTLOADER_RTC +void machine_bootloader_rtc(void); +#endif + #endif // MICROPY_INCLUDED_ESP32_MODMACHINE_H From 5aaa6d1751ab064a98a762d7d32a2f4071840770 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Thu, 22 Aug 2024 11:53:25 +0200 Subject: [PATCH 521/635] esp32/boards/ARDUINO_NANO_ESP32: Optionally use hardware bootloader. The custom machine.bootloader() function in the Nano ESP32 board currently calls the Arduino bootloader to allow DFU updates on the board. However there are situations where the hardware bootloader may still be useful, for example when a full flash is required. Make it so calling `machine.bootloader(1)` will fallback to the default bootloader; anything else will result in the one by Arduino being started. Signed-off-by: Luca Burelli --- ports/esp32/boards/ARDUINO_NANO_ESP32/board_init.c | 11 +++++++++-- ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h | 10 ++++++++-- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/ports/esp32/boards/ARDUINO_NANO_ESP32/board_init.c b/ports/esp32/boards/ARDUINO_NANO_ESP32/board_init.c index 3394bb1e2e2..19e3b99ec2a 100644 --- a/ports/esp32/boards/ARDUINO_NANO_ESP32/board_init.c +++ b/ports/esp32/boards/ARDUINO_NANO_ESP32/board_init.c @@ -27,6 +27,7 @@ #include #include "py/mphal.h" #include "shared/tinyusb/mp_usbd_cdc.h" +#include "modmachine.h" #include #include @@ -66,7 +67,13 @@ static void rgb_pulse_delay() { mp_hal_pin_write(LED_BLUE, 1); } -void NANO_ESP32_enter_bootloader(void) { +NORETURN void NANO_ESP32_enter_bootloader(size_t n_args, const void *args) { + mp_int_t mode; + if (n_args == 1 && mp_obj_get_int_maybe(*(const mp_obj_t *)args, &mode) && mode == 1) { + // jump to hardware bootloader (does not return) + machine_bootloader_rtc(); + } + if (!_recovery_active) { // check for valid partition scheme const esp_partition_t *ota_part = esp_ota_get_next_update_partition(NULL); @@ -104,7 +111,7 @@ void NANO_ESP32_board_startup(void) { _recovery_marker_found = double_tap_check_match(); if (_recovery_marker_found && !_recovery_active) { // double tap detected in user application, reboot to factory - NANO_ESP32_enter_bootloader(); + NANO_ESP32_enter_bootloader(0, NULL); } // delay with mark set then proceed diff --git a/ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h b/ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h index 855040b3cd9..e9d42438b9e 100644 --- a/ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h +++ b/ports/esp32/boards/ARDUINO_NANO_ESP32/mpconfigboard.h @@ -1,3 +1,5 @@ +#include // for size_t + #define MICROPY_HW_BOARD_NAME "Arduino Nano ESP32" #define MICROPY_HW_MCU_NAME "ESP32-S3" @@ -27,8 +29,12 @@ #define MICROPY_HW_USB_MANUFACTURER_STRING "Arduino" #define MICROPY_HW_USB_PRODUCT_FS_STRING "Nano ESP32" +// Custom bootloader function may fall back to the default one +#define MICROPY_ESP32_USE_BOOTLOADER_RTC (1) + #define MICROPY_BOARD_STARTUP NANO_ESP32_board_startup void NANO_ESP32_board_startup(void); -#define MICROPY_BOARD_ENTER_BOOTLOADER(nargs, args) NANO_ESP32_enter_bootloader() -void NANO_ESP32_enter_bootloader(void); +// args is an array of mp_obj_t, but that type isn't yet defined when this file is parsed +#define MICROPY_BOARD_ENTER_BOOTLOADER(nargs, args) NANO_ESP32_enter_bootloader(nargs, args) +void NANO_ESP32_enter_bootloader(size_t n_args, const void *args); From e238a8d1a612dad0de2636df77b17919efd54532 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 10 Jul 2026 14:25:52 +1000 Subject: [PATCH 522/635] tests/unicode: Split out unicode f-string test to separate file. So it can be skipped if the target has unicode enabled but doesn't support f-strings. For example ADAFRUIT_ITSYBITSY_M0_EXPRESS. Signed-off-by: Damien George --- tests/run-tests.py | 2 +- tests/unicode/unicode_char_format.py | 6 ------ tests/unicode/unicode_char_format_fstring.py | 6 ++++++ 3 files changed, 7 insertions(+), 7 deletions(-) create mode 100644 tests/unicode/unicode_char_format_fstring.py diff --git a/tests/run-tests.py b/tests/run-tests.py index 459ef693f20..593f82c0b6e 100755 --- a/tests/run-tests.py +++ b/tests/run-tests.py @@ -987,7 +987,7 @@ def run_one_test(test_file): is_slice = test_name.find("slice") != -1 is_async = test_name.startswith(("async_", "asyncio_")) or test_name.endswith("_async") is_const = test_name.startswith("const") - is_fstring = test_name.startswith("string_fstring") + is_fstring = test_name.startswith("string_fstring") or test_name.endswith("_fstring") is_tstring = test_name.startswith("string_tstring") or test_name.endswith("_tstring") is_inlineasm = test_name.startswith("asm") diff --git a/tests/unicode/unicode_char_format.py b/tests/unicode/unicode_char_format.py index 937806a6ae6..3d56ae92afa 100644 --- a/tests/unicode/unicode_char_format.py +++ b/tests/unicode/unicode_char_format.py @@ -22,12 +22,6 @@ print("{:c}".format(0x4E00)) print("{:c}{:c}".format(0x3BC, 0x1F40D)) -# test with f-strings -c = 169 -print(f"{c:c}") -c = 0x1F600 -print(f"{c:c}") - # Test boundary values - valid maximum unicode codepoint print("%c" % 0x10FFFF) # Last valid unicode codepoint diff --git a/tests/unicode/unicode_char_format_fstring.py b/tests/unicode/unicode_char_format_fstring.py new file mode 100644 index 00000000000..9dac1052e07 --- /dev/null +++ b/tests/unicode/unicode_char_format_fstring.py @@ -0,0 +1,6 @@ +# test %c formatting with unicode characters in f-strings + +c = 169 +print(f"{c:c}") +c = 0x1F600 +print(f"{c:c}") From 22642720a028aafce762b983ed5792ae1aa33ee4 Mon Sep 17 00:00:00 2001 From: Damien George Date: Sat, 11 Jul 2026 12:06:51 +1000 Subject: [PATCH 523/635] tests/run-multitests.py: Fix location of extmod for MICROPYPATH. Tests are run from within their directory, so extmod is actually two levels up, not one. Use `base_path()` to get the correct value, following how it's done in `run-tests.py`. Signed-off-by: Damien George --- tests/run-multitests.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/run-multitests.py b/tests/run-multitests.py index 40aac16c16f..de59db2dc38 100755 --- a/tests/run-multitests.py +++ b/tests/run-multitests.py @@ -598,7 +598,7 @@ def main(): cmd_args = cmd_parser.parse_args() # clear search path to make sure tests use only builtin modules and those in extmod - os.environ["MICROPYPATH"] = os.pathsep.join((".frozen", "../extmod")) + os.environ["MICROPYPATH"] = os.pathsep.join((".frozen", base_path("../extmod"))) test_files = prepare_test_file_list(cmd_args.files) max_instances = max(t[1] for t in test_files) From 4a40f5328e59bc5cf1bd210689fed30d809c48cd Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 24 Jul 2026 12:51:44 +1000 Subject: [PATCH 524/635] tests/net_inet: Use "ascii" encoding for HTTP Host. Instead of "latin" which is unsupported, and now an error since commit 770bb3b79b0df0b23f93ac9ccc0474f31a6ad650 Signed-off-by: Damien George --- tests/net_inet/test_tls_nonblock.py | 2 +- tests/net_inet/test_tls_sites.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/net_inet/test_tls_nonblock.py b/tests/net_inet/test_tls_nonblock.py index 2825e3b5d13..1f2b3a899fa 100644 --- a/tests/net_inet/test_tls_nonblock.py +++ b/tests/net_inet/test_tls_nonblock.py @@ -61,7 +61,7 @@ def test_one(site, opts): # print("shook hands") # Write HTTP request - out = b"GET / HTTP/1.0\r\nHost: %s\r\n\r\n" % bytes(site, "latin") + out = b"GET / HTTP/1.0\r\nHost: %s\r\n\r\n" % bytes(site, "ascii") while len(out) > 0: n = s.write(out) if n is None: diff --git a/tests/net_inet/test_tls_sites.py b/tests/net_inet/test_tls_sites.py index 3637194ad79..2f4ea3ce079 100644 --- a/tests/net_inet/test_tls_sites.py +++ b/tests/net_inet/test_tls_sites.py @@ -37,7 +37,7 @@ def test_one(site, opts): else: s = ssl_context.wrap_socket(s) - s.write(b"GET / HTTP/1.0\r\nHost: %s\r\n\r\n" % bytes(site, "latin")) + s.write(b"GET / HTTP/1.0\r\nHost: %s\r\n\r\n" % bytes(site, "ascii")) resp = s.read(4096) if resp[:7] != b"HTTP/1.": raise ValueError("response doesn't start with HTTP/1.") From 7a61d7c2e0be61afe2073aa555ff840d36ae38d1 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Jul 2026 14:33:56 +1000 Subject: [PATCH 525/635] esp8266/Makefile: Specify --chip option to esptool. Newer versions of `esptool` (eg v5.2.0) require the `--chip` option to be specified. And older versions (eg v4.5) accept it, so this change is backwards compatible. Signed-off-by: Damien George --- ports/esp8266/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ports/esp8266/Makefile b/ports/esp8266/Makefile index 699d174f69d..cb1b131c6b4 100644 --- a/ports/esp8266/Makefile +++ b/ports/esp8266/Makefile @@ -196,18 +196,18 @@ FROZEN_EXTRA_DEPS = $(CONFVARS_FILE) deploy: $(FWBIN) $(ECHO) "Writing $< to the board" - $(Q)$(ESPTOOL) --port $(PORT) --baud $(BAUD) write_flash --flash_size=$(FLASH_SIZE) --flash_mode=$(FLASH_MODE) 0 $< + $(Q)$(ESPTOOL) --chip esp8266 --port $(PORT) --baud $(BAUD) write_flash --flash_size=$(FLASH_SIZE) --flash_mode=$(FLASH_MODE) 0 $< erase: $(ECHO) "Erase flash" - $(Q)$(ESPTOOL) --port $(PORT) --baud $(BAUD) erase_flash + $(Q)$(ESPTOOL) --chip esp8266 --port $(PORT) --baud $(BAUD) erase_flash reset: echo -e "\r\nimport machine; machine.reset()\r\n" >$(PORT) $(FWBIN): $(BUILD)/firmware.elf $(ECHO) "Create $@" - $(Q)$(ESPTOOL) elf2image $^ + $(Q)$(ESPTOOL) --chip esp8266 elf2image $^ $(Q)$(PYTHON) makeimg.py $(BUILD)/firmware.elf-0x00000.bin $(BUILD)/firmware.elf-0x[0-5][1-f]000.bin $@ $(BUILD)/firmware.elf: $(OBJ) From f6c7803d49a6dddb11bc91f7f6c47c4a3e6219fd Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 23 May 2026 13:18:41 +1000 Subject: [PATCH 526/635] tools/manifest: Add c_module() function for specifying user C modules. Add a new c_module() function to the manifest API that lets a manifest declare which user C module directories should be included in the build. This pairs with the build system changes that pick up the resulting paths and feed them into USER_C_MODULES. The function validates the path exists, is a directory, and contains a micropython.mk or micropython.cmake, and supports the usual \$(MPY_DIR), \$(BOARD_DIR), \$(PORT_DIR), \$(MPY_LIB_DIR) substitutions. Unresolved \$(VAR) tokens raise a clear error rather than failing later. makemanifest.py gains --list-c-modules which prints one path per line so the build system can pick them up (newline output handles paths that contain whitespace on the cmake side). Signed-off-by: Andrew Leech --- tests/tools/test_manifestfile.py | 109 +++++++++++++++++++++++++++++++ tools/makemanifest.py | 39 ++++++++--- tools/manifestfile.py | 73 ++++++++++++++++++++- 3 files changed, 209 insertions(+), 12 deletions(-) create mode 100644 tests/tools/test_manifestfile.py diff --git a/tests/tools/test_manifestfile.py b/tests/tools/test_manifestfile.py new file mode 100644 index 00000000000..c16f5142886 --- /dev/null +++ b/tests/tools/test_manifestfile.py @@ -0,0 +1,109 @@ +#!/usr/bin/env python3 +# +# Unit tests for tools/manifestfile.py. Run with +# `python3 tests/tools/test_manifestfile.py`. + +import os +import sys +import tempfile +import unittest + +# Locate tools/manifestfile.py relative to this file. +sys.path.insert(0, os.path.join(os.path.dirname(os.path.abspath(__file__)), "..", "..", "tools")) +from manifestfile import ( + ManifestFile, + ManifestFileError, + MODE_COMPILE, + MODE_FREEZE, + MODE_PYPROJECT, +) + + +class TestCModule(unittest.TestCase): + def setUp(self): + self.tmpdir = tempfile.mkdtemp() + self.mf = ManifestFile(MODE_FREEZE, {"MPY_DIR": self.tmpdir}) + + def tearDown(self): + import shutil + + shutil.rmtree(self.tmpdir, ignore_errors=True) + + def _make_path(self, *parts): + path = os.path.join(self.tmpdir, *parts) + os.makedirs(os.path.dirname(path), exist_ok=True) + return path + + def test_missing_path(self): + with self.assertRaisesRegex(ManifestFileError, "C module path does not exist"): + self.mf.c_module(os.path.join(self.tmpdir, "no_such_dir")) + + def test_path_is_file_not_dir(self): + f = os.path.join(self.tmpdir, "regular_file") + open(f, "w").close() + with self.assertRaisesRegex(ManifestFileError, "C module path must be a directory"): + self.mf.c_module(f) + + def test_dir_missing_module_files(self): + d = os.path.join(self.tmpdir, "mymod") + os.makedirs(d) + with self.assertRaisesRegex( + ManifestFileError, "must contain micropython.mk or micropython.cmake" + ): + self.mf.c_module(d) + + def test_accepts_dir_with_mk(self): + d = os.path.join(self.tmpdir, "mymod_mk") + os.makedirs(d) + open(os.path.join(d, "micropython.mk"), "w").close() + self.mf.c_module(d) + self.assertIn(d, self.mf.c_modules()) + + def test_accepts_dir_with_cmake(self): + d = os.path.join(self.tmpdir, "mymod_cmake") + os.makedirs(d) + open(os.path.join(d, "micropython.cmake"), "w").close() + self.mf.c_module(d) + self.assertIn(d, self.mf.c_modules()) + + def test_path_var_substitution(self): + d = os.path.join(self.tmpdir, "submod") + os.makedirs(d) + open(os.path.join(d, "micropython.mk"), "w").close() + self.mf.c_module("$(MPY_DIR)/submod") + self.assertIn(d, self.mf.c_modules()) + + def test_unresolved_path_var(self): + with self.assertRaisesRegex( + ManifestFileError, r"Unresolved variable in c_module\(\) path" + ): + self.mf.c_module("$(BOARD_DIR)/nope") + + +class TestCModuleNonFreezeModes(unittest.TestCase): + # In MODE_COMPILE/MODE_PYPROJECT, c_module() is a silent no-op so a manifest + # using it can be evaluated in any mode without raising NameError. + + def setUp(self): + self.tmpdir = tempfile.mkdtemp() + + def tearDown(self): + import shutil + + shutil.rmtree(self.tmpdir, ignore_errors=True) + + def _no_op_in_mode(self, mode): + mf = ManifestFile(mode, {"MPY_DIR": self.tmpdir}) + # Path does not exist; would raise in MODE_FREEZE. + mf.c_module(os.path.join(self.tmpdir, "no_such_dir")) + self.assertEqual(mf.c_modules(), []) + + def test_compile_mode_noop(self): + self._no_op_in_mode(MODE_COMPILE) + + def test_pyproject_mode_noop(self): + self._no_op_in_mode(MODE_PYPROJECT) + + +if __name__ == "__main__": + unittest.main() diff --git a/tools/makemanifest.py b/tools/makemanifest.py index 860935397af..a149755c86d 100644 --- a/tools/makemanifest.py +++ b/tools/makemanifest.py @@ -136,6 +136,9 @@ def main(): ) cmd_parser.add_argument("-v", "--var", action="append", help="variables to substitute") cmd_parser.add_argument("--mpy-tool-flags", default="", help="flags to pass to mpy-tool") + cmd_parser.add_argument( + "--list-c-modules", action="store_true", help="list C module paths from manifest and exit" + ) cmd_parser.add_argument("files", nargs="+", help="input manifest list") args = cmd_parser.parse_args() @@ -150,6 +153,32 @@ def main(): print("MPY_DIR and PORT_DIR variables must be specified") sys.exit(1) + # Use a lighter mode when only listing C modules: freeze/package/module + # become no-ops so the listing doesn't fail on freeze targets that may not + # exist for every variant of the board (e.g. alif's modules/$(MCU_CORE)). + mode = manifestfile.MODE_LIST_C_MODULES if args.list_c_modules else manifestfile.MODE_FREEZE + manifest = manifestfile.ManifestFile(mode, VARS) + + # Include top-level inputs, to generate the manifest + for input_manifest in args.files: + try: + manifest.execute(input_manifest) + except manifestfile.ManifestFileError as er: + print( + 'manifest error executing "{}": {}'.format(input_manifest, er.args[0]), + file=sys.stderr, + ) + sys.exit(1) + + # If we're just listing C modules, output them and exit + if args.list_c_modules: + c_modules = manifest.c_modules() + if c_modules: + # Output one path per line to handle paths with spaces + for module in c_modules: + print(module) + sys.exit(0) + # Get paths to tools MPY_CROSS = VARS["MPY_DIR"] + "/mpy-cross/build/mpy-cross" if sys.platform == "win32": @@ -162,16 +191,6 @@ def main(): print("mpy-cross not found at {}, please build it first".format(MPY_CROSS)) sys.exit(1) - manifest = manifestfile.ManifestFile(manifestfile.MODE_FREEZE, VARS) - - # Include top-level inputs, to generate the manifest - for input_manifest in args.files: - try: - manifest.execute(input_manifest) - except manifestfile.ManifestFileError as er: - print('freeze error executing "{}": {}'.format(input_manifest, er.args[0])) - sys.exit(1) - # Process the manifest str_paths = [] mpy_files = [] diff --git a/tools/manifestfile.py b/tools/manifestfile.py index 9c7a6e140f9..2e2ade6783c 100644 --- a/tools/manifestfile.py +++ b/tools/manifestfile.py @@ -27,6 +27,7 @@ import contextlib import os +import re import sys import glob import tempfile @@ -40,6 +41,9 @@ MODE_COMPILE = 2 # Same as compile, but handles require(..., pypi="name") as a requirements.txt entry. MODE_PYPROJECT = 3 +# Same surface as MODE_FREEZE, but freeze/package/module are no-ops so callers +# can collect c_module() entries without touching files referenced by freeze(). +MODE_LIST_C_MODULES = 4 # In compile mode, .py -> KIND_COMPILE_AS_MPY # In freeze mode, .py -> KIND_FREEZE_AS_MPY, .mpy->KIND_FREEZE_MPY @@ -192,6 +196,8 @@ def __init__(self, mode, path_vars=None): self._manifest_files = [] # List of PyPI dependencies (when mode=MODE_PYPROJECT). self._pypi_dependencies = [] + # List of C module directories. + self._c_modules = [] # Don't allow including the same file twice. self._visited = set() # Stack of metadata for each level. @@ -201,7 +207,9 @@ def __init__(self, mode, path_vars=None): # List of directories to search for packages. self._library_dirs = [] # Add default micropython-lib libraries if $(MPY_LIB_DIR) has been specified. - if self._path_vars["MPY_LIB_DIR"]: + # Use .get() to avoid KeyError if MPY_LIB_DIR wasn't passed (shouldn't happen + # in normal cmake/make builds, but be defensive for direct tool invocations). + if self._path_vars.get("MPY_LIB_DIR"): for lib in BASE_LIBRARY_NAMES: self.add_library(lib, os.path.join("$(MPY_LIB_DIR)", lib)) @@ -221,11 +229,12 @@ def _manifest_globals(self, kwargs): "add_library": self.add_library, "package": self.package, "module": self.module, + "c_module": self.c_module, "options": IncludeOptions(**kwargs), } # Extra legacy functions only for freeze mode. - if self._mode == MODE_FREEZE: + if self._mode in (MODE_FREEZE, MODE_LIST_C_MODULES): g.update( { "freeze": self.freeze, @@ -244,6 +253,9 @@ def pypi_dependencies(self): # In MODE_PYPROJECT, this will return a list suitable for requirements.txt. return self._pypi_dependencies + def c_modules(self): + return self._c_modules + def execute(self, manifest_file): if manifest_file.endswith(".py"): # Execute file from filesystem. @@ -478,6 +490,9 @@ def package(self, package_path, files=None, base_path=".", opt=None): """ self._metadata[-1].check_initialised(self._mode) + if self._mode == MODE_LIST_C_MODULES: + return + # Include "base_path/package_path/**/*.py" --> "package_path/**/*.py" self._search(base_path, package_path, files, exts=(".py",), kind=KIND_AUTO, opt=opt) @@ -493,6 +508,9 @@ def module(self, module_path, base_path=".", opt=None): """ self._metadata[-1].check_initialised(self._mode) + if self._mode == MODE_LIST_C_MODULES: + return + # Include "base_path/module_path" --> "module_path" base_path = self._resolve_path(base_path) _, ext = os.path.splitext(module_path) @@ -501,7 +519,56 @@ def module(self, module_path, base_path=".", opt=None): # TODO: version None self._add_file(os.path.join(base_path, module_path), module_path, opt=opt) + def c_module(self, module_path): + """ + Include a C module directory in the build. + + The module_path should be a directory containing a micropython.mk and/or + micropython.cmake file. + + Supports $(VAR) path substitution: + c_module("$(MPY_DIR)/examples/usercmodule/cexample") + c_module("$(BOARD_DIR)/../../drivers/sensor") + + Can be called multiple times to include multiple C modules. + + Only has effect when collecting modules for the build system + (MODE_FREEZE / MODE_LIST_C_MODULES). Silent no-op in MODE_COMPILE / + MODE_PYPROJECT, so the same manifest can be evaluated in any mode. + """ + if self._mode not in (MODE_FREEZE, MODE_LIST_C_MODULES): + return + resolved = self._resolve_path(module_path) + # Reject unresolved $(VAR) up front so a bad manifest fails with a + # clear message rather than a confusing "path does not exist" containing + # the variable literal. + unresolved = re.search(r"\$\([^)]+\)", resolved) + if unresolved: + raise ManifestFileError( + "Unresolved variable in c_module() path: {}".format(unresolved.group(0)) + ) + module_path = resolved + if not os.path.exists(module_path): + raise ManifestFileError("C module path does not exist: {}".format(module_path)) + if not os.path.isdir(module_path): + raise ManifestFileError("C module path must be a directory: {}".format(module_path)) + # Verify the directory contains a micropython.mk or micropython.cmake file. + has_mk = os.path.isfile(os.path.join(module_path, "micropython.mk")) + has_cmake = os.path.isfile(os.path.join(module_path, "micropython.cmake")) + if not has_mk and not has_cmake: + raise ManifestFileError( + "C module directory must contain micropython.mk or micropython.cmake: {}".format( + module_path + ) + ) + self._c_modules.append(module_path) + def _freeze_internal(self, path, script, exts, kind, opt): + # In list-c-modules mode we only care about c_module() entries; skip + # the file-system walk so freeze targets that don't exist (e.g. a + # board-conditional modules directory) don't abort the listing. + if self._mode == MODE_LIST_C_MODULES: + return if script is None: self._search(path, None, None, exts=exts, kind=kind, opt=opt) elif isinstance(script, str) and os.path.isdir(os.path.join(path, script)): @@ -555,6 +622,8 @@ def freeze_as_str(self, path): Freeze the given `path` and all .py scripts within it as a string, which will be compiled upon import. """ + if self._mode == MODE_LIST_C_MODULES: + return self._search(path, None, None, exts=(".py",), kind=KIND_FREEZE_AS_STR) def freeze_as_mpy(self, path, script=None, opt=None): From 9d7845eecf4dfb2a934892eb100a0dcdd77222f4 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 23 May 2026 13:38:17 +1000 Subject: [PATCH 527/635] py: Add build system support for c_module() in manifests. When MICROPY_FROZEN_MANIFEST is set, the build system runs makemanifest.py with --list-c-modules to extract C module paths from the manifest and appends them to USER_C_MODULES so they go through the same code path as user modules specified on the command line. The Make side lives in py/manifest.mk (included from py/py.mk) and the CMake side lives in py/manifest.cmake (included from py/usermod.cmake). Both share defaulting for the MICROPY_MANIFEST_* substitution variables so a manifest can reference $(MPY_DIR) etc. consistently on either side. The make-side extraction is gated on the build target needing it and on micropython-lib being initialised, and surfaces makemanifest.py errors via .SHELLSTATUS. The cmake side uses FATAL_ERROR to match. Signed-off-by: Andrew Leech --- ports/zephyr/CMakeLists.txt | 13 ++++--- py/manifest.cmake | 73 +++++++++++++++++++++++++++++++++++++ py/manifest.mk | 56 ++++++++++++++++++++++++++++ py/mkrules.cmake | 35 +++++++----------- py/mkrules.mk | 31 +++++----------- py/py.cmake | 6 +++ py/py.mk | 53 +++++++++++++++++++++------ py/usermod.cmake | 7 ++++ 8 files changed, 214 insertions(+), 60 deletions(-) create mode 100644 py/manifest.cmake create mode 100644 py/manifest.mk diff --git a/ports/zephyr/CMakeLists.txt b/ports/zephyr/CMakeLists.txt index 6abb5e3c2eb..abd8d4551f4 100644 --- a/ports/zephyr/CMakeLists.txt +++ b/ports/zephyr/CMakeLists.txt @@ -34,6 +34,14 @@ string(TOUPPER ZEPHYR_${BOARD} MICROPY_BOARD) include(${MICROPY_DIR}/py/py.cmake) include(${MICROPY_DIR}/extmod/extmod.cmake) + +# Resolve MICROPY_FROZEN_MANIFEST before usermod.cmake (and thus +# py/manifest.cmake) runs, so c_module() entries in the manifest are picked up. +if (CONFIG_MICROPY_FROZEN_MODULES) + cmake_path(ABSOLUTE_PATH CONFIG_MICROPY_FROZEN_MANIFEST BASE_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}) + set(MICROPY_FROZEN_MANIFEST ${CONFIG_MICROPY_FROZEN_MANIFEST}) +endif() + include(${MICROPY_DIR}/py/usermod.cmake) list(APPEND DTS_ROOT ${CMAKE_CURRENT_SOURCE_DIR}/dts) @@ -57,11 +65,6 @@ elseif(CONFIG_RISCV_ISA_RV64I AND CONFIG_RISCV_ISA_EXT_M AND CONFIG_RISCV_ISA_EX set(MICROPY_CROSS_FLAGS -march=rv64imc) endif() -if (CONFIG_MICROPY_FROZEN_MODULES) - cmake_path(ABSOLUTE_PATH CONFIG_MICROPY_FROZEN_MANIFEST BASE_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}) - set(MICROPY_FROZEN_MANIFEST ${CONFIG_MICROPY_FROZEN_MANIFEST}) -endif() - set(MICROPY_SOURCE_PORT main.c help.c diff --git a/py/manifest.cmake b/py/manifest.cmake new file mode 100644 index 00000000000..446fb063b7e --- /dev/null +++ b/py/manifest.cmake @@ -0,0 +1,73 @@ +# Extract c_module() entries from MICROPY_FROZEN_MANIFEST and append them to +# USER_C_MODULES. Included from py/usermod.cmake; the port must have resolved +# MICROPY_FROZEN_MANIFEST (and any board-config default / cmake-command-line +# override) before usermod.cmake runs. +# +# Also sets default MICROPY_MANIFEST_* path variables that are forwarded to +# makemanifest.py here for c_module extraction and again from py/mkrules.cmake +# for the frozen content generation step, so both passes substitute the same +# values into manifest path expressions. + +if(MICROPY_FROZEN_MANIFEST) + # Set default path variables to be passed to makemanifest.py. These are + # available in path substitutions inside the manifest. Additional variables + # can be set per-board in mpconfigboard.cmake or on the cmake command line. + # MICROPY_LIB_DIR is set in py.cmake (included before usermod.cmake). + if(NOT DEFINED MICROPY_MANIFEST_PORT_DIR) + set(MICROPY_MANIFEST_PORT_DIR ${MICROPY_PORT_DIR}) + endif() + if(NOT DEFINED MICROPY_MANIFEST_BOARD_DIR) + set(MICROPY_MANIFEST_BOARD_DIR ${MICROPY_BOARD_DIR}) + endif() + if(NOT DEFINED MICROPY_MANIFEST_MPY_DIR) + set(MICROPY_MANIFEST_MPY_DIR ${MICROPY_DIR}) + endif() + if(NOT DEFINED MICROPY_MANIFEST_MPY_LIB_DIR) + set(MICROPY_MANIFEST_MPY_LIB_DIR ${MICROPY_LIB_DIR}) + endif() + + # Find all MICROPY_MANIFEST_* variables and turn them into command line + # arguments. Stored in MICROPY_MAKEMANIFEST_ARGS (outside the + # MICROPY_MANIFEST_ namespace) so it doesn't self-match the regex above + # on subsequent cmake configures. + get_cmake_property(_manifest_vars VARIABLES) + list(FILTER _manifest_vars INCLUDE REGEX "MICROPY_MANIFEST_.*") + set(MICROPY_MAKEMANIFEST_ARGS) + foreach(_manifest_var IN LISTS _manifest_vars) + list(APPEND MICROPY_MAKEMANIFEST_ARGS "-v") + string(REGEX REPLACE "MICROPY_MANIFEST_(.*)" "\\1" _manifest_var_name ${_manifest_var}) + list(APPEND MICROPY_MAKEMANIFEST_ARGS "${_manifest_var_name}=${${_manifest_var}}") + endforeach() + + # Skip extraction during UPDATE_SUBMODULES (require() would fail) and when + # micropython-lib is not initialised. Matches py/manifest.mk behaviour: + # warn and continue with an empty c_module list rather than fatal. + if(EXISTS ${MICROPY_FROZEN_MANIFEST} AND NOT UPDATE_SUBMODULES) + if(EXISTS ${MICROPY_LIB_DIR}/README.md) + if(NOT Python3_EXECUTABLE) + find_package(Python3 REQUIRED COMPONENTS Interpreter) + endif() + + execute_process( + COMMAND "${Python3_EXECUTABLE}" "${MICROPY_DIR}/tools/makemanifest.py" + --list-c-modules ${MICROPY_MAKEMANIFEST_ARGS} "${MICROPY_FROZEN_MANIFEST}" + OUTPUT_VARIABLE MANIFEST_C_MODULES + ERROR_VARIABLE MANIFEST_ERROR + OUTPUT_STRIP_TRAILING_WHITESPACE + RESULT_VARIABLE MANIFEST_RESULT + ) + + if(NOT MANIFEST_RESULT EQUAL 0) + message(FATAL_ERROR "Failed to extract C modules from manifest: ${MICROPY_FROZEN_MANIFEST}\nError: ${MANIFEST_ERROR}") + endif() + + if(MANIFEST_C_MODULES) + string(REPLACE "\n" ";" MANIFEST_C_MODULES_LIST "${MANIFEST_C_MODULES}") + list(APPEND USER_C_MODULES ${MANIFEST_C_MODULES_LIST}) + list(REMOVE_DUPLICATES USER_C_MODULES) + endif() + else() + message(WARNING "c_module() extraction skipped: micropython-lib not initialised, run 'make BOARD=${MICROPY_BOARD} submodules'") + endif() + endif() +endif() diff --git a/py/manifest.mk b/py/manifest.mk new file mode 100644 index 00000000000..8b415ebe859 --- /dev/null +++ b/py/manifest.mk @@ -0,0 +1,56 @@ +# Manifest processing for freeze(), require(), include(), and c_module(). +# This file handles both C module extraction and frozen Python content generation. + +ifneq ($(FROZEN_MANIFEST),) + +# Set default path variables to be passed to makemanifest.py. These will be +# available in path substitutions. Additional variables can be set per-board +# in mpconfigboard.mk or on the make command line. +MICROPY_MANIFEST_PORT_DIR ?= $(CURDIR) +MICROPY_MANIFEST_BOARD_DIR ?= $(BOARD_DIR) +MICROPY_MANIFEST_MPY_DIR ?= $(TOP) +MICROPY_MANIFEST_MPY_LIB_DIR ?= $(MPY_LIB_DIR) + +# Find all MICROPY_MANIFEST_* variables and turn them into command line +# arguments. Values must not contain whitespace (GNU make word-splits). +MANIFEST_VARIABLES = $(foreach var,$(filter MICROPY_MANIFEST_%, $(.VARIABLES)),-v "$(subst MICROPY_MANIFEST_,,$(var))=$($(var))") + +# Skip c_module extraction for targets that don't need a build. +MANIFEST_NON_BUILD_GOALS := clean clean-prog submodules help print-cfg print-def +MANIFEST_GOALS := $(filter-out $(MANIFEST_NON_BUILD_GOALS),$(or $(MAKECMDGOALS),build)) + +# Extract C module paths up front so downstream rules see them. Skipped when +# micropython-lib isn't initialised (require() would fail) or for non-build +# targets. $(shell) collapses newlines, so c_module() paths cannot contain +# whitespace on the make side (the cmake side handles it correctly). +MANIFEST_C_MODULES := +ifneq ($(MANIFEST_GOALS),) +ifeq ($(wildcard $(FROZEN_MANIFEST)),$(FROZEN_MANIFEST)) +ifeq ($(wildcard $(MPY_LIB_DIR)/README.md),$(MPY_LIB_DIR)/README.md) +MANIFEST_C_MODULES := $(shell $(MAKE_MANIFEST) --list-c-modules $(MANIFEST_VARIABLES) $(FROZEN_MANIFEST)) +# Treat a populated, non-zero .SHELLSTATUS as failure. GNU make < 4.2 (eg +# macOS 3.81) leaves .SHELLSTATUS empty, in which case skip the check; an +# empty filter result means "succeed (status was 0, or unavailable)". +ifneq ($(filter-out 0,$(.SHELLSTATUS)),) +$(error makemanifest.py --list-c-modules failed (exit $(.SHELLSTATUS)) for $(FROZEN_MANIFEST)) +endif +else +$(warning c_module() extraction skipped: micropython-lib not initialised, run 'make submodules') +endif +endif +endif + +# Merge manifest c_modules into USER_C_MODULES. $(sort) also de-duplicates; +# this changes USER_C_MODULES iteration order vs cmake's list(REMOVE_DUPLICATES) +# which preserves first occurrence. Module include order should not be +# behaviour-sensitive so this is acceptable. +USER_C_MODULES := $(sort $(USER_C_MODULES) $(MANIFEST_C_MODULES)) + +# Frozen content rule, requires $(BUILD) and other variables from the port. +ifdef BUILD +$(BUILD)/frozen_content.c: FORCE $(BUILD)/genhdr/qstrdefs.generated.h $(BUILD)/genhdr/root_pointers.h | $(MICROPY_MPYCROSS_DEPENDENCY) + $(Q)test -e "$(MPY_LIB_DIR)/README.md" || (echo -e $(HELP_MPY_LIB_SUBMODULE); false) + $(Q)$(MAKE_MANIFEST) -o $@ $(MANIFEST_VARIABLES) -b "$(BUILD)" $(if $(MPY_CROSS_FLAGS),-f"$(MPY_CROSS_FLAGS)",) --mpy-tool-flags="$(MPY_TOOL_FLAGS)" $(FROZEN_MANIFEST) +endif + +endif # FROZEN_MANIFEST diff --git a/py/mkrules.cmake b/py/mkrules.cmake index e3d769cc59b..0903f81d897 100644 --- a/py/mkrules.cmake +++ b/py/mkrules.cmake @@ -260,9 +260,12 @@ if(MICROPY_FROZEN_MANIFEST) # Note: target_compile_definitions already added earlier. - if(NOT MICROPY_LIB_DIR) + # Ensure micropython-lib is included in submodule updates, but only when + # MICROPY_LIB_DIR points at the in-tree submodule location; a user + # overriding MICROPY_LIB_DIR to an out-of-tree checkout shouldn't have + # the submodule updated. + if(MICROPY_LIB_DIR STREQUAL "${MICROPY_DIR}/lib/micropython-lib") list(APPEND GIT_SUBMODULES lib/micropython-lib) - set(MICROPY_LIB_DIR ${MICROPY_DIR}/lib/micropython-lib) endif() if(NOT UPDATE_SUBMODULES AND NOT EXISTS ${MICROPY_LIB_DIR}/README.md) @@ -278,9 +281,13 @@ if(MICROPY_FROZEN_MANIFEST) if(NOT MICROPY_MAKE_EXECUTABLE) set(MICROPY_MAKE_EXECUTABLE make) endif() + # Clear FROZEN_MANIFEST/USER_C_MODULES in the mpy-cross sub-make so a + # shell-env FROZEN_MANIFEST=... doesn't leak in and trigger + # manifest.mk against the wrong cwd. mkrules.mk does the same for the + # make-based port path. add_custom_command( OUTPUT ${MICROPY_MPYCROSS_DEPENDENCY} - COMMAND ${MICROPY_MAKE_EXECUTABLE} -C ${MICROPY_DIR}/mpy-cross USER_C_MODULES= + COMMAND ${MICROPY_MAKE_EXECUTABLE} -C ${MICROPY_DIR}/mpy-cross USER_C_MODULES= FROZEN_MANIFEST= ) endif() @@ -290,27 +297,13 @@ if(MICROPY_FROZEN_MANIFEST) set(MICROPY_CROSS_FLAGS "-f${MICROPY_CROSS_FLAGS}") endif() - # Set default path variables to be passed to makemanifest.py. These will - # be available in path substitutions. Additional variables can be set - # per-board in mpconfigboard.cmake. - set(MICROPY_MANIFEST_PORT_DIR ${MICROPY_PORT_DIR}) - set(MICROPY_MANIFEST_BOARD_DIR ${MICROPY_BOARD_DIR}) - set(MICROPY_MANIFEST_MPY_DIR ${MICROPY_DIR}) - set(MICROPY_MANIFEST_MPY_LIB_DIR ${MICROPY_LIB_DIR}) - - # Find all MICROPY_MANIFEST_* variables and turn them into command line arguments. - get_cmake_property(_manifest_vars VARIABLES) - list(FILTER _manifest_vars INCLUDE REGEX "MICROPY_MANIFEST_.*") - foreach(_manifest_var IN LISTS _manifest_vars) - list(APPEND _manifest_var_args "-v") - string(REGEX REPLACE "MICROPY_MANIFEST_(.*)" "\\1" _manifest_var_name ${_manifest_var}) - list(APPEND _manifest_var_args "${_manifest_var_name}=${${_manifest_var}}") - endforeach() - + # MICROPY_MAKEMANIFEST_ARGS is populated by py/manifest.cmake (included via + # py/usermod.cmake before this file). Reuse that list so both the c_module + # extraction pass and the frozen content step substitute the same values. add_custom_target( BUILD_FROZEN_CONTENT ALL BYPRODUCTS ${MICROPY_FROZEN_CONTENT} - COMMAND ${Python3_EXECUTABLE} ${MICROPY_DIR}/tools/makemanifest.py -o ${MICROPY_FROZEN_CONTENT} ${_manifest_var_args} -b "${CMAKE_BINARY_DIR}" ${MICROPY_CROSS_FLAGS} --mpy-tool-flags=${MICROPY_MPY_TOOL_FLAGS} ${MICROPY_FROZEN_MANIFEST} + COMMAND ${Python3_EXECUTABLE} ${MICROPY_DIR}/tools/makemanifest.py -o ${MICROPY_FROZEN_CONTENT} ${MICROPY_MAKEMANIFEST_ARGS} -b "${CMAKE_BINARY_DIR}" ${MICROPY_CROSS_FLAGS} --mpy-tool-flags=${MICROPY_MPY_TOOL_FLAGS} ${MICROPY_FROZEN_MANIFEST} DEPENDS ${MICROPY_QSTRDEFS_GENERATED} ${MICROPY_ROOT_POINTERS} diff --git a/py/mkrules.mk b/py/mkrules.mk index f94bcea2ae1..9c4dd26132b 100644 --- a/py/mkrules.mk +++ b/py/mkrules.mk @@ -74,12 +74,12 @@ QSTR_GEN_CXXFLAGS += $(QSTR_GEN_FLAGS) # can be located. By following this scheme, it allows a single build rule # to be used to compile all .c files. -vpath %.S . $(TOP) $(USER_C_MODULES) +vpath %.S . $(TOP) $(USER_C_MODULES) $(USERMOD_DIR_PARENTS) $(BUILD)/%.o: %.S $(ECHO) "CC $<" $(Q)$(CC) $(CFLAGS) -c -o $@ $< -vpath %.s . $(TOP) $(USER_C_MODULES) +vpath %.s . $(TOP) $(USER_C_MODULES) $(USERMOD_DIR_PARENTS) $(BUILD)/%.o: %.s $(ECHO) "AS $<" $(Q)$(AS) $(AFLAGS) -o $@ $< @@ -108,11 +108,11 @@ $(Q)$(CXX) $(CXXFLAGS) -c -MD -MF $(@:.o=.d) -o $@ $< || (echo -e $(HELP_BUILD_E $(RM) -f $(@:.o=.d) endef -vpath %.c . $(TOP) $(USER_C_MODULES) +vpath %.c . $(TOP) $(USER_C_MODULES) $(USERMOD_DIR_PARENTS) $(BUILD)/%.o: %.c $(call compile_c) -vpath %.cpp . $(TOP) $(USER_C_MODULES) +vpath %.cpp . $(TOP) $(USER_C_MODULES) $(USERMOD_DIR_PARENTS) $(BUILD)/%.o: %.cpp $(call compile_cxx) @@ -201,9 +201,12 @@ $(HEADER_BUILD): $(MKDIR) -p $@ ifneq ($(MICROPY_MPYCROSS_DEPENDENCY),) -# to automatically build mpy-cross, if needed +# Build mpy-cross automatically if needed. Clear USER_C_MODULES and +# FROZEN_MANIFEST so a port build with either set doesn't leak them into the +# mpy-cross sub-make and cause manifest.mk there to parse the port's manifest +# from the wrong cwd. $(MICROPY_MPYCROSS_DEPENDENCY): - $(MAKE) -C "$(abspath $(dir $@)..)" USER_C_MODULES= + $(MAKE) -C "$(abspath $(dir $@)..)" USER_C_MODULES= FROZEN_MANIFEST= endif ifneq ($(FROZEN_DIR),) @@ -225,22 +228,6 @@ endif CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool CFLAGS += -DMICROPY_MODULE_FROZEN_MPY CFLAGS += -DMICROPY_MODULE_FROZEN_STR - -# Set default path variables to be passed to makemanifest.py. These will be -# available in path substitutions. Additional variables can be set per-board -# in mpconfigboard.mk or on the make command line. -MICROPY_MANIFEST_MPY_LIB_DIR = $(MPY_LIB_DIR) -MICROPY_MANIFEST_PORT_DIR = $(shell pwd) -MICROPY_MANIFEST_BOARD_DIR = $(BOARD_DIR) -MICROPY_MANIFEST_MPY_DIR = $(TOP) - -# Find all MICROPY_MANIFEST_* variables and turn them into command line arguments. -MANIFEST_VARIABLES = $(foreach var,$(filter MICROPY_MANIFEST_%, $(.VARIABLES)),-v "$(subst MICROPY_MANIFEST_,,$(var))=$($(var))") - -# to build frozen_content.c from a manifest -$(BUILD)/frozen_content.c: FORCE $(BUILD)/genhdr/qstrdefs.generated.h $(BUILD)/genhdr/root_pointers.h | $(MICROPY_MPYCROSS_DEPENDENCY) - $(Q)test -e "$(MPY_LIB_DIR)/README.md" || (echo -e $(HELP_MPY_LIB_SUBMODULE); false) - $(Q)$(MAKE_MANIFEST) -o $@ $(MANIFEST_VARIABLES) -b "$(BUILD)" $(if $(MPY_CROSS_FLAGS),-f"$(MPY_CROSS_FLAGS)",) --mpy-tool-flags="$(MPY_TOOL_FLAGS)" $(FROZEN_MANIFEST) endif ifneq ($(PROG),) diff --git a/py/py.cmake b/py/py.cmake index c53c27909bf..e423bf8c184 100644 --- a/py/py.cmake +++ b/py/py.cmake @@ -4,6 +4,12 @@ set(MICROPY_PY_DIR "${MICROPY_DIR}/py") list(APPEND MICROPY_INC_CORE "${MICROPY_DIR}") +# Set MICROPY_LIB_DIR default if not already set by the port. +# This needs to happen before usermod.cmake is included (for c_module() in manifests). +if(NOT MICROPY_LIB_DIR) + set(MICROPY_LIB_DIR ${MICROPY_DIR}/lib/micropython-lib) +endif() + # All py/ source files set(MICROPY_SOURCE_PY ${MICROPY_PY_DIR}/argcheck.c diff --git a/py/py.mk b/py/py.mk index 5dadb7db81c..558f37d7d59 100644 --- a/py/py.mk +++ b/py/py.mk @@ -22,13 +22,14 @@ QSTR_GLOBAL_REQUIREMENTS += $(HEADER_BUILD)/mpversion.h CSUPEROPT = -O3 # External modules written in C. + +# Process manifest for C module extraction (appends to USER_C_MODULES). +include $(TOP)/py/manifest.mk + ifneq ($(USER_C_MODULES),) # pre-define USERMOD variables as expanded so that variables are immediate # expanded as they're added to them -# Confirm the provided path exists, show abspath if not to make it clearer to fix. -$(if $(wildcard $(USER_C_MODULES)/.),,$(error USER_C_MODULES doesn't exist: $(abspath $(USER_C_MODULES)))) - # C/C++ files that are included in the QSTR/module build SRC_USERMOD_C := SRC_USERMOD_CXX := @@ -46,19 +47,47 @@ LIBS_USERMOD := # added to SRC_USERMOD_C below SRC_USERMOD := -$(foreach module, $(wildcard $(USER_C_MODULES)/*/micropython.mk), \ - $(eval USERMOD_DIR = $(patsubst %/,%,$(dir $(module))))\ - $(info Including User C Module from $(USERMOD_DIR))\ - $(eval include $(module))\ +# For each C module directory, scan for micropython.mk and include it. +# Accumulate USERMOD_DIRS so we can later strip each module's parent path +# from its source files while preserving the module basename in the build +# tree (e.g. build/cexample/foo.o, not build/foo.o, so files that share a +# name across modules don't collide on the same .o target). +USERMOD_DIRS := +$(foreach _UDIR, $(USER_C_MODULES), \ + $(if $(wildcard $(_UDIR)/.),,$(error USER_C_MODULES path doesn't exist: $(abspath $(_UDIR)))) \ + $(foreach module, $(wildcard $(_UDIR)/micropython.mk) $(wildcard $(_UDIR)/*/micropython.mk), \ + $(eval USERMOD_DIR = $(patsubst %/,%,$(dir $(module))))\ + $(eval USERMOD_DIRS += $(USERMOD_DIR))\ + $(info Including User C Module from $(USERMOD_DIR))\ + $(eval include $(module))\ + )\ ) SRC_USERMOD_C += $(SRC_USERMOD) -SRC_USERMOD_PATHFIX_C += $(patsubst $(USER_C_MODULES)/%.c,%.c,$(SRC_USERMOD_C)) -SRC_USERMOD_PATHFIX_CXX += $(patsubst $(USER_C_MODULES)/%.cpp,%.cpp,$(SRC_USERMOD_CXX)) -SRC_USERMOD_PATHFIX_LIB_C += $(patsubst $(USER_C_MODULES)/%.c,%.c,$(SRC_USERMOD_LIB_C)) -SRC_USERMOD_PATHFIX_LIB_CXX += $(patsubst $(USER_C_MODULES)/%.cpp,%.cpp,$(SRC_USERMOD_LIB_CXX)) -SRC_USERMOD_PATHFIX_LIB_ASM += $(patsubst $(USER_C_MODULES)/%.S,%.S,$(SRC_USERMOD_LIB_ASM)) +# Strip each USERMOD_DIR's leading path from source files, keeping the module +# basename as the leading directory so build outputs land at +# BUILD//.o. Uses per-directory patsubst on the paths as-is +# rather than $(abspath) so a parent directory containing whitespace doesn't +# break word-based patsubst. +SRC_USERMOD_PATHFIX_C := $(SRC_USERMOD_C) +SRC_USERMOD_PATHFIX_CXX := $(SRC_USERMOD_CXX) +SRC_USERMOD_PATHFIX_LIB_C := $(SRC_USERMOD_LIB_C) +SRC_USERMOD_PATHFIX_LIB_CXX := $(SRC_USERMOD_LIB_CXX) +SRC_USERMOD_PATHFIX_LIB_ASM := $(SRC_USERMOD_LIB_ASM) +USERMOD_DIRS := $(sort $(USERMOD_DIRS)) +$(foreach _MDIR, $(USERMOD_DIRS), \ + $(eval _MBASE := $(notdir $(_MDIR))) \ + $(eval SRC_USERMOD_PATHFIX_C := $$(patsubst $(_MDIR)/%,$(_MBASE)/%,$$(SRC_USERMOD_PATHFIX_C))) \ + $(eval SRC_USERMOD_PATHFIX_CXX := $$(patsubst $(_MDIR)/%,$(_MBASE)/%,$$(SRC_USERMOD_PATHFIX_CXX))) \ + $(eval SRC_USERMOD_PATHFIX_LIB_C := $$(patsubst $(_MDIR)/%,$(_MBASE)/%,$$(SRC_USERMOD_PATHFIX_LIB_C))) \ + $(eval SRC_USERMOD_PATHFIX_LIB_CXX := $$(patsubst $(_MDIR)/%,$(_MBASE)/%,$$(SRC_USERMOD_PATHFIX_LIB_CXX))) \ + $(eval SRC_USERMOD_PATHFIX_LIB_ASM := $$(patsubst $(_MDIR)/%,$(_MBASE)/%,$$(SRC_USERMOD_PATHFIX_LIB_ASM))) \ +) + +# Parent directories of each USERMOD_DIR, added to vpath below so paths like +# cexample/foo.c (produced by the patsubst above) resolve to source files. +USERMOD_DIR_PARENTS := $(sort $(foreach _MDIR, $(USERMOD_DIRS), $(patsubst %/,%,$(dir $(_MDIR))))) CFLAGS += $(CFLAGS_USERMOD) CXXFLAGS += $(CXXFLAGS_USERMOD) diff --git a/py/usermod.cmake b/py/usermod.cmake index 4a8b99ff31b..648f315b9d5 100644 --- a/py/usermod.cmake +++ b/py/usermod.cmake @@ -39,6 +39,13 @@ function(usermod_gather_sources SOURCES_VARNAME INCLUDE_DIRECTORIES_VARNAME INCL endif() endfunction() +# Extract c_module() entries from MICROPY_FROZEN_MANIFEST and merge them into +# USER_C_MODULES, so the loop below picks them up alongside USER_C_MODULES paths +# passed on the cmake command line. The port is responsible for resolving +# MICROPY_FROZEN_MANIFEST (including any board-config defaults) before +# including this file. +include(${MICROPY_DIR}/py/manifest.cmake) + # Include CMake files for user modules. if (USER_C_MODULES) foreach(USER_C_MODULE_PATH ${USER_C_MODULES}) From 10b14515521fb7b89774665b0dcd7042adfc8e5a Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 23 May 2026 13:38:24 +1000 Subject: [PATCH 528/635] rp2: Resolve FROZEN_MANIFEST before usermod.cmake and quote for cmake. Move the MICROPY_USER_FROZEN_MANIFEST resolution to run right after the board config (rather than near the end of CMakeLists.txt) so it's applied before py/usermod.cmake is included; py/manifest.cmake (invoked from usermod.cmake) needs the final MICROPY_FROZEN_MANIFEST value to extract c_module() paths. Also quote FROZEN_MANIFEST when forwarding it from the Makefile to cmake so paths containing whitespace round-trip correctly. Signed-off-by: Andrew Leech --- ports/rp2/CMakeLists.txt | 20 ++++++++++++-------- ports/rp2/Makefile | 2 +- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/ports/rp2/CMakeLists.txt b/ports/rp2/CMakeLists.txt index e674b19adf7..ee6f1b803a2 100644 --- a/ports/rp2/CMakeLists.txt +++ b/ports/rp2/CMakeLists.txt @@ -45,9 +45,12 @@ if(MICROPY_BOARD_VARIANT) endif() endif() +# Save the cmake-command-line MICROPY_FROZEN_MANIFEST before board config +# inclusion may overwrite it; resolved back after, so command-line takes +# precedence over the board's default. set(MICROPY_USER_FROZEN_MANIFEST ${MICROPY_FROZEN_MANIFEST}) -# Include board config, it may override MICROPY_FROZEN_MANIFEST +# Include board config, it may set MICROPY_FROZEN_MANIFEST include(${MICROPY_BOARD_DIR}/mpconfigboard.cmake) if(NOT MICROPY_BOARD_VARIANT) include(${MICROPY_BOARD_DIR}/mpconfigvariant.cmake OPTIONAL) @@ -55,6 +58,14 @@ else() include(${MICROPY_BOARD_DIR}/mpconfigvariant_${MICROPY_BOARD_VARIANT}.cmake) endif() +# Resolve the frozen manifest now so it's available before py/manifest.cmake +# runs (via py/usermod.cmake below). +if(MICROPY_USER_FROZEN_MANIFEST) + set(MICROPY_FROZEN_MANIFEST ${MICROPY_USER_FROZEN_MANIFEST}) +elseif(NOT MICROPY_FROZEN_MANIFEST) + set(MICROPY_FROZEN_MANIFEST ${MICROPY_PORT_DIR}/boards/manifest.py) +endif() + # Set the PICO_BOARD if it's not already set (allow a board to override it). if(NOT PICO_BOARD) string(TOLOWER ${MICROPY_BOARD} PICO_BOARD) @@ -504,13 +515,6 @@ else() set(MICROPY_CROSS_FLAGS "-march=armv6m") endif() -# Set the frozen manifest file -if (MICROPY_USER_FROZEN_MANIFEST) - set(MICROPY_FROZEN_MANIFEST ${MICROPY_USER_FROZEN_MANIFEST}) -elseif (NOT MICROPY_FROZEN_MANIFEST) - set(MICROPY_FROZEN_MANIFEST ${MICROPY_PORT_DIR}/boards/manifest.py) -endif() - target_sources(${MICROPY_TARGET} PRIVATE ${MICROPY_SOURCE_PY} ${MICROPY_SOURCE_EXTMOD} diff --git a/ports/rp2/Makefile b/ports/rp2/Makefile index a6b48818bad..2b64ba88ab3 100644 --- a/ports/rp2/Makefile +++ b/ports/rp2/Makefile @@ -41,7 +41,7 @@ CMAKE_ARGS += -DUSER_C_MODULES=${USER_C_MODULES} endif ifneq ($(FROZEN_MANIFEST),) -CMAKE_ARGS += -DMICROPY_FROZEN_MANIFEST=${FROZEN_MANIFEST} +CMAKE_ARGS += -DMICROPY_FROZEN_MANIFEST="${FROZEN_MANIFEST}" endif ifeq ($(DEBUG),1) From ceaf65b8edd40b67825c0d01054560243f15db34 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 23 May 2026 13:38:30 +1000 Subject: [PATCH 529/635] esp32: Quote FROZEN_MANIFEST when forwarding it to idf.py. Quote FROZEN_MANIFEST when passing it through IDFPY_FLAGS so paths containing whitespace round-trip correctly to the cmake configure step; py/manifest.cmake (auto-included via py/usermod.cmake) needs the resolved value to extract c_module() paths from the manifest. Signed-off-by: Andrew Leech --- ports/esp32/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/esp32/Makefile b/ports/esp32/Makefile index 6a36b4da93c..610e4a2077f 100644 --- a/ports/esp32/Makefile +++ b/ports/esp32/Makefile @@ -52,7 +52,7 @@ endif IDFPY_FLAGS += -D MICROPY_BOARD=$(BOARD) -D MICROPY_BOARD_DIR="$(abspath $(BOARD_DIR))" $(CMAKE_ARGS) ifdef FROZEN_MANIFEST - IDFPY_FLAGS += -D MICROPY_FROZEN_MANIFEST=$(FROZEN_MANIFEST) + IDFPY_FLAGS += -D MICROPY_FROZEN_MANIFEST="$(FROZEN_MANIFEST)" endif ifdef BOARD_VARIANT From a28ce18f031a12864ea503b78c52fa5f36c301ff Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 23 May 2026 13:18:57 +1000 Subject: [PATCH 530/635] examples/usercmodule: Fix subpackage cmake source filename. The micropython.cmake referenced examplemodule.c but the source file is named modexamplepackage.c. The subpackage example wasn't built via cmake before, so the typo went unnoticed. Signed-off-by: Andrew Leech --- examples/usercmodule/subpackage/micropython.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/usercmodule/subpackage/micropython.cmake b/examples/usercmodule/subpackage/micropython.cmake index a51e7a80613..54253f94694 100644 --- a/examples/usercmodule/subpackage/micropython.cmake +++ b/examples/usercmodule/subpackage/micropython.cmake @@ -3,7 +3,7 @@ add_library(usermod_subpackage_example INTERFACE) # Add our source files to the lib target_sources(usermod_subpackage_example INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/examplemodule.c + ${CMAKE_CURRENT_LIST_DIR}/modexamplepackage.c ) # Add the current directory as an include directory. From 7909c9ce0db768f3f863cdd9344d7c905b404494 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 23 May 2026 13:19:04 +1000 Subject: [PATCH 531/635] docs: Document c_module() manifest function. Document the new c_module() function in the manifest reference, including the FROZEN_MANIFEST prerequisite, additive interaction with USER_C_MODULES, and the make-side whitespace limitation. Add a corresponding section to the cmodules developer guide so the feature is discoverable from both entry points. Signed-off-by: Andrew Leech --- docs/develop/cmodules.rst | 26 ++++++++++++++++++++++++++ docs/reference/manifest.rst | 31 +++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/docs/develop/cmodules.rst b/docs/develop/cmodules.rst index ec20e65f477..e1c6658f075 100644 --- a/docs/develop/cmodules.rst +++ b/docs/develop/cmodules.rst @@ -264,6 +264,32 @@ structures. If not done correctly it will compile but importing will fail to find the module. +Specifying C modules via a manifest +----------------------------------- + +As an alternative to passing ``USER_C_MODULES`` on the command line, C modules +can be listed inside a frozen manifest using ``c_module()``. This is convenient +when a board or project always pulls in the same set of C modules: the manifest +becomes the single place that declares both frozen Python code and the C +modules required to support it. + +.. code-block:: python3 + + # In ports/myboard/boards/MYBOARD/manifest.py + include("$(PORT_DIR)/boards/manifest.py") + c_module("$(MPY_DIR)/examples/usercmodule/cexample") + c_module("$(BOARD_DIR)/../../drivers/sensor") + +The manifest will need to be loaded via ``FROZEN_MANIFEST`` (either set in +``mpconfigboard.{mk,cmake}`` or passed on the make command line), and modules +listed with ``c_module()`` combine additively with any paths supplied via +``USER_C_MODULES`` on the command line. Duplicate paths are de-duplicated, so +mixing the two is safe. + +See :ref:`manifest` for the full ``c_module()`` API and supported +``$(VAR)`` path substitutions. + + Module usage in MicroPython --------------------------- diff --git a/docs/reference/manifest.rst b/docs/reference/manifest.rst index dc9d6dd75b2..1e43f4729a7 100644 --- a/docs/reference/manifest.rst +++ b/docs/reference/manifest.rst @@ -149,6 +149,37 @@ See :func:`micropython.opt_level`. You can use the variables above, such as ``$(PORT_DIR)`` in ``base_path``. +.. function:: c_module(module_path) + + Include a C module directory in the build. + + The *module_path* should be a directory containing a ``micropython.mk`` + and/or ``micropython.cmake`` file that defines the C module. + + This function can be called multiple times to include multiple C modules: + + .. code-block:: python3 + + c_module("$(MPY_DIR)/examples/usercmodule/cexample") + c_module("$(BOARD_DIR)/../../drivers/sensor") + + Supports ``$(VAR)`` path substitution just like other manifest functions. + + ``c_module()`` only takes effect when the manifest is loaded as a + ``FROZEN_MANIFEST`` (it has no effect when the manifest is processed in + package-build or compile-only modes). Modules added with ``c_module()`` + are merged with any paths passed on the command line via + ``USER_C_MODULES``; both sources combine additively and duplicate paths + are de-duplicated. + + The referenced C module directories must already be present on disk at + build time. If a path points into a submodule, ensure that + ``make submodules`` has been run first. + + Note: on Makefile-based ports, paths containing whitespace are not + supported (a GNU make limitation). CMake-based ports handle whitespace + paths correctly. + .. function:: require(name, library=None) Require a package by name (and its dependencies) from :term:`micropython-lib`. From 9f4eeaed585f836c87ac04b95ad02acdb8b48826 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 23 May 2026 13:19:10 +1000 Subject: [PATCH 532/635] tests: Add shared manifest_c_module test for c_module() CI. Provides tests/tools/manifest_c_module.py, a shared frozen manifest that pulls in the example user C modules via c_module() and includes the port's default board manifest via $(PORT_DIR). Wires it up in ci.sh so rp2 (RPI_PICO2), stm32 (PYBV11) and esp32 (SPIRAM variant) each exercise the c_module() manifest path alongside the legacy USER_C_MODULES= command-line variable. Signed-off-by: Andrew Leech --- .github/workflows/ports_stm32.yml | 1 + tests/tools/manifest_c_module.py | 13 +++++++++++++ tools/ci.sh | 17 ++++++++++++++--- 3 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 tests/tools/manifest_c_module.py diff --git a/.github/workflows/ports_stm32.yml b/.github/workflows/ports_stm32.yml index 095a1906f66..2099b8b7c03 100644 --- a/.github/workflows/ports_stm32.yml +++ b/.github/workflows/ports_stm32.yml @@ -24,6 +24,7 @@ jobs: matrix: ci_func: # names are functions in ci.sh - stm32_pyb_build + - stm32_build_cmod - stm32_nucleo_build - stm32_misc_build runs-on: ubuntu-22.04 diff --git a/tests/tools/manifest_c_module.py b/tests/tools/manifest_c_module.py new file mode 100644 index 00000000000..0dc89bd08e6 --- /dev/null +++ b/tests/tools/manifest_c_module.py @@ -0,0 +1,13 @@ +# Manifest for testing the c_module() build feature. +# +# Shared across ports; used in CI to exercise the c_module() manifest entry +# alongside per-port builds that also test the legacy USER_C_MODULES= +# command-line variable. + +# Include the port's default board manifest. +include("$(PORT_DIR)/boards/manifest.py") + +# Test user C modules via c_module(). +c_module("$(MPY_DIR)/examples/usercmodule/cexample") +c_module("$(MPY_DIR)/examples/usercmodule/cppexample") +c_module("$(MPY_DIR)/examples/usercmodule/subpackage") diff --git a/tools/ci.sh b/tools/ci.sh index 08af9f3f796..a9c0d65d8b7 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -254,14 +254,17 @@ function ci_esp32_build_common { function ci_esp32_build_cmod_spiram_s2 { ci_esp32_build_common + # Combined USER_C_MODULES + freeze manifest test on ESP32_GENERIC. make ${MAKEOPTS} -C ports/esp32 \ USER_C_MODULES=../../../examples/usercmodule/micropython.cmake \ - FROZEN_MANIFEST=$(pwd)/ports/esp32/boards/manifest_test.py + FROZEN_MANIFEST="$(pwd)/ports/esp32/boards/manifest_test.py" # Test building native .mpy with xtensawin architecture. ci_native_mpy_modules_build xtensawin - make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC BOARD_VARIANT=SPIRAM + # Test the c_module() codepath on the SPIRAM variant. + make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC BOARD_VARIANT=SPIRAM \ + FROZEN_MANIFEST="$(pwd)/tests/tools/manifest_c_module.py" make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_S2 } @@ -500,9 +503,11 @@ function ci_rp2_build { make ${MAKEOPTS} -C ports/rp2 submodules make ${MAKEOPTS} -C ports/rp2 make ${MAKEOPTS} -C ports/rp2 BOARD=RPI_PICO_W submodules + # Legacy USER_C_MODULES coverage on RPI_PICO_W. make ${MAKEOPTS} -C ports/rp2 BOARD=RPI_PICO_W USER_C_MODULES=../../examples/usercmodule/micropython.cmake make ${MAKEOPTS} -C ports/rp2 BOARD=RPI_PICO2 submodules - make ${MAKEOPTS} -C ports/rp2 BOARD=RPI_PICO2 + # Test c_module() on RPI_PICO2. + make ${MAKEOPTS} -C ports/rp2 BOARD=RPI_PICO2 FROZEN_MANIFEST="$(pwd)/tests/tools/manifest_c_module.py" make ${MAKEOPTS} -C ports/rp2 BOARD=W5100S_EVB_PICO submodules # This build doubles as a build test for disabling threads in the config make ${MAKEOPTS} -C ports/rp2 BOARD=W5100S_EVB_PICO CFLAGS_EXTRA=-DMICROPY_PY_THREAD=0 @@ -560,6 +565,12 @@ function ci_stm32_pyb_build { make ${MAKEOPTS} -C ports/stm32/mboot BOARD=STM32F769DISC CFLAGS_EXTRA='-DMBOOT_ADDRESS_SPACE_64BIT=1 -DMBOOT_SDCARD_ADDR=0x100000000ULL -DMBOOT_SDCARD_BYTE_SIZE=0x400000000ULL -DMBOOT_FSLOAD=1 -DMBOOT_VFS_FAT=1' } +function ci_stm32_build_cmod { + make ${MAKEOPTS} -C mpy-cross + make ${MAKEOPTS} -C ports/stm32 submodules + make ${MAKEOPTS} -C ports/stm32 BOARD=PYBV11 FROZEN_MANIFEST="$(pwd)/tests/tools/manifest_c_module.py" +} + function ci_stm32_nucleo_build { # This function builds the following MCU families: F0, H5, H7, L0, L4, WB. From 4033563755d592a3dc1f91a6ba1e5e536795f12e Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 23 May 2026 13:19:16 +1000 Subject: [PATCH 533/635] unix: Migrate coverage variant to use c_module() in manifest. The unix coverage variant set USER_C_MODULES from mpconfigvariant.mk to build the example user C modules into the test binary. Move that setting into the coverage manifest as a c_module() call to exercise the new manifest API end-to-end as part of the standard coverage test build. Signed-off-by: Andrew Leech --- ports/unix/variants/coverage/manifest.py | 5 +++++ ports/unix/variants/coverage/mpconfigvariant.mk | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/ports/unix/variants/coverage/manifest.py b/ports/unix/variants/coverage/manifest.py index 2d459103ef2..7c3cec65786 100644 --- a/ports/unix/variants/coverage/manifest.py +++ b/ports/unix/variants/coverage/manifest.py @@ -3,3 +3,8 @@ freeze_as_mpy("frzmpy") freeze_mpy("$(MPY_DIR)/tests/assets") require("ssl") + +# Include example user C modules. +c_module("$(MPY_DIR)/examples/usercmodule/cexample") +c_module("$(MPY_DIR)/examples/usercmodule/cppexample") +c_module("$(MPY_DIR)/examples/usercmodule/subpackage") diff --git a/ports/unix/variants/coverage/mpconfigvariant.mk b/ports/unix/variants/coverage/mpconfigvariant.mk index cc37ba15824..ea0d8149491 100644 --- a/ports/unix/variants/coverage/mpconfigvariant.mk +++ b/ports/unix/variants/coverage/mpconfigvariant.mk @@ -10,7 +10,6 @@ CFLAGS += \ LDFLAGS += -fprofile-arcs -ftest-coverage FROZEN_MANIFEST ?= $(VARIANT_DIR)/manifest.py -USER_C_MODULES = $(TOP)/examples/usercmodule SRC_C += coverage.c SRC_CXX += coveragecpp.cpp From f076c0fbae4ee826d805d32df250e6e406388a1f Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Jul 2026 14:38:42 +1000 Subject: [PATCH 534/635] mimxrt/machine_pin: Call NVIC_SetPriority with non-neg IRQ number. `NVIC_SetPriority` is an inline function with separate paths for IRQ number negative vs non-negative. When called here to set the GPIO IRQ priority, gcc sees that the IRQ number could potentially be NotAvail_IRQn=-128 (although in practice that never occurs). Gcc then issues an array-out-of-bounds error due to the negative code path only allowing down to -16 for the IRQ number. Fix that by forcing the IRQ number to be positive, similar to how stm32 does it. That also allows the compiler to optimise away the non-negative code path. Signed-off-by: Damien George --- ports/mimxrt/irq.h | 8 ++++++++ ports/mimxrt/machine_pin.c | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/ports/mimxrt/irq.h b/ports/mimxrt/irq.h index 8202a98e874..a74841af2d1 100644 --- a/ports/mimxrt/irq.h +++ b/ports/mimxrt/irq.h @@ -28,6 +28,14 @@ #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) +// Use this macro together with NVIC_SetPriority to indicate that an IRQn is +// non-negative, which helps the compiler optimise the resulting inline function. +#if NUMBER_OF_INT_VECTORS < 128 + 16 +#define IRQn_NONNEG(irq_num) ((irq_num) & 0x7f) +#else +#define IRQn_NONNEG(irq_num) ((irq_num) & 0xff) +#endif + static inline uint32_t query_irq(void) { return __get_PRIMASK(); } diff --git a/ports/mimxrt/machine_pin.c b/ports/mimxrt/machine_pin.c index e0c940879a9..254768b4650 100644 --- a/ports/mimxrt/machine_pin.c +++ b/ports/mimxrt/machine_pin.c @@ -249,7 +249,8 @@ void machine_pin_config(const machine_pin_obj_t *self, uint8_t mode, GPIO_PortEnableInterrupts(self->gpio, 1U << self->pin); GPIO_PortClearInterruptFlags(self->gpio, ~0); - NVIC_SetPriority(irq_num, IRQ_PRI_EXTINT); + assert(irq_num >= 0); // possible values include NotAvail_IRQn=-128, but in practice that never occurs + NVIC_SetPriority(IRQn_NONNEG(irq_num), IRQ_PRI_EXTINT); EnableIRQ(irq_num); } } From 5ebe8ddd4fdcacf196e7b9a222f0b6b5d0054789 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Jul 2026 14:39:15 +1000 Subject: [PATCH 535/635] mimxrt/machine_can: Remove unused triggers and irq_flags variables. These variables are never used by the function. Signed-off-by: Damien George --- ports/mimxrt/machine_can.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/ports/mimxrt/machine_can.c b/ports/mimxrt/machine_can.c index 67dfdfbcf31..1e8fa712b52 100644 --- a/ports/mimxrt/machine_can.c +++ b/ports/mimxrt/machine_can.c @@ -491,12 +491,7 @@ static void machine_can_port_set_filter_done(machine_can_obj_t *self) { // Update interrupt configuration based on the new contents of 'self' static void machine_can_update_irqs(machine_can_obj_t *self) { struct machine_can_port *port = self->port; - uint16_t triggers = self->mp_irq_trigger; - uint64_t irq_flags = 0; uint64_t irq_tx_mask = ~((1ULL << port->flexcan_txmb_start) - 1); - if (triggers & MP_CAN_IRQ_RX) { - irq_flags |= kFLEXCAN_RxFifoFrameAvlFlag; - } // Clear all pending MB interrupt flags FLEXCAN_ClearMbStatusFlags(port->can_inst, irq_tx_mask | (kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag)); From c5401d695649e88837f26f7a69eee7646a045edb Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Jul 2026 14:39:35 +1000 Subject: [PATCH 536/635] nrf/modules/machine/uart: Fix ioctl to return the polling value. MP_STREAM_POLL was previously just returning MP_STREAM_ERROR. Signed-off-by: Damien George --- ports/nrf/modules/machine/uart.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/ports/nrf/modules/machine/uart.c b/ports/nrf/modules/machine/uart.c index e46ece7dfb4..9b9e237e264 100644 --- a/ports/nrf/modules/machine/uart.c +++ b/ports/nrf/modules/machine/uart.c @@ -511,17 +511,16 @@ static mp_uint_t mp_machine_uart_write(mp_obj_t self_in, const void *buf, mp_uin static mp_uint_t mp_machine_uart_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) { machine_uart_obj_t *self = self_in; - (void)self; - mp_uint_t ret = 0; - if (request == MP_STREAM_POLL) { uintptr_t flags = arg; + mp_uint_t ret = 0; if ((flags & MP_STREAM_POLL_RD) && uart_rx_any(self) != 0) { ret |= MP_STREAM_POLL_RD; } if ((flags & MP_STREAM_POLL_WR) && !nrfx_uart_tx_in_progress(self->p_uart)) { ret |= MP_STREAM_POLL_WR; } + return ret; } else if (request == MP_STREAM_FLUSH) { while (nrfx_uart_tx_in_progress(self->p_uart)) { MICROPY_EVENT_POLL_HOOK; From 59ee03d5f7f2e49f5fc4b76595c3a5e63f9ba947 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Jul 2026 14:40:02 +1000 Subject: [PATCH 537/635] renesas-ra/ra/ra_adc: Fix ra_adc_set_resolution to write hw register. Signed-off-by: Damien George --- ports/renesas-ra/ra/ra_adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/renesas-ra/ra/ra_adc.c b/ports/renesas-ra/ra/ra_adc.c index fc6583e80e1..97377937b2b 100644 --- a/ports/renesas-ra/ra/ra_adc.c +++ b/ports/renesas-ra/ra/ra_adc.c @@ -332,7 +332,7 @@ void ra_adc_set_resolution(uint8_t res) { adcer = adc_reg->ADCER; adcer &= (uint16_t) ~0x0006; adcer |= (uint16_t)adprc; - adc_reg->ADCER; + adc_reg->ADCER = adcer; resolution = res; } #else @@ -347,7 +347,7 @@ void ra_adc_set_resolution(uint8_t res) { adcer = adc_reg->ADCER; adcer &= (uint16_t) ~0x0006; adcer |= (uint16_t)adprc; - adc_reg->ADCER; + adc_reg->ADCER = adcer; resolution = res; } #endif From 9dbb4b3597f35cea1b0bca039dfe0d024ac51a97 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Jul 2026 14:40:40 +1000 Subject: [PATCH 538/635] stm32/Makefile: Suppress ll_usb unused-but-set-variable error on F4/F7. The F4 and F7 HAL have a volatile debug variable that is only ever set. Signed-off-by: Damien George --- ports/stm32/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 08ca1ecb3e4..e89f4640584 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -372,6 +372,10 @@ HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\ hal_pcd_ex.c \ ll_usb.c \ ) +ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7)) +# HAL F4-1.16.0 and F7-1.7.0 have an unused debug variable in USB_ActivateDedicatedEndpoint. +$(BUILD)/$(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_ll_usb.o: CFLAGS += -Wno-error=unused-but-set-variable +endif endif ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),n6)) From a7eb15b3829b6559ee0ab76580e567e7660057d1 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 27 Jul 2026 14:04:45 +1000 Subject: [PATCH 539/635] Revert "stm32/main: Initialize network subsystem before boot.py.". This reverts commit 4edef8717da3a107e27628b0765040e64a1928d7. The `mod_network_init()` call was already moved before `boot.py` in commit 7d77d3e0dd1b883ddf80ac163a5990d16f938cb6. Signed-off-by: Damien George --- ports/stm32/main.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/ports/stm32/main.c b/ports/stm32/main.c index e3e7fd014eb..a569f126e39 100644 --- a/ports/stm32/main.c +++ b/ports/stm32/main.c @@ -673,12 +673,6 @@ void stm32_main(uint32_t reset_mode) { pyexec_frozen_module(MICROPY_BOARD_FROZEN_BOOT_FILE, false); #endif - #if MICROPY_PY_NETWORK - // Initialize network subsystem before boot.py so that network - // interfaces can be instantiated in boot.py. - mod_network_init(); - #endif - // Run boot.py (or whatever else a board configures at this stage). if (MICROPY_BOARD_RUN_BOOT_PY(&state) == BOARDCTRL_GOTO_SOFT_RESET_EXIT) { goto soft_reset_exit; From 08a824a4b2e1118f5470d082048334cc5cf27192 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 30 Jul 2026 10:17:02 +1000 Subject: [PATCH 540/635] unix: Don't generate debug info unless needed for final binary. Specifically, either a debug build or a non-stripped release build. Default build config is stripped, so it's redundant to generate debug info and then strip it from the final binary. This saves about 10% compile time compared to passing -g, and more than 10% compared to passing -ggdb3. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/unix/Makefile | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/ports/unix/Makefile b/ports/unix/Makefile index 0eee7b69840..1e0d8db7e48 100644 --- a/ports/unix/Makefile +++ b/ports/unix/Makefile @@ -63,21 +63,25 @@ CFLAGS += -D_FILE_OFFSET_BITS=64 # This option has no effect on 64-bit builds. CFLAGS += -D_TIME_BITS=64 +# Debug info flag is added if either DEBUG=1 or STRIP= is passed to make +# (to produce a debug binary, or a release binary with all symbols, respectively.) +DEBUG_INFO = -g + # Debugging/Optimization ifdef DEBUG COPT ?= -Og +CFLAGS += $(DEBUG_INFO) else COPT ?= -Os COPT += -DNDEBUG +ifndef STRIP +CFLAGS += $(DEBUG_INFO) endif +endif # ifdef DEBUG # Remove unused sections. COPT += -fdata-sections -ffunction-sections -# Note: Symbols and debug information will still be stripped from the final binary -# unless "DEBUG=1" or "STRIP=" is passed to make, see README.md for details. -CFLAGS += -g - ifndef DEBUG # _FORTIFY_SOURCE is a feature in gcc/glibc which is intended to provide extra # security for detecting buffer overflows. Some distros (Ubuntu at the very least) From 24c5974375951e2746749916629515b4919f9406 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 30 Jul 2026 14:18:41 +1000 Subject: [PATCH 541/635] unix: Build DEBUG as -ggdb3. Requires a tweak in makeqstrdefs to not enable debug output from the preprocessor, as -g3 adds a lot of extra macro definitions - some of which are picked up by makeqstrdefs otherwise. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/unix/Makefile | 2 +- py/mkrules.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/unix/Makefile b/ports/unix/Makefile index 1e0d8db7e48..e46a74b69c5 100644 --- a/ports/unix/Makefile +++ b/ports/unix/Makefile @@ -65,7 +65,7 @@ CFLAGS += -D_TIME_BITS=64 # Debug info flag is added if either DEBUG=1 or STRIP= is passed to make # (to produce a debug binary, or a release binary with all symbols, respectively.) -DEBUG_INFO = -g +DEBUG_INFO = -ggdb3 # Debugging/Optimization ifdef DEBUG diff --git a/py/mkrules.mk b/py/mkrules.mk index 9c4dd26132b..a04cd141943 100644 --- a/py/mkrules.mk +++ b/py/mkrules.mk @@ -53,7 +53,7 @@ endif # QSTR generation uses the same CFLAGS, with these modifications. QSTR_GEN_FLAGS = -DNO_QSTR # Note: := to force evaluation immediately. -QSTR_GEN_CFLAGS := $(CFLAGS) +QSTR_GEN_CFLAGS := $(filter-out -g%,$(CFLAGS)) QSTR_GEN_CFLAGS += $(QSTR_GEN_FLAGS) QSTR_GEN_CXXFLAGS := $(CXXFLAGS) QSTR_GEN_CXXFLAGS += $(QSTR_GEN_FLAGS) From f013bb5195d23887ebba468ed205469ccdfecf53 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 29 Jul 2026 11:05:30 +1000 Subject: [PATCH 542/635] ci: Build esp32 port ESP32_GENERIC variant D2WD in CI. This variant has the smallest application partition in flash. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- .github/workflows/ports_esp32.yml | 4 ++-- tools/ci.sh | 9 ++++++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/.github/workflows/ports_esp32.yml b/.github/workflows/ports_esp32.yml index ac18b82fc5d..0df5d7584b8 100644 --- a/.github/workflows/ports_esp32.yml +++ b/.github/workflows/ports_esp32.yml @@ -31,8 +31,8 @@ jobs: - *oldest - *newest ci_func: # names are functions in ci.sh - - esp32_build_cmod_spiram_s2 - - esp32_build_s3_c3 + - esp32_build_cmod_spiram_d2wd + - esp32_build_s2_s3_c3 - esp32_build_c2_c5_c6 - esp32_build_h2_p4 exclude: diff --git a/tools/ci.sh b/tools/ci.sh index a9c0d65d8b7..1d509423c0e 100755 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -251,7 +251,7 @@ function ci_esp32_build_common { make ${MAKEOPTS} -C ports/esp32 submodules } -function ci_esp32_build_cmod_spiram_s2 { +function ci_esp32_build_cmod_spiram_d2wd { ci_esp32_build_common # Combined USER_C_MODULES + freeze manifest test on ESP32_GENERIC. @@ -265,12 +265,15 @@ function ci_esp32_build_cmod_spiram_s2 { # Test the c_module() codepath on the SPIRAM variant. make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC BOARD_VARIANT=SPIRAM \ FROZEN_MANIFEST="$(pwd)/tests/tools/manifest_c_module.py" - make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_S2 + + # D2WD is the variant with smallest application partition in flash + make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC BOARD_VARIANT=D2WD } -function ci_esp32_build_s3_c3 { +function ci_esp32_build_s2_s3_c3 { ci_esp32_build_common + make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_S2 make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_S3 make ${MAKEOPTS} -C ports/esp32 BOARD=ESP32_GENERIC_C3 } From 71078759f85968ad528550cb0807f962787b039d Mon Sep 17 00:00:00 2001 From: Andrii Anoshyn Date: Sun, 17 May 2026 13:44:38 +0300 Subject: [PATCH 543/635] stm32/boards/WEACT_F411_BLACKPILL: Document SPI flash pin usage and PB4. The board's on-board SPI flash chip footprint shares pins with the side gpio headers, but the README only mentioned this in general terms. Add an explicit "Pin notes" subsection that lists which pins are used by SPI1 / FLASH_* per variant, calls out the SPI3 conflict on v2.0, and documents the empirical PB4 behaviour on v3.1 reported in issue #18432. Fixes #18432. Signed-off-by: Andrii Anoshyn --- .../stm32/boards/WEACT_F411_BLACKPILL/README.md | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/README.md b/ports/stm32/boards/WEACT_F411_BLACKPILL/README.md index 9af29e6b1e4..4c9dc00a1a6 100644 --- a/ports/stm32/boards/WEACT_F411_BLACKPILL/README.md +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/README.md @@ -25,6 +25,23 @@ If these peripherals / features are enabled then these external pins must be avo there are no conflicts. [pins.csv](pins.csv) should be consulted to check all pins assigned to alternate functions on the board. +Pin notes +--------- + +The on-board SPI flash chip footprint shares pins with the gpio headers, +so when the flash is loaded and enabled in the build the following pins +should not be used for other purposes: + +* PA4, PA5 and PA7 are used by SPI1 (FLASH_CS, FLASH_SCK, FLASH_MOSI) on all + variants. +* PA6 is used as FLASH_MISO on v1.3 and v3.1; on v2.0 the MISO line is + routed to PB4 instead. Because of this, SPI3 is not usable on v2.0 when + the flash is in use (PB4 conflicts with SPI3_MISO). +* On v3.1, users have reported that PB4 can behave unreliably as a + general-purpose input when a flash chip is loaded, even though MISO is + routed to PA6 on this revision. As a workaround, configure PB4 as an + output and drive it low before any other use. + Customising the build --------------------- From 72dee9699624b56a6a2266cf40273d8cc18c1639 Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Thu, 23 Jul 2026 16:56:04 -0600 Subject: [PATCH 544/635] stm32: Add all alternate functions for STM32N6. Signed-off-by: Dryw Wade --- ports/stm32/boards/make-pins.py | 2 +- ports/stm32/boards/stm32n657_af.csv | 242 ++++++++++++++++++++-------- ports/stm32/pin.h | 4 +- ports/stm32/pin_defs_stm32.h | 2 + 4 files changed, 178 insertions(+), 72 deletions(-) diff --git a/ports/stm32/boards/make-pins.py b/ports/stm32/boards/make-pins.py index 6f8a0a659d2..b7b42fcf4ec 100755 --- a/ports/stm32/boards/make-pins.py +++ b/ports/stm32/boards/make-pins.py @@ -215,7 +215,7 @@ def print_source(self, out_source): def validate_cpu_pin_name(cpu_pin_name): boardgen.Pin.validate_cpu_pin_name(cpu_pin_name) - if not re.match("P[A-O][0-9]+(_C)?$", cpu_pin_name): + if not re.match("P[A-Q][0-9]+(_C)?$", cpu_pin_name): raise boardgen.PinGeneratorError("Invalid cpu pin name '{}'".format(cpu_pin_name)) diff --git a/ports/stm32/boards/stm32n657_af.csv b/ports/stm32/boards/stm32n657_af.csv index 4a7ad20e6d6..4c934badaee 100644 --- a/ports/stm32/boards/stm32n657_af.csv +++ b/ports/stm32/boards/stm32n657_af.csv @@ -1,69 +1,173 @@ -Port ,Pin ,AF0 ,AF1 ,AF2 ,AF3 ,AF4 ,AF5 ,AF6 ,AF7 ,AF8 ,AF9 ,AF10 ,AF11 ,AF12 ,AF13 ,AF14 ,AF15 ,ADC - , ,SYS ,LPTIM1/TIM1/2/16/17,LPTIM3/PDM_SAI1/TIM3/4/5/12/15,I3C1/LPTIM2/3/LPUART1/OCTOSPI/TIM1/8,CEC/DCMI/I2C1/2/3/4/LPTIM1/2/SPI1/I2S1/TIM15/USART1,CEC/I3C1/LPTIM1/SPI1/I2S1/SPI2/I2S2/SPI3/I2S3/SPI4/5/6,I2C4/OCTOSPI/SAI1/SPI3/I2S3/SPI4/UART4/12/USART10/USB_PD,SDMMC1/SPI2/I2S2/SPI3/I2S3/SPI6/UART7/8/12/USART1/2/3/6/10/11,LPUART1/SAI2/SDMMC1/SPI6/UART4/5/8,FDCAN1/2/FMC[NAND16]/FMC[NORmux]/FMC[NOR_RAM]/OCTOSPI/SDMMC2/TIM13/14,CRS/FMC[NAND16]/OCTOSPI/SAI2/SDMMC2/TIM8/USB_,ETH[MII/RMII]/FMC[NAND16]/OCTOSPI/SDMMC2/UART7/9/USB_PD,FMC[NAND16]/FMC[NORmux]/FMC[NOR_RAM]/FMC[SDRAM_16bit]/SDMMC1,DCMI/FMC[NAND16]/FMC[NORmux]/FMC[NOR_RAM]/LPTIM5,LPTIM3/4/5/6/TIM2/UART5,SYS ,ADC -PortA,PA0 , ,TIM2_CH1 ,TIM5_CH1 ,TIM9_CH1 ,TIM15_BKIN , , , , , , ,SDMMC2_CMD , , , , ,ADC12_INP0/ADC12_INN1 -PortA,PA1 , ,TIM2_CH2 ,TIM5_CH2 ,LPTIM3_IN1 ,TIM15_CH1N , , , , , , , , , , , ,ADC12_INP1 -PortA,PA2 , ,TIM2_CH3 ,TIM5_CH3 ,LPTIM3_IN2 ,TIM15_CH1 , , , , , , , , , , , ,ADC12_INP14 -PortA,PA3 , ,TIM16_CH1 , , , ,SPI5_NSS , , , , , , , , , , , -PortA,PA5 , , , , , , , , , , , , , , , , ,ADC2_INP18 -PortA,PA8 , , , , , , , , , , , , , , , , ,ADC12_INP5 -PortA,PA9 , , , , , , , , , , , , , , , , ,ADC12_INP10 -PortA,PA10, , , , , , , , , , , , , , , , ,ADC12_INP11/ADC12_INN10 -PortA,PA11, , , , , ,SPI2_NSS ,CAN1_RX , ,UART4_RX , , , , , , , ,ADC12_INP12/ADC12_INN11 -PortA,PA12, , , , , ,SPI2_SCK ,CAN1_TX , ,UART4_TX , , , , , , , ,ADC12_INP13/ADC12_INN12 -PortB,PB4 , , , , , , , , , , , ,SDMMC2_D3 , , , , , -PortB,PB6 , , , , , ,SPI4_MISO , ,TIM15_CH1 , , , , , , , , , -PortB,PB7 , , , , , ,SPI4_MOSI , ,TIM15_CH2 , , , , , , , , , -PortB,PB8 , , , , , , , , , , , ,SDMMC2_D0 , , , , , -PortB,PB9 , , , , , , , , , , , ,SDMMC2_D2 , , , , , -PortB,PB10, ,TIM2_CH3 , ,I3C2_SCL ,I2C2_SCL , , ,USART3_TX , , , , , , , , , -PortB,PB11, ,TIM2_CH4 , ,I3C2_SDA ,I2C2_SDA , , ,USART3_RX , , , , , , , , , -PortC,PC8 , , , , , , , , , , ,SDMMC1_D0 , , , , , , -PortC,PC9 , , , , , , , , , , ,SDMMC1_D1 , , , , , , -PortC,PC10, , , , , , , , , , ,SDMMC1_D2 , , , , , , -PortC,PC11, , , , , , , , , , ,SDMMC1_D3 , , , , , , -PortC,PC12, , , , , , , , , , ,SDMMC1_CK , , , , , , -PortD,PD1 , , , , , , , , , , , ,ETH1_MDC , , , , , -PortD,PD2 , , , , , , , , , , , ,SDMMC2_CK , , , , , -PortD,PD5 , , , , , , , ,USART2_TX , , , , , , , , , -PortD,PD6 , , , , ,TIM15_CH2 , , , , , , , , , , , , -PortD,PD7 , , , , , ,SPI2_MOSI , , , , , , , , , , , -PortD,PD8 , , , , , , , ,USART3_TX , , , , , , , , , -PortD,PD9 , , , , , , , ,USART3_RX , , , , , , , , , -PortD,PD11, , , , , ,SPI2_MISO , , , , , , , , , , , -PortD,PD12, , , , , , , , , , , ,ETH1_MDIO , , , , , -PortD,PD13, , ,TIM4_CH2 , , , , , , , , , , , , , , -PortE,PE5 , , , , , , , ,USART1_TX , , , , , , , , , -PortE,PE6 , , , , , , , ,USART1_RX , , , , , , , , , -PortE,PE7 , , , , , , , , ,UART7_RX , , , , , , , , -PortE,PE8 , , , , , , , , ,UART7_TX , , , , , , , , -PortE,PE11, , , , , ,SPI4_NSS ,CAN3_TX , , , , , , , , , , -PortE,PE12, , , , , ,SPI4_SCK ,CAN3_RX , , , , , , , , , , -PortE,PE13, , , , ,I2C4_SCL , , , , , , , , , , , , -PortE,PE14, , , , ,I2C4_SDA , , , , , , , , , , , , -PortE,PE15, , , , , ,SPI5_SCK , , , , , , , , , , , -PortF,PF0 , , , , , , , , , , , , ,ETH1_RGMII_GTX_CLK , , , , -PortF,PF2 , , , , , , , , , , , ,ETH1_RGMII_CLK125 , , , , , -PortF,PF3 , , , , , , , ,USART2_RTS , , , , , , , , ,ADC1_INP16 -PortF,PF4 , , , , , , , , , , , ,ETH1_MDIO , , , , , -PortF,PF6 , , , , , , , ,USART2_RX , , , , , , , , , -PortF,PF7 , , , , , , , , , , , ,ETH1_RMII_REF_CLK/ETH1_RGMII_RX_CLK , , , , , -PortF,PF8 , , , , , , , , , , , ,ETH1_RGMII_RXD2 , , , , , -PortF,PF9 , , , , , , , , , , , ,ETH1_RGMII_RXD3 , , , , , -PortF,PF10, , , , , , , , , , , ,ETH1_RMII_CRS_DV/ETH1_RGMII_RX_CTL , , , , , -PortF,PF11, , , , , , , , , , , ,ETH1_RMII_TX_EN/ETH1_RGMII_TX_CTL , , , , , -PortF,PF12, , , , , , , , , , , ,ETH1_RMII_TXD0/ETH1_RGMII_TXD0 , , , , , -PortF,PF13, , , , , , , , , , , ,ETH1_RMII_TXD1/ETH1_RGMII_TXD1 , , , , , -PortF,PF14, , , , , , , , , , , ,ETH1_RMII_RXD0/ETH1_RGMII_RXD0 , , , , , -PortF,PF15, , , , , , , , , , , ,ETH1_RMII_RXD1/ETH1_RGMII_RXD1 , , , , , -PortG,PG0 , , ,TIM12_CH1 , , , , , , , , , , , , , , -PortG,PG1 , , , , , ,SPI5_MISO , , , , , , , , , , , -PortG,PG2 , , , , , ,SPI5_MOSI , , , , , , , , , , , -PortG,PG3 , , , , , , , , , , , ,ETH1_RGMII_TXD2 , , , , , -PortG,PG4 , , , , , , , , , , , ,ETH1_RGMII_TXD3 , , , , , -PortG,PG5 , , , , , , , ,USART2_CTS , , , , , , , , , -PortG,PG8 , , , , , , , , , , , ,SDMMC2_D1 , , , , , -PortG,PG11, , , , , , , , , , , ,ETH1_MDC , , , , , -PortG,PG12, ,TIM17_CH1 , , , , , , , , , , , , , , , -PortG,PG13, , ,TIM4_CH1 , , , , ,USART3_RTS , , , , , , , , , -PortG,PG15, , , , , , , , , , , , , , , , ,ADC12_INP7/ADC12_INN3 -PortC,PH2 , , , , , , , , , , ,SDMMC1_CMD , , , , , , +Port ,Pin ,AF0 ,AF1 ,AF2 ,AF3 ,AF4 ,AF5 ,AF6 ,AF7 ,AF8 ,AF9 ,AF10 ,AF11 ,AF12 ,AF13 ,AF14 ,AF15 ,ADC + , ,SYS ,TIM1/2/16/17/LPTIM1 ,PDM_SAI1/TIM3/4/5/12/15 ,LPUART1/TIM8/LPTIM2/3/DFSDM1/OCSPI1/2 ,I2C1/2/3/4/USART1/TIM15/LPTIM2/DFSDM1/2/DCMI/PSSI/CEC ,SPI1/I2S1/SPI2/I2S2/SPI3/I2S3/SPI4/5/6/I2S6/CEC ,SPI3/I2S3/SAI1/I2C4/UART4/DFSDM1/2/OCSPI1/USB_PD ,SPI2/I2S2/SPI3/I2S3/SPI6/I2S6/USART1/2/3/6/UART7/OCSPI2/SDIO1 ,SPI6/I2S6/SAI2/UART4/5/8/LPUART1/SDIO1/USB_PD/SPDIFRX ,FDCAN1/2/TIM13/14/OCSPI1/2/FMC/SDIO2/LCD/SPDIFRX ,SAI2/TIM8/OCSPI1/FMC/SDIO2/OTG1_HS/OTG1_FS/LCD/COMP/CRS ,I2C4/USART10/UART7/9/SWPMI1/TIM1/8/DFSDM1/2/OCSPI1/SDIO2/MDIOS/USB_PD/LCD/COMP ,TIM1/8/FMC/SDIO1/MDIOS/LCD/COMP ,TIM1/DCMI/PSSI/LCD/COMP ,UART5/LCD ,SYS ,ADC +PortA ,PA0 , ,TIM2_CH1 ,TIM5_CH1 ,TIM9_CH1 ,TIM15_BKIN ,SPI6_NSS/I2S6_WS , ,USART2_CTS/USART2_NSS ,UART4_TX , ,SAI2_SD_B ,SDMMC2_CMD ,FMC_AD7/FMC_D7 , ,LCD_G3 ,HDP0 ,ADC12_INP0/ADC12_INN1 +PortA ,PA1 , ,TIM2_CH2 ,TIM5_CH2 ,LPTIM3_IN1 ,TIM15_CH1N , , ,USART2_RTS ,UART4_RX ,DCMIPP_D0/DCMI_D0/PSSI_D0 ,SAI2_MCLK_B , ,FMC_AD6/FMC_D6 , ,LCD_G2 ,HDP1 ,ADC12_INP1 +PortA ,PA2 , ,TIM2_CH3 ,TIM5_CH3 ,LPTIM3_IN2 ,TIM15_CH1 , , ,USART2_TX , , ,SAI2_SCK_B ,MDIOS_MDIO ,FMC_AD5/FMC_D5 , ,LCD_B7 ,HDP2 ,ADC12_INP14 +PortA ,PA3 , ,TIM16_CH1 , , , ,SPI5_NSS ,SAI1_SD_B , ,UART7_RX , , , ,FMC_A17/FMC_ALE , , ,EVENTOUT , +PortA ,PA4 , , , , , ,SPI5_MOSI , ,USART6_RX , ,DCMIPP_D3/DCMI_D3/PSSI_D3 , , ,FMC_A13 , , ,EVENTOUT , +PortA ,PA5 ,PWR_CSTOP ,TIM2_CH1 ,TIM2_ETR ,TIM9_CH2 ,I3C1_SCL ,SPI1_SCK/I2S1_CK , , ,SPI6_SCK/I2S6_CK ,DCMIPP_D8/DCMI_D8/PSSI_D8 ,TIM10_CH1 , ,FMC_NOE , ,LCD_CLK ,HDP5 ,ADC2_INP18 +PortA ,PA6 ,BOOT1 ,TIM1_BKIN ,TIM3_CH1 ,LPTIM3_ETR ,I3C1_SDA ,SPI1_MISO/I2S1_SDI , , ,SPI6_MISO/I2S6_SDI ,DCMIPP_PIXCLK/DCMI_PIXCLK/PSSI_PDCK ,TIM13_CH1 ,MDIOS_MDC ,LCD_B7 , ,LCD_HSYNC ,HDP6 ,ADC12_INP3 +PortA ,PA7 , ,TIM1_CH1N ,TIM3_CH2 , , ,SPI1_MOSI/I2S1_SDO , ,USART1_RX ,SPI6_MOSI/I2S6_SDO , ,LCD_R4 ,TIM14_CH1 ,FMC_RNB , ,LCD_B1 ,HDP7 , +PortA ,PA8 ,MCO1 ,TIM1_CH1 ,I3C2_SCL , ,I2C3_SCL , , ,USART1_CK , ,TIM11_CH1 ,UART7_RX , ,FMC_AD4/FMC_D4 , ,LCD_B6 ,HDP0 ,ADC12_INP5 +PortA ,PA9 , ,TIM1_CH2 ,I3C2_SDA ,LPUART1_TX ,I2C3_SDA ,SPI2_SCK/I2S2_CK , ,USART1_TX , ,DCMIPP_D0/DCMI_D0/PSSI_D0 , , ,FMC_AD3/FMC_D3 , ,LCD_B5 ,HDP1 ,ADC12_INP10 +PortA ,PA10 ,PWR_CSLEEP ,TIM1_CH3 , ,LPUART1_RX , , , ,USART1_RX , ,DCMIPP_D1/DCMI_D1/PSSI_D1 , ,MDIOS_MDIO ,FMC_AD2/FMC_D2 , ,LCD_B4 ,HDP2 ,ADC12_INP11/ADC12_INN10 +PortA ,PA11 , ,TIM1_CH4 , ,LPUART1_CTS , ,SPI2_NSS/I2S2_WS ,FDCAN1_RX ,USART1_CTS/USART1_NSS ,UART4_RX , , , ,FMC_AD1/FMC_D1 , ,LCD_B3 ,HDP3 ,ADC12_INP12/ADC12_INN11 +PortA ,PA12 , ,TIM1_ETR , ,LPUART1_RTS , ,SPI2_SCK/I2S2_CK ,FDCAN1_TX ,USART1_RTS ,UART4_TX , ,SAI2_FS_B , ,FMC_AD0/FMC_D0 , ,LCD_B2 ,HDP4 ,ADC12_INP13/ADC12_INN12 +PortA ,PA13 ,JTMS/SWDIO , , , , , , , , , , , , , , ,HDP5 , +PortA ,PA14 ,JTCK/SWCLK , , , , , , , , , , , , , , ,HDP6 , +PortA ,PA15 ,JTDI ,TIM2_CH1 ,TIM2_ETR , , ,SPI1_NSS/I2S1_WS ,SPI3_NSS/I2S3_WS ,SPI6_NSS/I2S6_WS ,UART4_RTS , ,UART7_TX , ,FMC_D15/FMC_AD15 , ,LCD_R5 ,HDP7 , +PortB ,PB0 ,TRACED1 ,TIM1_CH4 ,SAI1_D2 ,ADF1_SDI0 ,MDF1_SDI2 ,SPI4_NSS ,SAI1_FS_A ,TIM15_CH1N , ,DCMIPP_D4/DCMI_D4/PSSI_D4 , , ,FMC_D13/FMC_AD13 , , ,EVENTOUT , +PortB ,PB1 , ,TIM1_CH3N ,TIM3_CH4 ,TIM9_CH2 , , ,FDCAN2_TX ,USART2_TX , , , , ,FMC_NOE , ,LCD_R1 ,HDP1 , +PortB ,PB2 ,RTC_OUT2 ,TIM1_CH1 ,SAI1_D1 ,ADF1_SDI0 ,MDF1_SDI1 , ,SAI1_SD_A ,SPI3_MOSI/I2S3_SDO , , , , ,FMC_D2/FMC_AD2 , ,LCD_B2 ,HDP2 , +PortB ,PB3 ,TRACECLK ,TIM1_CH4N ,GFXTIM_FCKCAL , ,MDF1_CKI1 , , ,USART1_CK , , ,SAI2_FS_B , ,FMC_NBL1 ,GFXTIM_LCKCAL ,FMC_A23 ,HDP0 , +PortB ,PB4 ,NJTRST ,TIM16_BKIN ,TIM3_CH1 ,LPTIM4_ETR , ,SPI1_MISO/I2S1_SDI ,SPI3_MISO/I2S3_SDI ,SPI2_NSS/I2S2_WS ,SPI6_MISO/I2S6_SDI ,DCMIPP_VSYNC/DCMI_VSYNC/PSSI_RDY ,UART7_TX ,SDMMC2_D3 ,FMC_D13/FMC_AD13 , ,LCD_R3 ,HDP4 , +PortB ,PB5 ,JTDO/TRACESWO ,TIM17_BKIN ,TIM3_CH2 ,LPTIM4_OUT ,I2C1_SMBA ,SPI1_MOSI/I2S1_SDO ,FDCAN2_RX ,SPI3_MOSI/I2S3_SDO ,SPI6_MOSI/I2S6_SDO ,DCMIPP_D10/DCMI_D10/PSSI_D10 , ,UART5_RX ,FMC_D12/FMC_AD12 , ,LCD_R2 ,HDP5 , +PortB ,PB6 ,TRACED2 , ,SAI1_CK2 ,ADF1_CCK1 ,MDF1_CCK1 ,SPI4_MISO ,SAI1_SCK_A ,TIM15_CH1 , ,DCMIPP_D6/DCMI_D6/PSSI_D6 , , ,FMC_D14/FMC_AD14 , , ,EVENTOUT , +PortB ,PB7 ,TRACED3 ,TIM1_BKIN2 ,SAI1_D1 ,ADF1_SDI0 ,MDF1_SDI1 ,SPI4_MOSI ,SAI1_SD_A ,TIM15_CH2 , ,DCMIPP_D7/DCMI_D7/PSSI_D7 ,SAI2_MCLK_B , ,FMC_D15/FMC_AD15 , , ,EVENTOUT , +PortB ,PB8 , , , , , ,SPI1_MISO/I2S1_SDI , ,USART6_RX ,SPDIFRX1_IN3 ,DCMIPP_VSYNC/DCMI_VSYNC/PSSI_RDY ,SAI2_FS_B ,SDMMC2_D0 ,FMC_D1/FMC_AD1 , , ,EVENTOUT , +PortB ,PB9 , ,LPTIM1_IN2 , , , ,SPI1_SCK/I2S1_CK ,USART10_TX , ,SPDIFRX1_IN0 ,DCMIPP_D3/DCMI_D3/PSSI_D3 , ,SDMMC2_D2 ,FMC_D3/FMC_AD3 , , ,EVENTOUT , +PortB ,PB10 , ,TIM2_CH3 ,I3C2_SCL ,LPTIM2_IN1 ,I2C2_SCL ,SPI2_SCK/I2S2_CK , ,USART3_TX , , , , ,FMC_D11/FMC_AD11 , ,LCD_G7 ,HDP2 ,ADC12_INP8/ADC12_INN4 +PortB ,PB11 , ,TIM2_CH4 ,I3C2_SDA ,LPTIM2_ETR ,I2C2_SDA , , ,USART3_RX , , , , ,FMC_D10/FMC_AD10 , ,LCD_G6 ,HDP3 ,ADC12_INP4 +PortB ,PB12 , ,TIM1_BKIN , ,LPTIM2_IN2 ,I2C2_SMBA ,SPI2_NSS/I2S2_WS ,FDCAN2_RX ,USART3_CK , , , ,UART5_RX ,FMC_D9/FMC_AD9 , ,LCD_G5 ,HDP4 , +PortB ,PB13 ,TRACED0 ,LPTIM1_CH1 ,TIM8_CH3N , , ,SPI6_SCK/I2S6_CK ,USART10_CTS/USART10_NSS ,USART6_CTS/USART6_NSS , , , ,SDMMC2_D6 ,FMC_D5/FMC_AD5 , ,LCD_CLK ,EVENTOUT , +PortB ,PB14 , ,LPTIM1_CH2 ,TIM8_CH4N , , , ,USART10_CK ,USART6_CTS/USART6_NSS , ,DCMIPP_D10/DCMI_D10/PSSI_D10 , , ,FMC_D7/FMC_AD7 , ,LCD_HSYNC ,EVENTOUT , +PortB ,PB15 , , , , , ,SPI6_NSS/I2S6_WS , ,USART6_RTS ,SPDIFRX1_IN2 , , , ,FMC_D0/FMC_AD0 , ,LCD_G4 ,EVENTOUT , +PortC ,PC0 , ,TIM2_CH2 , ,LPTIM4_IN1 ,MDF1_CKI1 ,SPI1_SCK/I2S1_CK ,SPI3_SCK/I2S3_CK , ,SPI6_SCK/I2S6_CK ,DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE ,UART7_RX ,SDMMC2_D2 ,FMC_D14/FMC_AD14 , ,LCD_R4 ,HDP3 , +PortC ,PC1 , ,TIM17_CH1 ,TIM4_CH4 , ,I2C1_SDA ,SPI2_NSS/I2S2_WS ,FDCAN1_TX ,I3C1_SDA ,UART4_TX ,DCMIPP_D7/DCMI_D7/PSSI_D7 ,SDMMC1_D5 ,SDMMC2_D5 ,SDMMC1_CDIR , , ,HDP1 , +PortC ,PC2 , , ,SAI1_D1 ,ADF1_SDI0 ,MDF1_SDI1 ,SPI3_MOSI/I2S3_SDO ,SAI1_SCK_A ,USART2_RX , ,DCMIPP_D13/DCMI_D13/PSSI_D13 , ,SDMMC2_CK ,FMC_NE3 , ,FMC_RNB ,EVENTOUT , +PortC ,PC3 , , , , , ,SPI1_MOSI/I2S1_SDO , ,USART2_CK ,SPDIFRX1_IN0 ,DCMIPP_D2/DCMI_D2/PSSI_D2 , ,SDMMC2_CMD ,FMC_D8/FMC_AD8 , , ,EVENTOUT , +PortC ,PC4 , ,TIM1_CH2N ,TIM12_CH1 ,LPTIM2_CH2 ,USART1_TX ,SPI2_MISO/I2S2_SDI , ,USART3_RTS ,UART4_RTS , ,LCD_VSYNC ,SDMMC2_D0 ,FMC_NE1 , ,LCD_DE ,HDP6 , +PortC ,PC5 , , , , , ,SPI1_NSS/I2S1_WS , , , ,DCMIPP_D2/DCMI_D2/PSSI_D2 ,SAI2_SD_B ,SDMMC2_D1 ,FMC_NWE , , ,EVENTOUT , +PortC ,PC6 , ,TIM1_CH1 ,TIM3_CH1 ,TIM9_CH1 , ,I2S2_MCK , ,USART6_TX , ,DCMIPP_D1/DCMI_D1/PSSI_D1 ,SDMMC1_D6 ,SDMMC2_D6 ,SDMMC1_D0DIR , , ,HDP6 , +PortC ,PC7 ,DBTRGIO ,TIM16_CH1N ,TIM3_CH2 ,TIM9_CH2 , , ,I2S3_MCK ,USART6_RX , ,DCMIPP_D1/DCMI_D1/PSSI_D1 ,SDMMC1_D7 ,SDMMC2_D7 ,SDMMC1_D123DIR , , ,HDP7 , +PortC ,PC8 ,TRACED1 , ,TIM3_CH3 , ,I2C3_SMBA , ,UCPD1_FRSTX1 ,USART6_CK , ,DCMIPP_D2/DCMI_D2/PSSI_D2 ,SDMMC1_D0 ,UART5_RTS ,FMC_NE4 , ,LCD_B0 ,HDP0 , +PortC ,PC9 ,MCO2 , ,TIM3_CH4 , ,I2C3_SDA ,AUDIOCLK ,UCPD1_FRSTX2 ,USART6_RX , ,DCMIPP_D3/DCMI_D3/PSSI_D3 ,SDMMC1_D1 ,UART5_CTS , , ,LCD_B3 ,HDP1 , +PortC ,PC10 , ,TIM1_BKIN ,I3C2_SCL , ,I2C4_SCL , ,SPI3_SCK/I2S3_CK ,USART3_TX ,UART4_TX ,DCMIPP_D14/PSSI_D14 ,SDMMC1_D2 , ,FMC_CLK , , ,HDP2 , +PortC ,PC11 , , ,I3C2_SDA , ,I2C4_SDA , ,SPI3_MISO/I2S3_SDI ,USART3_RX ,UART4_RX ,DCMIPP_D4/DCMI_D4/PSSI_D4 ,SDMMC1_D3 , , , , ,HDP3 , +PortC ,PC12 ,TRACED3 ,TIM1_CH4 , , ,TIM15_CH1 ,SPI6_SCK/I2S6_CK ,SPI3_MOSI/I2S3_SDO ,USART3_CK , ,DCMIPP_D9/DCMI_D9/PSSI_D9 ,SDMMC1_CK ,UART5_TX ,FMC_NL , , ,HDP4 , +PortC ,PC13 , , , , , , , , , , , , , , , ,HDP5 , +PortC ,PC14 , , , , , , , , , , , , , , , , , +PortC ,PC15 , , , , , , , , , , , , , , , , , +PortD ,PD0 , ,TIM1_ETR , , , , ,FDCAN1_RX ,UART9_CTS ,UART4_RX ,DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE , , ,FMC_A6 , ,FMC_A22 ,EVENTOUT , +PortD ,PD1 , , , , , , ,FDCAN1_TX , ,UART4_TX , , ,ETH1_MDC ,FMC_A7 , ,FMC_A23 ,EVENTOUT , +PortD ,PD2 ,TRACED0 ,TIM1_CH3 ,SAI1_D1 ,ADF1_SDI0 ,MDF1_SDI1 ,SPI2_MOSI/I2S2_SDO ,SAI1_SD_A ,TIM15_CH1N , , ,MDIOS_MDC ,SDMMC2_CK ,FMC_A0 , ,FMC_A16/FMC_CLE ,HDP1 , +PortD ,PD3 , , , , ,I2C2_SMBA , ,USART10_RX ,USART6_CTS , ,DCMIPP_D14/PSSI_D14 , ,ETH1_PHY_INTN ,FMC_A10 , , ,EVENTOUT , +PortD ,PD4 , ,TIM1_BKIN2 , , ,I2C2_SDA ,SPI5_MISO , ,USART6_RTS , ,DCMIPP_D9/DCMI_D9/PSSI_D9 , , ,FMC_A11 , , ,EVENTOUT , +PortD ,PD5 , ,TIM1_CH4N , , , , , ,USART2_TX , ,DCMIPP_PIXCLK/DCMI_PIXCLK/PSSI_PDCK , ,SDMMC2_D7 ,FMC_D6/FMC_AD6 , , ,EVENTOUT , +PortD ,PD6 , ,TIM1_CH1 , , ,TIM15_CH2 ,SPI2_MISO/I2S2_SDI , , , , , , ,FMC_A1 , ,FMC_A17/FMC_ALE ,HDP2 , +PortD ,PD7 , ,TIM1_CH2 , , ,TIM15_CH1N ,SPI2_MOSI/I2S2_SDO ,SPI3_NSS/I2S3_WS , , ,DCMIPP_D0/DCMI_D0/PSSI_D0 , , ,FMC_A2 , ,FMC_A18 ,HDP3 , +PortD ,PD8 , , , , , , , ,USART3_TX ,SPDIFRX1_IN1 ,DCMIPP_D11/DCMI_D11/PSSI_D11 , , ,FMC_NBL0 , ,LCD_R7 ,EVENTOUT , +PortD ,PD9 , , , , , , , ,USART3_RX , ,DCMIPP_D11/DCMI_D11/PSSI_D11 , , ,FMC_SDCLK , ,LCD_R1 ,EVENTOUT , +PortD ,PD10 ,TRACECLK ,TIM1_ETR , , ,MDF1_CKI3 ,I2S1_MCK ,UCPD1_FRSTX1 , ,SPDIFRX1_IN2 , ,SAI2_FS_B , ,FMC_A3 ,GFXTIM_TE ,FMC_A19 ,HDP4 , +PortD ,PD11 , , , , ,I2C4_SDA ,SPI2_MISO/I2S2_SDI ,UCPD1_FRSTX1 , , ,DCMIPP_D15/PSSI_D15 ,SDMMC1_D0 , ,FMC_D8/FMC_AD8 , , ,EVENTOUT , +PortD ,PD12 , , ,SAI1_D3 , ,MDF1_SDI3 , ,UCPD1_FRSTX2 , ,SPDIFRX1_IN3 ,DCMIPP_D12/DCMI_D12/PSSI_D12 , ,ETH1_MDIO ,FMC_A5 , ,FMC_A21 ,HDP5 , +PortD ,PD13 , ,LPTIM1_CH1 ,TIM4_CH2 , , , ,UCPD1_FRSTX2 ,UART9_RTS , ,DCMIPP_D13/DCMI_D13/PSSI_D13 ,SAI2_SCK_A , ,FMC_D4/FMC_AD4 , ,LCD_R6 ,EVENTOUT , +PortD ,PD14 , , , , ,I2C2_SCL , ,USART10_RX , , , , , ,FMC_A9 , , ,EVENTOUT , +PortD ,PD15 , , , , ,I2C2_SDA , ,USART10_TX , , , , , ,FMC_A8 , ,LCD_R2 ,EVENTOUT , +PortE ,PE0 , ,LPTIM1_ETR ,TIM4_ETR ,LPTIM2_ETR , , , ,USART3_RX ,UART8_RX ,DCMIPP_D2/DCMI_D2/PSSI_D2 ,SAI2_MCLK_A , ,FMC_D9/FMC_AD9 , , ,EVENTOUT , +PortE ,PE1 , ,LPTIM1_IN2 , ,LPTIM2_CH2 , , , ,USART3_TX ,UART8_TX ,DCMIPP_D8/DCMI_D8/PSSI_D8 , , ,FMC_D10/FMC_AD10 , , ,EVENTOUT , +PortE ,PE2 ,TRACECLK ,LPTIM5_IN1 ,SAI1_CK1 ,ADF1_CCK0 ,MDF1_CCK0 ,SPI4_SCK ,SAI1_MCLK_A ,UCPD1_FRSTX1 , , , , ,FMC_D11/FMC_AD11 ,TIM1_CH2N , ,EVENTOUT , +PortE ,PE3 ,TRACED0 ,LPTIM5_ETR , , ,MDF1_CKI2 , ,SAI1_SD_B ,TIM15_BKIN , , , , ,FMC_D12/FMC_AD12 , , ,EVENTOUT , +PortE ,PE4 , ,LPTIM1_IN1 , , , ,SPI6_MISO/I2S6_SDI ,USART10_RX ,USART6_RTS ,SPDIFRX1_IN1 ,DCMIPP_D5/DCMI_D5/PSSI_D5 , ,SDMMC2_D3 ,FMC_RNB , ,LCD_G1 ,EVENTOUT , +PortE ,PE5 , ,TIM16_CH1N ,TIM4_CH1 ,LPUART1_TX ,I2C1_SCL ,I3C1_SCL ,FDCAN2_TX ,USART1_TX , ,DCMIPP_D5/DCMI_D5/PSSI_D5 , ,UART5_TX ,FMC_SDNE1 , , ,HDP6 , +PortE ,PE6 , ,TIM17_CH1N ,TIM4_CH2 ,LPUART1_RX ,I2C1_SDA ,I3C1_SDA , ,USART1_RX , ,DCMIPP_VSYNC/DCMI_VSYNC/PSSI_RDY ,DCMIPP_D1/DCMI_D1/PSSI_D1 ,UART5_TX ,FMC_SDCKE1 , , ,HDP7 , +PortE ,PE7 , ,TIM1_ETR , , ,MDF1_CKI0 , , , ,UART7_RX , ,SAI2_SD_B , ,FMC_A4 , ,FMC_A20 ,EVENTOUT , +PortE ,PE8 , ,TIM1_CH1N , , ,MDF1_SDI0 , , ,USART3_TX ,UART7_TX ,DCMIPP_D4/DCMI_D4/PSSI_D4 , , ,FMC_A12 , , ,EVENTOUT , +PortE ,PE9 , ,TIM1_CH1 , , ,MDF1_CKI4 , , , ,UART7_RTS , , , ,FMC_A14/FMC_BA0 , , ,EVENTOUT , +PortE ,PE10 ,TRACECLK ,TIM1_CH2N , , ,MDF1_SDI4 , , ,USART3_RX ,UART7_CTS ,DCMIPP_D3/DCMI_D3/PSSI_D3 , , ,FMC_A15/FMC_BA1 , , ,EVENTOUT , +PortE ,PE11 , ,TIM1_CH2 , , ,MDF1_CKI5 ,SPI4_NSS ,FDCAN3_TX , , , ,SAI2_SD_B , ,FMC_SDNWE , ,LCD_VSYNC ,EVENTOUT , +PortE ,PE12 , ,TIM1_CH3N , , ,MDF1_SDI5 ,SPI4_SCK ,FDCAN3_RX , , , ,SAI2_SCK_B , ,FMC_NRAS , , ,EVENTOUT , +PortE ,PE13 , ,TIM1_CH3 , ,ADF1_CCK0 ,I2C4_SCL ,SPI4_MISO , , , , ,SAI2_FS_B , ,FMC_NCAS , , ,EVENTOUT , +PortE ,PE14 , ,TIM1_CH4 ,GFXTIM_FCKCAL ,ADF1_CCK1 ,I2C4_SDA ,SPI4_MOSI , , , , ,SAI2_MCLK_B , ,FMC_SDNE0 ,GFXTIM_LCKCAL ,FMC_NWE ,EVENTOUT , +PortE ,PE15 , ,TIM1_BKIN ,GFXTIM_LCKCAL , ,I2C4_SMBA ,SPI5_SCK ,USART10_CK ,USART2_CK , , ,SDMMC1_D0 , ,FMC_SDCKE0 ,GFXTIM_FCKCAL , ,EVENTOUT , +PortF ,PF0 , ,LPTIM5_OUT ,TIM4_CH4 , , , ,UCPD1_FRSTX2 ,UART9_TX ,UART8_RTS ,DCMIPP_D9/DCMI_D9/PSSI_D9 , ,ETH1_MII_TX_CLK ,ETH1_RGMII_GTX_CLK , , ,EVENTOUT , +PortF ,PF1 , ,LPTIM1_CH2 ,TIM4_CH3 ,LPTIM2_CH1 , , ,UCPD1_FRSTX1 ,UART9_RX ,UART8_CTS ,DCMIPP_D7/DCMI_D7/PSSI_D7 , ,ETH1_TX_ER , , , ,EVENTOUT , +PortF ,PF2 , ,TIM1_CH3N , , , ,SPI2_SCK/I2S2_CK ,FDCAN3_TX ,USART2_CTS/USART2_NSS , , , ,ETH1_RGMII_CLK125 ,FMC_NWAIT , ,LCD_B1 ,EVENTOUT , +PortF ,PF3 , , , , , , ,FDCAN3_RX ,USART2_RTS , ,DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE , ,ETH1_PPS_OUT ,FMC_NL , ,LCD_R4 ,EVENTOUT ,ADC1_INP16 +PortF ,PF4 , , ,TIM5_ETR ,LPTIM3_CH2 , ,SPI1_NSS/I2S1_WS ,SPI3_NSS/I2S3_WS ,USART2_CK ,SPI6_NSS/I2S6_WS ,DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE , ,ETH1_MDIO , , ,LCD_R3 ,HDP4 ,ADC1_INP18 +PortF ,PF5 , ,TIM1_ETR , ,LPTIM2_IN2 , , , ,USART3_CTS/USART3_NSS , ,DCMIPP_D6/DCMI_D6/PSSI_D6 ,SAI2_SD_A ,ETH1_CLK ,FMC_NE3 , ,LCD_G0 ,EVENTOUT , +PortF ,PF6 , ,TIM2_CH4 ,TIM5_CH4 ,LPTIM3_CH1 ,TIM15_CH2 ,I2S6_MCK ,SPI4_RDY ,USART2_RX , ,SPI5_RDY ,SPI1_RDY ,ETH1_MII_COL ,GFXTIM_FCKCAL ,TIM1_CH3 ,LCD_DE ,HDP3 ,ADC12_INP15 +PortF ,PF7 , ,TIM1_CH2N ,TIM3_CH3 ,TIM9_CH1 , ,SPI1_SCK/I2S1_CK , , ,UART4_CTS , , ,ETH1_MII_RX_CLK/ETH1_RMII_REF_CLK/ETH1_RGMII_RX_CLK ,GFXTIM_TE , ,LCD_VSYNC ,HDP0 ,ADC12_INP9/ADC12_INN5 +PortF ,PF8 ,TRACECLK , , , , , , ,UART9_TX , , , ,ETH1_MII_RXD2/ETH1_RGMII_RXD2 ,FMC_NWE , ,LCD_R6 ,EVENTOUT , +PortF ,PF9 ,TRACED0 , , , , , , , , , , ,ETH1_MII_RXD3/ETH1_RGMII_RXD3 , , ,LCD_HSYNC ,EVENTOUT , +PortF ,PF10 , ,TIM16_BKIN ,SAI1_D3 , ,MDF1_SDI3 , ,UCPD1_FRSTX1 , ,UART7_RX ,DCMIPP_D11/DCMI_D11/PSSI_D11 ,DCMIPP_D15/PSSI_D15 ,ETH1_MII_RX_DV/ETH1_RMII_CRS_DV/ETH1_RGMII_RX_CTL , , ,LCD_R1 ,EVENTOUT , +PortF ,PF11 , , , , , ,SPI5_MOSI , , , ,DCMIPP_D15/PSSI_D15 ,SAI2_SD_B ,ETH1_MII_TX_EN/ETH1_RMII_TX_EN/ETH1_RGMII_TX_CTL , , ,LCD_B0 ,EVENTOUT ,ADC1_INP2 +PortF ,PF12 , , , , ,USART1_RX ,SPI5_MISO , , , ,DCMIPP_D13/DCMI_D13/PSSI_D13 , ,ETH1_MII_TXD0/ETH1_RMII_TXD0/ETH1_RGMII_TXD0 , , , ,EVENTOUT ,ADC1_INP6/ADC1_INN2 +PortF ,PF13 , , , , ,USART1_TX ,SPI5_NSS , , , ,DCMIPP_D10/DCMI_D10/PSSI_D10 , ,ETH1_MII_TXD1/ETH1_RMII_TXD1/ETH1_RGMII_TXD1 , , , ,EVENTOUT ,ADC2_INP2 +PortF ,PF14 , ,TIM2_CH2 , , ,USART1_CTS ,SPI5_MOSI , , , , , ,ETH1_MII_RXD0/ETH1_RMII_RXD0/ETH1_RGMII_RXD0 , , ,LCD_G0 ,EVENTOUT ,ADC2_INP6/ADC2_INN2 +PortF ,PF15 , , , , ,USART1_RTS ,SPI5_SCK , , , , , ,ETH1_MII_RXD1/ETH1_RMII_RXD1/ETH1_RGMII_RXD1 , , ,LCD_G1 ,EVENTOUT , +PortG ,PG0 , ,TIM1_CH4N ,TIM12_CH1 , , , , ,UART9_RX , , ,LCD_VSYNC ,ETH1_PHY_INTN , , ,LCD_R0 ,EVENTOUT , +PortG ,PG1 , ,TIM16_CH1N , , , ,SPI5_MISO ,SAI1_SCK_B , ,UART7_RTS ,DCMIPP_PIXCLK/DCMI_PIXCLK/PSSI_PDCK ,TIM13_CH1 , ,FMC_A19 , ,LCD_G1 ,EVENTOUT , +PortG ,PG2 , ,TIM17_CH1N , , , ,SPI5_MOSI ,SAI1_FS_B ,USART3_RTS ,UART7_CTS ,DCMIPP_D6/DCMI_D6/PSSI_D6 ,SAI2_MCLK_B ,TIM14_CH1 ,FMC_A21 , ,LCD_R0 ,EVENTOUT , +PortG ,PG3 ,TRACED1 , , , , , , ,USART2_TX , ,DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE , ,ETH1_MII_TXD2/ETH1_RGMII_TXD2 , , , ,EVENTOUT , +PortG ,PG4 , ,TIM1_BKIN2 , , , , , , , , , ,ETH1_MII_TXD3/ETH1_RGMII_TXD3 , , ,LCD_B0 ,EVENTOUT , +PortG ,PG5 , ,TIM1_ETR , , , , , ,USART2_CTS/USART2_NSS , , , ,ETH1_MII_RX_ER , , ,LCD_B1 ,EVENTOUT , +PortG ,PG6 , ,TIM17_BKIN , , , , , ,USART6_CK , ,DCMIPP_D12/DCMI_D12/PSSI_D12 , ,ETH1_MII_CRS , , ,LCD_B3 ,EVENTOUT , +PortG ,PG7 ,TRACECLK , , , , , ,SAI1_MCLK_A ,USART6_CK , ,DCMIPP_D13/DCMI_D13/PSSI_D13 , ,ETH1_PHY_INTN , , , ,EVENTOUT , +PortG ,PG8 ,RTC_REFIN ,TIM1_CH3N ,TIM12_CH2 , ,USART1_RX ,SPI2_MOSI/I2S2_SDO ,SAI1_SCK_B , ,UART4_CTS , , ,SDMMC2_D1 ,FMC_A20 , ,LCD_G7 ,HDP7 , +PortG ,PG9 , , , , , , , , , , , , ,FMC_D8/FMC_AD8 , ,LCD_R7 ,EVENTOUT , +PortG ,PG10 , ,TIM1_CH1N , ,LPTIM2_CH1 , ,SPI2_SCK/I2S2_CK ,FDCAN2_TX ,USART3_CTS/USART3_NSS , ,DCMIPP_D2/DCMI_D2/PSSI_D2 , ,UART5_TX ,FMC_A16/FMC_CLE , ,LCD_G4 ,HDP5 , +PortG ,PG11 , , , , , , , , ,UART7_RX , , ,ETH1_MDC , , ,LCD_R6 ,EVENTOUT , +PortG ,PG12 , ,TIM17_CH1 , , , ,SPI5_SCK ,SAI1_MCLK_B , ,UART7_TX , , , ,FMC_A18 , ,LCD_G0 ,EVENTOUT , +PortG ,PG13 , ,LPTIM1_IN1 ,TIM4_CH1 ,LPTIM2_IN1 , , , ,USART3_RTS , ,DCMIPP_D12/DCMI_D12/PSSI_D12 ,SAI2_FS_A , ,FMC_NE1 , ,LCD_DE ,EVENTOUT , +PortG ,PG14 ,TRACED1 ,LPTIM1_ETR ,TIM8_CH4 , , ,SPI6_MOSI/I2S6_SDO ,USART10_RTS ,USART6_TX ,USART2_RTS ,DCMIPP_D11/DCMI_D11/PSSI_D11 ,FMC_NCE , ,FMC_NE2 , ,LCD_B1 ,EVENTOUT , +PortG ,PG15 , ,TIM1_CH4 , , , ,SPI5_RDY ,SPI4_RDY ,USART3_CK , ,DCMIPP_D4/DCMI_D4/PSSI_D4 ,SPI1_RDY ,ETH1_MII_RX_CLK/ETH1_RMII_REF_CLK ,FMC_CLK , ,LCD_B0 ,EVENTOUT ,ADC12_INP7/ADC12_INN3 +PortH ,PH0 , , , , , , , , , , , , , , , , , +PortH ,PH1 , , , , , , , , , , , , , , , , , +PortH ,PH2 ,TRACED2 ,TIM1_ETR ,TIM3_ETR , ,TIM15_BKIN , ,FDCAN1_TX , , ,DCMIPP_D11/DCMI_D11/PSSI_D11 ,SDMMC1_CMD ,UART5_RX ,FMC_NE3 , , ,EVENTOUT , +PortH ,PH3 ,TRACECLK , , , , , , , ,UART7_TX , , , , , ,LCD_B4 ,EVENTOUT , +PortH ,PH4 , , , , , , , , ,UART7_TX , , , , , ,LCD_R4 ,EVENTOUT , +PortH ,PH5 , , , , , ,SPI5_SCK , , , , , ,ETH1_MDC , , , ,EVENTOUT , +PortH ,PH6 , , , , , ,SPI5_NSS , , , , , , , , ,LCD_B5 ,EVENTOUT , +PortH ,PH7 , , ,I3C2_SCL , , ,SPI5_MOSI , , , , , , , , , ,EVENTOUT , +PortH ,PH8 , , ,I3C2_SDA , , ,SPI5_MISO , , , , , , , , , ,EVENTOUT , +PortH ,PH9 , ,TIM16_CH1 ,TIM4_CH3 ,USART3_CK ,I2C1_SCL , ,FDCAN1_RX ,I3C1_SCL ,UART4_RX ,DCMIPP_D6/DCMI_D6/PSSI_D6 ,SDMMC1_D4 ,SDMMC2_D4 ,SDMMC1_CKIN , ,FMC_D9/FMC_AD9 ,HDP0 , +PortH ,PH10 , , , , , , , , , , , , , , , , , +PortH ,PH11 , , , , , , , , , , , , , , , , , +PortH ,PH12 , , , , , , , , , , , , , , , , , +PortH ,PH13 , , , , , , , , , , , , , , , , , +PortH ,PH14 , , , , , , , , , , , , , , , , , +PortH ,PH15 , , , , , , , , , , , , , , , , , +PortN ,PN0 , , , , , , , , , ,XSPIM_P2_DQS0 , , ,FMC_A25 , , ,EVENTOUT , +PortN ,PN1 , , , , , , , , , ,XSPIM_P2_NCS1 , , ,FMC_A24 , , ,EVENTOUT , +PortN ,PN2 , , , , , , , , , ,XSPIM_P2_IO0 , , ,FMC_A23 , , ,EVENTOUT , +PortN ,PN3 , , , , , , , , , ,XSPIM_P2_IO1 , , ,FMC_A22 , , ,EVENTOUT , +PortN ,PN4 , , , , , , , , , ,XSPIM_P2_IO2 , , , , , ,EVENTOUT , +PortN ,PN5 , , , , , , , , , ,XSPIM_P2_IO3 , , , , , ,EVENTOUT , +PortN ,PN6 , , , , , , , , , ,XSPIM_P2_CLK , , , , , ,EVENTOUT , +PortN ,PN7 , , , , , , , , , ,XSPIM_P2_NCLK , , , , , ,EVENTOUT , +PortN ,PN8 , , , , , , , , , ,XSPIM_P2_IO4 , , , , , ,EVENTOUT , +PortN ,PN9 , , , , , , , , , ,XSPIM_P2_IO5 ,DCMIPP_D5/DCMI_D5/PSSI_D5 , , , , ,EVENTOUT , +PortN ,PN10 , , , , , , , , , ,XSPIM_P2_IO6 , , , , ,LCD_B4 ,EVENTOUT , +PortN ,PN11 , , , , , , , , , ,XSPIM_P2_IO7 , , , , ,LCD_B6 ,EVENTOUT , +PortN ,PN12 , , , , , , , , , ,XSPIM_P2_NCS2 , , , , , ,EVENTOUT , +PortO ,PO0 , , , , , , , , , ,XSPIM_P1_NCS1 , , ,FMC_A22 , , ,EVENTOUT , +PortO ,PO1 , , , , , , , , , ,XSPIM_P1_NCS2 , , ,FMC_A23 , , ,EVENTOUT , +PortO ,PO2 , , , , , , , , , ,XSPIM_P1_DQS0 , , ,FMC_A24 , ,LCD_B7 ,EVENTOUT , +PortO ,PO3 , , , , , , , , , ,XSPIM_P1_DQS1 , , ,FMC_A25 , ,LCD_G3 ,EVENTOUT , +PortO ,PO4 , , , , , , , , , ,XSPIM_P1_CLK ,LCD_B4 , ,FMC_A24 , ,FMC_NBL2 ,EVENTOUT , +PortO ,PO5 , , , , , , , , , ,XSPIM_P1_NCLK , , ,FMC_A25 , ,FMC_NBL3 ,EVENTOUT , +PortP ,PP0 , , , , , , , , , ,XSPIM_P1_IO0 , , ,FMC_D16 , , ,EVENTOUT , +PortP ,PP1 , , , , , , , , , ,XSPIM_P1_IO1 , , ,FMC_D17 , , ,EVENTOUT , +PortP ,PP2 , , , , , , , , , ,XSPIM_P1_IO2 , , ,FMC_D18 , , ,EVENTOUT , +PortP ,PP3 , , , , , , , , , ,XSPIM_P1_IO3 , , ,FMC_D19 , , ,EVENTOUT , +PortP ,PP4 , , , , , , , , , ,XSPIM_P1_IO4 , , ,FMC_D20 , , ,EVENTOUT , +PortP ,PP5 , , , , , , , , , ,XSPIM_P1_IO5 , , ,FMC_D21 , , ,EVENTOUT , +PortP ,PP6 , , , , , , , , , ,XSPIM_P1_IO6 , , ,FMC_D22 , , ,EVENTOUT , +PortP ,PP7 , , , , , , , , , ,XSPIM_P1_IO7 , , ,FMC_D23 , , ,EVENTOUT , +PortP ,PP8 , , , , , ,SPI2_MISO , , , ,XSPIM_P1_IO8 , , ,FMC_D24 , , ,EVENTOUT , +PortP ,PP9 , , , , , ,SPI2_MOSI , , , ,XSPIM_P1_IO9 , , ,FMC_D25 , , ,EVENTOUT , +PortP ,PP10 , , , , , , , , , ,XSPIM_P1_IO1O , ,ETH1_MDC ,FMC_D26 , , ,EVENTOUT , +PortP ,PP11 , , , , , , , , , ,XSPIM_P1_IO11 , , ,FMC_D27 , , ,EVENTOUT , +PortP ,PP12 , , , , , , , , , ,XSPIM_P1_IO12 , , ,FMC_D28 , , ,EVENTOUT , +PortP ,PP13 , , , , , , , , , ,XSPIM_P1_IO13 , , ,FMC_D29 , , ,EVENTOUT , +PortP ,PP14 , , , , , , , , , ,XSPIM_P1_IO14 , , ,FMC_D30 , , ,EVENTOUT , +PortP ,PP15 , , , , , , , , , ,XSPIM_P1_IO15 , , ,FMC_D31 , ,LCD_B5 ,EVENTOUT , +PortQ ,PQ0 ,TRACECLK , ,TIM8_ETR , , , , , , , , , , , , ,EVENTOUT , +PortQ ,PQ1 , , ,TIM8_BKIN , , , , , , , , , , , , ,EVENTOUT , +PortQ ,PQ2 , , ,TIM8_BKIN2 , , , , , , ,SAI2_SCK_B , , , , , ,EVENTOUT , +PortQ ,PQ3 , , ,TIM8_CH1 , , , , , , , , , , , , ,EVENTOUT , +PortQ ,PQ4 , , ,TIM8_CH1N , , , , , , , , , , , , ,EVENTOUT , +PortQ ,PQ5 , , ,TIM8_CH2 , , , , , , ,SAI2_FS_B , , , , , ,EVENTOUT , +PortQ ,PQ6 , , ,TIM8_CH2N , , , , , , ,SAI2_SD_B , , , , , ,EVENTOUT , +PortQ ,PQ7 , , ,TIM8_CH3 , , , , , , ,SAI2_MCLK_B , , , , , ,EVENTOUT , diff --git a/ports/stm32/pin.h b/ports/stm32/pin.h index 09dad7eb487..269e74d88b6 100644 --- a/ports/stm32/pin.h +++ b/ports/stm32/pin.h @@ -46,12 +46,12 @@ typedef struct { mp_obj_base_t base; qstr_short_t name; uint16_t pin_mask; - uint32_t port : 4; // Allows GPIOA through GPIOP + uint32_t port : 5; // Allows GPIOA through GPIOQ uint32_t pin : 4; // ST MCUs have a maximum of 16 pins per port uint32_t num_af : 4; uint32_t adc_channel : 5; // Some ARM processors use 32 bits/PORT uint32_t adc_num : 3; // 1 bit per ADC - // 12 bits available here + // 11 bits available here pin_gpio_t *gpio; const pin_af_obj_t *af; } machine_pin_obj_t; diff --git a/ports/stm32/pin_defs_stm32.h b/ports/stm32/pin_defs_stm32.h index 1020381abb8..06725dc8b2b 100644 --- a/ports/stm32/pin_defs_stm32.h +++ b/ports/stm32/pin_defs_stm32.h @@ -43,6 +43,8 @@ enum { PORT_M, PORT_N, PORT_O, + PORT_P, + PORT_Q, }; // Must have matching entries in SUPPORTED_FN in boards/make-pins.py From 4137e7c0b25caac833e21e4c37dda53787a0072b Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Fri, 17 Jul 2026 14:54:14 +1000 Subject: [PATCH 545/635] stm32/eth: Move DHCP restart to end of link-status poll. Set a flag in the link-up transition and MAC-reconfig branches of eth_phy_link_status_poll(), then call eth_dhcp_restart_if_needed() once at the end of the function guarded by the flag. Avoids the back-to-back stop/start that occurred when both branches ran in the same poll iteration. Reported by @dpgeorge in the PR review of the original hot-plug support. Signed-off-by: Andrew Leech --- ports/stm32/eth.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/ports/stm32/eth.c b/ports/stm32/eth.c index 924d751e4cd..4e96fbb546c 100644 --- a/ports/stm32/eth.c +++ b/ports/stm32/eth.c @@ -1149,6 +1149,9 @@ void eth_phy_link_status_poll(void) { uint16_t bsr = eth_phy_read(self->phy_addr, PHY_BSR); bool current_link_status = (bsr & PHY_BSR_LINK_STATUS) != 0; + // DHCP restart runs at end of function, after any MAC reconfig. + bool needs_dhcp_restart = false; + // Handle link up/down transitions. if (current_link_status != self->last_link_status) { self->last_link_status = current_link_status; @@ -1158,7 +1161,7 @@ void eth_phy_link_status_poll(void) { netif_set_link_up(netif); self->mac_speed_configured = false; self->autoneg_start_ms = mp_hal_ticks_ms(); - eth_dhcp_restart_if_needed(netif); + needs_dhcp_restart = true; } else { netif_set_link_down(netif); self->mac_speed_configured = false; @@ -1237,7 +1240,10 @@ void eth_phy_link_status_poll(void) { self->mac_reconfig_in_progress = false; self->mac_speed_configured = true; - // MAC was reconfigured; restart DHCP if needed. + needs_dhcp_restart = true; + } + + if (needs_dhcp_restart) { struct netif *netif = &self->netif; MICROPY_PY_LWIP_ENTER eth_dhcp_restart_if_needed(netif); From 0228d9c07049e89e9956401724f0851e2f4aa4fe Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Fri, 17 Jul 2026 14:55:08 +1000 Subject: [PATCH 546/635] stm32/eth: Remove dead re-check of last_link_status in poll. The transition block just above unconditionally assigns self->last_link_status = current_link_status, and the surrounding if condition already tested current_link_status true. So by the time this check runs, last_link_status is always true here and the early return can never fire. Signed-off-by: Andrew Leech --- ports/stm32/eth.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/ports/stm32/eth.c b/ports/stm32/eth.c index 4e96fbb546c..0aae79453b6 100644 --- a/ports/stm32/eth.c +++ b/ports/stm32/eth.c @@ -1179,11 +1179,6 @@ void eth_phy_link_status_poll(void) { // If link is up but MAC speed/duplex not yet configured, check if // autonegotiation has completed. if (current_link_status && !self->mac_speed_configured) { - // Re-verify link is still up before proceeding (it may have dropped). - if (!self->last_link_status) { - return; - } - bsr = eth_phy_read(self->phy_addr, PHY_BSR); bool autoneg_timeout = (mp_hal_ticks_ms() - self->autoneg_start_ms) > PHY_AUTONEG_TIMEOUT_MS; From 664c8b7a144d144f2c478a155fde2a122286e524 Mon Sep 17 00:00:00 2001 From: Dryw Wade Date: Thu, 30 Jul 2026 09:49:23 -0600 Subject: [PATCH 547/635] stm32/mboot: Enable USB sleep clock for STM32N6. Fixes #19505. A regression was introduced in e48b985, where the USB sleep clock got enabled in stm32/main.c instead of the shared USB code, so mboot/main.c no longer enabled the USB sleep clock, causing failed enumeration. Signed-off-by: Dryw Wade --- ports/stm32/mboot/main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/ports/stm32/mboot/main.c b/ports/stm32/mboot/main.c index 7251bc1562e..de885b5f1e8 100644 --- a/ports/stm32/mboot/main.c +++ b/ports/stm32/mboot/main.c @@ -1590,6 +1590,12 @@ void stm32_main(uint32_t initial_r0) { enter_bootloader: + #if defined(STM32N6) + // Enable USB OTG peripherals during sleep, so they run during WFI. + LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1); + LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2); + #endif + #if defined(STM32H5) // MPU is needed for H5 to access the unique id. mpu_init(); From 1a76bc3434b29cc2454e5ccea40789b2a8d97080 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 31 Jul 2026 13:44:09 +1000 Subject: [PATCH 548/635] stm32/boards/OPENMV_N6: Fix MICROPY_HW_USRSW_PIN to use pyb_pin_SW. BUTTON was renamed to SW in 64c7045213514d7d57abeee8705f6b4e70222785. Signed-off-by: Damien George --- ports/stm32/boards/OPENMV_N6/mpconfigboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/stm32/boards/OPENMV_N6/mpconfigboard.h b/ports/stm32/boards/OPENMV_N6/mpconfigboard.h index 359302a8bb8..a2adfbeb759 100644 --- a/ports/stm32/boards/OPENMV_N6/mpconfigboard.h +++ b/ports/stm32/boards/OPENMV_N6/mpconfigboard.h @@ -87,7 +87,7 @@ // #define MICROPY_HW_CAN3_RX (pyb_pin_CAN3_RX) // USER is pulled high, and pressing the button makes the input go low. -#define MICROPY_HW_USRSW_PIN (pyb_pin_BUTTON) +#define MICROPY_HW_USRSW_PIN (pyb_pin_SW) #define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) #define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) #define MICROPY_HW_USRSW_PRESSED (0) From 2af2defbe9305a2fd4cc9d18d2e3957fe2cfa98d Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 16 Jun 2026 16:41:32 +1000 Subject: [PATCH 549/635] extmod/vfs: Specify new MP_VFS_ROM_IOCTL_GET_MIN_PREPARE function. This allows devices to support partial update of the ROM segments. Signed-off-by: Damien George --- extmod/vfs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/extmod/vfs.h b/extmod/vfs.h index e5386344275..e9a6e54f09f 100644 --- a/extmod/vfs.h +++ b/extmod/vfs.h @@ -55,11 +55,13 @@ #define MP_BLOCKDEV_IOCTL_BLOCK_ERASE (6) // Constants for vfs.rom_ioctl() function. +// The 4-arg form of WRITE_PREPARE is only available if GET_MIN_PREPARE returns >0. #define MP_VFS_ROM_IOCTL_GET_NUMBER_OF_SEGMENTS (1) // rom_ioctl(1) #define MP_VFS_ROM_IOCTL_GET_SEGMENT (2) // rom_ioctl(2, ) -#define MP_VFS_ROM_IOCTL_WRITE_PREPARE (3) // rom_ioctl(3, , ) +#define MP_VFS_ROM_IOCTL_WRITE_PREPARE (3) // rom_ioctl(3, , ) or rom_ioctl(3, , , ) #define MP_VFS_ROM_IOCTL_WRITE (4) // rom_ioctl(4, , , ) #define MP_VFS_ROM_IOCTL_WRITE_COMPLETE (5) // rom_ioctl(5, ) +#define MP_VFS_ROM_IOCTL_GET_MIN_PREPARE (6) // rom_ioctl(6, ) #if MICROPY_VFS_BLOCKDEV_NATIVE // Function signatures used when MP_BLOCKDEV_FLAG_NATIVE is set. From 6ab72487a68a441da2d99b41d70b055fb4cfe800 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 16 Jun 2026 16:42:23 +1000 Subject: [PATCH 550/635] alif/vfs_rom_ioctl: Implement 4-arg WRITE_PREPARE and GET_MIN_PREPARE. Signed-off-by: Damien George --- ports/alif/vfs_rom_ioctl.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/ports/alif/vfs_rom_ioctl.c b/ports/alif/vfs_rom_ioctl.c index d82ac6f8417..4c6d067017a 100644 --- a/ports/alif/vfs_rom_ioctl.c +++ b/ports/alif/vfs_rom_ioctl.c @@ -103,7 +103,15 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { return MP_OBJ_NEW_SMALL_INT(-MP_EINVAL); } uint32_t dest = romfs_base; - uint32_t dest_max = dest + mp_obj_get_int(args[2]); + uint32_t dest_max; + if (n_args == 3) { + // Only length given, offset defaults to start of partition. + dest_max = dest + mp_obj_get_int(args[2]); + } else { + // Both offset and length given. + dest += mp_obj_get_int(args[2]); + dest_max = dest + mp_obj_get_int(args[3]); + } if (dest_max > romfs_base + romfs_len) { return MP_OBJ_NEW_SMALL_INT(-MP_EINVAL); } @@ -169,6 +177,20 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { #endif } + if (cmd == MP_VFS_ROM_IOCTL_GET_MIN_PREPARE) { + // Get minimum erase size. + + if (mram_is_valid_addr(romfs_base)) { + return MP_OBJ_NEW_SMALL_INT(MRAM_SECTOR_SIZE); + } + + #if MICROPY_HW_ENABLE_OSPI + if (ospi_is_valid_addr(ospi_base, romfs_base)) { + return MP_OBJ_NEW_SMALL_INT(MICROPY_HW_FLASH_BLOCK_SIZE_BYTES); + } + #endif + } + return MP_OBJ_NEW_SMALL_INT(-MP_EINVAL); } From 61d11a4470200564294d7eb092b7b96e1fbca1a8 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 16 Jun 2026 16:43:21 +1000 Subject: [PATCH 551/635] samd/samd_flash: Implement 4-arg WRITE_PREPARE and GET_MIN_PREPARE. Signed-off-by: Damien George --- ports/samd/samd_flash.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/ports/samd/samd_flash.c b/ports/samd/samd_flash.c index c99df9d0f89..c40a313b613 100644 --- a/ports/samd/samd_flash.c +++ b/ports/samd/samd_flash.c @@ -236,7 +236,15 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { return MP_OBJ_NEW_SMALL_INT(-MP_EINVAL); } uint32_t dest_addr = MICROPY_HW_ROMFS_BASE; - uint32_t bytes_used = mp_obj_get_int(args[2]); + uint32_t bytes_used; + if (n_args == 3) { + // Only length given, offset defaults to start of partition. + bytes_used = mp_obj_get_int(args[2]); + } else { + // Both offset and length given. + dest_addr += mp_obj_get_int(args[2]); + bytes_used = mp_obj_get_int(args[3]); + } mp_int_t page_size = flash_get_page_size(&flash_desc); // adf4 API call flash_erase(&flash_desc, dest_addr, (bytes_used + page_size - 1) / page_size); return MP_OBJ_NEW_SMALL_INT(4); @@ -254,6 +262,11 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { return MP_OBJ_NEW_SMALL_INT(0); } + case MP_VFS_ROM_IOCTL_GET_MIN_PREPARE: { + // Get minimum erase size. + return MP_OBJ_NEW_SMALL_INT(flash_get_page_size(&flash_desc)); + } + #endif default: From 768bc8fe0a5fe843f22bd726e1a7b5518cb24bc0 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 16 Jun 2026 16:44:01 +1000 Subject: [PATCH 552/635] stm32/flash: Implement flash_get_max_sector_size helper function. Signed-off-by: Damien George --- ports/stm32/flash.c | 10 ++++++++++ ports/stm32/flash.h | 1 + 2 files changed, 11 insertions(+) diff --git a/ports/stm32/flash.c b/ports/stm32/flash.c index fcf46049c0a..4dfcc950c2f 100644 --- a/ports/stm32/flash.c +++ b/ports/stm32/flash.c @@ -259,6 +259,16 @@ bool flash_is_valid_addr(uint32_t addr) { return base <= addr && addr < end_of_flash; } +uint32_t flash_get_max_sector_size(void) { + #if FLASH_LAYOUT_IS_HOMOGENEOUS + // All sectors are the same size. + return FLASH_LAYOUT_SECTOR_SIZE; + #else + // The last sector is the largest. + return flash_layout[MP_ARRAY_SIZE(flash_layout) - 1].sector_size; + #endif +} + int32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) { #if FLASH_LAYOUT_IS_HOMOGENEOUS if (addr >= FLASH_LAYOUT_START_ADDR) { diff --git a/ports/stm32/flash.h b/ports/stm32/flash.h index e5ba35cf7d2..78427a6b472 100644 --- a/ports/stm32/flash.h +++ b/ports/stm32/flash.h @@ -27,6 +27,7 @@ #define MICROPY_INCLUDED_STM32_FLASH_H bool flash_is_valid_addr(uint32_t addr); +uint32_t flash_get_max_sector_size(void); int32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size); int flash_erase(uint32_t flash_dest); int flash_write(uint32_t flash_dest, const uint32_t *src, uint32_t num_word32); From aef040348e58eb346a51d23d9f98b2d232810594 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 16 Jun 2026 16:44:27 +1000 Subject: [PATCH 553/635] stm32/vfs_rom_ioctl: Implement 4-arg WRITE_PREPARE and GET_MIN_PREPARE. Signed-off-by: Damien George --- ports/stm32/vfs_rom_ioctl.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/ports/stm32/vfs_rom_ioctl.c b/ports/stm32/vfs_rom_ioctl.c index 480924b0105..7ab9ffa8aaf 100644 --- a/ports/stm32/vfs_rom_ioctl.c +++ b/ports/stm32/vfs_rom_ioctl.c @@ -110,7 +110,15 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { return MP_OBJ_NEW_SMALL_INT(-MP_EINVAL); } uint32_t dest = romfs_base; - uint32_t dest_max = dest + mp_obj_get_int(args[2]); + uint32_t dest_max; + if (n_args == 3) { + // Only length given, offset defaults to start of partition. + dest_max = dest + mp_obj_get_int(args[2]); + } else { + // Both offset and length given. + dest += mp_obj_get_int(args[2]); + dest_max = dest + mp_obj_get_int(args[3]); + } if (dest_max > romfs_base + romfs_len) { return MP_OBJ_NEW_SMALL_INT(-MP_EINVAL); } @@ -217,6 +225,28 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { #endif } + if (cmd == MP_VFS_ROM_IOCTL_GET_MIN_PREPARE) { + // Get minimum erase size. + + #if MICROPY_HW_ROMFS_ENABLE_INTERNAL_FLASH + if (flash_is_valid_addr(romfs_base)) { + return MP_OBJ_NEW_SMALL_INT(flash_get_max_sector_size()); + } + #endif + + #if MICROPY_HW_ROMFS_ENABLE_EXTERNAL_QSPI + if (qspi_is_valid_addr(romfs_base)) { + return MP_OBJ_NEW_SMALL_INT(MP_SPIFLASH_ERASE_BLOCK_SIZE); + } + #endif + + #if MICROPY_HW_ROMFS_ENABLE_EXTERNAL_XSPI + if (xspi_is_valid_addr(&xspi_flash2, romfs_base)) { + return MP_OBJ_NEW_SMALL_INT(MP_SPIFLASH_ERASE_BLOCK_SIZE); + } + #endif + } + return MP_OBJ_NEW_SMALL_INT(-MP_EINVAL); } From f777bc7e7b14d2d2c9ea6785f1d041006a406c8d Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 16 Jun 2026 17:08:40 +1000 Subject: [PATCH 554/635] tools/mpremote: Implement incremental preparation for romfs deploy. This uses the new GET_MIN_PREPARE ioctl to support incremental preparation of the ROM partition. On very large partitions the preparation can take a long time (eg due to the erase time of many blocks) and this can lead to a timeout of mpremote. Using incremental preparation prevents the timeout and gives better feedback to the user as to the progress. Signed-off-by: Damien George --- tools/mpremote/mpremote/commands.py | 66 +++++++++++++++++------------ 1 file changed, 38 insertions(+), 28 deletions(-) diff --git a/tools/mpremote/mpremote/commands.py b/tools/mpremote/mpremote/commands.py index 4974c71e2e9..7c5e0c5ee2f 100644 --- a/tools/mpremote/mpremote/commands.py +++ b/tools/mpremote/mpremote/commands.py @@ -561,6 +561,29 @@ def do_rtc(state, args): print(state.transport.eval("machine.RTC().datetime()")) +def _do_romfs_query_partition(transport, rom_id): + transport.exec(f"dev=vfs.rom_ioctl(2,{rom_id})") + if transport.eval("isinstance(dev,int) and dev<0"): + raise CommandError(f"ROMFS{rom_id} partition not found on device") + + has_object = transport.eval("hasattr(dev,'ioctl')") + if has_object: + rom_block_count = transport.eval("dev.ioctl(4,0)") + rom_block_size = transport.eval("dev.ioctl(5,0)") + rom_size = rom_block_count * rom_block_size + else: + rom_size = transport.eval("len(dev)") + rom_block_size = transport.eval(f"vfs.rom_ioctl(6,{rom_id})") + if rom_block_size <= 0: + rom_block_size = rom_size + + print( + f"ROMFS{rom_id} partition has size {rom_size} bytes ({rom_size // rom_block_size} blocks of {rom_block_size} bytes each)" + ) + + return has_object, rom_size, rom_block_size + + def _do_romfs_query(state, args): state.ensure_raw_repl() state.did_action() @@ -576,18 +599,7 @@ def _do_romfs_query(state, args): return for rom_id in range(num_rom_partitions): - state.transport.exec(f"dev=vfs.rom_ioctl(2,{rom_id})") - has_object = state.transport.eval("hasattr(dev,'ioctl')") - if has_object: - rom_block_count = state.transport.eval("dev.ioctl(4,0)") - rom_block_size = state.transport.eval("dev.ioctl(5,0)") - rom_size = rom_block_count * rom_block_size - print( - f"ROMFS{rom_id} partition has size {rom_size} bytes ({rom_block_count} blocks of {rom_block_size} bytes each)" - ) - else: - rom_size = state.transport.eval("len(dev)") - print(f"ROMFS{rom_id} partition has size {rom_size} bytes") + _do_romfs_query_partition(state.transport, rom_id) romfs = state.transport.eval("bytes(memoryview(dev)[:12])") print(f" Raw contents: {romfs.hex(':')} ...") if not romfs.startswith(b"\xd2\xcd\x31"): @@ -644,20 +656,7 @@ def _do_romfs_deploy(state, args): state.transport.exec("import vfs") if not state.transport.eval("hasattr(vfs,'rom_ioctl')"): raise CommandError("ROMFS is not enabled on this device") - transport.exec(f"dev=vfs.rom_ioctl(2,{rom_id})") - if transport.eval("isinstance(dev,int) and dev<0"): - raise CommandError(f"ROMFS{rom_id} partition not found on device") - has_object = transport.eval("hasattr(dev,'ioctl')") - if has_object: - rom_block_count = transport.eval("dev.ioctl(4,0)") - rom_block_size = transport.eval("dev.ioctl(5,0)") - rom_size = rom_block_count * rom_block_size - print( - f"ROMFS{rom_id} partition has size {rom_size} bytes ({rom_block_count} blocks of {rom_block_size} bytes each)" - ) - else: - rom_size = transport.eval("len(dev)") - print(f"ROMFS{rom_id} partition has size {rom_size} bytes") + has_object, rom_size, rom_block_size = _do_romfs_query_partition(transport, rom_id) # Check if ROMFS image is valid if not romfs.startswith(VfsRomWriter.ROMFS_HEADER): @@ -670,16 +669,27 @@ def _do_romfs_deploy(state, args): sys.exit(1) # Prepare ROMFS partition for writing. - print(f"Preparing ROMFS{rom_id} partition for writing") transport.exec("import vfs\ntry:\n vfs.umount('/rom')\nexcept:\n pass") chunk_size = 4096 if has_object: for offset in range(0, len(romfs), rom_block_size): + print(f"\rPreparing at offset {offset}", end="") transport.exec(f"dev.ioctl(6,{offset // rom_block_size})") chunk_size = min(chunk_size, rom_block_size) else: - rom_min_write = transport.eval(f"vfs.rom_ioctl(3,{rom_id},{len(romfs)})") + if rom_block_size < rom_size: + offset = 0 + while offset < len(romfs): + print(f"\rPreparing at offset {offset}", end="") + remain = min(len(romfs) - offset, 32768) + prepare = (remain + rom_block_size - 1) // rom_block_size * rom_block_size + rom_min_write = transport.eval(f"vfs.rom_ioctl(3,{rom_id},{offset},{prepare})") + offset += prepare + else: + print("\rPreparing at offset 0", end="") + rom_min_write = transport.eval(f"vfs.rom_ioctl(3,{rom_id},{len(romfs)})") chunk_size = max(chunk_size, rom_min_write) + print() # Detect capabilities of the device to use the fastest method of transfer. has_bytes_fromhex = transport.eval("hasattr(bytes,'fromhex')") From 4f2c101ce6b8cb32a1d0f957da9a92fb396ce502 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 31 Jul 2026 03:58:40 +0000 Subject: [PATCH 555/635] github/workflows: Bump actions/setup-python from 6 to 7. Bumps [actions/setup-python](https://github.com/actions/setup-python) from 6 to 7. - [Release notes](https://github.com/actions/setup-python/releases) - [Commits](https://github.com/actions/setup-python/compare/v6...v7) --- updated-dependencies: - dependency-name: actions/setup-python dependency-version: '7' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/code_formatting.yml | 2 +- .github/workflows/commit_formatting.yml | 2 +- .github/workflows/docs.yml | 2 +- .github/workflows/mpremote.yml | 2 +- .github/workflows/ports_unix.yml | 28 ++++++++++++------------- .github/workflows/ports_windows.yml | 4 ++-- 6 files changed, 20 insertions(+), 20 deletions(-) diff --git a/.github/workflows/code_formatting.yml b/.github/workflows/code_formatting.yml index 3fa60c5387c..5616fe33d7c 100644 --- a/.github/workflows/code_formatting.yml +++ b/.github/workflows/code_formatting.yml @@ -11,7 +11,7 @@ jobs: runs-on: ubuntu-22.04 steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 - name: Install packages run: tools/ci.sh c_code_formatting_setup - name: Run code formatting diff --git a/.github/workflows/commit_formatting.yml b/.github/workflows/commit_formatting.yml index 997532fde63..0e38ebcf868 100644 --- a/.github/workflows/commit_formatting.yml +++ b/.github/workflows/commit_formatting.yml @@ -13,6 +13,6 @@ jobs: - uses: actions/checkout@v7 with: fetch-depth: 100 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 - name: Check commit message formatting run: tools/ci.sh commit_formatting_run diff --git a/.github/workflows/docs.yml b/.github/workflows/docs.yml index 74b6eb3f0f4..a27196734ad 100644 --- a/.github/workflows/docs.yml +++ b/.github/workflows/docs.yml @@ -18,7 +18,7 @@ jobs: steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 - name: Install Python packages run: pip install -r docs/requirements.txt - name: Build unix port diff --git a/.github/workflows/mpremote.yml b/.github/workflows/mpremote.yml index 6df7a2e4956..65ae823a14b 100644 --- a/.github/workflows/mpremote.yml +++ b/.github/workflows/mpremote.yml @@ -16,7 +16,7 @@ jobs: # Setting this to zero means fetch all history and tags, # which hatch-vcs can use to discover the version tag. fetch-depth: 0 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 - name: Install build tools run: pip install build - name: Build mpremote wheel diff --git a/.github/workflows/ports_unix.yml b/.github/workflows/ports_unix.yml index c9048687db0..8231c1eb1ea 100644 --- a/.github/workflows/ports_unix.yml +++ b/.github/workflows/ports_unix.yml @@ -95,7 +95,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -136,7 +136,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -173,7 +173,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -192,7 +192,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -267,7 +267,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -284,7 +284,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -303,7 +303,7 @@ jobs: runs-on: macos-26 steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 with: python-version: '3.8' - name: Build @@ -318,7 +318,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -337,7 +337,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -356,7 +356,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -375,7 +375,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -394,7 +394,7 @@ jobs: runs-on: ubuntu-24.04-arm steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -413,7 +413,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: @@ -438,7 +438,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # Python 3.12 is the default for ubuntu-24.04, but that has compatibility issues with settrace tests. # Can remove this step when ubuntu-latest uses a more recent Python 3.x as the default. with: diff --git a/.github/workflows/ports_windows.yml b/.github/workflows/ports_windows.yml index 0512c4289de..af830ca194e 100644 --- a/.github/workflows/ports_windows.yml +++ b/.github/workflows/ports_windows.yml @@ -49,7 +49,7 @@ jobs: - name: Install Python 3.11 # As of 20260112 the default Python version in Windows image is 3.12, which breaks settrace tests # Use 3.11 for now - uses: actions/setup-python@v6 + uses: actions/setup-python@v7 with: python-version: '3.11' - uses: microsoft/setup-msbuild@v3 @@ -106,7 +106,7 @@ jobs: run: shell: msys2 {0} steps: - - uses: actions/setup-python@v6 + - uses: actions/setup-python@v7 # note: can go back to installing mingw-w64-${{ matrix.env }}-python after # MSYS2 updates to Python >3.12 (due to settrace compatibility issue) with: From 61b2b4dd233e25ecb58d05e5e0dc61e0fe31b7bb Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Tue, 28 Jul 2026 13:11:28 +0200 Subject: [PATCH 556/635] docs/psoc-edge/general: Fix product name typo. Signed-off-by: jaenrig-ifx --- docs/psoc-edge/general.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/psoc-edge/general.rst b/docs/psoc-edge/general.rst index ce8a2c6957c..5b6f4105cd9 100644 --- a/docs/psoc-edge/general.rst +++ b/docs/psoc-edge/general.rst @@ -10,7 +10,7 @@ The PSOC™ Edge devices are based on high performance Arm® Cortex®-M55, inclu The PSOC™ Edge port supports boards powered by the `Infineon PSOC™ Edge family of microcontrollers `_ and currently supports the following MCUs: -* PSoC™ Edge 84 +* PSOC™ Edge E84 .. _Supported boards: From 6b3a4683cc54418bbc3374a9faa71709afcdcb02 Mon Sep 17 00:00:00 2001 From: jaenrig-ifx Date: Tue, 28 Jul 2026 13:17:07 +0200 Subject: [PATCH 557/635] docs/psoc-edge/quickref: Add link to latest dev fork. Signed-off-by: jaenrig-ifx --- docs/psoc-edge/quickref.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/docs/psoc-edge/quickref.rst b/docs/psoc-edge/quickref.rst index d592a7c7a07..eb0a504bbcf 100644 --- a/docs/psoc-edge/quickref.rst +++ b/docs/psoc-edge/quickref.rst @@ -21,6 +21,13 @@ working with this port it may be useful to get an overview of the microcontrolle general.rst installation.rst +.. note:: + + You can follow the latest progress for this port in the `Infineon MicroPython + PSOC™ Edge fork `_. + We are working to bring those features here. Meanwhile, you can try them early + by installing the fork version. + Pins and GPIO ------------- From 06bcfd5b74c6d275ae0991a19dab8704299e4e05 Mon Sep 17 00:00:00 2001 From: Harris Date: Tue, 28 Jul 2026 19:56:24 +0100 Subject: [PATCH 558/635] webassembly/main: Fix unused-variable build error in standard. external_call_depth is only read back (to detect the top-level call boundary) when MICROPY_GC_SPLIT_HEAP_AUTO is enabled. The "standard" variant does not enable this option, so its build was failing with: main.c:50:15: error: variable 'external_call_depth' set but not used [-Werror,-Wunused-but-set-global] Fix by guarding the variable's declaration, increment, and decrement all under the same #if, instead of leaving the decrement outside the guard while the increment and declaration were inside/outside inconsistently. Fixes regression introduced by cdaf2de80cd8. Signed-off-by: Harris --- ports/webassembly/main.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/ports/webassembly/main.c b/ports/webassembly/main.c index 0ab84e5b221..670d404da06 100644 --- a/ports/webassembly/main.c +++ b/ports/webassembly/main.c @@ -47,7 +47,9 @@ // This counter tracks the current depth of calls into C code that originated // externally, ie from JavaScript. When the counter is 0 that corresponds to // the top-level call into C. +#if MICROPY_GC_SPLIT_HEAP_AUTO static size_t external_call_depth = 0; +#endif // Emscripten defaults to a 64k C-stack, so our limit should be less than that. #define CSTACK_SIZE (32 * 1024) @@ -57,12 +59,14 @@ static void gc_collect_top_level(mp_obj_t root_obj); #endif void external_call_depth_inc(void) { + #if MICROPY_GC_SPLIT_HEAP_AUTO ++external_call_depth; + #endif } void external_call_depth_dec(mp_obj_t root_obj) { - --external_call_depth; #if MICROPY_GC_SPLIT_HEAP_AUTO + --external_call_depth; if (external_call_depth == 0) { gc_collect_top_level(root_obj); } From d9f669a98d6442f8ad8509a18f556009267bcd76 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 15 Jul 2026 00:46:46 +1000 Subject: [PATCH 559/635] py/modmicropython: Support scheduling a KeyboardInterrupt from Python. This commit allows scheduling a KeyboardInterrupt to be raised "very soon" in the main thread. Calling the C function `mp_sched_keyboard_interrupt()` directly won't work as expected, because that will raise the exception almost immediately, even if running within a scheduled context. So that call is pretty much equivalent to raise KeyboardInterrupt from the Python side. Instead, this commit adds a way to schedule a call to `mp_sched_keyboard_interrupt()`, so that the exception is never raised within a schedule context, but rather always in the main thread context. To reduce code size existing functions are reused: micropython.schedule(micropython.kbd_intr, None) Addresses #19424. Signed-off-by: Damien George --- docs/library/micropython.rst | 4 ++ py/modmicropython.c | 22 +++++++ tests/micropython/schedule_kbd_intr.py | 72 ++++++++++++++++++++++ tests/micropython/schedule_kbd_intr.py.exp | 3 + 4 files changed, 101 insertions(+) create mode 100644 tests/micropython/schedule_kbd_intr.py create mode 100644 tests/micropython/schedule_kbd_intr.py.exp diff --git a/docs/library/micropython.rst b/docs/library/micropython.rst index 65fa204315a..c2302929662 100644 --- a/docs/library/micropython.rst +++ b/docs/library/micropython.rst @@ -186,6 +186,10 @@ Functions There is a finite queue to hold the scheduled functions and `schedule()` will raise a `RuntimeError` if the queue is full. + As a special case, it's possible to pass `micropython.kbd_intr` to this function + as the first argument (and ``None`` as the second argument), and that will + schedule a `KeyboardInterrupt` to be raised "very soon" in the main thread. + Classes ------- diff --git a/py/modmicropython.c b/py/modmicropython.c index 4d676cb4ab2..35ca98eb881 100644 --- a/py/modmicropython.c +++ b/py/modmicropython.c @@ -157,13 +157,35 @@ static MP_DEFINE_CONST_FUN_OBJ_1(mp_micropython_kbd_intr_obj, mp_micropython_kbd #endif #if MICROPY_ENABLE_SCHEDULER + +#if MICROPY_KBD_EXCEPTION && MICROPY_SCHEDULER_STATIC_NODES +static mp_sched_node_t mp_keyboard_interrupt_sched_node; +static void mp_sched_keyboard_interrupt_wrapper(mp_sched_node_t *node) { + mp_sched_keyboard_interrupt(); +} +#endif + static mp_obj_t mp_micropython_schedule(mp_obj_t function, mp_obj_t arg) { + #if MICROPY_KBD_EXCEPTION + if (function == MP_OBJ_FROM_PTR(&mp_micropython_kbd_intr_obj)) { + #if MICROPY_SCHEDULER_STATIC_NODES + // Allow calling `micropython.schedule(micropython.kbd_intr, None)` as a + // special case to schedule a keyboard interrupt. + mp_sched_schedule_node(&mp_keyboard_interrupt_sched_node, mp_sched_keyboard_interrupt_wrapper); + return mp_const_none; + #else + // Signal that passing `micropython.kbd_intr` is not supported. + mp_raise_ValueError(NULL); + #endif + } + #endif if (!mp_sched_schedule(function, arg)) { mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("schedule queue full")); } return mp_const_none; } static MP_DEFINE_CONST_FUN_OBJ_2(mp_micropython_schedule_obj, mp_micropython_schedule); + #endif static const mp_rom_map_elem_t mp_module_micropython_globals_table[] = { diff --git a/tests/micropython/schedule_kbd_intr.py b/tests/micropython/schedule_kbd_intr.py new file mode 100644 index 00000000000..ec7ef5a5d07 --- /dev/null +++ b/tests/micropython/schedule_kbd_intr.py @@ -0,0 +1,72 @@ +# Test using micropython.schedule() to schedule a KeyboardInterrupt. +# Note: this test cannot use unittest because the unittest overhead +# may trigger the scheduler when we don't want it to. + +try: + from time import sleep + from micropython import schedule, kbd_intr +except ImportError: + print("SKIP") + raise SystemExit + +######################################################################## +# Test basic scheduling. + +try: + schedule(kbd_intr, None) +except ValueError: + # Scheduling `kbd_intr` is not supported on this target. + print("SKIP") + raise SystemExit + +try: + sleep(0) + sleep(0) + print("fail") +except KeyboardInterrupt: + print("KeyboardInterrupt") + +######################################################################## +# Should be able to schedule it many times without error, and that +# should only trigger one KeyboardInterrupt. + +schedule(kbd_intr, None) +schedule(kbd_intr, None) +schedule(kbd_intr, None) +schedule(kbd_intr, None) +schedule(kbd_intr, None) +schedule(kbd_intr, None) +schedule(kbd_intr, None) +schedule(kbd_intr, None) +schedule(kbd_intr, None) +schedule(kbd_intr, None) +try: + sleep(0) + sleep(0) + print("fail") +except KeyboardInterrupt: + print("KeyboardInterrupt") + +# This should not raise. +for _ in range(100): + sleep(0) + +######################################################################## +# Test nested scheduling. + + +def callback(_): + schedule(kbd_intr, None) + # This should not raise because we are in schedule context. + for _ in range(100): + sleep(0) + + +schedule(callback, None) +sleep(0) +try: + sleep(0) + sleep(0) + print("fail") +except KeyboardInterrupt: + print("KeyboardInterrupt") diff --git a/tests/micropython/schedule_kbd_intr.py.exp b/tests/micropython/schedule_kbd_intr.py.exp new file mode 100644 index 00000000000..c4ba7730c52 --- /dev/null +++ b/tests/micropython/schedule_kbd_intr.py.exp @@ -0,0 +1,3 @@ +KeyboardInterrupt +KeyboardInterrupt +KeyboardInterrupt From f6234333330f8a1b665fbf23fddb894607560a1f Mon Sep 17 00:00:00 2001 From: Jeongseop Lim Date: Tue, 21 Jul 2026 16:21:43 +0900 Subject: [PATCH 560/635] py/mpz: Fix 3-arg pow() with zero base and zero exponent. pow(0, 0, m) returned 0 instead of 1 because mpz_pow3_inpl() folded the zero-base check into the guard that returns 0, without looking at the exponent. Move that check below the zero-exponent early return, where the exponent is already known to be non-zero. This keeps the existing short-circuit for a zero base with a large exponent, and does not change the code size. Signed-off-by: Jeongseop Lim --- py/mpz.c | 7 ++++++- tests/basics/builtin_pow3.py | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/py/mpz.c b/py/mpz.c index d8fca0adf95..b6ec8a85faf 100644 --- a/py/mpz.c +++ b/py/mpz.c @@ -1356,7 +1356,7 @@ void mpz_pow_inpl(mpz_t *dest, const mpz_t *lhs, const mpz_t *rhs) { can have dest, lhs, rhs the same; mod can't be the same as dest */ void mpz_pow3_inpl(mpz_t *dest, const mpz_t *lhs, const mpz_t *rhs, const mpz_t *mod) { - if (lhs->len == 0 || rhs->neg != 0 || (mod->len == 1 && mod->dig[0] == 1)) { + if (rhs->neg != 0 || (mod->len == 1 && mod->dig[0] == 1)) { mpz_set_from_int(dest, 0); return; } @@ -1367,6 +1367,11 @@ void mpz_pow3_inpl(mpz_t *dest, const mpz_t *lhs, const mpz_t *rhs, const mpz_t return; } + if (lhs->len == 0) { + mpz_set_from_int(dest, 0); + return; + } + mpz_t *x = mpz_clone(lhs); mpz_t *n = mpz_clone(rhs); mpz_t quo; diff --git a/tests/basics/builtin_pow3.py b/tests/basics/builtin_pow3.py index 2dbe0d33e4b..33b8b198dec 100644 --- a/tests/basics/builtin_pow3.py +++ b/tests/basics/builtin_pow3.py @@ -12,6 +12,9 @@ print(pow(0, 1, 1)) print(pow(1, 0, 1)) print(pow(1, 0, 2)) +print(pow(0, 0, 5)) +print(pow(0, 1, 5)) +print(pow(0, 0, 1)) # 3 arg pow is defined to only work on integers try: From ff318fa58fa4cef17664685feaac0fedf228046c Mon Sep 17 00:00:00 2001 From: Jeongseop Lim Date: Wed, 22 Jul 2026 22:55:00 +0900 Subject: [PATCH 561/635] py/mpz: Fix 3-arg pow() with zero exponent and negative modulus. pow(x, 0, m) returned 1 for every modulus, but in Python the result of a 3-arg pow() takes the sign of the modulus, so pow(3, 0, -5) is -4 and not 1. mpz_pow3_inpl() sets the accumulator to 1 and returns straight away when the exponent is zero, which skips the square-and-multiply loop and with it the mpz_divmod_inpl() calls that are the only place the modulus is ever applied. A non-zero exponent is therefore already correct. Reduce the accumulator before that early return. The entry guard has already rejected abs(mod) == 1, so 1 % mod is exactly 1 + mod for a negative modulus and a single mpz_add_inpl() is enough. This adds 40 bytes to the unix x64 build-standard firmware. Signed-off-by: Jeongseop Lim --- py/mpz.c | 4 ++++ tests/basics/builtin_pow3.py | 7 +++++++ tests/basics/builtin_pow3_intbig.py | 3 +++ 3 files changed, 14 insertions(+) diff --git a/py/mpz.c b/py/mpz.c index b6ec8a85faf..e9fd0f45f02 100644 --- a/py/mpz.c +++ b/py/mpz.c @@ -1364,6 +1364,10 @@ void mpz_pow3_inpl(mpz_t *dest, const mpz_t *lhs, const mpz_t *rhs, const mpz_t mpz_set_from_int(dest, 1); if (rhs->len == 0) { + // Python style modulo: 1 % mod is 1 + mod, as abs(mod) >= 2 here + if (mod->neg) { + mpz_add_inpl(dest, dest, mod); + } return; } diff --git a/tests/basics/builtin_pow3.py b/tests/basics/builtin_pow3.py index 33b8b198dec..3a183a80467 100644 --- a/tests/basics/builtin_pow3.py +++ b/tests/basics/builtin_pow3.py @@ -16,6 +16,13 @@ print(pow(0, 1, 5)) print(pow(0, 0, 1)) +# a negative modulus gives a result with the sign of the modulus +print(pow(1, 0, -1)) +print(pow(1, 0, -2)) +print(pow(3, 0, -5)) +print(pow(-3, 0, -5)) +print(pow(3, 4, -5)) + # 3 arg pow is defined to only work on integers try: print(pow("x", 5, 6)) diff --git a/tests/basics/builtin_pow3_intbig.py b/tests/basics/builtin_pow3_intbig.py index 41d2acbc0cc..c91b4d173dd 100644 --- a/tests/basics/builtin_pow3_intbig.py +++ b/tests/basics/builtin_pow3_intbig.py @@ -9,6 +9,9 @@ print(pow(555557, 1000002, 1000003)) +# a zero exponent with a large negative modulus +print(pow(3, 0, -(2**70))) + # Tests for 3 arg pow with large values # This value happens to be prime From 2210d28792f4b29f7028bed9f475ccc642f7593e Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Thu, 23 Jul 2026 17:03:22 +0200 Subject: [PATCH 562/635] py/emitnative: Do not clobber source register in unary operations. This commit updates the native code generator to use a different registers set when emitting code for unary negations and bitwise inversions on integers. Originally, the native emitter would perform an in-place operation on the value and thus clobber the register holding the value for further operations. This meant that code like @micropython.viper def f() -> int: x = -1 x1 = -x print(x1, x) return x1 would print the same value twice, as x would get updated with the negated value and then assigned to x1. With these changes, the value is placed in the return register directly whenever possible, and away from potential registers that may be reused later. This is performed in a way that is compatible with the NEG and NOT implementations of all currently implemented emitters. Additional validation of this new behaviour is provided with an extension to the `micropython/viper_unop` test, performing additional checks on whether clobbering did take place or not. Signed-off-by: Alessandro Gatti --- py/emitnative.c | 25 +++++++++++----------- tests/micropython/viper_unop.py | 33 +++++++++++++++++++++++++++++ tests/micropython/viper_unop.py.exp | 3 +++ 3 files changed, 49 insertions(+), 12 deletions(-) diff --git a/py/emitnative.c b/py/emitnative.c index 7533f8374f1..14f6423d354 100644 --- a/py/emitnative.c +++ b/py/emitnative.c @@ -2338,22 +2338,23 @@ static void emit_native_unary_op(emit_t *emit, mp_unary_op_t op) { if (op == MP_UNARY_OP_POSITIVE) { // No-operation, just leave the argument on the stack. } else if (op == MP_UNARY_OP_NEGATIVE) { - int reg = REG_RET; - emit_pre_pop_reg_flexible(emit, &vtype, ®, reg, reg); - ASM_NEG_REG(emit->as, reg); - emit_post_push_reg(emit, vtype, reg); + emit_pre_pop_reg(emit, &vtype, REG_RET); + ASM_NEG_REG(emit->as, REG_RET); + emit_post_push_reg(emit, vtype, REG_RET); } else if (op == MP_UNARY_OP_INVERT) { + emit_pre_pop_reg(emit, &vtype, REG_RET); #ifdef ASM_NOT_REG - int reg = REG_RET; - emit_pre_pop_reg_flexible(emit, &vtype, ®, reg, reg); - ASM_NOT_REG(emit->as, reg); + ASM_NOT_REG(emit->as, REG_RET); #else - int reg = REG_RET; - emit_pre_pop_reg_flexible(emit, &vtype, ®, REG_ARG_1, reg); - ASM_MOV_REG_IMM(emit->as, REG_ARG_1, -1); - ASM_XOR_REG_REG(emit->as, reg, REG_ARG_1); + #if REG_RET != REG_ARG_1 + int reg = REG_ARG_1; + #else + int reg = REG_ARG_2; + #endif + ASM_MOV_REG_IMM(emit->as, reg, -1); + ASM_XOR_REG_REG(emit->as, REG_RET, reg); #endif - emit_post_push_reg(emit, vtype, reg); + emit_post_push_reg(emit, vtype, REG_RET); } else { EMIT_NATIVE_VIPER_TYPE_ERROR(emit, MP_ERROR_TEXT("'not' not implemented"), mp_binary_op_method_name[op]); diff --git a/tests/micropython/viper_unop.py b/tests/micropython/viper_unop.py index 61cbd5125f1..80c247a581e 100644 --- a/tests/micropython/viper_unop.py +++ b/tests/micropython/viper_unop.py @@ -29,3 +29,36 @@ def inv(x: int) -> int: print(inv(0)) print(inv(1)) print(inv(-2)) + + +@micropython.viper +def posc() -> int: + x = -1 + x1 = +x + assert x == -1 + return x1 + + +print(posc()) + + +@micropython.viper +def negc() -> int: + x = -1 + x1 = -x + assert x == -1 + return x1 + + +print(negc()) + + +@micropython.viper +def invc() -> int: + x = -1 + x1 = ~x + assert x == -1 + return x1 + + +print(invc()) diff --git a/tests/micropython/viper_unop.py.exp b/tests/micropython/viper_unop.py.exp index 6d93312caa1..9e9a5f4715f 100644 --- a/tests/micropython/viper_unop.py.exp +++ b/tests/micropython/viper_unop.py.exp @@ -7,3 +7,6 @@ -1 -2 1 +-1 +1 +0 From 5f2181f938713dd79134d95318a7a0ab9bace6d4 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 22 Jul 2026 16:41:04 +1000 Subject: [PATCH 563/635] py/gc: Track the min/max of the entire heap area when using split heap. This allows short-circuiting the gc_get_ptr_area() call for values which aren't in the overall range of any of the GC areas. Without this, scanning of buffers is walking the linked list of areas for every value (including all zeros, etc). Splits the gc_get_ptr_area() function into two - gc_verify_ptr_get_area() which inlines "fast path" cases for non-pointer data, and gc_get_ptr_area() where the pointer is expected to be valid. This might be something we can revert if we later on add "no scan" allocations for byte arrays, etc. as that will preempt the need to scan most of these structures. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- py/gc.c | 41 +++++++++++++++++++++++++++++++++-------- py/mpstate.h | 4 ++++ 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/py/gc.c b/py/gc.c index c1a19da3efa..a75d26eca9e 100644 --- a/py/gc.c +++ b/py/gc.c @@ -206,6 +206,10 @@ static void gc_setup_area(mp_state_mem_area_t *area, void *start, void *end) { #if MICROPY_GC_SPLIT_HEAP area->next = NULL; + + // Update the global min/max region that covers all heaps + MP_STATE_MEM(area_pool_min) = MIN(MP_STATE_MEM(area_pool_min), area->gc_pool_start); + MP_STATE_MEM(area_pool_max) = MAX(MP_STATE_MEM(area_pool_max), area->gc_pool_end); #endif DEBUG_printf("GC layout:\n"); @@ -235,6 +239,13 @@ void gc_init(void *start, void *end) { end = (void *)((uintptr_t)end & (~(BYTES_PER_BLOCK - 1))); DEBUG_printf("Initializing GC heap: %p..%p = " UINT_FMT " bytes\n", start, end, (byte *)end - (byte *)start); + #if MICROPY_GC_SPLIT_HEAP + // Note: min/max are deliberately swapped here, gc_setup_area() will update them to + // the correct values for the min/max of the first actual pool region + MP_STATE_MEM(area_pool_min) = end; + MP_STATE_MEM(area_pool_max) = start; + #endif + gc_setup_area(&MP_STATE_MEM(area), start, end); // set last free ATB index to start of heap @@ -392,12 +403,24 @@ bool gc_is_locked(void) { } #if MICROPY_GC_SPLIT_HEAP -// Returns the area to which this pointer belongs, or NULL if it isn't -// allocated on the GC-managed heap. -static inline mp_state_mem_area_t *gc_get_ptr_area(const void *ptr) { - if (((uintptr_t)(ptr) & (BYTES_PER_BLOCK - 1)) != 0) { // must be aligned on a block - return NULL; +static mp_state_mem_area_t *gc_get_ptr_area(const void *ptr); + +// Returns the area to which this arbitrary pointer belongs, or NULL if it isn't +// allocated on the GC-managed heap. Contains "fast path" inline checks for invalid +// data which isn't a pointer to the heap. Equivalent of VERIFY_PTR for the non-split-heap case. +static inline MP_ALWAYSINLINE mp_state_mem_area_t *gc_verify_ptr_get_area(const void *ptr) { + // These inline checks are similar to VERIFY_PTR macro, below + if ((byte *)ptr < MP_STATE_MEM(area_pool_min) || (byte *)ptr > MP_STATE_MEM(area_pool_max)) { + return NULL; // not in the overall pool region + } + if (((uintptr_t)(ptr) & (BYTES_PER_BLOCK - 1)) != 0) { + return NULL; // not aligned on a block boundary } + return gc_get_ptr_area(ptr); +} + +// Returns the area to which a pointer belongs. Assumes pointer is valid to a heap block. +static mp_state_mem_area_t *gc_get_ptr_area(const void *ptr) { for (mp_state_mem_area_t *area = &MP_STATE_MEM(area); area != NULL; area = NEXT_AREA(area)) { if (ptr >= (void *)area->gc_pool_start // must be above start of pool && ptr < (void *)area->gc_pool_end) { // must be below end of pool @@ -406,7 +429,7 @@ static inline mp_state_mem_area_t *gc_get_ptr_area(const void *ptr) { } return NULL; } -#endif +#else // ptr should be of type void* #define VERIFY_PTR(ptr) ( \ @@ -415,6 +438,8 @@ static inline mp_state_mem_area_t *gc_get_ptr_area(const void *ptr) { && ptr < (void *)MP_STATE_MEM(area).gc_pool_end /* must be below end of pool */ \ ) +#endif + #ifdef TRACE_MARK #error "TRACE_MARK is replaced by TRACE_MARK_R and TRACE_MARK_S" #endif @@ -470,7 +495,7 @@ void gc_collect_root(void **ptrs, size_t len) { MICROPY_GC_HOOK_LOOP(i); void *ptr = gc_get_ptr(ptrs, i); #if MICROPY_GC_SPLIT_HEAP - mp_state_mem_area_t *area = gc_get_ptr_area(ptr); + mp_state_mem_area_t *area = gc_verify_ptr_get_area(ptr); if (!area) { continue; } @@ -527,7 +552,7 @@ static void gc_mark_subtree(size_t block) // If this is a heap pointer that hasn't been marked, mark it and push // it's children to the stack. #if MICROPY_GC_SPLIT_HEAP - mp_state_mem_area_t *ptr_area = gc_get_ptr_area(ptr); + mp_state_mem_area_t *ptr_area = gc_verify_ptr_get_area(ptr); if (!ptr_area) { // Not a heap-allocated pointer (might even be random data). continue; diff --git a/py/mpstate.h b/py/mpstate.h index 004593496e2..73353092073 100644 --- a/py/mpstate.h +++ b/py/mpstate.h @@ -129,6 +129,10 @@ typedef struct _mp_state_mem_t { #endif mp_state_mem_area_t area; + #if MICROPY_GC_SPLIT_HEAP + byte *area_pool_min; // Min of all gc_pool_start values across all areas + byte *area_pool_max; // Max of all gc_pool_end values across all areas + #endif int gc_stack_overflow; MICROPY_GC_STACK_ENTRY_TYPE gc_block_stack[MICROPY_ALLOC_GC_STACK_SIZE]; From 916f042bbbf8df0119eb06f5228b5552e6e0fd9f Mon Sep 17 00:00:00 2001 From: Tomasz Cwik Date: Sat, 17 Jan 2026 13:36:13 +0100 Subject: [PATCH 564/635] docs/rp2: Update general and PIO docs for RP2350 support. Update rp2/general.rst to include detailed technical specifications for the RP2350 microcontroller Extend rp2/tutorial/pio.rst to cover RP2350 PIO enhancements Signed-off-by: Tomasz Cwik --- docs/rp2/general.rst | 40 ++++++++++++++++--- docs/rp2/tutorial/pio.rst | 81 +++++++++++++++++++++++++++++++-------- 2 files changed, 101 insertions(+), 20 deletions(-) diff --git a/docs/rp2/general.rst b/docs/rp2/general.rst index 05b44f051ee..c63560bae38 100644 --- a/docs/rp2/general.rst +++ b/docs/rp2/general.rst @@ -4,17 +4,18 @@ General information about the RP2xxx port ========================================= The rp2 port supports boards powered by the Raspberry Pi Foundation's RP2xxx -family of microcontrollers, most notably the Raspberry Pi Pico that employs -the RP2040. +family of microcontrollers, including the RP2040 and RP2350. Technical specifications and SoC datasheets ------------------------------------------- -For detailed technical specifications, please refer to the `datasheets -`_ +RP2040 +^^^^^^ The RP2040 microcontroller is manufactured on a 40 nm silicon process in a 7x7mm -QFN-56 SMD package. The key features include: +QFN-56 SMD package. + +The key features include: * 133 MHz dual ARM Cortex-M0+ cores (overclockable to over 400 MHz) * 264KB SRAM in six independent banks @@ -34,3 +35,32 @@ The peripherals include: * 16 PWM channels * USB 1.1 controller * 8 PIO state machines + +For detailed technical specifications, please refer to the `rp2040-datasheet +`_ + +RP2350 +^^^^^^ + +The RP2350 microcontroller is manufactured on a 40 nm silicon process and is available in +QFN-60 (RP2350A) or QFN-80 (RP2350B) packages. + +The key features include: + +* Dual-core Arm Cortex-M33 or Hazard3 RISC-V processors at up to 150MHz +* 520KB on-chip SRAM +* Support for up to 16MB of off-chip Flash memory via QSPI +* USB 2.0 Full-Speed/Low-Speed controller +* 30 GPIO pins (RP2350A) or 48 GPIO pins (RP2350B) + +The peripherals include: + +* 2 UARTs +* 2 SPI controllers +* 2 I2C controllers +* 24 PWM channels +* 12 PIO state machines +* HSTX high-speed transmitter + +For detailed technical specifications, please refer to the `rp2350-datasheet +`_ diff --git a/docs/rp2/tutorial/pio.rst b/docs/rp2/tutorial/pio.rst index 4e519650eea..65b7cd97637 100644 --- a/docs/rp2/tutorial/pio.rst +++ b/docs/rp2/tutorial/pio.rst @@ -1,21 +1,57 @@ Programmable IO =============== -The RP2040 has hardware support for standard communication protocols like I2C, -SPI and UART. For protocols where there is no hardware support, or where there -is a requirement of custom I/O behaviour, Programmable Input Output (PIO) comes -into play. Also, some MicroPython applications make use of a technique called -bit banging in which pins are rapidly turned on and off to transmit data. This -can make the entire process slow as the processor concentrates on bit banging -rather than executing other logic. However, PIO allows bit banging to happen -in the background while the CPU is executing the main work. - -Along with the two central Cortex-M0+ processing cores, the RP2040 has two PIO -blocks each of which has four independent state machines. These state machines -can transfer data to/from other entities using First-In-First-Out (FIFO) buffers, -which allow the state machine and main processor to work independently yet also -synchronise their data. Each FIFO has four words (each of 32 bits) which can be -linked to the DMA to transfer larger amounts of data. +The RP2xxx family of microcontrollers provides hardware support for standard +communication protocols like I2C, SPI and UART. For protocols where there +is no hardware support, or where there is a requirement of custom I/O +behaviour, Programmable Input Output (PIO) comes into play. Also, some +MicroPython applications make use of a technique called bit banging in which +pins are rapidly turned on and off to transmit data. This can make the entire +process slow as the processor concentrates on bit banging rather than executing +other logic. However, PIO allows bit banging to happen in the background while +the CPU is executing the main work. + +PIO State Machines +------------------ + +State machines transfer data to/from other entities using First-In-First-Out (FIFO) +buffers, which allow the state machine and main processor to work independently +yet also synchronise their data. The FIFOs can be linked to the DMA to transfer +larger amounts of data without extensive CPU usage. + + +**RP2040** +^^^^^^^^^^ + +The RP2040 has two PIO blocks, each with four independent state machines (total of 8). + +Each FIFO has four words (each of 32 bits) per state machine (TX and RX). + +**RP2350** +^^^^^^^^^^ + +The RP2350 has three PIO blocks, each with four independent state machines (total of 12). + +Similar to the RP2040, each state machine has a four-word FIFO per state machine (TX and RX), +but they have some additional functions + +For each state machine: + +- TX or RX FIFOs can be combined into a single 8-word FIFO for higher bandwidth. +- The RX FIFO supports random read/write access to its registers. + +**Compatibility** +^^^^^^^^^^^^^^^^^ + +RP2350 PIO is backward-compatible with RP2040, with some additional enhancements. + +At the moment, native support for RP2350 PIO enhancements is very limited, +but work for some features are already in progress + +Instructions +------------ + +Each PIO block has 32 instructions of memory shared among its four state machines. All PIO instructions follow a common pattern:: @@ -124,3 +160,18 @@ the following: The entire routine takes exactly 2000 cycles of the state machine. Setting the frequency of the state machine to 2000Hz makes the LED blink at 1Hz. + +This example works identically on both RP2040 and RP2350 (using StateMachine ID 0). On +RP2350, higher ``freq`` values are possible due to the faster system clock. + +Compatibility Notes +------------------- + +PIO programs using the basic instructions shown here are fully compatible between RP2040 +and RP2350. The MicroPython ``rp2`` module API (including ``@rp2.asm_pio``, +``StateMachine``, etc.) is the same, though RP2350 supports StateMachine IDs 0–11. + +RP2350 offers additional advanced features (new instructions, FIFO modes, security, GPIO +relocation) not covered in this introduction; see the RP2350 datasheet for details. Some +programs may require minor adjustments due to differences in default GPIO reset states +between the two chips. From af6ec91475ec3c9e03d986da8ebabd01320e1bb3 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Wed, 21 Jan 2026 23:43:00 +1100 Subject: [PATCH 565/635] docs: Improve micropython.const() documentation and consistency. Expanded the micropython.const() documentation in library/micropython.rst to address gaps identified through investigation of GitHub issues and user confusion: - Added explicit scope requirement (module-level only) with explanation of why using const() in functions/classes causes confusing behavior - Added import syntax requirement warning (must use bare name "const", not "micropython.const()" or aliased imports) - Clarified storage and visibility differences between underscore and non-underscore prefixed constants, with RAM quantification - Added complete list of valid expression types (integers, floats, strings, bytes, booleans, None, tuples) - Documented cross-module mutability behavior and typing.Final alternative - Added limitations section covering all known issues including type hint incompatibility - Added substitution rules explaining when values are not substituted - Expanded examples section Fixed inconsistency in reference/speed_python.rst that incorrectly claimed const() only accepts integers. Updated to correctly state it accepts any compile-time constant. Added cross-references from all const documentation locations (speed_python.rst, constrained.rst, optimizations.rst) back to the comprehensive micropython.const() documentation. These changes address confusion reported in GitHub issues #573, #11929, #15246, #15608, and #17453. Signed-off-by: Andrew Leech Signed-off-by: Andrew Leech --- docs/develop/optimizations.rst | 3 ++ docs/library/micropython.rst | 73 +++++++++++++++++++++++++++++---- docs/reference/constrained.rst | 3 ++ docs/reference/speed_python.rst | 8 +++- 4 files changed, 76 insertions(+), 11 deletions(-) diff --git a/docs/develop/optimizations.rst b/docs/develop/optimizations.rst index 533dd64116f..3f07aebbc66 100644 --- a/docs/develop/optimizations.rst +++ b/docs/develop/optimizations.rst @@ -59,6 +59,9 @@ Compiles to: X = 1 foo(1, 2) +See :func:`micropython.const` for complete details on usage requirements and +limitations. + Allocation of memory -------------------- diff --git a/docs/library/micropython.rst b/docs/library/micropython.rst index c2302929662..c5fdf41099d 100644 --- a/docs/library/micropython.rst +++ b/docs/library/micropython.rst @@ -17,15 +17,70 @@ Functions CONST_X = const(123) CONST_Y = const(2 * CONST_X + 1) - Constants declared this way are still accessible as global variables from - outside the module they are declared in. On the other hand, if a constant - begins with an underscore then it is hidden, it is not available as a global - variable, and does not take up any memory during execution. - - This `const` function is recognised directly by the MicroPython parser and is - provided as part of the :mod:`micropython` module mainly so that scripts can be - written which run under both CPython and MicroPython, by following the above - pattern. + When the parser encounters ``NAME = const(expr)``, it evaluates the expression + at compile time and substitutes the resulting value directly into the bytecode at + every use of ``NAME``, avoiding a global dictionary lookup each time. + + The ``const`` name is recognised directly by the parser so no import is actually + required in MicroPython. However ``from micropython import const`` is recommended + so the script also runs on CPython where ``const`` is provided as an identity + function. Note that the parser only recognises the bare name ``const`` -- using + ``micropython.const()`` (with module prefix) or an alias will not trigger the + optimisation. + + Constants declared this way are still stored as global variables in the module's + dictionary, so other modules can access them (e.g. + ``import mymodule; print(mymodule.X)``). Reassigning the global from another + module does not affect the inlined values within the defining module. This global + entry costs at least two machine words of RAM. + + **Module-private constants:** To avoid this RAM cost, prefix the name with an + underscore (e.g. ``_X = const(1)``). This prevents the variable from being added + to the module dictionary and hides it from other modules. + + The expression passed to ``const()`` must be evaluable at compile time. Supported + types are: + + - ``int`` (including expressions with arithmetic and bitwise operators) + - ``float`` + - ``str`` + - ``bytes`` + - ``bool`` (``True``, ``False``), ``None``, ``...`` (Ellipsis) + - ``tuple`` of constants + + The expression can reference previously defined constants. Using runtime values + or function calls raises ``SyntaxError: not a constant``. + + Examples:: + + BUFFER_SIZE = const(1024) + BUFFER_MASK = const(BUFFER_SIZE - 1) + FLAGS = const(0x01 | 0x02) + _SCALE = const(0.001) + _PREFIX = const("data_") + _HEADER = const(b"\x00\xff") + _MODES = const(("read", "write")) + + Because the compiler evaluates boolean constants at compile time, ``const()`` + can be used for conditional compilation. Code guarded by a false constant is + eliminated from the bytecode entirely, and when frozen via ``mpy-cross`` the + unreachable code is stripped from the output:: + + FEATURE_X = const(True) + + if FEATURE_X: + def feature_x_handler(): + ... + + For cross-platform compatibility with CPython, the typical pattern is:: + + try: + from micropython import const + except ImportError: + const = lambda x: x + + See also :ref:`constrained` and :ref:`speed_python` for practical guidance on + using constants to reduce memory usage and improve performance. .. function:: opt_level([level]) diff --git a/docs/reference/constrained.rst b/docs/reference/constrained.rst index 60f76b9c783..224a2c58067 100644 --- a/docs/reference/constrained.rst +++ b/docs/reference/constrained.rst @@ -116,6 +116,9 @@ to a constant e.g. ``0x100``, ``1 << 8`` or ``(True, "string", b"bytes")`` (see section below for details). It can even include other const symbols that have already been defined, e.g. ``1 << BIT``. +See :func:`micropython.const` for complete documentation including scope +requirements, import syntax, and other important limitations. + **Constant data structures** Where there is a substantial volume of constant data and the platform supports diff --git a/docs/reference/speed_python.rst b/docs/reference/speed_python.rst index 6382394bd50..b3357066175 100644 --- a/docs/reference/speed_python.rst +++ b/docs/reference/speed_python.rst @@ -182,9 +182,13 @@ The const() declaration MicroPython provides a ``const()`` declaration. This works in a similar way to ``#define`` in C in that when the code is compiled to bytecode the compiler -substitutes the numeric value for the identifier. This avoids a dictionary +substitutes the constant value for the identifier. This avoids a dictionary lookup at runtime. The argument to ``const()`` may be anything which, at -compile time, evaluates to an integer e.g. ``0x100`` or ``1 << 8``. +compile time, evaluates to a constant e.g. ``0x100``, ``1 << 8``, +``"string"``, ``0.001``, ``b"\x00\xff"`` or ``("read", "write")``. + +See :func:`micropython.const` for complete documentation including usage +requirements, limitations, and examples. .. _Caching: From c78230b81c1ccf4827b73ab6ee84b6895816f571 Mon Sep 17 00:00:00 2001 From: MarcelloTheArcane <21159570+MarcelloTheArcane@users.noreply.github.com> Date: Sat, 7 Mar 2026 20:46:21 +0000 Subject: [PATCH 566/635] docs/rp2/quickref: Add REPL over UART information. Add link and example to os.dupterm. Add link and example for building from source. Co-authored-by: Angus Gratton Signed-off-by: MarcelloTheArcane --- docs/rp2/quickref.rst | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/docs/rp2/quickref.rst b/docs/rp2/quickref.rst index e678d67e6ea..8e0f6d6bae7 100644 --- a/docs/rp2/quickref.rst +++ b/docs/rp2/quickref.rst @@ -207,10 +207,26 @@ See :ref:`machine.UART `. :: uart1.write('hello') # write 5 bytes uart1.read(5) # read up to 5 bytes -.. note:: +It is possible to access the REPL over UART, but this is disabled by +default. To duplicate the REPL stream over UART, use :func:`os.dupterm`. +This code should be in :ref:`boot.py` or :ref:`main.py` to establish UART on boot. + +.. code-block:: python + + from machine import UART + import os + uart = UART(0) + os.dupterm(uart, 0) + uart.irq(os.dupterm_notify, UART.IRQ_RXIDLE) # ensure inputs are handled + +To use UART for REPL instead of the standard USB interface (for example if you are +using :mod:`machine.USBDevice`), you will need to :doc:`build MicroPython from source `. +Modify ``ports/rp2/mpconfigport.h``, and change the ``MICROPY_HW_ENABLE_UART_REPL`` +variable to ``1``: + +.. code-block:: c - REPL over UART is disabled by default. You can see the :ref:`rp2_intro` for - details on how to enable REPL over UART. + #define MICROPY_HW_ENABLE_UART_REPL (1) // useful if there is no USB PWM (pulse width modulation) From 0ee1eba9e1d425edb416cf4b483250a8a3331e89 Mon Sep 17 00:00:00 2001 From: Andrii Anoshyn Date: Sun, 17 May 2026 13:52:47 +0300 Subject: [PATCH 567/635] docs/reference/mpremote: Clarify how the run command treats main.py. Issue #15955 reports the impression that ``mpremote run /path/to/main.py`` runs the device's own ``main.py`` instead of the local file. In practice ``run`` reads the local file as bytes and executes them in raw REPL after a soft reset, so the local filename has no special meaning and the device's ``main.py`` is not executed beforehand. Add a short Note that spells this out, since the existing description does not mention the soft-reset / raw-REPL execution flow. Fixes #15955. Signed-off-by: Andrii Anoshyn --- docs/reference/mpremote.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/reference/mpremote.rst b/docs/reference/mpremote.rst index 8aecc3a5d48..14f6b81996f 100644 --- a/docs/reference/mpremote.rst +++ b/docs/reference/mpremote.rst @@ -215,6 +215,12 @@ The full list of supported commands are: terminates. The ``--no-follow`` flag can be specified to return immediately and leave the device running the script in the background. + **Note:** Only the contents of the local file are sent to the device; the + local filename has no special meaning, so passing a file called ``main.py`` + is no different from any other name. The script is executed in raw REPL + after a soft reset, so the device's own ``main.py`` is not run beforehand. + Any ``main.py`` already stored on the device filesystem is left untouched. + .. _mpremote_command_fs: - **fs** -- execute filesystem commands on the device: From 1645d3d24263997591de2975a09caeb7b72b088c Mon Sep 17 00:00:00 2001 From: Howard Lovatt Date: Sat, 30 May 2026 11:32:27 +1000 Subject: [PATCH 568/635] docs/library/machine: Clarify Signal constructor with inverted pins. The behaviour of the two constructors have a subtle difference that is worth documenting. Signed-off-by: Howard Lovatt --- docs/library/machine.Signal.rst | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/docs/library/machine.Signal.rst b/docs/library/machine.Signal.rst index 46f487b0d29..57b07e304bc 100644 --- a/docs/library/machine.Signal.rst +++ b/docs/library/machine.Signal.rst @@ -93,6 +93,34 @@ Constructors - ``invert`` - if True, the signal will be inverted (active low). + .. note:: + The value of the pin can be set in the Pin constructor *and/or* the Signal constructor. + If the Signal is also *inverted* then a value set in the *Pin* constructor will be in the opposite sense. + + Example:: + + >>> c0 = Signal(Pin(0, Pin.OUT, value=0), invert=True) + >>> c0() + 1 + >>> c1 = Signal(1, Pin.OUT, value=0, invert=True) + >>> c1() + 0 + + The first creates the pin and sets it's initial value and then Signal inverts the logic. + Whereas, the second sets the pin to the inverted value. + + This behavior is only different after construction and before a call + to a 'set' method. + + Example:: + + >>> c0.off() + >>> c0() + 0 + >>> c1.off() + >>> c1() + 0 + Methods ------- From aee96a01b7128aa8003740c7bcd2ee975a1a2f3f Mon Sep 17 00:00:00 2001 From: IhorNehrutsa Date: Mon, 3 Aug 2026 15:19:15 +0300 Subject: [PATCH 569/635] docs/esp32/quickref: Add config for ESP32-WROOM-32UE with KSZ8863 LAN. Signed-off-by: Ihor Nehrutsa --- docs/esp32/quickref.rst | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/docs/esp32/quickref.rst b/docs/esp32/quickref.rst index d0662ea8763..6b3fa951653 100644 --- a/docs/esp32/quickref.rst +++ b/docs/esp32/quickref.rst @@ -192,9 +192,19 @@ These are working configurations for LAN interfaces of some popular ESP32 boards # Espressif ESP32-Ethernet-Kit_A_V1.2 - lan = network.LAN(id=0, mdc=Pin(23), mdio=Pin(18), power=Pin(5), + lan = network.LAN(id=0, mdc=machine.Pin(23), mdio=machine.Pin(18), power=machine.Pin(5), phy_type=network.PHY_IP101, phy_addr=1) + # ESP32-WROOM-32UE with KSZ8863RLL (Integrated 3-Port 10/100 Managed Switch with PHYs) + + lan = network.LAN(mdc=machine.Pin(23), # connected to SCL_MDC pin of KSZ8863RLL + mdio=machine.Pin(15), # connected to SDA_MDIO pin of KSZ8863RLL + power=machine.Pin(16), # connected to RSTN pin of KSZ8863RLL + phy_type=network.PHY_GENERIC, + phy_addr=3, + ref_clk_mode=machine.Pin.IN, + ref_clk=machine.Pin(0)) # REF_CLK 50MHz from KSZ8863RLL + .. _esp32_spi_ethernet: From fe22d575fe0261b6de550fc352bf0f7d9d59247e Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Sun, 7 Jun 2026 17:15:14 +0200 Subject: [PATCH 570/635] docs/esp8266: Clarify flashing ESP8266 devices with >4 MB flash. Updated to current firmware variants Removed python 2.7 references. Signed-off-by: Jos Verlinde --- docs/esp8266/tutorial/intro.rst | 151 ++++++++++++++++++++++++-------- 1 file changed, 116 insertions(+), 35 deletions(-) diff --git a/docs/esp8266/tutorial/intro.rst b/docs/esp8266/tutorial/intro.rst index 0d4bc42e2da..789fc287c27 100644 --- a/docs/esp8266/tutorial/intro.rst +++ b/docs/esp8266/tutorial/intro.rst @@ -20,12 +20,25 @@ characteristic of a board is how much flash it has, how the GPIO pins are connected to the outside world, and whether it includes a built-in USB-serial converter to make the UART available to your PC. -The minimum requirement for flash size is 1Mbyte. There is also a special -build for boards with 512KB, but it is highly limited comparing to the -normal build: there is no support for filesystem, and thus features which -depend on it won't work (WebREPL, mip, etc.). As such, 512KB build will -be more interesting for users who build from source and fine-tune parameters -for their particular application. +MicroPython is distributed as several firmware variants to suit the amount of +flash on your board: + +* The standard build (``ESP8266_GENERIC``) targets boards with **2MiB or more** + of flash. This is the recommended build and the best choice for most users. +* The ``FLASH_1M`` variant is for boards with **1MiB** of flash. It removes + asyncio and FAT-filesystem support, as well as some modules from + micropython-lib. +* The ``FLASH_2M_ROMFS`` variant targets **2MiB** boards and reserves part of + the flash for a read-only ROMFS filesystem. +* The ``FLASH_512K`` variant is for boards with only **512kiB** of flash. It is + highly limited compared to the other builds: there is no filesystem support, + and so features that depend on it won't work (WebREPL, mip, etc.). It also + drops framebuffer support, some Python language features, and has less + detailed error messages. This variant is mainly of interest to users who + build from source and fine-tune parameters for their particular application. + +The minimum recommended flash size is therefore 1MiB, with 2MiB or more giving +the best experience. Names of pins will be given in this tutorial using the chip names (eg GPIO0) and it should be straightforward to find which pin this corresponds to on your @@ -43,23 +56,31 @@ Getting the firmware The first thing you need to do is download the most recent MicroPython firmware .bin file to load onto your ESP8266 device. You can download it from the -`MicroPython downloads page `_. -From here, you have 3 main choices +`ESP8266 download page `_. -* Stable firmware builds for 1024kb modules and above. -* Daily firmware builds for 1024kb modules and above. -* Daily firmware builds for 512kb modules. +The download page offers the firmware variants described above. Pick the one +that matches your board's flash size: -If you are just starting with MicroPython, the best bet is to go for the Stable -firmware builds. If you are an advanced, experienced MicroPython ESP8266 user -who would like to follow development closely and help with testing new -features, there are daily builds (note: you actually may need some -development experience, e.g. being ready to follow git history to know -what new changes and features were introduced). +========================================================= ========================================= +Firmware file Board flash size +========================================================= ========================================= +``ESP8266_GENERIC--.bin`` 2MiB-4MiB, 8MiB-16MiB** (the standard build) +``ESP8266_GENERIC-FLASH_1M--.bin`` 1MiB +``ESP8266_GENERIC-FLASH_2M_ROMFS--.bin`` 2MiB-4MiB, 8MiB-16MiB** (includes a ROMFS) +``ESP8266_GENERIC-FLASH_512K--.bin`` 512kiB +========================================================= ========================================= -Support for 512kb modules is provided on a feature preview basis. For end -users, it's recommended to use modules with flash of 1024kb or more. As -such, only daily builds for 512kb modules are provided. +** Boards with 8MiB or 16MiB of flash can use the standard build, +but require an manual step to set up the RF calibration data, see :ref:`esp8266_large_flash` below. + +For each variant the page lists *release* builds and *preview* builds. If you +are just starting with MicroPython, choose the latest release build. If you are +an experienced user who would like to follow development closely and help with +testing new features, the preview builds are automatic builds of the +development branch. + +Throughout the rest of this tutorial the example commands use the standard +``ESP8266_GENERIC`` firmware; substitute the exact filename you downloaded. Deploying the firmware ---------------------- @@ -88,10 +109,6 @@ using pip:: pip install esptool -Versions starting with 1.3 support both Python 2.7 and Python 3.4 (or newer). -An older version (at least 1.2.1 is needed) works fine but will require Python -2.7. - Any other flashing program should work, so feel free to try them out or refer to the documentation for your board to see its recommendations. @@ -101,20 +118,33 @@ Using esptool.py you can erase the flash with the command:: And then deploy the new firmware using:: - esptool.py --port /dev/ttyUSB0 --baud 460800 write_flash --flash_size=detect 0 esp8266-20170108-v1.8.7.bin + esptool.py --port /dev/ttyUSB0 --baud 460800 write_flash --flash_size=detect 0 ESP8266_GENERIC-20260406-v1.28.0.bin You might need to change the "port" setting to something else relevant for your PC. You may also need to reduce the baudrate if you get errors when flashing (eg down to 115200). The filename of the firmware should also match the file that you have. +The ``--flash_size=detect`` option tells esptool.py to read the flash size from +the chip's JEDEC ID. MicroPython itself also autodetects the flash size at +runtime for chips up to **4MB**, so a single firmware build adapts to the actual +flash on your board without any extra configuration. The filesystem is +automatically sized to use all of the available flash. + +The ESP8266 needs a small block of RF calibration data, known as +``esp_init_data``, near the end of the flash before WiFi will start. On first +boot MicroPython checks this region and, if it is blank (for example because you +just ran ``erase_flash``), it automatically writes the default calibration data +for you. For boards with **4MB of flash or less**, no manual step is needed. See +:ref:`esp8266_large_flash` below for boards larger than 4MB. + For some boards with a particular FlashROM configuration (e.g. some variants of a NodeMCU board) you may need to manually set a compatible `SPI Flash Mode `_. You'd usually pick the fastest option that is compatible with your device, but the ``-fm dout`` option (the slowest option) should have the best compatibility:: - esptool.py --port /dev/ttyUSB0 --baud 460800 write_flash --flash_size=detect -fm dout 0 esp8266-20170108-v1.8.7.bin + esptool.py --port /dev/ttyUSB0 --baud 460800 write_flash --flash_size=detect -fm dout 0 ESP8266_GENERIC-20260406-v1.28.0.bin If the above commands run without error then MicroPython should be installed on your board! @@ -123,6 +153,64 @@ If you pulled GPIO0 manually to ground to enter programming mode, release it now and reset the device by again pulling the reset pin to ground for a short duration. +.. _esp8266_large_flash: + +Boards with more than 4MB of flash +---------------------------------- + +Boards with **8MB or 16MB** of flash need one extra step. The flash routines +built into the ESP8266 boot ROM (which MicroPython uses to write the calibration +data on first boot) cannot address flash beyond 4MB: the ROM reads the chip's +device ID but clamps the reported size to 4MB, so any access above that offset +fails. As a result MicroPython can only write the ``esp_init_data`` RF +calibration block automatically within the first 4MB of flash. +So after a full flash erase MicroPython cannot place the calibration data at the correct end-of-flash +address by itself. Without it the WiFi subsystem will not start (typically +showing up as a continuous reset loop or ``rf_cal`` errors). For more background +on this ROM limitation see +`ESP8266 16MB Flash Handling `_. + +To fix this, flash the ``esp_init_data_default.bin`` file (shipped with the +Espressif NONOS SDK) to the calibration address, which is the flash size minus +``0x4000``, see table below. + +You can download ``esp_init_data_default.bin`` from the Espressif repository +(open the link and click "View raw" to download the file): +``__ + +The calibration addresses are: + +=========== ===================================== +Flash size ``esp_init_data`` address +=========== ===================================== +8MB ``0x7FC000`` +16MB ``0xFFC000`` +=========== ===================================== + +The full procedure for a 16MB board is:: + + # 1. Make sure esptool is up to date + pip install --upgrade esptool + + # 2. Erase the flash + esptool.py --port /dev/ttyUSB0 --baud 460800 erase_flash + + # 3. Flash the RF calibration blob at the end of flash (16MB example) + esptool.py --port /dev/ttyUSB0 write_flash 0xFFC000 esp_init_data_default.bin + + # 4. Flash MicroPython, telling esptool the real flash size + esptool.py --port /dev/ttyUSB0 --baud 460800 \ + write_flash -fm dio --flash_size 16MB 0 ESP8266_GENERIC-20260406-v1.28.0.bin + + # 5. Check detected flash size in the REPL + mpremote exec "import esp;print(f'Detected flash: {esp.flash_size():_}')" + +For an 8MB board, use ``0x7FC000`` in step 3 and ``--flash_size 8MB`` in step 4. + +The filesystem is sized automatically from the detected flash size, so it +will use all of the available space once the board boots. + + Serial prompt ------------- @@ -173,15 +261,8 @@ after it, here are troubleshooting recommendations: rate may be too high and lead to errors. Try a more common 115200 baud rate instead in such cases. -* If lower baud rate didn't help, you may want to try older version of - esptool.py, which had a different programming algorithm:: - - pip install esptool==1.0.1 - - This version doesn't support ``--flash_size=detect`` option, so you will - need to specify FlashROM size explicitly (in megabits). It also requires - Python 2.7, so you may need to use ``pip2`` instead of ``pip`` in the - command above. +* If lower baud rate didn't help, you may want to try a different version of + esptool.py, which may use a different programming algorithm. * The ``--flash_size`` option in the commands above is mandatory. Omitting it will lead to a corrupted firmware. From 30f4b9a93b6238c922ad312956100b1539455a4e Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Sun, 7 Jun 2026 17:17:41 +0200 Subject: [PATCH 571/635] esp8266/boards: Add note on flashing boards with >4MiB flash. Signed-off-by: Jos Verlinde --- ports/esp8266/boards/ESP8266_GENERIC/board.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/ports/esp8266/boards/ESP8266_GENERIC/board.md b/ports/esp8266/boards/ESP8266_GENERIC/board.md index b83d2910cd6..96ca8296f05 100644 --- a/ports/esp8266/boards/ESP8266_GENERIC/board.md +++ b/ports/esp8266/boards/ESP8266_GENERIC/board.md @@ -9,6 +9,11 @@ well as some modules from micropython-lib. The 512kiB variant further removes all filesystem support, as well as framebuffer support, some Python language features, and has less detailed error messages. +Boards with more than 4MiB of flash (e.g. 8MiB or 16MiB) need an extra +step to write the `esp_init_data` RF calibration data, otherwise WiFi will not +start. See [Boards with more than 4MB of flash](https://docs.micropython.org/en/latest/esp8266/tutorial/intro.html#boards-with-more-than-4mb-of-flash) +in the tutorial for details. + Note: v1.12-334 and newer (including v1.13) require an ESP8266 module with 2MiB of flash or more, and use littlefs as the filesystem by default. When upgrading from older firmware please backup your files first, and either From 514eb3d19c77d74dce9c5e315bdb18abbf5611a2 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Sun, 9 Aug 2026 20:49:44 +0200 Subject: [PATCH 572/635] tests/README: Explain how to create cpydiff tests. A simple addition to the test README explaining how to create and run cpydiff tests. Signed-off-by: Jos Verlinde --- tests/README.md | 97 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/tests/README.md b/tests/README.md index 534e7e0a059..4edd3e1088e 100644 --- a/tests/README.md +++ b/tests/README.md @@ -3,6 +3,17 @@ This directory contains tests for most parts of MicroPython. To run it you will need CPython 3.8.2 or newer, which is used to validate MicroPython's behaviour. +The tests are organized into several categories: +- Unit and regression tests: tests for MicroPython's core functionality, including the + compiler, runtime, and built-in modules +- perf_bench: performance benchmarks +- internal_bench: internal performance benchmarks +- Serial reliability and performance test +- Test key/certificates +- CPython vs MicroPython Differences + +## Unit and regression tests + To run all stable tests, run the "run-tests.py" script in this directory. By default that will run the test suite against the unix port of MicroPython. @@ -63,7 +74,7 @@ module, should go in the import/ subdirectory. The `perf_bench` directory contains some performance benchmarks that can be used to benchmark different MicroPython firmwares or host ports. -The runner utility is `run-perfbench,py`. Execute `./run-perfbench.py --help` +The runner utility is `run-perfbench.py`. Execute `./run-perfbench.py --help` for a full list of command line options. ### Benchmarking a target @@ -249,3 +260,87 @@ $ openssl ecparam -name prime256v1 -genkey -noout -out ec_key.pem $ openssl pkey -in ec_key.pem -out ec_key.der -outform DER $ openssl req -new -x509 -key ec_key.pem -out ec_cert.der -outform DER -days 3650 -nodes -subj '/CN=micropython.local/O=MicroPython/C=AU' ``` + +## CPython vs MicroPython Differences + +The `tests/cpydiff` folder contains test files that document and verify the differences +between the CPython and MicroPython implementations. + +These tests are designed to: +- Execute the same code on both CPython and MicroPython +- Document behavioral differences between the two implementations +- Generate documentation pages that help users understand these differences + +### How It Works + +1. Each test file contains Python code that demonstrates a specific difference. +2. The tests are executed on both CPython and MicroPython. +3. The output from both implementations is captured and compared. If the outputs are the + same, the generation will fail (because the outputs should be different). +4. The results, along with metadata from the file docstrings, are used to generate + documentation. + +### Documentation Generation + +The documentation is automatically generated using: +``` +tools/gen-cpydiff.py +``` + +This script: +- Parses the docstring metadata from each test file +- Runs the tests on both implementations +- Combines the results to create comprehensive documentation pages +- Outputs formatted reStructuredText documentation showing the differences + +**Note:** This script is automatically executed as part of the documentation publishing +process when building the docs. + +### Test File Format + +The test filename should match the categories of the test. For example, a test with +categories `Syntax,Operators` should be named `syntax_operators_*.py`. + +Each test file should include a docstring with the following format, and include a +minimal code snippet that reproduces the difference when run on both CPython and the +unix port of MicroPython: + +```python +""" +categories: Category,Subcategory +description: Brief description of the difference being tested +cause: Explanation of why this difference exists +workaround: How to work around this difference (or "Unknown" if none) +""" +# Minimal Python code reproducing the difference +import sys +print(sys.implementation.name) +``` + +The categories and subcategories are used to organize the documentation into sections. +Files with the same category and/or subcategory will be placed in the same section. + +Common categories include: +- Syntax +- Core (Core language) +- Types (Builtin types) +- Modules + +### Building the Documentation + +The documentation is automatically regenerated during the documentation build process. +To manually regenerate after adding or modifying tests: + +1. Set environment variables if needed: + - `MICROPY_MICROPYTHON`: Path to MicroPython executable + - `MICROPY_CPYTHON3`: Path to CPython 3.x executable (default: "python3") + +2. Run the generation script from the project root: + ``` + python tools/gen-cpydiff.py + ``` + +The generated documentation will be placed in `docs/genrst/` as reStructuredText files. + +Also see `docs/README.md` for more information on building the documentation locally +to validate the rendering of the resulting documentation page(s). From 73080efb9f4d7ff6eab4081d3fca50265fbfed40 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Tue, 21 Jul 2026 23:05:53 +0200 Subject: [PATCH 573/635] pyproject.toml: Make ruff aware of MicroPython builtins. This commit updates the project-wide configuration for `ruff`, in order to not let it flag usages of MicroPython-specific types and keywords when performing code checks. The tool currently has an exceptions list that covers almost all Python code that ships with MicroPython, however code placed in `ports//modules` (or elsewhere) by users for customisation purposes will end up raising errors for otherwise valid MicroPython-flavoured code. Changes only let `ruff` assume that it knows about the existence of the `micropython` module (used without an initial import) for decorators (eg. `native`, `viper`, `asm_...`, etc.), Viper pointer types (`ptr`, `ptr8`, `ptr16`, `ptr32`), the unsigned integer return type (`uint`), the `const` constructor, and the `execfile` builtin. For code that is placed elsewhere, these rules won't apply, so it might be an option to add further configuration instructions in the "getting started" documentation files. Signed-off-by: Alessandro Gatti --- pyproject.toml | 1 + 1 file changed, 1 insertion(+) diff --git a/pyproject.toml b/pyproject.toml index ef0a9a31174..46665df2930 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -34,6 +34,7 @@ extend-exclude = [ extend-include = ["tools/cc1"] line-length = 99 target-version = "py38" +builtins = ["ptr", "ptr8", "ptr16", "ptr32", "uint", "micropython", "const", "execfile"] [tool.ruff.lint] exclude = [ # Ruff finds Python SyntaxError in these files From 3a89fc2411d78c63b4092e5c00b7b0e01e68513c Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 31 Jul 2026 20:19:48 +0200 Subject: [PATCH 574/635] extmod/vfs_posix: Fix renaming with a non-empty VFS root. This commit fixes an issue occurring when renaming a file through the POSIX VFS interface, if the internal VFS root is non-empty. The code would translate the old and new logical file paths into their physical counterparts by reusing the same buffer to build the path data, and returning a pointer to the buffer in question. These changes simply make a copy of the first path being built so it won't be replaced by the time the second path is built. Signed-off-by: Alessandro Gatti --- extmod/vfs_posix.c | 6 +++++- tests/extmod/vfs_posix.py | 9 +++++++++ tests/extmod/vfs_posix.py.exp | 2 ++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/extmod/vfs_posix.c b/extmod/vfs_posix.c index 27f833e802f..90030db1965 100644 --- a/extmod/vfs_posix.c +++ b/extmod/vfs_posix.c @@ -341,10 +341,14 @@ static mp_obj_t vfs_posix_rename(mp_obj_t self_in, mp_obj_t old_path_in, mp_obj_ vfs_posix_require_writable(self_in); mp_obj_vfs_posix_t *self = MP_OBJ_TO_PTR(self_in); const char *old_path = vfs_posix_get_path_str(self, old_path_in); + size_t old_path_len = strlen(old_path) + 1; + char *old_path_copy = m_new(char, old_path_len); + memcpy(old_path_copy, old_path, old_path_len); const char *new_path = vfs_posix_get_path_str(self, new_path_in); MP_THREAD_GIL_EXIT(); - int ret = rename(old_path, new_path); + int ret = rename(old_path_copy, new_path); MP_THREAD_GIL_ENTER(); + m_del(char, old_path_copy, old_path_len); if (ret != 0) { mp_raise_OSError(errno); } diff --git a/tests/extmod/vfs_posix.py b/tests/extmod/vfs_posix.py index b3ca2753ba9..22e6e07d3b6 100644 --- a/tests/extmod/vfs_posix.py +++ b/tests/extmod/vfs_posix.py @@ -97,6 +97,15 @@ def write_files_without_closing(): os.rename(temp_dir + "/test", temp_dir + "/test2") print(os.listdir(temp_dir)) +# construct new VfsPosix with absolute path +fs = vfs.VfsPosix(os.getcwd() + os.sep + temp_dir) +f = fs.open("/test", "w") +f.close() +print(sorted(os.listdir(temp_dir))) +fs.rename("/test", "/_test") +print(sorted(os.listdir(temp_dir))) +fs.remove("/_test") + # construct new VfsPosix with path argument fs = vfs.VfsPosix(temp_dir) # when VfsPosix is used the intended way via vfs.mount(), it can only be called diff --git a/tests/extmod/vfs_posix.py.exp b/tests/extmod/vfs_posix.py.exp index bd1ec7bad67..28dee4c101a 100644 --- a/tests/extmod/vfs_posix.py.exp +++ b/tests/extmod/vfs_posix.py.exp @@ -6,6 +6,8 @@ True hello next_file_no <= base_file_no True ['test2'] +['test', 'test2'] +['_test', 'test2'] ['test2'] From 0f8f60e8cce80bea8c8983d36ef29cd38ca9c803 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 17 Jul 2026 13:59:53 +0200 Subject: [PATCH 575/635] mpy-cross/mpconfigport: Use setjmp GC helper on macOS for Intel. This commit forces the setjmp/longjmp GC helper when building for macOS targeting Intel-based processors. Modern versions of macOS development tools do not like the GC helper's usage of the EBP/RBP register and will raise an error since that register is now reserved for internal use. Signed-off-by: Alessandro Gatti --- mpy-cross/mpconfigport.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/mpy-cross/mpconfigport.h b/mpy-cross/mpconfigport.h index ee7f98e69d5..1bc06bbb046 100644 --- a/mpy-cross/mpconfigport.h +++ b/mpy-cross/mpconfigport.h @@ -82,9 +82,13 @@ #define MICROPY_PY_TSTRINGS (1) #define MICROPY_PY_BUILTINS_STR_UNICODE (1) -#if !(defined(MICROPY_GCREGS_SETJMP) || defined(__x86_64__) || defined(__i386__) || defined(__thumb2__) || defined(__thumb__) || defined(__arm__)) -// Fall back to setjmp() implementation for discovery of GC pointers in registers. -#define MICROPY_GCREGS_SETJMP (1) +// Fall back to setjmp() implementation for discovery of GC pointers in registers +// if running on intel-based macOS, or on architectures for which there is no +// specialised GC pointer discovery mechanism. +#if (defined(__APPLE__) && defined(__MACH__) && (defined(__i386__) || defined(__x86_64__))) || \ + (!(defined(MICROPY_GCREGS_SETJMP) || defined(__x86_64__) || defined(__i386__) || \ + defined(__thumb2__) || defined(__thumb__) || defined(__arm__))) +#define MICROPY_GCREGS_SETJMP (1) #endif #define MICROPY_MODULE___FILE__ (0) From b006887db6e4b18bce967ea87c7e63398f60b296 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 17 Jul 2026 14:03:31 +0200 Subject: [PATCH 576/635] unix/mpconfigport: Use setjmp GC helper on macOS for Intel. This commit forces the setjmp/longjmp GC helper when building for macOS targeting Intel-based processors. Modern versions of macOS development tools do not like the GC helper's usage of the EBP/RBP register and will raise an error since that register is now reserved for internal use. Signed-off-by: Alessandro Gatti --- ports/unix/mpconfigport.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/ports/unix/mpconfigport.h b/ports/unix/mpconfigport.h index 0f4ee97657f..9b66d8684e0 100644 --- a/ports/unix/mpconfigport.h +++ b/ports/unix/mpconfigport.h @@ -106,9 +106,12 @@ typedef long mp_off_t; // Always enable GC. #define MICROPY_ENABLE_GC (1) -#if !(defined(MICROPY_GCREGS_SETJMP) || defined(__x86_64__) || defined(__i386__) || defined(__thumb2__) || defined(__thumb__) || defined(__arm__) || (defined(__riscv) && __riscv_xlen <= 64) || (defined(__loongarch__) && defined(__loongarch64))) -// Fall back to setjmp() implementation for discovery of GC pointers in registers. -#define MICROPY_GCREGS_SETJMP (1) +// Fall back to setjmp() implementation for discovery of GC pointers in registers +// if running on intel-based macOS, or on architectures for which there is no +// specialised GC pointer discovery mechanism. +#if (defined(__APPLE__) && defined(__MACH__) && (defined(__i386__) || defined(__x86_64__))) || \ + (!(defined(MICROPY_GCREGS_SETJMP) || defined(__x86_64__) || defined(__i386__) || defined(__thumb2__) || defined(__thumb__) || defined(__arm__) || (defined(__riscv) && __riscv_xlen <= 64) || (defined(__loongarch__) && defined(__loongarch64)))) +#define MICROPY_GCREGS_SETJMP (1) #endif // Enable the VFS, and enable the posix "filesystem". From cfae255291337e391945c1e37882df104e16d10b Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 30 Jul 2026 15:42:40 +1000 Subject: [PATCH 577/635] esp32: Fix virtual timers on ESP32-C3. For some reason SOC_TIMER_GROUP_TOTAL_TIMERS is defined as unsigned (1U) on ESP32-C3 but is a signed integer on all other platforms. Therefore id -1 for virtual timer would be implicitly converted to unsigned and raise a ValueError as out of range. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/esp32/machine_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/esp32/machine_timer.c b/ports/esp32/machine_timer.c index 26d9cd03855..df9a11c4e0a 100644 --- a/ports/esp32/machine_timer.c +++ b/ports/esp32/machine_timer.c @@ -89,7 +89,7 @@ static bool machine_timer_handler(machine_timer_obj_t *self) { machine_timer_obj_t *machine_timer_create(mp_int_t id) { // Check hardware timer ID is valid - if (id >= SOC_TIMER_GROUP_TOTAL_TIMERS) { + if (id >= (mp_int_t)SOC_TIMER_GROUP_TOTAL_TIMERS) { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Timer(%d) doesn't exist, there are only %d hardware timers"), id, SOC_TIMER_GROUP_TOTAL_TIMERS); } From 7d7ac1c066bd46631d446779c96201382e4e2463 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 30 Jul 2026 15:54:19 +1000 Subject: [PATCH 578/635] tests/extmod/machine_timer: Add support for ESP32-C2. This SoC only has one hardware timer available. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- tests/extmod/machine_timer.py | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/tests/extmod/machine_timer.py b/tests/extmod/machine_timer.py index a8f33bfa030..cb5f3fa67e2 100644 --- a/tests/extmod/machine_timer.py +++ b/tests/extmod/machine_timer.py @@ -17,7 +17,14 @@ import unittest # Hardware timers are only supported on the esp32 port -SUPPORTS_HARDWARE_TIMERS = sys.platform == "esp32" +NUM_HARDWARE_TIMERS = 0 +if sys.platform == "esp32": + if "ESP32-C2" in sys.implementation._machine: + # Only one hardware timer on ESP32-C2 + NUM_HARDWARE_TIMERS = 1 + else: + # at least two on other ESP32 SoCs + NUM_HARDWARE_TIMERS = 2 # Hard IRQs are not supported on the esp32 port SUPPORTS_HARD_IRQ = sys.platform != "esp32" @@ -28,9 +35,12 @@ def test_virtual_create(self): self._test_create(-1) self._test_create_multiple(-1, -1) - @unittest.skipUnless(SUPPORTS_HARDWARE_TIMERS, "no hardware timers") + @unittest.skipUnless(NUM_HARDWARE_TIMERS > 0, "no hardware timers") def test_hardware_create(self): self._test_create(0) + + @unittest.skipUnless(NUM_HARDWARE_TIMERS >= 2, "less than 2 hardware timers") + def test_hardware_create_multiple(self): self._test_create_multiple(0, 1) def test_virtual_softirq(self): @@ -42,12 +52,12 @@ def test_virtual_hardirq(self): self._test_all_freq_period(-1, Timer.ONE_SHOT, True) self._test_all_freq_period(-1, Timer.PERIODIC, True) - @unittest.skipUnless(SUPPORTS_HARDWARE_TIMERS, "no hardware timers") + @unittest.skipUnless(NUM_HARDWARE_TIMERS > 0, "no hardware timers") def test_hardware_softirq(self): self._test_all_freq_period(0, Timer.ONE_SHOT, False) self._test_all_freq_period(0, Timer.PERIODIC, False) - @unittest.skipUnless(SUPPORTS_HARDWARE_TIMERS, "no hardware timers") + @unittest.skipUnless(NUM_HARDWARE_TIMERS > 0, "no hardware timers") @unittest.skipUnless(SUPPORTS_HARD_IRQ, "no hard-irq support") def test_hardware_hardirq(self): self._test_all_freq_period(0, Timer.ONE_SHOT, True) From 3e892434fbb3a4b36628adeac22c3e5eec09375e Mon Sep 17 00:00:00 2001 From: Owen Date: Fri, 31 Jul 2026 12:52:05 +0200 Subject: [PATCH 579/635] esp32/boards/esp32-p4: Support pre-v3 chip revisions as variants. Creates 3 new variants for the esp32-p4 generic board, supporting compiling and loading compatible code for revision 0.x and 1.x chips. By default only build for revision 3.x and later. Signed-off-by: Owen --- .../esp32/boards/ESP32_GENERIC_P4/board.json | 5 +++- ports/esp32/boards/ESP32_GENERIC_P4/board.md | 23 +++++++++++++++---- .../mpconfigvariant_PRE_REV3.cmake | 7 ++++++ .../mpconfigvariant_PRE_REV3_C5_WIFI.cmake | 11 +++++++++ .../mpconfigvariant_PRE_REV3_C6_WIFI.cmake | 11 +++++++++ ports/esp32/boards/sdkconfig.p4 | 6 +++-- ports/esp32/boards/sdkconfig.p4_pre_rev3 | 9 ++++++++ 7 files changed, 64 insertions(+), 8 deletions(-) create mode 100644 ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3.cmake create mode 100644 ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3_C5_WIFI.cmake create mode 100644 ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3_C6_WIFI.cmake create mode 100644 ports/esp32/boards/sdkconfig.p4_pre_rev3 diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/board.json b/ports/esp32/boards/ESP32_GENERIC_P4/board.json index 480b4fbfd1d..b1f9dd41093 100644 --- a/ports/esp32/boards/ESP32_GENERIC_P4/board.json +++ b/ports/esp32/boards/ESP32_GENERIC_P4/board.json @@ -19,7 +19,10 @@ "url": "https://www.espressif.com/en/products/modules", "variants": { "C5_WIFI": "Support for external C5 WiFi/BLE", - "C6_WIFI": "Support for external C6 WiFi/BLE" + "C6_WIFI": "Support for external C6 WiFi/BLE", + "PRE_REV3": "Boards with early 0.x and 1.x chip revisions", + "PRE_REV3_C5_WIFI": "0.x and 1.x chip revisions with external C5 WiFi/BLE", + "PRE_REV3_C6_WIFI": "0.x and 1.x chip revisions with external C6 WiFi/BLE" }, "vendor": "Espressif" } diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/board.md b/ports/esp32/boards/ESP32_GENERIC_P4/board.md index 29f72832aa6..21470488186 100644 --- a/ports/esp32/boards/ESP32_GENERIC_P4/board.md +++ b/ports/esp32/boards/ESP32_GENERIC_P4/board.md @@ -1,11 +1,24 @@ The following firmware is applicable to most development boards based on ESP32-P4, and the development boards must be equipped with at least 16 MiB external SPI Flash. -This board has multiple variants available: +The P4 chip had major changes at chip revision 3.0, and these require that builds +for earlier (`PRE_REV3`) chips are done as variants. -* If your board has a standalone ESP32-P4 processor (or the board has a coprocessor but - you do not want to use it) then choose the generic variant (first heading below). +Espressif denote the revision 3+ chips by appending an **`X`** to the part numbers: + +|part|revisions 0.x and 1.x|revisions 3.x and later| +|----|---------------------|-----------------------| +|ESP32-P4 16Mb PSRAM|ESP32-P4NRW16|ESP32-P4NRW16**X**| +|ESP32-P4 32Mb PSRAM|ESP32-P4NRW32|ESP32-P4NRW32**X**| +|Multimedia DEVBOARD|ESP32-P4-Function-EV-Board|ESP32-P4**X**-Function-EV-Board| + +etc.. + +This board also has variants available to select the Wireless CoProcessor (if any): + +* If your board has a standalone revision 3.x or later ESP32-P4 processor (or the board has a coprocessor but you do not want to use it) then choose the generic variant (first heading below). +* If you have an early (revisions 0.x and 1.x) chip revision choose the "PRE REV3" variants. * If your board has an external ESP32-C5 coprocessor for WiFi and BLE then choose the - "C5 WiFi/BLE" variant. + "C5 WiFi/BLE" variants. * If your board has an external ESP32-C6 coprocessor for WiFi and BLE then choose the - "C6 WiFi/BLE" variant. + "C6 WiFi/BLE" variants. diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3.cmake b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3.cmake new file mode 100644 index 00000000000..f59c9005fc8 --- /dev/null +++ b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3.cmake @@ -0,0 +1,7 @@ +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.p4_pre_rev3 +) + +list(APPEND MICROPY_DEF_BOARD + MICROPY_HW_BOARD_NAME="Generic ESP32P4 with pre revision 3 chip" +) diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3_C5_WIFI.cmake b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3_C5_WIFI.cmake new file mode 100644 index 00000000000..583deea5c43 --- /dev/null +++ b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3_C5_WIFI.cmake @@ -0,0 +1,11 @@ +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.p4_pre_rev3 + boards/sdkconfig.p4_wifi_common + boards/sdkconfig.p4_wifi_c5 +) + +list(APPEND MICROPY_DEF_BOARD + MICROPY_HW_BOARD_NAME="Generic ESP32P4 module with pre revision 3 chip and ESP32C5 hosted WIFI" + MICROPY_PY_NETWORK_WLAN=1 + MICROPY_PY_BLUETOOTH=1 +) diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3_C6_WIFI.cmake b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3_C6_WIFI.cmake new file mode 100644 index 00000000000..9d55e9ff3e5 --- /dev/null +++ b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigvariant_PRE_REV3_C6_WIFI.cmake @@ -0,0 +1,11 @@ +list(APPEND SDKCONFIG_DEFAULTS + boards/sdkconfig.p4_pre_rev3 + boards/sdkconfig.p4_wifi_common + boards/sdkconfig.p4_wifi_c6 +) + +list(APPEND MICROPY_DEF_BOARD + MICROPY_HW_BOARD_NAME="Generic ESP32P4 module with pre revision 3 chip and ESP32C6 hosted WIFI" + MICROPY_PY_NETWORK_WLAN=1 + MICROPY_PY_BLUETOOTH=1 +) diff --git a/ports/esp32/boards/sdkconfig.p4 b/ports/esp32/boards/sdkconfig.p4 index 042eec40cf7..936deaf8f99 100644 --- a/ports/esp32/boards/sdkconfig.p4 +++ b/ports/esp32/boards/sdkconfig.p4 @@ -1,5 +1,7 @@ -# Select the minimum chip revision to cover all possible boards. -CONFIG_ESP32P4_REV_MIN_0=y +# By default only build for and support ESP32-P4 revisions 3.x and above +# - Use the 'PRE_REV3' variants to build for earlier revisions +# - https://docs.espressif.com/projects/esp-idf/en/stable/esp32p4/api-reference/kconfig-reference.html +CONFIG_ESP32P4_REV_MIN_300=y # Flash CONFIG_FLASHMODE_QIO=y diff --git a/ports/esp32/boards/sdkconfig.p4_pre_rev3 b/ports/esp32/boards/sdkconfig.p4_pre_rev3 new file mode 100644 index 00000000000..f17593a7dc3 --- /dev/null +++ b/ports/esp32/boards/sdkconfig.p4_pre_rev3 @@ -0,0 +1,9 @@ +# ESP32-P4 sdkconfig variant for revision 0.x and 1.x chips +# - https://docs.espressif.com/projects/esp-idf/en/stable/esp32p4/api-reference/kconfig-reference.html +# +# Override and set the minimum chip revision to cover all possible boards. +CONFIG_ESP32P4_REV_MIN_300=n +CONFIG_ESP32P4_REV_MIN_0=y +# +# Enable support for ESP32-P4 revisions 0.x and 1.x +CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y From 6f97ed85297e45fadedbce021a6a6fb7aa122c9a Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Tue, 28 Jul 2026 08:03:30 +0200 Subject: [PATCH 580/635] esp32/machine_sdcard: Make default SDMMC pins board-configurable. Add MICROPY_HW_SDMMC_CLK, _CMD and _D0..D7 board defaults, grouped by bus width: a board defines the pins for the width it wires, i.e. CLK/CMD/D0 (1-bit), plus D1-D3 (4-bit) and D4-D7 (8-bit eMMC). They apply on chips whose SD/MMC host uses the GPIO matrix, guarded by SOC_SDMMC_USE_GPIO_MATRIX, so a board with a fixed SD connector can use the native SD/MMC host without pin arguments, like the existing MICROPY_HW_SDCARD_SPI_* mechanism, completing the board-configurable set next to the slot and width defaults. An explicit clk/cmd/data argument still overrides. Signed-off-by: Pavel Revak --- ports/esp32/machine_sdcard.c | 22 +++++++++++++++++++++- ports/esp32/machine_sdcard.h | 25 ++++++++++++++++++++++++- 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/ports/esp32/machine_sdcard.c b/ports/esp32/machine_sdcard.c index 3a7174ae3aa..ce0419bd514 100644 --- a/ports/esp32/machine_sdcard.c +++ b/ports/esp32/machine_sdcard.c @@ -407,7 +407,27 @@ static mp_obj_t machine_sdcard_make_new(const mp_obj_type_t *type, size_t n_args } #if SOC_SDMMC_USE_GPIO_MATRIX - // Optionally configure all the SDMMC pins, if chip supports this + // Apply board-level pin defaults (mpconfigboard.h), then let an explicit + // clk/cmd/data argument override below. Grouped by bus width and nested + // so each wider mode builds on the narrower one: CLK/CMD/D0 (1-bit), then + // D1-D3 (4-bit), then D4-D7 (8-bit eMMC). An unset group stays at the + // driver default (GPIO_NUM_NC). + if (MICROPY_HW_SDMMC_CLK != GPIO_NUM_NC) { + slot_config.clk = MICROPY_HW_SDMMC_CLK; + slot_config.cmd = MICROPY_HW_SDMMC_CMD; + slot_config.d0 = MICROPY_HW_SDMMC_D0; + if (MICROPY_HW_SDMMC_D1 != GPIO_NUM_NC) { + slot_config.d1 = MICROPY_HW_SDMMC_D1; + slot_config.d2 = MICROPY_HW_SDMMC_D2; + slot_config.d3 = MICROPY_HW_SDMMC_D3; + if (MICROPY_HW_SDMMC_D4 != GPIO_NUM_NC) { + slot_config.d4 = MICROPY_HW_SDMMC_D4; + slot_config.d5 = MICROPY_HW_SDMMC_D5; + slot_config.d6 = MICROPY_HW_SDMMC_D6; + slot_config.d7 = MICROPY_HW_SDMMC_D7; + } + } + } SET_CONFIG_PIN(slot_config, clk, ARG_sck); // reuse SPI SCK for CLK SET_CONFIG_PIN(slot_config, cmd, ARG_cmd); if (arg_vals[ARG_data].u_obj != mp_const_none) { diff --git a/ports/esp32/machine_sdcard.h b/ports/esp32/machine_sdcard.h index e417cd04f33..f54263b7750 100644 --- a/ports/esp32/machine_sdcard.h +++ b/ports/esp32/machine_sdcard.h @@ -29,7 +29,7 @@ // Default pins for the primary SPI-mode SD card bus (slot 2). SPI mode is // available on every ESP32 variant, so a board may override these in its // mpconfigboard.h to make machine.SDCard(slot=2) work without explicit pins. -// SDMMC-mode pins (slots 0/1) are not affected. +// Native SD/MMC pins (slots 0/1) have their own defaults, see below. #ifndef MICROPY_HW_SDCARD_SPI_SCK #if CONFIG_IDF_TARGET_ESP32 #define MICROPY_HW_SDCARD_SPI_SCK (GPIO_NUM_18) @@ -50,4 +50,27 @@ #endif #endif +// Default pins for a native SD/MMC slot, for ESP32 variants whose SD/MMC host +// uses the GPIO matrix (SOC_SDMMC_USE_GPIO_MATRIX) and so has assignable pins. +// A board may override these in mpconfigboard.h so machine.SDCard(slot=1) needs +// no pin arguments; an explicit clk/cmd/data still wins. Grouped by bus width +// like the SPI defaults: define CLK/CMD/D0 (1-bit), optionally D1-D3 (4-bit) +// and D4-D7 (8-bit eMMC), each group together (unset groups stay GPIO_NUM_NC). +#ifndef MICROPY_HW_SDMMC_CLK +#define MICROPY_HW_SDMMC_CLK (GPIO_NUM_NC) +#define MICROPY_HW_SDMMC_CMD (GPIO_NUM_NC) +#define MICROPY_HW_SDMMC_D0 (GPIO_NUM_NC) +#endif +#ifndef MICROPY_HW_SDMMC_D1 +#define MICROPY_HW_SDMMC_D1 (GPIO_NUM_NC) +#define MICROPY_HW_SDMMC_D2 (GPIO_NUM_NC) +#define MICROPY_HW_SDMMC_D3 (GPIO_NUM_NC) +#endif +#ifndef MICROPY_HW_SDMMC_D4 +#define MICROPY_HW_SDMMC_D4 (GPIO_NUM_NC) +#define MICROPY_HW_SDMMC_D5 (GPIO_NUM_NC) +#define MICROPY_HW_SDMMC_D6 (GPIO_NUM_NC) +#define MICROPY_HW_SDMMC_D7 (GPIO_NUM_NC) +#endif + #endif // MICROPY_INCLUDED_ESP32_MACHINE_SDCARD_H From ba65ef029960cc7bdd169ace3008124a8b86c175 Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Tue, 28 Jul 2026 08:04:01 +0200 Subject: [PATCH 581/635] esp32/boards/SEEED_XIAO_ESP32S3: Use native SD/MMC for the microSD. The Sense expansion's microSD is SPI-wired, so only D0 is broken out (1-bit). Reuse those pins for the native SD/MMC host as CLK=SCK(7), CMD=MOSI(9) and D0=MISO(8). Since the ESP32-S3 default slot is 1 (SD/MMC) and default width 1, a bare machine.SDCard() now uses the native host -- noticeably faster than SPI mode (SDCard(slot=2)), especially on reads. Signed-off-by: Pavel Revak --- ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h b/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h index 5376b6d840a..7cbd86055dc 100644 --- a/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h +++ b/ports/esp32/boards/SEEED_XIAO_ESP32S3/mpconfigboard.h @@ -16,3 +16,10 @@ #define MICROPY_HW_SDCARD_SPI_MISO (8) #define MICROPY_HW_SDCARD_SPI_SCK (7) #define MICROPY_HW_SDCARD_SPI_CS (21) + +// The same microSD via native SD/MMC (1-bit): machine.SDCard(slot=1, width=1). +// Noticeably faster than SPI (esp. reads). The slot is SPI-wired, so only D0 is +// available (1-bit): CLK=SPI SCK, CMD=SPI MOSI, D0=SPI MISO. +#define MICROPY_HW_SDMMC_CLK (7) +#define MICROPY_HW_SDMMC_CMD (9) +#define MICROPY_HW_SDMMC_D0 (8) From 2aa39667b43ceed637cec21086eee5469749bdbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dani=C3=ABl=20van=20de=20Giessen?= Date: Wed, 15 Jul 2026 10:57:05 +0200 Subject: [PATCH 582/635] esp32: Note CONFIG_SPI_FLASH_ROM_IMPL may cause cache error / MMU fault. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Daniël van de Giessen --- ports/esp32/boards/sdkconfig.free_ram | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ports/esp32/boards/sdkconfig.free_ram b/ports/esp32/boards/sdkconfig.free_ram index 36c6455e3e6..ed79b6c2711 100644 --- a/ports/esp32/boards/sdkconfig.free_ram +++ b/ports/esp32/boards/sdkconfig.free_ram @@ -20,6 +20,9 @@ CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH=y # Use the SPI flash functions in ROM (when available). This may limit flash chip # support and cause issues with some flash chips. Each SoC family has different # set of chip support baked into ROM. +# IMPORTANT: On some chips such as the ESP32-S3-WROOM-1-N8R8 it may cause panics +# (Cache error / MMU entry fault error) when writing to high PSRAM addresses, see +# https://github.com/micropython/micropython/pull/19469 for more details. CONFIG_SPI_FLASH_ROM_IMPL=y # Run the Bluetooth controller from flash not IRAM From 1345700f866054c1f8d9bafa630535273eb0b09b Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 30 Jul 2026 16:02:54 +1000 Subject: [PATCH 583/635] esp32: Only disable hardware timers that were previously enabled. Avoids logging an ESP-IDF driver error by calling gptimer_disable() on an never-enabled timer. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- ports/esp32/machine_timer.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/ports/esp32/machine_timer.c b/ports/esp32/machine_timer.c index df9a11c4e0a..a41f006f42f 100644 --- a/ports/esp32/machine_timer.c +++ b/ports/esp32/machine_timer.c @@ -219,9 +219,11 @@ mp_obj_t machine_timer_deinit(mp_obj_t self_in) { machine_timer_obj_t *self = self_in; machine_timer_stop(self); if (self->id >= 0) { - esp_err_t result = gptimer_disable(self->handle.hardware); - if (result != ESP_ERR_INVALID_STATE) { - check_esp_err(result); + if (self->handler != NULL) { + esp_err_t result = gptimer_disable(self->handle.hardware); + if (result != ESP_ERR_INVALID_STATE) { + check_esp_err(result); + } } } else { // Virtual timers may be immediately garbage collected From a1aae8df1512d982182d699b3691c7b4e311fa7a Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Fri, 7 Aug 2026 10:52:58 +0200 Subject: [PATCH 584/635] esp32/boards: Fix ineffective ESP-Hosted WiFi buffer config. On an ESP-Hosted board (e.g. ESP32-P4 with an ESP32-C6/C5 co-processor) the WiFi runs on the co-processor and its RX/TX buffer counts are taken from the host-side wifi_init_config_t. The ESP32-P4 config set these via CONFIG_ESP_WIFI_*, but on ESP-Hosted those symbols are derived and not settable -- esp_wifi_remote exposes the settable ones as CONFIG_WIFI_RMT_*. The intended tuning therefore never applied and the co-processor ran with the defaults (dynamic TX/RX 32, static RX 10). The undersized dynamic TX buffer count is the most harmful: with 32 (~43 KB) a single large TCP response overruns the co-processor TX queue at the tail and drops packets, which the host lwIP only recovers from via RTO (~1.4 s), producing a periodic ~1 s stall over WiFi (e.g. when streaming JPEG frames; the same workload is stable over Ethernet). Rename the buffer settings to the CONFIG_WIFI_RMT_* symbols so they take effect. Measured on an ESP32-P4 + C6 (raw TCP, RSSI ~-37 dBm) the sustained throughput of a single connection rises from ~5 to ~26 Mbit/s outbound and from ~13 to ~23 Mbit/s inbound, and the stalls are gone. Signed-off-by: Pavel Revak --- ports/esp32/boards/sdkconfig.p4_wifi_common | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/ports/esp32/boards/sdkconfig.p4_wifi_common b/ports/esp32/boards/sdkconfig.p4_wifi_common index a55e941ba68..a5a5ac835db 100644 --- a/ports/esp32/boards/sdkconfig.p4_wifi_common +++ b/ports/esp32/boards/sdkconfig.p4_wifi_common @@ -3,13 +3,11 @@ # Wifi CONFIG_ESP_HOSTED_ENABLED=y -CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=16 -CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=64 -CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=64 -CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y -CONFIG_ESP_WIFI_TX_BA_WIN=32 -CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y -CONFIG_ESP_WIFI_RX_BA_WIN=32 +# ESP-Hosted: the WiFi runs on the co-processor; the settable buffer symbols are +# WIFI_RMT_* -- the plain ESP_WIFI_* ones are derived and have no effect here. +CONFIG_WIFI_RMT_STATIC_RX_BUFFER_NUM=16 +CONFIG_WIFI_RMT_DYNAMIC_RX_BUFFER_NUM=64 +CONFIG_WIFI_RMT_DYNAMIC_TX_BUFFER_NUM=64 CONFIG_LWIP_TCP_SND_BUF_DEFAULT=65534 CONFIG_LWIP_TCP_WND_DEFAULT=65534 From 83f92d5000e233442e80eb09ae5080a624e22f17 Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 10 Aug 2026 23:54:42 +0200 Subject: [PATCH 585/635] extmod/network_wiznet5k: Avoid hardcoded socket count. Signed-off-by: Jos Verlinde --- extmod/network_wiznet5k.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/extmod/network_wiznet5k.c b/extmod/network_wiznet5k.c index f595eccc473..e32eb31f1bb 100644 --- a/extmod/network_wiznet5k.c +++ b/extmod/network_wiznet5k.c @@ -802,7 +802,7 @@ static mp_obj_t wiznet5k_regs(mp_obj_t self_in) { #endif printf(" %02x", WIZCHIP_READ(reg)); } - for (int sn = 0; sn < 4; ++sn) { + for (int sn = 0; sn < _WIZCHIP_SOCK_NUM_; ++sn) { printf("\nWiz SREG[%d]:", sn); for (int i = 0; i < 0x30; ++i) { if (i % 16 == 0) { From 8356e6732f53ad8bc183b23f25f4eca531e807a2 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 31 Jul 2026 16:08:44 +1000 Subject: [PATCH 586/635] extmod/mbedtls: Enable PEM parsing in common mbedTLS config. MicroPython currently supports loading certificates in binary .der format. But to load a chain of them requires have each one as a separate file/binary blob and loading them one at a time. That's not very user friendly and possibly prone to error. And as usual with security/crypto related things, it's best to make things as simple as possible to reduce the chance of a mistake. So, enable PEM parsing for mbedTLS. That allows many certificates to be loaded at once from the same file, making it much easier to manage and update certificates on a device. ESP32 already enables this by default, so this updates bare metal and unix ports. Addresses issue #19423. Signed-off-by: Damien George --- extmod/mbedtls/mbedtls_config_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/extmod/mbedtls/mbedtls_config_common.h b/extmod/mbedtls/mbedtls_config_common.h index 36d80ca2039..3d93f8b219e 100644 --- a/extmod/mbedtls/mbedtls_config_common.h +++ b/extmod/mbedtls/mbedtls_config_common.h @@ -68,6 +68,7 @@ #define MBEDTLS_AES_C #define MBEDTLS_ASN1_PARSE_C #define MBEDTLS_ASN1_WRITE_C +#define MBEDTLS_BASE64_C #define MBEDTLS_BIGNUM_C #define MBEDTLS_CIPHER_C #define MBEDTLS_CTR_DRBG_C @@ -80,6 +81,7 @@ #define MBEDTLS_MD_C #define MBEDTLS_MD5_C #define MBEDTLS_OID_C +#define MBEDTLS_PEM_PARSE_C #define MBEDTLS_PKCS5_C #define MBEDTLS_PK_C #define MBEDTLS_PK_HAVE_ECC_KEYS From e9236f2fe818429007beff01145cbd73c1cb59d8 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 31 Jul 2026 16:09:47 +1000 Subject: [PATCH 587/635] tests/net_inet: Add test for tls loading a PEM certificate. Signed-off-by: Damien George --- tests/net_inet/isrgrootx1.pem | 31 ++++++++++++++++++++++++++++++ tests/net_inet/tls_cert_pem.py | 27 ++++++++++++++++++++++++++ tests/net_inet/tls_cert_pem.py.exp | 1 + 3 files changed, 59 insertions(+) create mode 100644 tests/net_inet/isrgrootx1.pem create mode 100644 tests/net_inet/tls_cert_pem.py create mode 100644 tests/net_inet/tls_cert_pem.py.exp diff --git a/tests/net_inet/isrgrootx1.pem b/tests/net_inet/isrgrootx1.pem new file mode 100644 index 00000000000..b85c8037f6b --- /dev/null +++ b/tests/net_inet/isrgrootx1.pem @@ -0,0 +1,31 @@ +-----BEGIN CERTIFICATE----- +MIIFazCCA1OgAwIBAgIRAIIQz7DSQONZRGPgu2OCiwAwDQYJKoZIhvcNAQELBQAw +TzELMAkGA1UEBhMCVVMxKTAnBgNVBAoTIEludGVybmV0IFNlY3VyaXR5IFJlc2Vh +cmNoIEdyb3VwMRUwEwYDVQQDEwxJU1JHIFJvb3QgWDEwHhcNMTUwNjA0MTEwNDM4 +WhcNMzUwNjA0MTEwNDM4WjBPMQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJu +ZXQgU2VjdXJpdHkgUmVzZWFyY2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBY +MTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAK3oJHP0FDfzm54rVygc +h77ct984kIxuPOZXoHj3dcKi/vVqbvYATyjb3miGbESTtrFj/RQSa78f0uoxmyF+ +0TM8ukj13Xnfs7j/EvEhmkvBioZxaUpmZmyPfjxwv60pIgbz5MDmgK7iS4+3mX6U +A5/TR5d8mUgjU+g4rk8Kb4Mu0UlXjIB0ttov0DiNewNwIRt18jA8+o+u3dpjq+sW +T8KOEUt+zwvo/7V3LvSye0rgTBIlDHCNAymg4VMk7BPZ7hm/ELNKjD+Jo2FR3qyH +B5T0Y3HsLuJvW5iB4YlcNHlsdu87kGJ55tukmi8mxdAQ4Q7e2RCOFvu396j3x+UC +B5iPNgiV5+I3lg02dZ77DnKxHZu8A/lJBdiB3QW0KtZB6awBdpUKD9jf1b0SHzUv +KBds0pjBqAlkd25HN7rOrFleaJ1/ctaJxQZBKT5ZPt0m9STJEadao0xAH0ahmbWn +OlFuhjuefXKnEgV4We0+UXgVCwOPjdAvBbI+e0ocS3MFEvzG6uBQE3xDk3SzynTn +jh8BCNAw1FtxNrQHusEwMFxIt4I7mKZ9YIqioymCzLq9gwQbooMDQaHWBfEbwrbw +qHyGO0aoSCqI3Haadr8faqU9GY/rOPNk3sgrDQoo//fb4hVC1CLQJ13hef4Y53CI +rU7m2Ys6xt0nUW7/vGT1M0NPAgMBAAGjQjBAMA4GA1UdDwEB/wQEAwIBBjAPBgNV +HRMBAf8EBTADAQH/MB0GA1UdDgQWBBR5tFnme7bl5AFzgAiIyBpY9umbbjANBgkq +hkiG9w0BAQsFAAOCAgEAVR9YqbyyqFDQDLHYGmkgJykIrGF1XIpu+ILlaS/V9lZL +ubhzEFnTIZd+50xx+7LSYK05qAvqFyFWhfFQDlnrzuBZ6brJFe+GnY+EgPbk6ZGQ +3BebYhtF8GaV0nxvwuo77x/Py9auJ/GpsMiu/X1+mvoiBOv/2X/qkSsisRcOj/KK +NFtY2PwByVS5uCbMiogziUwthDyC3+6WVwW6LLv3xLfHTjuCvjHIInNzktHCgKQ5 +ORAzI4JMPJ+GslWYHb4phowim57iaztXOoJwTdwJx4nLCgdNbOhdjsnvzqvHu7Ur +TkXWStAmzOVyyghqpZXjFaH3pO3JLF+l+/+sKAIuvtd7u+Nxe5AW0wdeRlN8NwdC +jNPElpzVmbUq4JUagEiuTDkHzsxHpFKVK7q4+63SM1N95R1NbdWhscdCb+ZAJzVc +oyi3B43njTOQ5yOf+1CceWxG1bQVs5ZufpsMljq4Ui0/1lvh+wjChP4kqKOJ2qxq +4RgqsahDYVvTH9w7jXbyLeiNdd8XM2w9U/t7y0Ff/9yi0GE44Za4rF2LN9d11TPA +mRGunUHBcnWEvgJBQl9nJEiU0Zsnvgc/ubhPgXRR4Xq37Z0j4r7g1SgEEzwxA57d +emyPxgcYxn/eR44/KJ4EBs+lVDR3veyJm+kXQ99b21/+jh5Xos1AnX5iItreGCc= +-----END CERTIFICATE----- diff --git a/tests/net_inet/tls_cert_pem.py b/tests/net_inet/tls_cert_pem.py new file mode 100644 index 00000000000..5f333c565a0 --- /dev/null +++ b/tests/net_inet/tls_cert_pem.py @@ -0,0 +1,27 @@ +# Test tls.load_verify_locations loading a .pem file. + +import socket +import tls + +if not hasattr(tls, "CERT_REQUIRED"): + print("SKIP") + raise SystemExit + +# For details about this cert, see comment in test_sslcontext_client.py +root_cert_path = "isrgrootx1.pem" + +with open(root_cert_path) as ca: + cadata = ca.read() + +context = tls.SSLContext(tls.PROTOCOL_TLS_CLIENT) +context.verify_mode = tls.CERT_REQUIRED +context.load_verify_locations(cadata) + +s = socket.socket(socket.AF_INET, socket.SOCK_STREAM) +addr = socket.getaddrinfo("micropython.org", 443)[0][-1] + +s.connect(addr) +ssl_sock = context.wrap_socket(s, server_hostname="micropython.org") +ssl_sock.write(b"GET / HTTP/1.0\r\n\r\n") +print(ssl_sock.read(17)) +ssl_sock.close() diff --git a/tests/net_inet/tls_cert_pem.py.exp b/tests/net_inet/tls_cert_pem.py.exp new file mode 100644 index 00000000000..fb69ecf1a66 --- /dev/null +++ b/tests/net_inet/tls_cert_pem.py.exp @@ -0,0 +1 @@ +b'HTTP/1.1 200 OK\r\n' From 817b66bae3c925e71bf155b32b3b56b9354988da Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 12 Aug 2026 16:05:55 +1000 Subject: [PATCH 588/635] docs/library/ssl: Mention that PEM certificates are now supported. Signed-off-by: Damien George --- docs/library/ssl.rst | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/library/ssl.rst b/docs/library/ssl.rst index 0daea7e018a..2c0365dd2c9 100644 --- a/docs/library/ssl.rst +++ b/docs/library/ssl.rst @@ -25,8 +25,9 @@ Functions Note that for mbedtls based ports, ``ssl.CERT_NONE`` and ``ssl.CERT_OPTIONAL`` will not validate any certificate, only ``ssl.CERT_REQUIRED`` will. - - *cadata* is a bytes object containing the CA certificate chain (in DER format) that will - validate the peer's certificate. Currently only a single DER-encoded certificate is supported. + - *cadata* is a str or bytes object containing the CA certificate chain that will validate the + peer's certificate. It can be one or more certificates in PEM format, or single DER-encoded + certificate. Depending on the underlying module implementation in a particular :term:`MicroPython port`, some or all keyword arguments above may be not supported. From 153800656f2a3a3d1251c07d563acfc42a18135b Mon Sep 17 00:00:00 2001 From: Jos Verlinde Date: Mon, 10 Aug 2026 23:13:46 +0200 Subject: [PATCH 589/635] docs: Add ROMFS documentation. Includes a new romfs reference page, and updates the mpremote and and vfs pages. Addresses issue #19124. Signed-off-by: Jos Verlinde --- docs/library/vfs.rst | 79 +++++++++++ docs/reference/index.rst | 1 + docs/reference/mpremote.rst | 118 ++++++++++++++--- docs/reference/romfs.rst | 253 ++++++++++++++++++++++++++++++++++++ 4 files changed, 435 insertions(+), 16 deletions(-) create mode 100644 docs/reference/romfs.rst diff --git a/docs/library/vfs.rst b/docs/library/vfs.rst index 54eefa6c3b4..97f96510bbb 100644 --- a/docs/library/vfs.rst +++ b/docs/library/vfs.rst @@ -50,6 +50,9 @@ represented by VFS classes. Will raise ``OSError(EINVAL)`` if *mount_point* is not found. +Filesystem Types +---------------- + .. class:: VfsFat(block_dev) Create a filesystem object that uses the FAT filesystem format. Storage of @@ -107,11 +110,87 @@ represented by VFS classes. as the root of the ``VfsPosix`` object. Otherwise the current directory of the host filesystem is used. +.. class:: VfsRom(buffer) + + This class is only available when the firmware is built with + ``MICROPY_VFS_ROM`` enabled. + + Create a filesystem object that uses the :ref:`ROMFS read-only filesystem + format `. *buffer* must be an object supporting the buffer protocol + (e.g. ``bytes``, ``bytearray``, or ``memoryview``) that contains a valid + ROMFS image. + The constructor validates that *buffer* begins with the ROMFS magic bytes + (``b"\xd2\xcd\x31"``). If the buffer is too small or not a valid ROMFS + then ``OSError(ENODEV)`` is raised. + + See :ref:`romfs` for more information on the ROMFS filesystem and how to + deploy images using :ref:`mpremote `. + + .. method:: VfsRom.open(path, mode) + + Open a file from the ROMFS. Only read modes (``''``, ``'r'``, + ``'rt'``, ``'rb'``) are supported. + For binary files opened in read mode, + the returned object also supports the buffer protocol so that a + ``memoryview`` of the file data can be obtained, which refers + directly into the ROMFS memory (zero-copy). + + .. method:: VfsRom.statvfs(path) + + The block size is reported as 1 and + the block count represents the total size of the ROMFS image in bytes. + + .. method:: VfsRom.chdir(path) + + Change directory within the ROMFS. Only the root (``'/'``) is + supported; changing to any subdirectory raises ``OSError(EOPNOTSUPP)``. + .. _littlefs v1 filesystem format: https://github.com/ARMmbed/littlefs/tree/v1 .. _littlefs v2 filesystem format: https://github.com/ARMmbed/littlefs .. _littlefs issue 295: https://github.com/ARMmbed/littlefs/issues/295 .. _littlefs issue 347: https://github.com/ARMmbed/littlefs/issues/347 +Miscellaneous Functions +----------------------- + +.. function:: rom_ioctl(op, ...) + + Low-level interface for accessing the read-only memory (ROM) partition(s) + of the device. This function is only available on ports that support ROMFS + (i.e. where ``MICROPY_VFS_ROM_IOCTL`` is enabled). + + The supported operations are: + + - ``vfs.rom_ioctl(1)`` -- Return the number of available ROM partitions. + - ``vfs.rom_ioctl(2, id)`` -- Return ROM partition *id* as an object that + supports the buffer protocol. Depending on the port, this is either a + block device or a ``memoryview``. A block device supports the standard + block protocol, including erase and write operations. If a ``memoryview`` + is returned, the port must provide erase and write operations through + ``vfs.rom_ioctl()`` operations 3, 4, and 5 below. + - ``vfs.rom_ioctl(3, id, length)`` -- Prepare the first *length* bytes of + ROM partition *id* for writing (for example, by erasing flash). Returns + the minimum write size in bytes (the alignment required for subsequent + writes). + - ``vfs.rom_ioctl(3, id, offset, length)`` -- Prepare *length* bytes of ROM + partition *id*, starting at byte *offset*, for writing. This form allows + a partition to be prepared incrementally. Returns + the minimum write size in bytes. + - ``vfs.rom_ioctl(4, id, offset, buf)`` -- Write *buf* (a bytes-like object) + to the ROM partition with index *id* at byte *offset*. + - ``vfs.rom_ioctl(5, id)`` -- Complete a write sequence to partition *id* + (performs any finalisation needed after writing, such as cache flushing). + - ``vfs.rom_ioctl(6, id)`` -- Return the minimum number of bytes of ROM + partition *id* that can be prepared at once. A positive return value + indicates that the four-argument form of operation 3 is supported; + *offset* and *length* must be aligned to this value. Otherwise, only the + three-argument form of operation 3 is supported. + + These operations are used internally by ``mpremote`` to deploy ROMFS images. + Most users do not need to call ``vfs.rom_ioctl()`` directly. + + See :ref:`romfs` for more information. + Block devices ------------- diff --git a/docs/reference/index.rst b/docs/reference/index.rst index 24fe5746eb0..18be1c80342 100644 --- a/docs/reference/index.rst +++ b/docs/reference/index.rst @@ -31,6 +31,7 @@ implementation and the best practices to use them. packages.rst asm_thumb2_index.rst filesystem.rst + romfs.rst unicode_support.rst pyboard.py.rst micropython2_migration.rst diff --git a/docs/reference/mpremote.rst b/docs/reference/mpremote.rst index 14f6b81996f..32986c2161d 100644 --- a/docs/reference/mpremote.rst +++ b/docs/reference/mpremote.rst @@ -382,28 +382,13 @@ The full list of supported commands are: This happens automatically when ``mpremote`` terminates, but it can be used in a sequence to unmount an earlier mount before subsequent command are run. -.. _mpremote_command_romfs: - - **romfs** -- manage ROMFS partitions on the device: .. code-block:: bash $ mpremote romfs - ```` may be: - - - ``romfs query`` to list all the available ROMFS partitions and their size - - ``romfs [-o ] build `` to create a ROMFS image from the given - source directory; the default output file is the source appended by ``.romfs`` - - ``romfs [-p ] deploy `` to deploy a ROMFS image to the device; - will also create a temporary ROMFS image if the source is a directory - - The ``build`` and ``deploy`` sub-commands both support the ``-m``/``--mpy`` option - to automatically compile ``.py`` files to ``.mpy`` when creating the ROMFS image. - This option is enabled by default, but only works if the ``mpy_cross`` Python - package has been installed (eg via ``pip install mpy_cross``). If the package is - not installed then a warning is printed and ``.py`` files remain as is. Compiling - of ``.py`` files can be disabled with the ``--no-mpy`` option. + See :ref:`mpremote ROMFS commands ` for details. .. _mpremote_command_rtc: @@ -454,6 +439,107 @@ The full list of supported commands are: This will make the device enter its bootloader. The bootloader is port- and board-specific (e.g. DFU on stm32, UF2 on rp2040/Pico). +.. _mpremote_command_romfs: + +ROMFS commands +-------------- + +The ``romfs`` command provides three sub-commands for managing ROMFS images on +a connected device. + +.. _mpremote_command_romfs_query: + +mpremote romfs query +~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: bash + + $ mpremote romfs query + +Lists all available ROMFS partitions on the device and their sizes. Also +shows the first 12 bytes of each partition in hex and reports whether a +valid ROMFS image is present. + +Example output:: + + ROMFS0 partition has size 131072 bytes (32 blocks of 4096 bytes each) + Raw contents: d2:cd:31:XX:XX:XX:XX:XX:XX:XX:XX:XX ... + ROMFS image size: 1234 + +.. _mpremote_command_romfs_build: + +mpremote romfs build +~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: bash + + $ mpremote romfs [-o ] build + +Build a ROMFS image from the directory *source* on the host PC. The image +is written to *output* (default: ``.romfs``). + +Options: + +- ``-o ``, ``--output ``: Specify the output file path. +- ``-m``, ``--mpy`` (default): Automatically compile ``.py`` files to + ``.mpy`` using ``mpy_cross`` before adding them to the image. This requires + the ``mpy_cross`` Python package (``pip install mpy_cross``); without it, + ``mpremote`` prints a warning and leaves the ``.py`` files unchanged. +- ``--no-mpy``: Disable automatic compilation of ``.py`` files. + +Example:: + + $ mpremote romfs build myapp/ + Building romfs filesystem, source directory: myapp/ + / + |-- main.py -> .mpy + \-- lib/ + \-- helper.py -> .mpy + Writing 2048 bytes to output file myapp.romfs + +.. _mpremote_command_romfs_deploy: + +mpremote romfs deploy +~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: bash + + $ mpremote romfs [-p ] deploy + +Deploy a ROMFS image to the device. *source* can be either: + +- A directory on the host: the ROMFS image is built in memory and deployed + directly. +- A ``.romfs`` or ``.img`` file: the image is read from disk and deployed. + +Options: + +- ``-p ``, ``--partition ``: Specify the target + partition index (default: ``0``). +- ``-m``, ``--mpy`` (default): Compile ``.py`` to ``.mpy`` when *source* + is a directory. If ``mpy_cross`` is not installed, ``mpremote`` prints a + warning and leaves the ``.py`` files unchanged. +- ``--no-mpy``: Disable automatic compilation of ``.py`` files. + +After deployment, the device must be soft-reset for the new ROMFS to be +mounted at ``/rom``. + +Example:: + + $ mpremote romfs deploy myapp/ + Building romfs filesystem, source directory: myapp/ + / + |-- main.py -> .mpy + \-- lib/ + \-- helper.py -> .mpy + Image size is 2048 bytes + ROMFS0 partition has size 131072 bytes (32 blocks of 4096 bytes each) + Preparing ROMFS0 partition for writing + Deploying ROMFS to ROMFS0 partition + ROMFS image deployed + + $ mpremote soft-reset + .. _mpremote_reset: Auto connection and soft-reset diff --git a/docs/reference/romfs.rst b/docs/reference/romfs.rst new file mode 100644 index 00000000000..ec4643ae757 --- /dev/null +++ b/docs/reference/romfs.rst @@ -0,0 +1,253 @@ +.. _romfs: + +Working with ROMFS +================== + +.. contents:: + +Overview +-------- + +ROMFS (Read-Only Memory Filesystem) is a lightweight, read-only filesystem +optimised for microcontrollers and embedded systems +where code and data need to be stored in flash memory and +accessed efficiently without being copied into RAM. + +The key benefits of ROMFS are: + +- **Zero-copy imports**: ``.mpy`` bytecode files stored in a ROMFS can be + executed directly from flash memory (memory-mapped) rather than being copied + into RAM first. This is similar to how :ref:`frozen modules ` work, + but does not require reflashing the entire firmware. +- **Low RAM overhead**: String and byte constant objects in ``.mpy`` + files loaded from ROMFS are referenced directly from flash, not duplicated + in RAM. +- **Flexible deployment**: A ROMFS image can be built on a host PC and deployed + to the device using ``mpremote``, without rebuilding the firmware. +- **Standard filesystem interface**: A ROMFS is mounted in the :ref:`VFS + ` and accessed via normal Python file operations (``open``, + ``os.listdir``, ``import``, etc.). + +ROMFS is complementary to both the read-write LittleFS/FAT filesystems (which +live in other flash partitions) and to :ref:`frozen modules ` (which +are compiled into the firmware itself). + +.. note:: + + ROMFS requires firmware that has been built with ROMFS support enabled + (``MICROPY_VFS_ROM``). Not all ports or boards include this by default; + check your board's documentation or build configuration. + +Port support +------------ + +The following ports support ROMFS. On these ports, if a ROMFS partition is +configured for the board, it will be automatically detected at boot time and +mounted at ``/rom`` in the VFS. Both ``/rom`` and ``/rom/lib`` are +automatically added to ``sys.path`` so that modules stored there can be +imported directly. + +============== ==================================================== +Port Notes +============== ==================================================== +alif Supported on boards with ROMFS partition configured. +esp32 Supported with custom partition table. +esp8266 Supported on 2MiB+ boards (ESP8266_GENERIC FLASH_2M_ROMFS variant). +mimxrt Supported on boards with ROMFS partition configured. +nrf Supported on boards with ROMFS partition configured. +qemu Supported (used for CI testing). +renesas-ra Supported on boards with ROMFS partition configured. +rp2 Supported on boards with ROMFS partition configured. +samd Supported on boards with ROMFS partition configured. +stm32 Supported on boards with ROMFS partition configured. +unix Supported (primarily for testing). +============== ==================================================== + +Enabling ROMFS for a port or board +---------------------------------- + +The ROMFS implementation is port specific at this time and requires too much detail to explain here. + +Workflow +-------- + +The typical workflow for using ROMFS is: + +1. Create a directory on your PC with the Python files (or ``.mpy`` files) + you want to deploy. +2. Use ``mpremote romfs deploy `` to build and deploy the ROMFS + image to the device. +3. The ROMFS will be mounted at ``/rom`` on next boot (or can be mounted + immediately if the device is soft-reset). +4. Python code on the device can then ``import`` modules from the ROMFS just + like from any other filesystem. + +For example, on the host PC, with a directory "myapp/" containing app.py:: + + $ mpremote romfs deploy myapp/ + +After a soft-reset, the device will have ``/rom/app.mpy`` available for import +(or ``/rom/app.py`` if ``mpy_cross`` is not installed). + +Alternatively, you can build the ROMFS image on the host PC first, then deploy +it to the device:: + + $ mpremote romfs build myapp + $ mpremote romfs deploy myapp.romfs + +See the :ref:`mpremote romfs commands ` section for +full details of the ``mpremote`` commands. + +Automatic mounting at boot +-------------------------- + +When ROMFS support is enabled in the firmware, MicroPython will automatically +attempt to mount the first ROM partition at ``/rom`` during initialisation +(after ``mp_init()``). If the partition contains a valid ROMFS image, it is +mounted and both ``/rom`` and ``/rom/lib`` are added to ``sys.path`` +automatically. + +This means that after deploying a ROMFS image with ``mpremote``, a soft-reset +is sufficient to make the new modules importable. + +If no valid ROMFS image is found in the partition (e.g. on a freshly-programmed +board), the mount is silently skipped. + +Using mpremote to manage ROMFS +------------------------------ + +The :ref:`mpremote ` ``romfs`` command can query ROMFS partitions, +build ROMFS images, and deploy images to a connected device. See +:ref:`mpremote ROMFS commands ` for command syntax, +options, and examples. + +ROMFS usage examples +-------------------- + +Deploying a simple application +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Suppose you have a project directory ``myapp/`` with the following structure:: + + ── myapp + ├── myapp.py + ├── utils.py + └── lib + └── helper.py + +To deploy it to the device's ROMFS:: + + $ mpremote romfs deploy myapp/ + $ mpremote tree + tree : + :/ + └── rom + ├── lib + │ └── helper.mpy + ├── myapp.mpy + └── utils.mpy + +After a soft-reset, the modules are importable from the ROMFS as its mount point +and lib folder have been added to ``sys.path``:: + + import myapp + import utils + import helper + +Listing ROMFS contents from Python +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +After mounting, the ROMFS contents can be explored like any other +filesystem:: + + import os + + for entry in os.ilistdir('/rom'): + print(entry) + + # Or simply: + print(os.listdir('/rom')) + +Manually mount a second ROMFS image +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If there are multiple ROMFS partitions, it is possible to mount +a second ROMFS image from another partition on the device. +For example, if the second ROMFS partition is at index 2, you can +mount it using:: + + import vfs + dev = vfs.rom_ioctl(2, 1) # get second partition + vfs.mount(vfs.VfsRom(dev), "/rom2") + +Mount a ROMFS image stored in a file +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +A ROMFS image stored as a file within a ROMFS can be mounted as a +nested filesystem without copying it into RAM. For example, if +``/rom/data.romfs`` exists, you can mount it using:: + + # boot.py + import vfs + with open('/rom/data.romfs', 'rb') as f: + fs = vfs.VfsRom(f) + vfs.mount(fs, '/data') + +Then after a soft-reset, the nested ROMFS is available at ``/data``:: + + $ mpremote tree + tree : + :/ + ├── boot.py + ├── data + │ └── facts.db + ├── main.py + └── rom + ├── data.romfs + ├── lib + │ └── helper.mpy + ├── myapp.mpy + └── utils.mpy + +ROMFS filesystem format +======================= +ROMFS is a flexible and extensible filesystem format designed to represent a +directory hierarchy with files, where those files are read-only and their data +can be memory mapped. + +Concepts: + +- ``varuint`` : An unsigned integer that is encoded in a variable number of bytes. + It is stored big-endian with the high bit of the byte set if there are following bytes. +- ``record`` : A variable sized element with a type. It is stored as two ``varuint``'s and then + a payload. The first ``varuint`` is the record kind and the second ``varuint`` is the + payload length (which may be zero bytes long). + +A ROMFS filesystem is a record with record kind 0x14a6b1, chosen so the encoded value +is ``0xd2-0xcd-0x31`` which is ``"RM1"`` with the first two bytes having their high bit set. +If the ROMFS record's payload is non-empty then it contains records. + +Record types: + +- ``0`` -- **unused**: Can be used to detect corruption of the filesystem. +- ``1`` -- **padding/comments**: Can contain any data in the payload. +- ``2`` -- **verbatim data**: Used to store file data. +- ``3`` -- **indirect data**: Points to an offset within the ROMFS payload. +- ``4`` -- **directory**: The payload contains a ``varuint`` giving the length of + the directory name in bytes, followed by the name and optional nested records + for the directory contents (including optional metadata). +- ``5`` -- **file**: The payload contains a ``varuint`` giving the length of the + filename in bytes, followed by the name and optional nested records. + +Unknown record types are silently skipped, providing forwards compatibility. + +This format is defined in ``extmod/vfs_rom.c`` in the MicroPython source. +The Python implementation used by ``mpremote`` to build images is in +``tools/mpremote/mpremote/romfs.py``. + +.. seealso:: + + - :ref:`filesystem` -- Overview of the MicroPython VFS and available + filesystem types. + - :ref:`manifest` -- How to freeze Python modules into firmware. + - :ref:`mpy_files` -- MicroPython ``.mpy`` binary file format. + - :ref:`mpremote` -- The full ``mpremote`` command reference. From 8f6fe0d218a8a711d914e9b2cf9b1400edaa9586 Mon Sep 17 00:00:00 2001 From: Chris Mason Date: Thu, 6 Aug 2026 20:51:11 +1000 Subject: [PATCH 590/635] stm32/uart: Add missing UART 11 and 12 and Flow Control. For STM32H5 add USART11 and UART12 with flow control. For STM32H7 add flow control for UART9 and USART10. Signed-off-by: Chris Mason --- ports/stm32/machine_uart.c | 8 ++++ ports/stm32/stm32_it.c | 16 +++++++ ports/stm32/uart.c | 90 ++++++++++++++++++++++++++++++++++++++ ports/stm32/uart.h | 2 + 4 files changed, 116 insertions(+) diff --git a/ports/stm32/machine_uart.c b/ports/stm32/machine_uart.c index 4f251bd660d..97c607a89da 100644 --- a/ports/stm32/machine_uart.c +++ b/ports/stm32/machine_uart.c @@ -367,6 +367,14 @@ static mp_obj_t mp_machine_uart_make_new(const mp_obj_type_t *type, size_t n_arg } else if (strcmp(port, MICROPY_HW_UART10_NAME) == 0) { uart_id = PYB_UART_10; #endif + #ifdef MICROPY_HW_UART11_NAME + } else if (strcmp(port, MICROPY_HW_UART11_NAME) == 0) { + uart_id = PYB_UART_11; + #endif + #ifdef MICROPY_HW_UART12_NAME + } else if (strcmp(port, MICROPY_HW_UART12_NAME) == 0) { + uart_id = PYB_UART_12; + #endif #ifdef MICROPY_HW_LPUART1_NAME } else if (strcmp(port, MICROPY_HW_LPUART1_NAME) == 0) { uart_id = PYB_LPUART_1; diff --git a/ports/stm32/stm32_it.c b/ports/stm32/stm32_it.c index d8cba90f94e..85240f19ef2 100644 --- a/ports/stm32/stm32_it.c +++ b/ports/stm32/stm32_it.c @@ -1044,6 +1044,22 @@ void USART10_IRQHandler(void) { } #endif +#if defined(USART11) +void USART11_IRQHandler(void) { + IRQ_ENTER(USART11_IRQn); + uart_irq_handler(11); + IRQ_EXIT(USART11_IRQn); +} +#endif + +#if defined(UART12) +void UART12_IRQHandler(void) { + IRQ_ENTER(UART12_IRQn); + uart_irq_handler(12); + IRQ_EXIT(UART12_IRQn); +} +#endif + #endif #if defined(LPUART1) diff --git a/ports/stm32/uart.c b/ports/stm32/uart.c index 0235078b61a..1ee8f878b09 100644 --- a/ports/stm32/uart.c +++ b/ports/stm32/uart.c @@ -248,6 +248,16 @@ bool uart_exists(int uart_id) { return true; #endif + #if defined(MICROPY_HW_UART11_TX) && defined(MICROPY_HW_UART11_RX) + case PYB_UART_11: + return true; + #endif + + #if defined(MICROPY_HW_UART12_TX) && defined(MICROPY_HW_UART12_RX) + case PYB_UART_12: + return true; + #endif + #if defined(MICROPY_HW_LPUART1_TX) && defined(MICROPY_HW_LPUART1_RX) case PYB_LPUART_1: return true; @@ -557,9 +567,22 @@ bool uart_init(machine_uart_obj_t *uart_obj, __HAL_RCC_UART9_CLK_ENABLE(); pins[0] = MICROPY_HW_UART9_TX; pins[1] = MICROPY_HW_UART9_RX; + #if defined(MICROPY_HW_UART9_RTS) + if (flow & UART_HWCONTROL_RTS) { + pins[2] = MICROPY_HW_UART9_RTS; + } + #endif + #if defined(MICROPY_HW_UART9_CTS) + if (flow & UART_HWCONTROL_CTS) { + pins[3] = MICROPY_HW_UART9_CTS; + } + #endif #if defined(MICROPY_HW_UART9_RX_PULL) pins_pull[1] = MICROPY_HW_UART9_RX_PULL; #endif + #if defined(MICROPY_HW_UART9_CTS_PULL) + pins_pull[3] = MICROPY_HW_UART9_CTS_PULL; + #endif break; #endif @@ -577,9 +600,76 @@ bool uart_init(machine_uart_obj_t *uart_obj, #endif pins[0] = MICROPY_HW_UART10_TX; pins[1] = MICROPY_HW_UART10_RX; + #if defined(MICROPY_HW_UART10_RTS) + if (flow & UART_HWCONTROL_RTS) { + pins[2] = MICROPY_HW_UART10_RTS; + } + #endif + #if defined(MICROPY_HW_UART10_CTS) + if (flow & UART_HWCONTROL_CTS) { + pins[3] = MICROPY_HW_UART10_CTS; + } + #endif #if defined(MICROPY_HW_UART10_RX_PULL) pins_pull[1] = MICROPY_HW_UART10_RX_PULL; #endif + #if defined(MICROPY_HW_UART10_CTS_PULL) + pins_pull[3] = MICROPY_HW_UART10_CTS_PULL; + #endif + break; + #endif + + #if defined(MICROPY_HW_UART11_TX) && defined(MICROPY_HW_UART11_RX) + case PYB_UART_11: + uart_unit = 11; + UARTx = USART11; + irqn = USART11_IRQn; + __HAL_RCC_USART11_CLK_ENABLE(); + pins[0] = MICROPY_HW_UART11_TX; + pins[1] = MICROPY_HW_UART11_RX; + #if defined(MICROPY_HW_UART11_RTS) + if (flow & UART_HWCONTROL_RTS) { + pins[2] = MICROPY_HW_UART11_RTS; + } + #endif + #if defined(MICROPY_HW_UART11_CTS) + if (flow & UART_HWCONTROL_CTS) { + pins[3] = MICROPY_HW_UART11_CTS; + } + #endif + #if defined(MICROPY_HW_UART11_RX_PULL) + pins_pull[1] = MICROPY_HW_UART11_RX_PULL; + #endif + #if defined(MICROPY_HW_UART11_CTS_PULL) + pins_pull[3] = MICROPY_HW_UART11_CTS_PULL; + #endif + break; + #endif + + #if defined(MICROPY_HW_UART12_TX) && defined(MICROPY_HW_UART12_RX) + case PYB_UART_12: + uart_unit = 12; + UARTx = UART12; + irqn = UART12_IRQn; + __HAL_RCC_UART12_CLK_ENABLE(); + pins[0] = MICROPY_HW_UART12_TX; + pins[1] = MICROPY_HW_UART12_RX; + #if defined(MICROPY_HW_UART12_RTS) + if (flow & UART_HWCONTROL_RTS) { + pins[2] = MICROPY_HW_UART12_RTS; + } + #endif + #if defined(MICROPY_HW_UART12_CTS) + if (flow & UART_HWCONTROL_CTS) { + pins[3] = MICROPY_HW_UART12_CTS; + } + #endif + #if defined(MICROPY_HW_UART12_RX_PULL) + pins_pull[1] = MICROPY_HW_UART12_RX_PULL; + #endif + #if defined(MICROPY_HW_UART12_CTS_PULL) + pins_pull[3] = MICROPY_HW_UART12_CTS_PULL; + #endif break; #endif diff --git a/ports/stm32/uart.h b/ports/stm32/uart.h index 448140f1778..27af496adb4 100644 --- a/ports/stm32/uart.h +++ b/ports/stm32/uart.h @@ -41,6 +41,8 @@ typedef enum { PYB_UART_8 = 8, PYB_UART_9 = 9, PYB_UART_10 = 10, + PYB_UART_11 = 11, + PYB_UART_12 = 12, #ifdef LPUART1 PYB_LPUART_1 = MICROPY_HW_MAX_UART + 1, #endif From 764ff230ff416bfbe2d9abb0df6934beb42358db Mon Sep 17 00:00:00 2001 From: Chris Mason Date: Thu, 6 Aug 2026 22:58:43 +1000 Subject: [PATCH 591/635] stm32/boards/NUCLEO_H563ZI: Add USART11, UART12 to mpconfigboard.h. Add USART11 and UART12. Note that UART11_Rx and LED2 share a pin. Signed-off-by: Chris Mason --- ports/stm32/boards/NUCLEO_H563ZI/mpconfigboard.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/ports/stm32/boards/NUCLEO_H563ZI/mpconfigboard.h b/ports/stm32/boards/NUCLEO_H563ZI/mpconfigboard.h index 1e802eda5b0..e8608df6f08 100644 --- a/ports/stm32/boards/NUCLEO_H563ZI/mpconfigboard.h +++ b/ports/stm32/boards/NUCLEO_H563ZI/mpconfigboard.h @@ -44,6 +44,10 @@ #define MICROPY_HW_UART1_RX (pin_B7) // SB63: Arduino Connector CN10-Pin16 (D0) #define MICROPY_HW_UART3_TX (pin_D8) // SB23: ST-Link #define MICROPY_HW_UART3_RX (pin_D9) // SB18: ST-Link +#define MICROPY_HW_UART11_TX (pin_F3) // CN12-58 +#define MICROPY_HW_UART11_RX (pin_F4) // CN12-38 Shared with yellow LED2. +#define MICROPY_HW_UART12_TX (pin_E10) // CN12-47 +#define MICROPY_HW_UART12_RX (pin_E9) // CN12-52 // Connect REPL to UART3 which is provided on ST-Link USB interface #define MICROPY_HW_UART_REPL PYB_UART_3 @@ -70,7 +74,7 @@ // LEDs #define MICROPY_HW_LED1 (pin_B0) // Green -#define MICROPY_HW_LED2 (pin_F4) // Orange +#define MICROPY_HW_LED2 (pin_F4) // Yellow shared with UART11 #define MICROPY_HW_LED3 (pin_G4) // Red #define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin)) #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin)) From 182763128200021aee1c1c4bf85bf9cce40fb0fe Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 5 Aug 2026 12:13:57 +1000 Subject: [PATCH 592/635] stm32/mpu: Reuse MPU_ATTRIBUTES_NUMBER0 for all non-cacheable uses. On H5 and N6 MCUs, `MPU_ATTRIBUTES_NUMBER0` is unconditionally set to non- cacheable (mode 0x44) in `mpu_init()`, and used for accessing the unique device signature. `MPU_ATTRIBUTES_NUMBER1` is also configured to the same 0x44 mode in `mpu_config_region()` and used for ETH, uncached DMA and backup SRAM access. This commit cleans that up by using `MPU_ATTRIBUTES_NUMBER0` in both cases, removing the need for `MPU_ATTRIBUTES_NUMBER1`. History: the use of `MPU_ATTRIBUTES_NUMBER1` was added for H5 in commit 51da8cc28bb6073588e4938489194f2f937006df which could have at the time have reused `MPU_ATTRIBUTES_NUMBER0`. The code was later extended to support N6 in eb3ea9ee13093d81053f5d07b8c96e4fc0e1383d, and backup SRAM in fb1375b57853202eb55c63741f1e6d927bc7bb64. Fixes issue #19578. Signed-off-by: Damien George --- ports/stm32/mpu.h | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/ports/stm32/mpu.h b/ports/stm32/mpu.h index de7b35819b7..2d74069b9f8 100644 --- a/ports/stm32/mpu.h +++ b/ports/stm32/mpu.h @@ -164,7 +164,8 @@ static inline void mpu_config_end(uint32_t irq_state) { #endif static inline void mpu_init(void) { - // Configure attribute 0, inner-outer non-cacheable (=0x44). + // Configure MPU_ATTRIBUTES_NUMBER0: inner-outer non-cacheable (=0x44). + // This attribute is used both here and in mpu_config_region(). __DMB(); MPU->MAIR0 = (MPU->MAIR0 & ~MPU_MAIR0_Attr0_Msk) | 0x44 << MPU_MAIR0_Attr0_Pos; @@ -200,12 +201,6 @@ static inline void mpu_config_region(uint32_t region, uint32_t base_addr, uint32 } else if (region == MPU_REGION_ETH || region == MPU_REGION_DMA_UNCACHED_1 || region == MPU_REGION_DMA_UNCACHED_2 || region == MPU_REGION_BKPSRAM) { // Configure region to make DMA memory non-cacheable. - __DMB(); - // Configure attribute 1, inner-outer non-cacheable (=0x44). - MPU->MAIR0 = (MPU->MAIR0 & ~MPU_MAIR0_Attr1_Msk) - | 0x44 << MPU_MAIR0_Attr1_Pos; - __DMB(); - // RBAR // BASE Bits [31:5] of base address // SH[4:3] 00 = Non-shareable @@ -214,15 +209,16 @@ static inline void mpu_config_region(uint32_t region, uint32_t base_addr, uint32 // RLAR // LIMIT Limit address. Contains bits[31:5] of the upper inclusive limit of the selected MPU memory region - // AT[3:1] 001 = Attribute 1 + // AT[3:1] 000 = Attribute 0 // EN[0] 1 = Enabled + __DMB(); MPU->RNR = region; MPU->RBAR = (base_addr & MPU_RBAR_BASE_Msk) | MPU_ACCESS_NOT_SHAREABLE << MPU_RBAR_SH_Pos | MPU_REGION_ALL_RW << MPU_RBAR_AP_Pos | MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RBAR_XN_Pos; MPU->RLAR = ((base_addr + size - 1) & MPU_RLAR_LIMIT_Msk) - | MPU_ATTRIBUTES_NUMBER1 << MPU_RLAR_AttrIndx_Pos + | MPU_ATTRIBUTES_NUMBER0 << MPU_RLAR_AttrIndx_Pos | MPU_REGION_ENABLE << MPU_RLAR_EN_Pos; } __DMB(); From c5d5e71f8985455eb6773e7534e1e90aa3c06e08 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 5 Aug 2026 14:31:42 +1000 Subject: [PATCH 593/635] stm32/boards/NUCLEO_H723ZG: Enable MICROPY_HW_ENABLE_RNG. The RNG works on the H723 since af2c47965b4b385d007f1c4ec7cc091c23408099. It's needed because mbedTLS is enabled, which needs `mp_hal_get_random()` to provide a good source of randomness. Signed-off-by: Damien George --- ports/stm32/boards/NUCLEO_H723ZG/mpconfigboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/stm32/boards/NUCLEO_H723ZG/mpconfigboard.h b/ports/stm32/boards/NUCLEO_H723ZG/mpconfigboard.h index 095b7f4b155..51f366577b2 100644 --- a/ports/stm32/boards/NUCLEO_H723ZG/mpconfigboard.h +++ b/ports/stm32/boards/NUCLEO_H723ZG/mpconfigboard.h @@ -2,7 +2,7 @@ #define MICROPY_HW_MCU_NAME "STM32H723ZGT6" #define MICROPY_HW_ENABLE_RTC (1) -#define MICROPY_HW_ENABLE_RNG (0) // RNG needs proper configuration +#define MICROPY_HW_ENABLE_RNG (1) #define MICROPY_HW_ENABLE_ADC (1) #define MICROPY_HW_ENABLE_DAC (1) #define MICROPY_HW_ENABLE_USB (1) From 798a61a43857cbd278410b52ca5bd258500d9ab0 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 5 Aug 2026 14:48:53 +1000 Subject: [PATCH 594/635] stm32/mpconfigport: Only enable RANDOM_SEED_INIT_FUNC if hw RNG avail. Signed-off-by: Damien George --- ports/stm32/mpconfigport.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ports/stm32/mpconfigport.h b/ports/stm32/mpconfigport.h index d1c480649de..0c32f48bcca 100644 --- a/ports/stm32/mpconfigport.h +++ b/ports/stm32/mpconfigport.h @@ -104,8 +104,10 @@ #define MICROPY_PY_OS_DUPTERM_STREAM_DETACHED_ATTACHED (1) #define MICROPY_PY_OS_SYNC (1) #define MICROPY_PY_OS_UNAME (1) -#define MICROPY_PY_OS_URANDOM (MICROPY_HW_ENABLE_RNG) +#if MICROPY_HW_ENABLE_RNG +#define MICROPY_PY_OS_URANDOM (1) #define MICROPY_PY_RANDOM_SEED_INIT_FUNC (rng_get()) +#endif #define MICROPY_PY_TIME_GMTIME_LOCALTIME_MKTIME (1) #define MICROPY_PY_TIME_TIME_TIME_NS (1) #define MICROPY_PY_TIME_INCLUDEFILE "ports/stm32/modtime.c" From 7750bf8488a4cbb535132898488fe754268d683e Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 5 Aug 2026 14:27:53 +1000 Subject: [PATCH 595/635] stm32/mphalport: Only build mp_hal_get_random if hardware RNG available. So that there's a build error if `mp_hal_get_random()` is used without being backed by a hardware RNG. Signed-off-by: Damien George --- ports/stm32/mphalport.c | 2 ++ ports/stm32/mphalport.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/ports/stm32/mphalport.c b/ports/stm32/mphalport.c index 0481a962f7b..18c6bbd617d 100644 --- a/ports/stm32/mphalport.c +++ b/ports/stm32/mphalport.c @@ -222,6 +222,7 @@ void mp_hal_get_mac_ascii(int idx, size_t chr_off, size_t chr_len, char *dest) { } } +#if MICROPY_HW_ENABLE_RNG void mp_hal_get_random(size_t n, uint8_t *buf) { uint32_t val = 0; for (int i = 0; i < n; i++) { @@ -232,5 +233,6 @@ void mp_hal_get_random(size_t n, uint8_t *buf) { val >>= 8; } } +#endif MP_REGISTER_ROOT_POINTER(struct _machine_uart_obj_t *pyb_stdio_uart); diff --git a/ports/stm32/mphalport.h b/ports/stm32/mphalport.h index fe144c6eedd..1469837ae4b 100644 --- a/ports/stm32/mphalport.h +++ b/ports/stm32/mphalport.h @@ -173,7 +173,9 @@ enum { void mp_hal_generate_laa_mac(int idx, uint8_t buf[6]); void mp_hal_get_mac(int idx, uint8_t buf[6]); void mp_hal_get_mac_ascii(int idx, size_t chr_off, size_t chr_len, char *dest); +#if MICROPY_HW_ENABLE_RNG void mp_hal_get_random(size_t n, uint8_t *buf); +#endif static inline void mp_hal_wake_main_task_from_isr(void) { // Defined for tinyusb support, nothing needs to be done here. From 370d4ed91bf60eec1b5b60d2625587efc299e9c0 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 5 Aug 2026 14:35:42 +1000 Subject: [PATCH 596/635] stm32/rng: Remove PRNG implementation of rng_get. Due to parent commits it's no longer needed. Boards must enable `MICROPY_HW_ENABLE_RNG` to get features needing a random number. Signed-off-by: Damien George --- ports/stm32/rng.c | 39 +-------------------------------------- 1 file changed, 1 insertion(+), 38 deletions(-) diff --git a/ports/stm32/rng.c b/ports/stm32/rng.c index 5f9bf1448df..87ee592a216 100644 --- a/ports/stm32/rng.c +++ b/ports/stm32/rng.c @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2013-2018 Damien P. George + * Copyright (c) 2013-2026 Damien P. George * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,7 +25,6 @@ */ #include "py/mphal.h" -#include "rtc.h" #include "rng.h" #if MICROPY_HW_ENABLE_RNG @@ -77,40 +76,4 @@ static mp_obj_t pyb_rng_get(void) { } MP_DEFINE_CONST_FUN_OBJ_0(pyb_rng_get_obj, pyb_rng_get); -#else // MICROPY_HW_ENABLE_RNG - -// For MCUs that don't have an RNG we still need to provide a rng_get() function, -// eg for lwIP and random.seed(). A pseudo-RNG is not really ideal but we go with -// it for now, seeding with numbers which will be somewhat different each time. We -// don't want to use random's pRNG because then the user won't see a reproducible -// random stream. - -// Yasmarang random number generator by Ilya Levin -// http://www.literatecode.com/yasmarang -static uint32_t pyb_rng_yasmarang(void) { - static bool seeded = false; - static uint32_t pad = 0, n = 0, d = 0; - static uint8_t dat = 0; - - if (!seeded) { - seeded = true; - rtc_init_finalise(); - pad = *(uint32_t *)MP_HAL_UNIQUE_ID_ADDRESS ^ SysTick->VAL; - n = RTC->TR; - d = RTC->SSR; - } - - pad += dat + d * n; - pad = (pad << 3) + (pad >> 29); - n = pad | 2; - d ^= (pad << 31) + (pad >> 1); - dat ^= (char)pad ^ (d >> 8) ^ 1; - - return pad ^ (d << 5) ^ (pad >> 18) ^ (dat << 1); -} - -uint32_t rng_get(void) { - return pyb_rng_yasmarang(); -} - #endif // MICROPY_HW_ENABLE_RNG From 7a6c6549cf28837270153b477add7b1114325948 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 12 Aug 2026 17:16:22 +1000 Subject: [PATCH 597/635] stm32/rng: Rename rng_get to mp_hal_get_hw_random_u32. Makes it a bit clearer what the function does. Signed-off-by: Damien George --- ports/stm32/lwip_inc/lwipopts.h | 4 ++-- ports/stm32/mboot/Particle.h | 10 ++++++---- ports/stm32/mpconfigport.h | 4 ++-- ports/stm32/mphalport.c | 2 +- ports/stm32/rng.c | 4 ++-- ports/stm32/rng.h | 2 +- 6 files changed, 14 insertions(+), 12 deletions(-) diff --git a/ports/stm32/lwip_inc/lwipopts.h b/ports/stm32/lwip_inc/lwipopts.h index 62b0dab4844..f3bc11fb41d 100644 --- a/ports/stm32/lwip_inc/lwipopts.h +++ b/ports/stm32/lwip_inc/lwipopts.h @@ -8,7 +8,7 @@ #define LWIP_LOOPIF_MULTICAST 1 #define LWIP_LOOPBACK_MAX_PBUFS 8 -#define LWIP_RAND() rng_get() +#define LWIP_RAND() mp_hal_get_hw_random_u32() // Increase memory for lwIP to get better performance. #if defined(STM32N6) @@ -23,6 +23,6 @@ // Include common lwIP configuration (also mpconfig.h). #include "extmod/lwip-include/lwipopts_common.h" -extern uint32_t rng_get(void); +extern uint32_t mp_hal_get_hw_random_u32(void); #endif // MICROPY_INCLUDED_STM32_LWIP_LWIPOPTS_H diff --git a/ports/stm32/mboot/Particle.h b/ports/stm32/mboot/Particle.h index 5e0953739a7..0daf8247efc 100644 --- a/ports/stm32/mboot/Particle.h +++ b/ports/stm32/mboot/Particle.h @@ -1,10 +1,12 @@ // Header for libhydrogen use only. Act like a Particle board for the random // implementation. This code is not actually called when just decrypting and -// verifying a signature, but a correct implementation is provided anyway. +// verifying a signature, so call a function that does not exist in order to +// trigger a link error if it is unintentionally used. -#include "py/mphal.h" -#include "rng.h" +#include + +uint32_t invalid_function_used_to_prevent_code_being_used(void); static inline uint32_t HAL_RNG_GetRandomNumber(void) { - return rng_get(); + return invalid_function_used_to_prevent_code_being_used(); } diff --git a/ports/stm32/mpconfigport.h b/ports/stm32/mpconfigport.h index 0c32f48bcca..5c5bb5d107c 100644 --- a/ports/stm32/mpconfigport.h +++ b/ports/stm32/mpconfigport.h @@ -106,7 +106,7 @@ #define MICROPY_PY_OS_UNAME (1) #if MICROPY_HW_ENABLE_RNG #define MICROPY_PY_OS_URANDOM (1) -#define MICROPY_PY_RANDOM_SEED_INIT_FUNC (rng_get()) +#define MICROPY_PY_RANDOM_SEED_INIT_FUNC (mp_hal_get_hw_random_u32()) #endif #define MICROPY_PY_TIME_GMTIME_LOCALTIME_MKTIME (1) #define MICROPY_PY_TIME_TIME_TIME_NS (1) @@ -300,4 +300,4 @@ typedef long mp_off_t; #include // Needed for MICROPY_PY_RANDOM_SEED_INIT_FUNC. -uint32_t rng_get(void); +uint32_t mp_hal_get_hw_random_u32(void); diff --git a/ports/stm32/mphalport.c b/ports/stm32/mphalport.c index 18c6bbd617d..892098c2910 100644 --- a/ports/stm32/mphalport.c +++ b/ports/stm32/mphalport.c @@ -227,7 +227,7 @@ void mp_hal_get_random(size_t n, uint8_t *buf) { uint32_t val = 0; for (int i = 0; i < n; i++) { if ((i & 3) == 0) { - val = rng_get(); + val = mp_hal_get_hw_random_u32(); } buf[i] = val; val >>= 8; diff --git a/ports/stm32/rng.c b/ports/stm32/rng.c index 87ee592a216..f0cbc7a11ff 100644 --- a/ports/stm32/rng.c +++ b/ports/stm32/rng.c @@ -32,7 +32,7 @@ #define RNG_TIMEOUT_MS (10) #define RNG_RETRY_MAX_COUNT (10) -uint32_t rng_get(void) { +uint32_t mp_hal_get_hw_random_u32(void) { // Enable the RNG peripheral if it's not already enabled if (!(RNG->CR & RNG_CR_RNGEN)) { #if defined(STM32H7) @@ -72,7 +72,7 @@ uint32_t rng_get(void) { // Return a 30-bit hardware generated random number. static mp_obj_t pyb_rng_get(void) { - return mp_obj_new_int(rng_get() >> 2); + return mp_obj_new_int(mp_hal_get_hw_random_u32() >> 2); } MP_DEFINE_CONST_FUN_OBJ_0(pyb_rng_get_obj, pyb_rng_get); diff --git a/ports/stm32/rng.h b/ports/stm32/rng.h index ed9cc80f2b8..3083dd7a37c 100644 --- a/ports/stm32/rng.h +++ b/ports/stm32/rng.h @@ -28,7 +28,7 @@ #include "py/obj.h" -uint32_t rng_get(void); +uint32_t mp_hal_get_hw_random_u32(void); MP_DECLARE_CONST_FUN_OBJ_0(pyb_rng_get_obj); From 240240e065640a7f5bbb63936bf33314657ce961 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 12 Aug 2026 23:09:33 +1000 Subject: [PATCH 598/635] stm32/rng: Raise an exception if hardware RNG fails. When code relies on the RNG to generate proper random numbers, it's a critical system error if the RNG fails. In that case raise an OSError. Signed-off-by: Damien George --- ports/stm32/rng.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/ports/stm32/rng.c b/ports/stm32/rng.c index f0cbc7a11ff..0fb4aed8b33 100644 --- a/ports/stm32/rng.c +++ b/ports/stm32/rng.c @@ -25,6 +25,7 @@ */ #include "py/mphal.h" +#include "py/runtime.h" #include "rng.h" #if MICROPY_HW_ENABLE_RNG @@ -52,17 +53,16 @@ uint32_t mp_hal_get_hw_random_u32(void) { while (!(RNG->SR & RNG_SR_DRDY)) { if (HAL_GetTick() - start >= RNG_TIMEOUT_MS) { #if defined(RNG_CR_CONDRST) - if (retry_count > RNG_RETRY_MAX_COUNT) { - return 0; + if (retry_count <= RNG_RETRY_MAX_COUNT) { + // Reset and retry waiting RNG_SR_DRDY. + RNG->CR |= RNG_CR_CONDRST; + RNG->CR = (RNG->CR & ~RNG_CR_CONDRST); + start = HAL_GetTick(); + retry_count++; + continue; } - // Reset and retry waiting RNG_SR_DRDY. - RNG->CR |= RNG_CR_CONDRST; - RNG->CR = (RNG->CR & ~RNG_CR_CONDRST); - start = HAL_GetTick(); - retry_count++; - #else - return 0; #endif + mp_raise_msg(&mp_type_OSError, MP_ERROR_TEXT("RNG failed")); } } From 9e64b04411edbf96d2767023f0fddf323de25bfd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Pierson?= Date: Wed, 24 Jun 2026 15:40:01 +0200 Subject: [PATCH 599/635] stm32/mpu: Support STM32F412 MCUs. Signed-off-by: Damien George --- ports/stm32/mpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ports/stm32/mpu.h b/ports/stm32/mpu.h index 2d74069b9f8..1c0da7bc866 100644 --- a/ports/stm32/mpu.h +++ b/ports/stm32/mpu.h @@ -28,7 +28,9 @@ #include "irq.h" -#if (defined(STM32F4) && defined(MICROPY_HW_ETH_MDC)) || defined(STM32F469xx) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) +#if (defined(STM32F4) && defined(MICROPY_HW_ETH_MDC)) || \ + defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || \ + defined(STM32F469xx) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define MPU_REGION_ETH (MPU_REGION_NUMBER0) #define MPU_REGION_QSPI1 (MPU_REGION_NUMBER1) From 43efed3f3aa43b3734338bd37eeb121e536ebb2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Pierson?= Date: Wed, 24 Jun 2026 15:40:01 +0200 Subject: [PATCH 600/635] stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC: Add new Garatronic board. Signed-off-by: Damien George --- .../GARATRONIC_PYMATE_CORE8ADI8DOSC/bdev.c | 45 +++++ .../board.json | 15 ++ .../f412_qspi.ld | 45 +++++ .../mpconfigboard.h | 159 ++++++++++++++++++ .../mpconfigboard.mk | 19 +++ .../GARATRONIC_PYMATE_CORE8ADI8DOSC/pins.csv | 45 +++++ .../stm32f4xx_hal_conf.h | 22 +++ 7 files changed, 350 insertions(+) create mode 100644 ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/bdev.c create mode 100644 ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/board.json create mode 100644 ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/f412_qspi.ld create mode 100644 ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/mpconfigboard.h create mode 100644 ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/mpconfigboard.mk create mode 100644 ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/pins.csv create mode 100644 ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/stm32f4xx_hal_conf.h diff --git a/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/bdev.c b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/bdev.c new file mode 100644 index 00000000000..c81cb69e352 --- /dev/null +++ b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/bdev.c @@ -0,0 +1,45 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Garatronic, thanks to Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "storage.h" +#include "qspi.h" + +#if MICROPY_HW_SPIFLASH_ENABLE_CACHE +// Shared cache for first SPI block device +static mp_spiflash_cache_t spi_bdev_cache; +#endif + +// First external SPI flash uses hardware QSPI interface +const mp_spiflash_config_t spiflash_config = { + .bus_kind = MP_SPIFLASH_BUS_QSPI, + .bus.u_qspi.data = NULL, + .bus.u_qspi.proto = &qspi_proto, + #if MICROPY_HW_SPIFLASH_ENABLE_CACHE + .cache = &spi_bdev_cache, + #endif +}; + +spi_bdev_t spi_bdev; diff --git a/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/board.json b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/board.json new file mode 100644 index 00000000000..dfadffce415 --- /dev/null +++ b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/board.json @@ -0,0 +1,15 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [], + "images": [ + "PyMateIO_Core.jpg" + ], + "mcu": "stm32f4", + "product": "GARATRONIC_PYMATE_CORE8ADI8DOSC", + "thumbnail": "", + "url": "https://www.pymate.io/product/pymateio-core-8-digital-analog-inputs-8-digital-outputs-rs485-port-can-port/", + "vendor": "PyMateIO" +} diff --git a/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/f412_qspi.ld b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/f412_qspi.ld new file mode 100644 index 00000000000..b8570599225 --- /dev/null +++ b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/f412_qspi.ld @@ -0,0 +1,45 @@ +/* + Linker script for PYBSTICK26-PRO with STM32F412 + QSPI flash + + Memory layout for mboot configuration (this here describes the app part): + + FLASH_APP .isr_vector + FLASH_APP .text + FLASH_APP .data + + RAM .data + RAM .bss + RAM .heap + RAM .stack +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* sectors 0-1 */ + FLASH_APP (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* sectors 2-7 */ + FLASH_QSPI (rx) : ORIGIN = 0x90000000, LENGTH = 1024K /* external QSPI */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K /* SRAM */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define the stack. The stack is full descending so begins just above last byte + of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve; +_sstack = _estack - 16K; + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = _ebss; /* heap starts just after statically allocated memory */ +_heap_end = _sstack; + +/* ROMFS location */ +_micropy_hw_romfs_part0_start = ORIGIN(FLASH_QSPI); +_micropy_hw_romfs_part0_size = LENGTH(FLASH_QSPI); + +_micropy_hw_internal_flash_storage_start = ORIGIN (FLASH_QSPI); +_micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_QSPI) + LENGTH(FLASH_QSPI); diff --git a/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/mpconfigboard.h b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/mpconfigboard.h new file mode 100644 index 00000000000..116fedc3656 --- /dev/null +++ b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/mpconfigboard.h @@ -0,0 +1,159 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Garatronic SAS, thanks to Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#define MICROPY_HW_BOARD_NAME "PymateIO CORE8ADI8DOSC V0.2.0" +#define MICROPY_HW_MCU_NAME "STM32F412RE" +#define MICROPY_PY_THREAD (1) + +#define MICROPY_PY_PYB_LEGACY (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0) +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_RNG (1) +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_ENABLE_USB (1) +#define MICROPY_HW_ENABLE_SERVO (1) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_SDCARD (0) +#define MICROPY_HW_ENABLE_MMCARD (0) + +// board HSE is 16MHz, run SYS at 96 MHz +// board is 3.3V powered, 75 to 100 MHz: 3 wait states +#define MICROPY_HW_CLK_PLLM (16) +#define MICROPY_HW_CLK_PLLN (192) +#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2) +#define MICROPY_HW_CLK_PLLQ (4) +#define MICROPY_HW_CLK_LAST_FREQ (1) +#define MICROPY_HW_CLK_AHB_DIV (RCC_SYSCLK_DIV1) +#define MICROPY_HW_CLK_APB1_DIV (RCC_HCLK_DIV2) +#define MICROPY_HW_CLK_APB2_DIV (RCC_HCLK_DIV1) +#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_3 + +// board haves 32kHz crystal +#define MICROPY_HW_RTC_USE_LSE (1) +#define MICROPY_HW_RTC_USE_US (1) +#define MICROPY_HW_RTC_USE_CALOUT (0) + + +// 8MBit external QSPI flash +#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (23) +#define MICROPY_HW_QSPIFLASH_CS (pin_B6) +#define MICROPY_HW_QSPIFLASH_SCK (pin_B2) +#define MICROPY_HW_QSPIFLASH_IO0 (pin_C9) +#define MICROPY_HW_QSPIFLASH_IO1 (pin_C10) +#define MICROPY_HW_QSPIFLASH_IO2 (pin_C8) +#define MICROPY_HW_QSPIFLASH_IO3 (pin_A1) + +// ROMFS config +#define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_QSPI (1) +#define MICROPY_HW_ROMFS_QSPI_SPIFLASH_OBJ (&spi_bdev.spiflash) +#define MICROPY_HW_ROMFS_ENABLE_PART0 (1) + +// SPI flash, block device config (when used as the filesystem) +extern const struct _mp_spiflash_config_t spiflash_config; +extern struct _spi_bdev_t spi_bdev; + +#if !USE_QSPI_XIP +#define MICROPY_HW_SPIFLASH_ENABLE_CACHE (1) +#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev) +#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config) +#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES ((1 << MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2) / 8) +#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol +#endif + +// UART config +#define MICROPY_HW_UART1_NAME "X" +#define MICROPY_HW_UART1_TX (pin_A15) +#define MICROPY_HW_UART1_RX (pin_A10) +#define MICROPY_HW_UART2_NAME "M" +#define MICROPY_HW_UART2_TX (pin_A2) +#define MICROPY_HW_UART2_RX (pin_A3) + + +// I2C buses +// Requires support for FMPI2C on STM32F4xx +// #define MICROPY_HW_I2C4_NAME "X" +// #define MICROPY_HW_I2C4_SCL (pin_B15) +// #define MICROPY_HW_I2C4_SDA (pin_B14) +// #define MICROPY_HW_I2C4_SMB (pin_B13) + +// CAN buse +#define MICROPY_HW_CAN1_NAME "X" +#define MICROPY_HW_CAN1_TX (pin_B9) +#define MICROPY_HW_CAN1_RX (pin_B8) + +// SPI buses +#define MICROPY_HW_SPI1_NAME "X" +#define MICROPY_HW_SPI1_NSS (pin_A4) +#define MICROPY_HW_SPI1_SCK (pin_B3) +#define MICROPY_HW_SPI1_MISO (pin_B4) +#define MICROPY_HW_SPI1_MOSI (pin_B5) + +// USRSW has external pullup, and pressing the switch makes the input go low +#define MICROPY_HW_USRSW_PIN (pin_B12) +#define MICROPY_HW_USRSW_PULL (GPIO_PULLUP) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// The board has 2 LEDs, LED1 & LED2 as fusionned +#define MICROPY_HW_LED1 (pin_A13) // RED legacy +#define MICROPY_HW_LED2 (pin_A13) // GREEN legacy +#define MICROPY_HW_LED3 (pin_A14) // YELLOW lecacy +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin)) +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin)) + +// USB config +#define MICROPY_HW_USB_FS (1) +#define MICROPY_HW_FLASH_FS_LABEL "pymate_io" + +/******************************************************************************/ +// Mboot bootloader configuration : only for QSPI version +// else STM32 rom based bootloader with BOOT0 trigger at reset need to be used + +#if 0 +#define MBOOT_SPIFLASH_ADDR (0x90000000) +#define MBOOT_SPIFLASH_BYTE_SIZE (1024 * 1024) +#define MBOOT_SPIFLASH_LAYOUT "/0x90000000/256*4Kg" +#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1) +#define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash) +#define MBOOT_SPIFLASH_CONFIG (&spiflash_config) + +#define MBOOT_USB_AUTODETECT_PORT (1) +#define MBOOT_FSLOAD (1) +#define MBOOT_VFS_LFS2 (1) + +#define MBOOT_BOOTPIN_PIN (pin_B12) +#define MBOOT_BOOTPIN_PULL (MP_HAL_PIN_PULL_UP) +#define MBOOT_BOOTPIN_ACTIVE (0) + +#define MBOOT_I2C_PERIPH_ID 1 +#define MBOOT_I2C_SCL (pin_B8) +#define MBOOT_I2C_SDA (pin_B9) +#define MBOOT_I2C_ALTFUNC (4) + +#define MBOOT_BOARD_EARLY_INIT(initial_r0) mboot_board_early_init() +void mboot_board_early_init(void); +#endif diff --git a/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/mpconfigboard.mk b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/mpconfigboard.mk new file mode 100644 index 00000000000..638a040c65d --- /dev/null +++ b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/mpconfigboard.mk @@ -0,0 +1,19 @@ +# MCU settings +MCU_SERIES = f4 +CMSIS_MCU = STM32F412Rx +MICROPY_FLOAT_IMPL = single +AF_FILE = boards/stm32f412_af.csv +LD_FILES = boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/f412_qspi.ld boards/common_bl.ld +TEXT0_ADDR = 0x08000000 +TEXT0_SECTIONS = .isr_vector .text .data .ARM + +# MicroPython settings +MICROPY_VFS_LFS2 = 1 + +#I2C4 needs fmpi2c +SRC_HAL += $(STM32LIB_HAL_BASE)/Src/stm32f4xx_hal_fmpi2c.c + +# wiznet5k module for ethernet support; valid values are: +# 0 : no Wiznet support +# 5500 : support for W5500 module +MICROPY_PY_NETWORK_WIZNET5K = 5500 diff --git a/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/pins.csv b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/pins.csv new file mode 100644 index 00000000000..a16a393f97a --- /dev/null +++ b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/pins.csv @@ -0,0 +1,45 @@ +In1,PA0 +In2,PC4 +In3,PB0 +In4,PB1 +In5,PC0 +In6,PC1 +In7,PC2 +In8,PC3 +Out1,PA7 +Out2,PA6 +Out3,PC6 +Out4,PC7 +Out5,PA8 +Out6,PA9 +Out7,PB7 +Out8,PD2 +MES_VIN,PA5 +USER_SW,PB12 +LED_1,PA13 +LED_2,PA14 +USB_DM,PA11 +USB_DP,PA12 +UART1_TX,PA15 +UART1_RX,PA10 +RS422_TX,PA2 +RS422_RX,PA3 +RS422_MODE,PC12 +CAN1_RX,PB8 +CAN1_TX,PB9 +CAN1_SB,PC11 +I2C4_SMB,PB13 +I2C4_SDA,PB14 +I2C4_SCL,PB15 +UART3_TX,PB10 +UART3_RX,PC5 +SPI1_MOSI,PB5 +SPI1_MISO,PB4 +SPI1_SCLK,PB3 +SPI1_NSS,PA4 +QSPI1_D0,PC9 +QSPI1_D1,PC10 +QSPI1_D2,PC8 +QSPI1_D3,PA1 +QSPI1_CS,PB6 +QSPI1_CLK,PB2 diff --git a/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/stm32f4xx_hal_conf.h b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/stm32f4xx_hal_conf.h new file mode 100644 index 00000000000..dfa27200eca --- /dev/null +++ b/ports/stm32/boards/GARATRONIC_PYMATE_CORE8ADI8DOSC/stm32f4xx_hal_conf.h @@ -0,0 +1,22 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2019 Damien P. George + */ +#ifndef MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H +#define MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H + +#define HAL_FMPI2C_MODULE_ENABLED + +// Oscillator values in Hz +#define HSE_VALUE (16000000) +#define LSE_VALUE (32768) +#define EXTERNAL_CLOCK_VALUE (12288000) + +// Oscillator timeouts in ms +#define HSE_STARTUP_TIMEOUT (100) +#define LSE_STARTUP_TIMEOUT (5000) + +#include "boards/stm32f4xx_hal_conf_base.h" +#include "stm32f4xx_hal_fmpi2c.h" + +#endif // MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H From 6bde1b58a722ebf0aec33042029286ae11f4e18f Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 12 Aug 2026 12:45:17 +1000 Subject: [PATCH 601/635] shared/tinyusb: Use new static config for TX persistence. The runtime config was replaced with simpler static macro config in TinyUSB commit 222af862aa2b3898980e3ed8f28e70fe6c9a7ee9. Signed-off-by: Damien George --- shared/tinyusb/mp_usbd.h | 8 -------- shared/tinyusb/tusb_config.h | 1 + 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/shared/tinyusb/mp_usbd.h b/shared/tinyusb/mp_usbd.h index c455f0bc343..51209947e34 100644 --- a/shared/tinyusb/mp_usbd.h +++ b/shared/tinyusb/mp_usbd.h @@ -64,14 +64,6 @@ // Initialise TinyUSB device. static inline void mp_usbd_init_tud(void) { tusb_init(); - #if MICROPY_HW_USB_CDC - tud_cdc_configure_t cfg = { - .rx_persistent = 0, - .tx_persistent = 1, - .tx_overwritabe_if_not_connected = 1, - }; - tud_cdc_configure(&cfg); - #endif } // Run the TinyUSB device task diff --git a/shared/tinyusb/tusb_config.h b/shared/tinyusb/tusb_config.h index 8abd021548d..521bdfa838d 100644 --- a/shared/tinyusb/tusb_config.h +++ b/shared/tinyusb/tusb_config.h @@ -83,6 +83,7 @@ #ifndef CFG_TUD_CDC_TX_BUFSIZE #define CFG_TUD_CDC_TX_BUFSIZE ((CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED) ? 512 : 256) #endif +#define CFG_TUD_CDC_TX_PERSISTENT (1) #endif // CFG_TUD_CDC // MSC Configuration From 791ba6ea37cd1f07b7bb10dcb22d20a1713272d8 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 12 Aug 2026 15:13:55 +1000 Subject: [PATCH 602/635] lib/tinyusb: Update tinyusb submodule to MicroPython's fork. With a patch to fix the CDC TX persistence issue. Signed-off-by: Damien George --- .gitmodules | 2 +- lib/tinyusb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index a7dc79c2c18..425bf7fd333 100644 --- a/.gitmodules +++ b/.gitmodules @@ -26,7 +26,7 @@ branch = circuitpython [submodule "lib/tinyusb"] path = lib/tinyusb - url = https://github.com/hathach/tinyusb + url = https://github.com/micropython/tinyusb.git [submodule "lib/mynewt-nimble"] path = lib/mynewt-nimble url = https://github.com/micropython/mynewt-nimble.git diff --git a/lib/tinyusb b/lib/tinyusb index dae3f9a366b..b549ac1d84c 160000 --- a/lib/tinyusb +++ b/lib/tinyusb @@ -1 +1 @@ -Subproject commit dae3f9a366bfcddbf9dcf1b48d7500286a849539 +Subproject commit b549ac1d84cbbe550c9590951e2290098b3fb16c From 2e3304a128b3166d48d6877f4e5c9fbd2e48122f Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 7 Aug 2026 13:20:52 +1000 Subject: [PATCH 603/635] shared/runtime/pyexec: Don't execute empty line in event driven REPL. Commit 617c7dba3b7163996ff49f99839f40041d76591a exposed a bug in the event driven REPL code: an empty input line (user pressing enter without entering anything else) would pass a zero-length string to `parse_compile_execute()` and this is not valid input to `mp_lexer_new_from_str_len()`, which requires at least one character in the input string. Fix that by restarting the input REPL state machine when nothing is entered. This follows how the non-event-driver REPL code works. Fixes issue #19583. Signed-off-by: Damien George --- shared/runtime/pyexec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/shared/runtime/pyexec.c b/shared/runtime/pyexec.c index 112ae8761b4..bbb85543c11 100644 --- a/shared/runtime/pyexec.c +++ b/shared/runtime/pyexec.c @@ -470,6 +470,8 @@ static int pyexec_friendly_repl_process_char(int c) { vstr_reset(MP_STATE_VM(repl_line)); repl.paste_mode = true; return 0; + } else if (vstr_len(MP_STATE_VM(repl_line)) == 0) { + goto input_restart; } if (ret < 0) { From 60c81a08a75d4ed10a2c3be9c8a4837dbda37234 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 4 Aug 2026 23:44:16 +1000 Subject: [PATCH 604/635] alif/modmachine: Reserve 16 bytes of backup SRAM for system use. Signed-off-by: Damien George --- docs/library/machine.rst | 2 +- ports/alif/machine_mem_backup.c | 6 ++---- ports/alif/modmachine.h | 6 ++++++ 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/docs/library/machine.rst b/docs/library/machine.rst index 557224c5078..6389b3f0883 100644 --- a/docs/library/machine.rst +++ b/docs/library/machine.rst @@ -111,7 +111,7 @@ To always read a positive integer ====== =============================================== =========== ============== Port Backing storage Total bytes Battery-backed ====== =============================================== =========== ============== - alif Backup SRAM 4096 yes + alif Backup SRAM 4080 yes esp32 RTC slow memory 2048 no mimxrt SNVS LPGPR registers (4 per chip) 12-16 yes nrf POWER GPREGRET registers 1-2 no diff --git a/ports/alif/machine_mem_backup.c b/ports/alif/machine_mem_backup.c index e4cb92bb7c9..e2f4ac62c1c 100644 --- a/ports/alif/machine_mem_backup.c +++ b/ports/alif/machine_mem_backup.c @@ -27,10 +27,8 @@ // This file is never compiled standalone, it's included directly from // extmod/machine_mem.c via MICROPY_PY_MACHINE_MEM_BACKUP_INCLUDEFILE. -// Backup SRAM is in peripheral space; word writes only. No CMSIS macro exists. -#define ALIF_BACKUP_SRAM_BASE (0x4902C000U) -#define ALIF_BACKUP_SRAM_BYTES (4096U) +#include "modmachine.h" static const mp_obj_array_t machine_mem_backup_regions[] = { - BACKUP_MV('I', ALIF_BACKUP_SRAM_BYTES / 4, (void *)ALIF_BACKUP_SRAM_BASE), + BACKUP_MV('I', MP_BACKUP_SRAM_BYTES / 4, (void *)MP_BACKUP_SRAM_BASE), }; diff --git a/ports/alif/modmachine.h b/ports/alif/modmachine.h index 3d59199d332..c7ce5c1ceb7 100644 --- a/ports/alif/modmachine.h +++ b/ports/alif/modmachine.h @@ -26,6 +26,12 @@ #ifndef MICROPY_INCLUDED_ALIF_MODMACHINE_H #define MICROPY_INCLUDED_ALIF_MODMACHINE_H +// Backup SRAM is in peripheral space; word writes only. No CMSIS macro exists. +// 16 bytes are reserved for MicroPython alif system use. +#define MP_BACKUP_SRAM_BASE (0x4902C000U) +#define MP_BACKUP_SRAM_BYTES (4096U - 16U) +#define MP_BACKUP_STATE_BASE (0x4902C000U + MP_BACKUP_SRAM_BYTES) + void machine_rtc_init(void); void machine_rtc_set_wakeup(uint32_t seconds); void machine_rtc_cancel_wakeup(void); From 1f042fdd6ae2f7701c4aefb0f0f226f74b2f14d3 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 4 Aug 2026 23:44:45 +1000 Subject: [PATCH 605/635] alif/modmachine: Implement the 5 states of machine.reset_cause. Signed-off-by: Damien George --- ports/alif/machine_wdt.c | 2 ++ ports/alif/main.c | 2 ++ ports/alif/modmachine.c | 55 ++++++++++++++++++++++++++++++++++++---- ports/alif/modmachine.h | 4 +++ 4 files changed, 58 insertions(+), 5 deletions(-) diff --git a/ports/alif/machine_wdt.c b/ports/alif/machine_wdt.c index 2b8c18792d2..55fcbe4933c 100644 --- a/ports/alif/machine_wdt.c +++ b/ports/alif/machine_wdt.c @@ -30,6 +30,7 @@ #include "cgu_ext.h" #include "wdt.h" #include "se_services.h" +#include "modmachine.h" #if CORE_M55_HP #define WDT_CTRL (WDT_CTRL_Type *)(WDT_HP_CTRL_BASE) @@ -50,6 +51,7 @@ static machine_wdt_obj_t machine_wdt = {{&machine_wdt_type}, 0}; void NMI_Handler(void) { wdt_unlock(WDT_CTRL); wdt_stop(WDT_CTRL); + machine_set_wdt_reset(); se_services_reset_soc(); } diff --git a/ports/alif/main.c b/ports/alif/main.c index 5f986842173..9357b3f44d3 100644 --- a/ports/alif/main.c +++ b/ports/alif/main.c @@ -82,6 +82,7 @@ int main(void) { MICROPY_BOARD_EARLY_INIT(); lptimer_init(); + machine_init(); machine_rtc_init(); #if MICROPY_HW_ENABLE_UART_REPL @@ -179,6 +180,7 @@ int main(void) { soft_timer_deinit(); machine_pwm_deinit_all(); machine_pin_irq_deinit(); + machine_set_soft_reset(); gc_sweep_all(); mp_deinit(); } diff --git a/ports/alif/modmachine.c b/ports/alif/modmachine.c index 950c5da1bc4..5a379fbcfb4 100644 --- a/ports/alif/modmachine.c +++ b/ports/alif/modmachine.c @@ -32,12 +32,54 @@ #include "se_services.h" #include "tusb.h" +// Use 4 bytes of backup SRAM to store the reset cause state. +// Note that this will be reset to a random value upon power on. +#define RESET_CAUSE_STATE_PTR ((uint32_t *)MP_BACKUP_STATE_BASE) +#define RESET_CAUSE_VALID_MASK (0xfffffff0) +#define RESET_CAUSE_VALID (0xa170) + extern void dcd_uninit(void); #define MICROPY_PY_MACHINE_EXTRA_GLOBALS \ { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&machine_pin_type) }, \ { MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&machine_timer_type) }, \ { MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&machine_rtc_type) }, \ + \ + { MP_ROM_QSTR(MP_QSTR_PWRON_RESET), MP_ROM_INT(MACHINE_RESET_PWRON) }, \ + { MP_ROM_QSTR(MP_QSTR_HARD_RESET), MP_ROM_INT(MACHINE_RESET_HARD) }, \ + { MP_ROM_QSTR(MP_QSTR_WDT_RESET), MP_ROM_INT(MACHINE_RESET_WDT) }, \ + { MP_ROM_QSTR(MP_QSTR_DEEPSLEEP_RESET), MP_ROM_INT(MACHINE_RESET_DEEPSLEEP) }, \ + { MP_ROM_QSTR(MP_QSTR_SOFT_RESET), MP_ROM_INT(MACHINE_RESET_SOFT) }, \ + +enum { + MACHINE_RESET_PWRON = 1, + MACHINE_RESET_HARD, + MACHINE_RESET_WDT, + MACHINE_RESET_DEEPSLEEP, + MACHINE_RESET_SOFT, +}; + +static uint8_t reset_cause; + +void machine_init(void) { + // Get the current reset cause. + if ((*RESET_CAUSE_STATE_PTR & RESET_CAUSE_VALID_MASK) == RESET_CAUSE_VALID) { + reset_cause = *RESET_CAUSE_STATE_PTR & 0xf; + } else { + reset_cause = MACHINE_RESET_PWRON; + } + + // Set the reset cause state in case there is a spontaneous hard reset. + *RESET_CAUSE_STATE_PTR = RESET_CAUSE_VALID | MACHINE_RESET_HARD; +} + +void machine_set_wdt_reset(void) { + *RESET_CAUSE_STATE_PTR = RESET_CAUSE_VALID | MACHINE_RESET_WDT; +} + +void machine_set_soft_reset(void) { + reset_cause = MACHINE_RESET_SOFT; +} static void mp_machine_idle(void) { mp_event_wait_indefinite(); @@ -50,9 +92,14 @@ static mp_obj_t mp_machine_unique_id(void) { } MP_NORETURN static void mp_machine_reset(void) { + *RESET_CAUSE_STATE_PTR = RESET_CAUSE_VALID | MACHINE_RESET_HARD; se_services_reset_soc(); } +static mp_int_t mp_machine_reset_cause(void) { + return reset_cause; +} + MP_NORETURN void mp_machine_bootloader(size_t n_args, const mp_obj_t *args) { __disable_irq(); @@ -63,11 +110,6 @@ MP_NORETURN void mp_machine_bootloader(size_t n_args, const mp_obj_t *args) { } } -static mp_int_t mp_machine_reset_cause(void) { - // TODO - return 0; -} - static mp_obj_t mp_machine_get_freq(void) { return MP_OBJ_NEW_SMALL_INT(SystemCoreClock); } @@ -164,6 +206,9 @@ MP_NORETURN static void mp_machine_deepsleep(size_t n_args, const mp_obj_t *args mp_machine_config_wakeup(sleep_ms, true); + // Set the reset cause for when the device wakes up. + *RESET_CAUSE_STATE_PTR = RESET_CAUSE_VALID | MACHINE_RESET_DEEPSLEEP; + // If power is removed from the subsystem, the function does // not return, and the CPU will reboot when/if the subsystem // is next powered up. diff --git a/ports/alif/modmachine.h b/ports/alif/modmachine.h index c7ce5c1ceb7..4487da67442 100644 --- a/ports/alif/modmachine.h +++ b/ports/alif/modmachine.h @@ -32,6 +32,10 @@ #define MP_BACKUP_SRAM_BYTES (4096U - 16U) #define MP_BACKUP_STATE_BASE (0x4902C000U + MP_BACKUP_SRAM_BYTES) +void machine_init(void); +void machine_set_wdt_reset(void); +void machine_set_soft_reset(void); + void machine_rtc_init(void); void machine_rtc_set_wakeup(uint32_t seconds); void machine_rtc_cancel_wakeup(void); From 9b2d80ccb9d9fa62058d18b645bc825e2c9a6888 Mon Sep 17 00:00:00 2001 From: Sandor Attila Gerendi Date: Sat, 13 Feb 2021 21:14:11 +0200 Subject: [PATCH 606/635] examples/rp2: Add PIO example for quadrature encoding. Example that is using StateMachine to offload quadrature encoder polling. Signed-off-by: Damien George --- examples/rp2/pio_quadrature_encoder.py | 96 ++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 examples/rp2/pio_quadrature_encoder.py diff --git a/examples/rp2/pio_quadrature_encoder.py b/examples/rp2/pio_quadrature_encoder.py new file mode 100644 index 00000000000..725a9242318 --- /dev/null +++ b/examples/rp2/pio_quadrature_encoder.py @@ -0,0 +1,96 @@ +# This implementation offloads the quadrature sensor continuous polling to the StateMachine +# pio_quadrature. pio_quadrature will detect state changes, push the values and then raise +# an interrupt that is handled by encoder_state_changed_irq_handler. +# +# encoder_state_changed_irq_handler was inspired from +# https://electronics.stackexchange.com/questions/360637/quadrature-encoder-most-efficient-software-implementation + +# ruff: noqa: F821 - @asm_pio decorator adds names to function scope + +import array +import time + +import rp2 +from machine import Pin +from rp2 import PIO, StateMachine + +state_look_up_table = array.array( + "b", + [ + # Direction = 1 + 0, # 00 to 00 + -1, # 00 to 01 + +1, # 00 to 10 + +2, # 00 to 11 + +1, # 01 to 00 + 0, # 01 to 01 + +2, # 01 to 10 + -1, # 01 to 11 + -1, # 10 to 00 + +2, # 10 to 01 + 0, # 10 to 10 + +1, # 10 to 11 + +2, # 11 to 00 + +1, # 11 to 01 + -1, # 11 to 10 + 0, # 11 to 11 + # Direction = 0 + 0, # 00 to 00 + -1, # 00 to 01 + +1, # 00 to 10 + -2, # 00 to 11 + +1, # 01 to 00 + 0, # 01 to 01 + -2, # 01 to 10 + -1, # 01 to 11 + -1, # 10 to 00 + -2, # 10 to 01 + 0, # 10 to 10 + +1, # 10 to 11 + -2, # 11 to 00 + +1, # 11 to 01 + -1, # 11 to 10 + 0, # 11 to 11 + ], +) + + +counter = 0 +direction = 0 +lut_index = 0 + + +def encoder_state_changed_irq_handler(sm): + global counter, direction, lut_index + while sm.rx_fifo(): + lut_index |= sm.get() & 3 + counter += state_look_up_table[lut_index] + if state_look_up_table[lut_index] != 0: + direction = 1 if (state_look_up_table[lut_index] > 0) else 0 + lut_index = ((lut_index << 2) & 0b1100) | (direction << 4) + + +@rp2.asm_pio() +def pio_quadrature(in_init=rp2.PIO.IN_LOW): + wrap_target() + label("again") + in_(pins, 2) + mov(x, isr) + jmp(x_not_y, "push_data") + mov(isr, null) + jmp("again") + label("push_data") + push() + irq(block, rel(0)) + mov(y, x) + wrap() + + +sm = StateMachine(0, pio_quadrature, freq=160000, in_base=Pin(2)) +sm.irq(encoder_state_changed_irq_handler) +sm.exec("set(y, 99)") # add a last value for y that would be always different then the input +sm.active(1) + +while True: + time.sleep(2) + print(counter) From 537c2db2948ba109f61674febfe3777630dc5da7 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 13 Aug 2026 14:32:15 +1000 Subject: [PATCH 607/635] tests/multi_exmod/machine_can_05: Fix test setup race. Follow-up to b35383b which fixed one test setup race, but seemed to introduce failures - at least intermittently on some stm32 test configs. Guessing at a root cause: the 100ms sleep may not have been enough for the host to always coordinate instances, in which case instance1 might start sending onto the bus before instance0. Fix is to add an explicit synchronisation point so instance1 doesn't try to send until after instance0 has definitely started "babbling". This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton --- tests/multi_extmod/machine_can_05_tx_prio_cancel.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/tests/multi_extmod/machine_can_05_tx_prio_cancel.py b/tests/multi_extmod/machine_can_05_tx_prio_cancel.py index 0c5f28c4cd7..c3f67b372df 100644 --- a/tests/multi_extmod/machine_can_05_tx_prio_cancel.py +++ b/tests/multi_extmod/machine_can_05_tx_prio_cancel.py @@ -43,6 +43,8 @@ def instance0(): # requirement) multitest.wait("instance1 ready") + bcast_countdown = 5 + # "Babble" medium priority messages onto the bus to prevent # instance1() from sending anything lower priority than this while len(recv) < ITERS: @@ -50,6 +52,12 @@ def instance0(): can.send(id, b"BABBLE", CAN.FLAG_EXT_ID) if len(recv) >= ITERS: break + if bcast_countdown > 0: + # queue some "babble" messages onto the bus before signalling to + # instance1 that it can start trying to send + bcast_countdown -= 1 + if not bcast_countdown: + multitest.broadcast("instance0 babbling") print("received", ITERS, "messages") for can_id in recv: @@ -92,7 +100,7 @@ def instance1(): # make sure instance0 can queue outgoing medium-priority # babble before we start trying to send, so we're trying to # send onto an already busy bus - time.sleep_ms(100) + multitest.wait("instance0 babbling") for i in range(ITERS): # Fill the transmit queue with low priority messages (all extended IDs) From 6adb2784b29117217ea6f330185c25d036dcd363 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sun, 26 Jul 2026 12:59:23 +0200 Subject: [PATCH 608/635] qemu/mcu/arm: Refactor Cortex-M targets linkerscript. This commit extracts the parts in common across linkerscripts targeting Cortex-M processors after being made memory section-neutral, and adapts other linkerscripts to use the shared parts. All Cortex-M linkerscripts ended up having the same sections duplicated in their respective files, but with minimum changes. With these changes a new Cortex-M target can reuse all of the shared directives, so bring-up time is reduced. Signed-off-by: Alessandro Gatti --- ports/qemu/mcu/arm/cortex-m.ld | 49 ++++++++++++++++++++++++++++++++++ ports/qemu/mcu/arm/mps2.ld | 48 +++++---------------------------- ports/qemu/mcu/arm/mps3.ld | 48 +++++---------------------------- ports/qemu/mcu/arm/nrf51.ld | 45 +++++-------------------------- ports/qemu/mcu/arm/stm32.ld | 44 +++++------------------------- 5 files changed, 73 insertions(+), 161 deletions(-) create mode 100644 ports/qemu/mcu/arm/cortex-m.ld diff --git a/ports/qemu/mcu/arm/cortex-m.ld b/ports/qemu/mcu/arm/cortex-m.ld new file mode 100644 index 00000000000..5aa5e14a4cb --- /dev/null +++ b/ports/qemu/mcu/arm/cortex-m.ld @@ -0,0 +1,49 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2018 Damien P. George + */ + +SECTIONS +{ + .isr_vector : { + . = ALIGN(4); + KEEP(*(.isr_vector)) + . = ALIGN(4); + } > ISR + + .text : { + . = ALIGN(4); + *(.text*) + *(.rodata*) + . = ALIGN(4); + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + __exidx_end = .; + . = ALIGN(4); + _etext = .; + _sidata = _etext; + } > TEXT + + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; + *(.data*) + . = ALIGN(4); + _edata = .; + } > DATA + + .bss : + { + . = ALIGN(4); + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } > BSS +} diff --git a/ports/qemu/mcu/arm/mps2.ld b/ports/qemu/mcu/arm/mps2.ld index a26a3dcb3f4..e528f001767 100644 --- a/ports/qemu/mcu/arm/mps2.ld +++ b/ports/qemu/mcu/arm/mps2.ld @@ -8,47 +8,11 @@ MEMORY RAM : ORIGIN = 0x00000000, LENGTH = 4M } -_estack = ORIGIN(RAM) + LENGTH(RAM); - -SECTIONS -{ - .text : { - . = ALIGN(4); - KEEP(*(.isr_vector)) - *(.text*) - *(.rodata*) - . = ALIGN(4); - _etext = .; - } > RAM +REGION_ALIAS("ISR", RAM) +REGION_ALIAS("TEXT", RAM) +REGION_ALIAS("DATA", RAM) +REGION_ALIAS("BSS", RAM) - .ARM.exidx : AT ( _etext ) { - . = ALIGN(4); - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - *(.gnu.linkonce.armexidx.*) - __exidx_end = .; - _sidata = __exidx_end; - } > RAM - - .data : AT ( _sidata ) - { - . = ALIGN(4); - _sdata = .; - *(.data*) - . = ALIGN(4); - _edata = .; - } >RAM +_estack = ORIGIN(RAM) + LENGTH(RAM); - .bss : - { - . = ALIGN(4); - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >RAM -} +INCLUDE "mcu/arm/cortex-m.ld" diff --git a/ports/qemu/mcu/arm/mps3.ld b/ports/qemu/mcu/arm/mps3.ld index 545181e9b25..282927dce7a 100644 --- a/ports/qemu/mcu/arm/mps3.ld +++ b/ports/qemu/mcu/arm/mps3.ld @@ -9,47 +9,11 @@ MEMORY RAM : ORIGIN = 0x01000000, LENGTH = 2M } -_estack = ORIGIN(RAM) + LENGTH(RAM); - -SECTIONS -{ - .isr_vector : { - KEEP(*(.isr_vector)) - . = ALIGN(4); - } > ITCM +REGION_ALIAS("ISR", ITCM) +REGION_ALIAS("TEXT", RAM) +REGION_ALIAS("DATA", RAM) +REGION_ALIAS("BSS", RAM) - .text : { - *(.text*) - *(.rodata*) - . = ALIGN(4); - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - *(.gnu.linkonce.armexidx.*) - __exidx_end = .; - . = ALIGN(4); - _etext = .; - _sidata = _etext; - } > RAM - - .data : AT ( _sidata ) - { - . = ALIGN(4); - _sdata = .; - *(.data*) - . = ALIGN(4); - _edata = .; - } >RAM +_estack = ORIGIN(RAM) + LENGTH(RAM); - .bss : - { - . = ALIGN(4); - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >RAM -} +INCLUDE "mcu/arm/cortex-m.ld" diff --git a/ports/qemu/mcu/arm/nrf51.ld b/ports/qemu/mcu/arm/nrf51.ld index 2232e165194..37a150a0633 100644 --- a/ports/qemu/mcu/arm/nrf51.ld +++ b/ports/qemu/mcu/arm/nrf51.ld @@ -9,44 +9,11 @@ MEMORY RAM : ORIGIN = 0x20000000, LENGTH = 256K } -_estack = ORIGIN(RAM) + LENGTH(RAM); - -SECTIONS -{ - .text : { - . = ALIGN(4); - KEEP(*(.isr_vector)) - *(.text*) - *(.rodata*) - . = ALIGN(4); - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - *(.gnu.linkonce.armexidx.*) - __exidx_end = .; - . = ALIGN(4); - _etext = .; - _sidata = _etext; - } > ROM +REGION_ALIAS("ISR", ROM) +REGION_ALIAS("TEXT", ROM) +REGION_ALIAS("DATA", RAM) +REGION_ALIAS("BSS", RAM) - .data : AT ( _sidata ) - { - . = ALIGN(4); - _sdata = .; - *(.data*) - . = ALIGN(4); - _edata = .; - } >RAM +_estack = ORIGIN(RAM) + LENGTH(RAM); - .bss : - { - . = ALIGN(4); - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >RAM -} +INCLUDE "mcu/arm/cortex-m.ld" diff --git a/ports/qemu/mcu/arm/stm32.ld b/ports/qemu/mcu/arm/stm32.ld index b19edf73031..d1fbdd9ceea 100644 --- a/ports/qemu/mcu/arm/stm32.ld +++ b/ports/qemu/mcu/arm/stm32.ld @@ -9,43 +9,11 @@ MEMORY RAM : ORIGIN = 0x20000000, LENGTH = 128K } -_estack = ORIGIN(RAM) + LENGTH(RAM); - -SECTIONS -{ - .text : { - . = ALIGN(4); - KEEP(*(.isr_vector)) - *(.text*) - *(.rodata*) - . = ALIGN(4); - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - __exidx_start = .; - *(.ARM.exidx*) - *(.gnu.linkonce.armexidx.*) - __exidx_end = .; - . = ALIGN(4); - _etext = .; - _sidata = _etext; - } > ROM +REGION_ALIAS("ISR", ROM) +REGION_ALIAS("TEXT", ROM) +REGION_ALIAS("DATA", RAM) +REGION_ALIAS("BSS", RAM) - .data : AT ( _sidata ) - { - . = ALIGN(4); - _sdata = .; - *(.data*) - . = ALIGN(4); - _edata = .; - } >RAM +_estack = ORIGIN(RAM) + LENGTH(RAM); - .bss : - { - . = ALIGN(4); - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >RAM -} +INCLUDE "mcu/arm/cortex-m.ld" From 61e751f04b06b278eaf40a8c67213181de5740fb Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sun, 26 Jul 2026 13:03:24 +0200 Subject: [PATCH 609/635] qemu/mcu/riscv: Refactor RISC-V targets linkerscript. This commit extracts the parts in common across linkerscripts targeting RISC-V processors for QEMU's VIRT target after being made register size independent, and adapts other linkerscripts to use the shared parts. All RISC-V linkerscripts present in this port ended up having the same sections duplicated in their respective files, but with minimum changes. With these changes a new RISC-V target can reuse all of the shared directives, so bring-up time is reduced. Signed-off-by: Alessandro Gatti --- ports/qemu/mcu/riscv/virt.ld | 76 ++++++++++++++++++++++++++++++++++++ ports/qemu/mcu/rv32/virt.ld | 51 +----------------------- ports/qemu/mcu/rv64/virt.ld | 51 +----------------------- 3 files changed, 80 insertions(+), 98 deletions(-) create mode 100644 ports/qemu/mcu/riscv/virt.ld diff --git a/ports/qemu/mcu/riscv/virt.ld b/ports/qemu/mcu/riscv/virt.ld new file mode 100644 index 00000000000..eb0bf65bc54 --- /dev/null +++ b/ports/qemu/mcu/riscv/virt.ld @@ -0,0 +1,76 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2023 Alessandro Gatti + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +SECTIONS +{ + /* Code + Read-Only data segment */ + + .text : ALIGN (4K) + { + *(.start) + *(.text) + . = ALIGN (4K); + *(.rodata) + _sirodata = .; + } > ROM + + .rodata : AT (_sirodata) ALIGN (4K) + { + *(.rodata) + } > ROM + + /* Data + BSS segment */ + + .data : ALIGN (4K) + { + *(.data) + _sibss = .; + } > RAM + + .bss : AT (_sibss) ALIGN (4K) + { + /* Mark global pointer address. */ + _global_pointer = .; + + /* Mark BSS start. */ + . = . + _pointer_size; + _sbss = .; + *(.bss) + /* Mark BSS end. */ + _ebss = .; + } > RAM + + /* Isolated stack segment. */ + + .stack : ALIGN(4K) + { + /* Mark stack start. */ + _sstack = .; + . = . + LENGTH(STACK); + /* Mark stack end. */ + _estack = .; + } > STACK +} diff --git a/ports/qemu/mcu/rv32/virt.ld b/ports/qemu/mcu/rv32/virt.ld index 5d625ac343f..c674756aedb 100644 --- a/ports/qemu/mcu/rv32/virt.ld +++ b/ports/qemu/mcu/rv32/virt.ld @@ -48,53 +48,6 @@ MEMORY ROMFS (xr) : ORIGIN = ORIGIN(STACK) + LENGTH(STACK), LENGTH = 4M } -SECTIONS -{ - /* Code + Read-Only data segment */ - - .text : ALIGN (4K) - { - *(.start) - *(.text) - . = ALIGN (4K); - *(.rodata) - _sirodata = .; - } > ROM - - .rodata : AT (_sirodata) ALIGN (4K) - { - *(.rodata) - } > ROM - - /* Data + BSS segment */ - - .data : ALIGN (4K) - { - *(.data) - _sibss = .; - } > RAM +_pointer_size = 4; - .bss : AT (_sibss) ALIGN (4K) - { - /* Mark global pointer address. */ - _global_pointer = .; - - /* Mark BSS start. */ - . = . + 4; - _sbss = .; - *(.bss) - /* Mark BSS end. */ - _ebss = .; - } > RAM - - /* Isolated stack segment. */ - - .stack : ALIGN(4K) - { - /* Mark stack start. */ - _sstack = .; - . = LENGTH(STACK); - /* Mark stack end. */ - _estack = .; - } > STACK -} +INCLUDE "mcu/riscv/virt.ld" diff --git a/ports/qemu/mcu/rv64/virt.ld b/ports/qemu/mcu/rv64/virt.ld index 4373be30c15..6c16f94b566 100644 --- a/ports/qemu/mcu/rv64/virt.ld +++ b/ports/qemu/mcu/rv64/virt.ld @@ -48,53 +48,6 @@ MEMORY ROMFS (xr) : ORIGIN = ORIGIN(STACK) + LENGTH(STACK), LENGTH = 4M } -SECTIONS -{ - /* Code + Read-Only data segment */ - - .text : ALIGN (4K) - { - *(.start) - *(.text) - . = ALIGN (4K); - *(.rodata) - _sirodata = .; - } > ROM - - .rodata : AT (_sirodata) ALIGN (4K) - { - *(.rodata) - } > ROM - - /* Data + BSS segment */ - - .data : ALIGN (4K) - { - *(.data) - _sibss = .; - } > RAM +_pointer_size = 8; - .bss : AT (_sibss) ALIGN (4K) - { - /* Mark global pointer address. */ - _global_pointer = .; - - /* Mark BSS start. */ - . = . + 4; - _sbss = .; - *(.bss) - /* Mark BSS end. */ - _ebss = .; - } > RAM - - /* Isolated stack segment. */ - - .stack : ALIGN(4K) - { - /* Mark stack start. */ - _sstack = .; - . = LENGTH(STACK); - /* Mark stack end. */ - _estack = .; - } > STACK -} +INCLUDE "mcu/riscv/virt.ld" From 5d0139621a6b5d604f7eb0c41d64c0609787288f Mon Sep 17 00:00:00 2001 From: "Kwabena W. Agyeman" Date: Mon, 17 Aug 2026 17:05:53 -0700 Subject: [PATCH 610/635] stm32/boards/OPENMV_N6: Add a name for the camera FSYNC pin. Name PD6 (header pin P10) FSYNC. The camera driver normally drives this pin as a trigger output, but the sensor can also be configured to output its exposure strobe on it, in which case scripts need to attach a pin interrupt to it to timestamp when the camera actually triggers. Signed-off-by: Kwabena W. Agyeman --- ports/stm32/boards/OPENMV_N6/pins.csv | 1 + 1 file changed, 1 insertion(+) diff --git a/ports/stm32/boards/OPENMV_N6/pins.csv b/ports/stm32/boards/OPENMV_N6/pins.csv index 7c36181c016..7f896fe724a 100644 --- a/ports/stm32/boards/OPENMV_N6/pins.csv +++ b/ports/stm32/boards/OPENMV_N6/pins.csv @@ -65,6 +65,7 @@ P11,PC13 ,PD3 ,PD4 ,PD5 +FSYNC,PD6 P10,PD6 SPI2_MOSI,PD7 P0,PD7 From 14ba594537b6cc811b842df7d15c31acc0e5a7ac Mon Sep 17 00:00:00 2001 From: "Kwabena W. Agyeman" Date: Mon, 17 Aug 2026 17:05:53 -0700 Subject: [PATCH 611/635] alif/boards/OPENMV_AE3: Add a name for the camera FSYNC pin. Name P13_0 FSYNC. The camera driver normally drives this pin as a trigger output, but the sensor can also be configured to output its exposure strobe on it. The pin is not externally accessible on this board, so naming it is the only way scripts can attach a pin interrupt to it to timestamp when the camera actually triggers. Signed-off-by: Kwabena W. Agyeman --- ports/alif/boards/OPENMV_AE3/pins.csv | 1 + 1 file changed, 1 insertion(+) diff --git a/ports/alif/boards/OPENMV_AE3/pins.csv b/ports/alif/boards/OPENMV_AE3/pins.csv index a507bbdfd55..7c723b8d86e 100644 --- a/ports/alif/boards/OPENMV_AE3/pins.csv +++ b/ports/alif/boards/OPENMV_AE3/pins.csv @@ -8,6 +8,7 @@ LED_GREEN,P6_3 LED_BLUE,P6_0 # Sensor interrupts +FSYNC,P13_0 IMU_INT1,P15_4 IMU_INT2,P15_5 TOF_I2C_INT,P15_6 From 7de32aa1aed87595ec399772e624e0c1f790ebd5 Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 13 Aug 2026 14:14:09 +1000 Subject: [PATCH 612/635] py/runtime: Ignore AttributeError when looking up __all__. Commit 570744d06c5ba9dba59b4c3f432ca4f0abd396b6 introduced a regression when using `from foo import *`: if the module used `__getattr__` and raised an `AttributeError` when doing `__getattr__("__all__")` then that exception would be raised up to the caller of the import, rather than being ignored. This commit fixes that by protecting the lookup of "__all__". Tests are added which makes sure the behaviour matches CPython. Fixes issue #19265. Signed-off-by: Damien George --- py/runtime.c | 3 +-- tests/import/import_star.py | 12 ++++++++++++ tests/import/pkgstar_getattr_attr_er/__init__.py | 15 +++++++++++++++ tests/import/pkgstar_getattr_value_er/__init__.py | 3 +++ 4 files changed, 31 insertions(+), 2 deletions(-) create mode 100644 tests/import/pkgstar_getattr_attr_er/__init__.py create mode 100644 tests/import/pkgstar_getattr_value_er/__init__.py diff --git a/py/runtime.c b/py/runtime.c index 173b0a4ac21..dcfb9689a70 100644 --- a/py/runtime.c +++ b/py/runtime.c @@ -1602,8 +1602,7 @@ void mp_import_all(mp_obj_t module) { mp_obj_t dest[2]; #if MICROPY_MODULE___ALL__ - - mp_load_method_maybe(module, MP_QSTR___all__, dest); + mp_load_method_protected(module, MP_QSTR___all__, dest, false); if (dest[0] != MP_OBJ_NULL) { // When __all__ is defined, we must explicitly load all specified // symbols, possibly invoking the module __getattr__ function diff --git a/tests/import/import_star.py b/tests/import/import_star.py index 2cb21b877d7..dc34577d772 100644 --- a/tests/import/import_star.py +++ b/tests/import/import_star.py @@ -57,3 +57,15 @@ print("missed detection of incorrect __all__ definition") except TypeError as er: print("TypeError triggered for bad __all__ definition") + +# 6. test when package uses __getattr__ and raises AttributeError for __getattr__("__all__") +from pkgstar_getattr_attr_er import * + +print("publicFun3" in globals()) +print(publicFun3()) + +# 7. test when package uses __getattr__ and raises ValueError for __getattr__("__all__") +try: + from pkgstar_getattr_value_er import * +except ValueError as er: + print("ValueError triggered with args", er.args) diff --git a/tests/import/pkgstar_getattr_attr_er/__init__.py b/tests/import/pkgstar_getattr_attr_er/__init__.py new file mode 100644 index 00000000000..123463d3cd6 --- /dev/null +++ b/tests/import/pkgstar_getattr_attr_er/__init__.py @@ -0,0 +1,15 @@ +_print_msg = True + + +def publicFun3(): + return 3 + + +def __getattr__(attr): + global _print_msg + if _print_msg: + # CPython calls __getattr__("__all__") twice, but MicroPython only once. + # To make the output match, only print the message once. + print("__getattr__", attr) + _print_msg = False + raise AttributeError(attr) diff --git a/tests/import/pkgstar_getattr_value_er/__init__.py b/tests/import/pkgstar_getattr_value_er/__init__.py new file mode 100644 index 00000000000..43d6cdf250f --- /dev/null +++ b/tests/import/pkgstar_getattr_value_er/__init__.py @@ -0,0 +1,3 @@ +def __getattr__(attr): + print("__getattr__", attr) + raise ValueError(attr) From 5d68d7043732c644e42194c241844d8eac961dc0 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 17 Aug 2026 22:57:22 +1000 Subject: [PATCH 613/635] tests/extmod/vfs_basic.py: Tweak test to support namedtuple stat result. CPython specifies the return of `os.stat()` as a `os.stat_result` instance, but MicroPython allows a 10-tuple for simplicity. The latest version of micropython-lib's `os` extension module now returns a `namedtuple` for `os.stat()`. Update the vfs test to accommodate both a 10-tuple and a `namedtuple`. Signed-off-by: Damien George --- tests/extmod/vfs_basic.py | 8 ++++---- tests/extmod/vfs_basic.py.exp | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/extmod/vfs_basic.py b/tests/extmod/vfs_basic.py index 09fe5dce022..e88df1a776d 100644 --- a/tests/extmod/vfs_basic.py +++ b/tests/extmod/vfs_basic.py @@ -45,7 +45,7 @@ def rmdir(self, path): def stat(self, path): print(self.id, "stat", repr(path)) - return (self.id,) + return (self.id, 0, 0, 0, 0, 0, 0, 0, 0, 0) def statvfs(self, path): print(self.id, "statvfs", repr(path)) @@ -64,7 +64,7 @@ def open(self, file, mode): vfs.umount("/" + path) # stat root dir -print(os.stat("/")) +print(tuple(os.stat("/"))) # statvfs root dir; verify that f_namemax has a sensible size print(os.statvfs("/")[9] >= 32) @@ -131,7 +131,7 @@ def open(self, file, mode): os.remove("test_file") os.rename("test_file", "test_file2") os.rmdir("test_dir") -print(os.stat("test_file")) +print(tuple(os.stat("test_file"))) print(os.statvfs("/test_mnt")) open("test_file") open("test_file", "wb") @@ -148,7 +148,7 @@ def open(self, file, mode): # root dir vfs.mount(Filesystem(3), "/") -print(os.stat("/")) +print(tuple(os.stat("/"))) print(os.statvfs("/")) print(os.listdir()) open("test") diff --git a/tests/extmod/vfs_basic.py.exp b/tests/extmod/vfs_basic.py.exp index a03176a3c44..39a16c444ee 100644 --- a/tests/extmod/vfs_basic.py.exp +++ b/tests/extmod/vfs_basic.py.exp @@ -40,7 +40,7 @@ OSError 1 rename 'test_file' 'test_file2' 1 rmdir 'test_dir' 1 stat 'test_file' -(1,) +(1, 0, 0, 0, 0, 0, 0, 0, 0, 0) 1 statvfs '/' (1,) 1 open test_file r From 0cf6f38f646a291c10df125d15396e61f773b090 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 17 Aug 2026 22:13:13 +1000 Subject: [PATCH 614/635] lib/micropython-lib: Update submodule to latest. This update to micropython-lib brings in the following changes. aioble/security: only schedule save when needed aiohttp: match response header names case-insensitively aiorepl: - fix Enter key handling in raw terminal mode - optimize sys.stdout.write calls collections-defaultdict: add items() function colorsys: add colorsys and test_colorsys from CPython copy: provide top-level documentation lora: fix CRC error IRQ bit mask for sx126x mip: add an alias for codeberg repos ntptime: use NTPv4 operator: add mul and some other operators os: provide namedtuple response for os.stat() pathlib: - fix glob/rglob to return Path objects rather than strings - add Path.expanduser() pprint: - add simple and partial implementation for depth of 1 - refactor implementation and add PrettyPrint class - implement depth recursion - add test_pprint.py - fix use of micropython.const - bump version to 0.1.0 requests: - add context manager for response object - switch to HTTP/1.1 with Content-Length and raw streaming - add support for relative redirect URLs - support unicode in json and data payloads - add support for query and anchor chars directly after domain - add tests for query and anchor in URL - add chunked response body support - test chunked response decoding - document chunked response support - match response header names case-insensitively - reuse lowerl for Content-Length matching ssd1306: add I2C protocol example for SSD1306 display uaiohttpclient: - use "utf8" encoding instead of "latin-1" - add basic test for uaiohttpclient.request umqtt.robust: - let reconnect() call the connect() method of parent class - document and add examples overriding the connect() method - ease document readability umqtt.simple: - add example for mqtt tls - close any old socket on connect - add call to main() at end of example scripts - encode subscribe Remaining Length as VBI - share subscribe/unsubscribe packet encoding - share Remaining Length VBI encoding - avoid None comparisons in _send_subunsub unittest: - remove f-strings - optimise by reusing AssertRaisesContext for assertWarns - optimise by removing support for CPython - optimise calling of _handle_test_exception - optimise by only formatting msg if needed - optimise skipUnless in terms of skipIf - optimise to only create a single nop lambda - bump minor version due to recent optimisations unix-ffi: - json: fix json.loads() of a bytes object - ffilib: extend libc versions range - signal: add alarm() and pause() functions - signal: add SIGALRM constant usb: - examples: put timeout=0 in CDCInterface constructor - usb-device-cdc: fix default timeout in CDCInterface.init() - usb-device-cdc: optimise CDCInterface constructor - usb-device-core: fix comment describing the signature of done_cb - usb-device-hid: enable configuring the bInterval on hid devices - usb-device-keyboard: add a simpler keyboard example, document releasing uuid: - provide UUID class and uuid4() implementation using os.urandom() - convert test to use unittest - use bytes.hex instead of binascii.hexlify - add UUID.bytes attribute - make UUID.__repr__ match CPython Signed-off-by: Damien George --- lib/micropython-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/micropython-lib b/lib/micropython-lib index 8380c7bb8f9..ee4bb8ff139 160000 --- a/lib/micropython-lib +++ b/lib/micropython-lib @@ -1 +1 @@ -Subproject commit 8380c7bb8f9e5e5260e9539156742925e00366b2 +Subproject commit ee4bb8ff139e24c42b739935fbd8ec7c4d061e02 From f86bd73c35790369fdf3d4d05b8f7ecf0b95c505 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 21 Jun 2025 22:44:40 +1000 Subject: [PATCH 615/635] shared/tinyusb: Add USB Network (NCM) TinyUSB integration. Adds TinyUSB configuration and descriptor support for USB Network Control Model (NCM) interface. This provides the low-level USB infrastructure needed for USB networking. Signed-off-by: Andrew Leech --- shared/tinyusb/mp_usbd.h | 9 +- shared/tinyusb/mp_usbd_descriptor.c | 16 +++- shared/tinyusb/tusb_config.h | 137 ++++++++++++++++++++-------- 3 files changed, 121 insertions(+), 41 deletions(-) diff --git a/shared/tinyusb/mp_usbd.h b/shared/tinyusb/mp_usbd.h index 51209947e34..e8a435f06e3 100644 --- a/shared/tinyusb/mp_usbd.h +++ b/shared/tinyusb/mp_usbd.h @@ -82,10 +82,11 @@ extern void mp_usbd_port_get_serial_number(char *buf); void mp_usbd_hex_str(char *out_str, const uint8_t *bytes, size_t bytes_len); // Length of built-in configuration descriptor -#define MP_USBD_BUILTIN_DESC_CFG_LEN (TUD_CONFIG_DESC_LEN + \ - (CFG_TUD_CDC ? (TUD_CDC_DESC_LEN) : 0) + \ - (CFG_TUD_MSC ? (TUD_MSC_DESC_LEN) : 0) \ - ) +#define MP_USBD_BUILTIN_DESC_CFG_LEN ( \ + (CFG_TUD_CDC ? (TUD_CDC_DESC_LEN) : 0) + \ + (CFG_TUD_MSC ? (TUD_MSC_DESC_LEN) : 0) + \ + (CFG_TUD_NCM ? (TUD_CDC_NCM_DESC_LEN) : 0) + \ + TUD_CONFIG_DESC_LEN) // Built-in USB device and configuration descriptor values extern const tusb_desc_device_t mp_usbd_builtin_desc_dev; diff --git a/shared/tinyusb/mp_usbd_descriptor.c b/shared/tinyusb/mp_usbd_descriptor.c index 0b3f5752469..f6b1fe9297d 100644 --- a/shared/tinyusb/mp_usbd_descriptor.c +++ b/shared/tinyusb/mp_usbd_descriptor.c @@ -35,6 +35,7 @@ #define USBD_CDC_CMD_MAX_SIZE (8) #define USBD_CDC_IN_OUT_MAX_SIZE ((CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED) ? 512 : 64) #define USBD_MSC_IN_OUT_MAX_SIZE ((CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED) ? 512 : 64) +#define USBD_NCM_IN_OUT_MAX_SIZE ((CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED) ? 512 : 64) const tusb_desc_device_t mp_usbd_builtin_desc_dev = { .bLength = sizeof(tusb_desc_device_t), @@ -77,7 +78,11 @@ const uint8_t mp_usbd_builtin_desc_cfg[MP_USBD_BUILTIN_DESC_CFG_LEN] = { USBD_CDC_CMD_MAX_SIZE, USBD_CDC_EP_OUT, USBD_CDC_EP_IN, USBD_CDC_IN_OUT_MAX_SIZE), #endif #if CFG_TUD_MSC - TUD_MSC_DESCRIPTOR(USBD_ITF_MSC, USBD_STR_MSC, EPNUM_MSC_OUT, EPNUM_MSC_IN, USBD_MSC_IN_OUT_MAX_SIZE), + TUD_MSC_DESCRIPTOR(USBD_ITF_MSC, USBD_STR_MSC, USBD_MSC_EP_OUT, USBD_MSC_EP_IN, USBD_MSC_IN_OUT_MAX_SIZE), + #endif + #if CFG_TUD_NCM + // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size, notification interval, network capabilities. + TUD_CDC_NCM_DESCRIPTOR(USBD_ITF_NCM, USBD_STR_NCM, USBD_STR_NCM_MAC, USBD_NCM_EP_CMD, 64, USBD_NCM_EP_OUT, USBD_NCM_EP_IN, USBD_NCM_IN_OUT_MAX_SIZE, CFG_TUD_NET_MTU, 50, 0), #endif }; @@ -130,6 +135,15 @@ const uint16_t *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { desc_str = MICROPY_HW_USB_MSC_INTERFACE_STRING; break; #endif + #if CFG_TUD_NCM + case USBD_STR_NCM: + desc_str = MICROPY_PY_NETWORK_USBD_NCM_INTERFACE_STRING; + break; + case USBD_STR_NCM_MAC: + mp_usbd_hex_str(serial_buf, (uint8_t *)tud_network_mac_address, sizeof(tud_network_mac_address)); + desc_str = serial_buf; + break; + #endif default: break; } diff --git a/shared/tinyusb/tusb_config.h b/shared/tinyusb/tusb_config.h index 521bdfa838d..5432b9ca22f 100644 --- a/shared/tinyusb/tusb_config.h +++ b/shared/tinyusb/tusb_config.h @@ -95,14 +95,59 @@ #define CFG_TUD_MSC_BUFSIZE (MICROPY_FATFS_MAX_SS) #endif // CFG_TUD_MSC +#if MICROPY_PY_NETWORK_USBD_NCM +// TinyUSB supports both RNDIS and NCM protocols. +// NCM is now recommended by Microsoft on Win 11 and above. +#define CFG_TUD_NCM (1) + +// NCM TinyUSB buffer configuration. +// These depend on lwIP parameters (TCP_MSS, LWIP_MDNS_RESPONDER); lwipopts.h +// is safe to include here because MICROPY_PY_NETWORK_USBD_NCM implies LWIP. +#include "lwipopts.h" + +// Must be >> MTU; can be set to 2048 without impact. +#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE +#define CFG_TUD_NCM_IN_NTB_MAX_SIZE ((2 + LWIP_MDNS_RESPONDER) * TCP_MSS + 100) +#endif +#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE +#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE ((2 + LWIP_MDNS_RESPONDER) * TCP_MSS + 100) +#endif + +// Number of NCM transfer blocks for reception side. +#ifndef CFG_TUD_NCM_OUT_NTB_N +#define CFG_TUD_NCM_OUT_NTB_N 1 +#endif +// Number of NCM transfer blocks for transmission side. +#ifndef CFG_TUD_NCM_IN_NTB_N +#define CFG_TUD_NCM_IN_NTB_N (2 + LWIP_MDNS_RESPONDER) +#endif + +#ifndef MICROPY_PY_NETWORK_USBD_NCM_INTERFACE_STRING +#define MICROPY_PY_NETWORK_USBD_NCM_INTERFACE_STRING "Board NET" +#endif +#endif // MICROPY_PY_NETWORK_USBD_NCM + // Define built-in interface, string and endpoint numbering based on the above config -#define USBD_STR_0 (0x00) -#define USBD_STR_MANUF (0x01) -#define USBD_STR_PRODUCT (0x02) -#define USBD_STR_SERIAL (0x03) -#define USBD_STR_CDC (0x04) -#define USBD_STR_MSC (0x05) +enum _USBD_STR { + USBD_STR_0 = (0x00), + USBD_STR_MANUF = (0x01), + USBD_STR_PRODUCT = (0x02), + USBD_STR_SERIAL = (0x03), + #if CFG_TUD_CDC + USBD_STR_CDC, + #endif + #if CFG_TUD_MSC + USBD_STR_MSC, + #endif + #if CFG_TUD_NCM + USBD_STR_NCM, + USBD_STR_NCM_MAC, + #endif + // One more than the highest built-in string index; runtime device string + // indexes should start at or above this value to avoid collisions. + USBD_STR_BUILTIN_MAX, +}; #define USBD_MAX_POWER_MA (250) @@ -110,40 +155,60 @@ #define MICROPY_HW_USB_DESC_STR_MAX (40) #endif +enum _USBD_ITF { + #if CFG_TUD_CDC + USBD_ITF_CDC, + USBD_ITF_CDC_I2, + #endif // CFG_TUD_CDC + #if CFG_TUD_MSC + USBD_ITF_MSC, + #endif // CFG_TUD_MSC + #if CFG_TUD_NCM + USBD_ITF_NCM, + USBD_ITF_NCM_DATA, + #endif +}; + +enum _USBD_EP { + USBD_EP_BASE = 0x80, + #if CFG_TUD_CDC + USBD_CDC_EP_CMD, + USBD_CDC_EP_IN, + #endif // CFG_TUD_CDC + #if CFG_TUD_MSC + USBD_MSC_EP_IN, + #endif // CFG_TUD_MSC + #if CFG_TUD_NCM + USBD_NCM_EP_CMD, + USBD_NCM_EP_IN, + #endif // CFG_TUD_NCM +}; + +// define the matching in endpoints to each EP_OUT #if CFG_TUD_CDC -#define USBD_ITF_CDC (0) // needs 2 interfaces -#define USBD_CDC_EP_CMD (0x81) -#define USBD_CDC_EP_OUT (0x02) -#define USBD_CDC_EP_IN (0x82) -#endif // CFG_TUD_CDC - +#define USBD_CDC_EP_OUT (USBD_CDC_EP_IN & ~TUSB_DIR_IN_MASK) +#endif #if CFG_TUD_MSC -// Interface & Endpoint numbers for MSC come after CDC, if it is enabled -#if CFG_TUD_CDC -#define USBD_ITF_MSC (2) -#define EPNUM_MSC_OUT (0x03) -#define EPNUM_MSC_IN (0x83) -#else -#define USBD_ITF_MSC (0) -#define EPNUM_MSC_OUT (0x01) -#define EPNUM_MSC_IN (0x81) -#endif // CFG_TUD_CDC -#endif // CFG_TUD_MSC +#define USBD_MSC_EP_OUT (USBD_MSC_EP_IN & ~TUSB_DIR_IN_MASK) +#endif +#if CFG_TUD_NCM +#define USBD_NCM_EP_OUT (USBD_NCM_EP_IN & ~TUSB_DIR_IN_MASK) +#endif + /* Limits of builtin USB interfaces, endpoints, strings */ -#if CFG_TUD_MSC -#define USBD_ITF_BUILTIN_MAX (USBD_ITF_MSC + 1) -#define USBD_STR_BUILTIN_MAX (USBD_STR_MSC + 1) -#define USBD_EP_BUILTIN_MAX (EPNUM_MSC_OUT + 1) -#elif CFG_TUD_CDC -#define USBD_ITF_BUILTIN_MAX (USBD_ITF_CDC + 2) -#define USBD_STR_BUILTIN_MAX (USBD_STR_CDC + 1) -#define USBD_EP_BUILTIN_MAX (((USBD_CDC_EP_IN)&~TUSB_DIR_IN_MASK) + 1) -#else // !CFG_TUD_MSC && !CFG_TUD_CDC -#define USBD_ITF_BUILTIN_MAX (0) -#define USBD_STR_BUILTIN_MAX (0) -#define USBD_EP_BUILTIN_MAX (0) -#endif +// Number of interfaces used by all enabled classes +#define USBD_ITF_BUILTIN_MAX ( \ + (CFG_TUD_CDC ? 2 : 0) + \ + (CFG_TUD_MSC ? 1 : 0) + \ + (CFG_TUD_NCM ? 2 : 0)) + +// 1 plus the number of interfaces used by all enabled classes +#define USBD_EP_BUILTIN_MAX ( \ + (CFG_TUD_CDC ? 2 : 0) + \ + (CFG_TUD_MSC ? 1 : 0) + \ + (CFG_TUD_NCM ? 2 : 0) + \ + 1) #endif // MICROPY_HW_ENABLE_USBDEV From 1c3c201149f37fe8d81246191b3127bb198d6306 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Sat, 21 Jun 2025 22:44:55 +1000 Subject: [PATCH 616/635] extmod: Add USB Network (NCM) driver implementation. Implements a USB NCM driver providing ethernet-over-USB backed by the lwIP stack. Reuses MicroPython's string hash over the MAC address to derive a deterministic link-local IP (169.254.x.1), a built-in DHCP server so the host is immediately reachable, and full lwIP netif integration including IPv6 support. Exposes a Python network.USBD_NCM class compatible with the AbstractNIC interface. Signed-off-by: Andrew Leech --- docs/library/network.USBD_NCM.rst | 82 ++++++ docs/library/network.rst | 1 + extmod/extmod.cmake | 1 + extmod/extmod.mk | 1 + extmod/modnetwork.c | 14 ++ extmod/network_usbd_ncm.c | 400 ++++++++++++++++++++++++++++++ extmod/network_usbd_ncm.h | 40 +++ 7 files changed, 539 insertions(+) create mode 100644 docs/library/network.USBD_NCM.rst create mode 100644 extmod/network_usbd_ncm.c create mode 100644 extmod/network_usbd_ncm.h diff --git a/docs/library/network.USBD_NCM.rst b/docs/library/network.USBD_NCM.rst new file mode 100644 index 00000000000..e807f930b8c --- /dev/null +++ b/docs/library/network.USBD_NCM.rst @@ -0,0 +1,82 @@ +.. currentmodule:: network +.. _network.USBD_NCM: + +class USBD_NCM -- USB NCM network interface +=========================================== + +This class provides a network interface over USB using the NCM (Network +Control Model) protocol. The host computer sees this device as a USB +Ethernet adapter and assigns it an IP address via DHCP (served by the +MicroPython device). + +.. note:: ``network.USBD_NCM`` requires a port with TinyUSB and NCM support, + enabled at build time by defining ``MICROPY_PY_NETWORK_USBD_NCM`` + (off by default). + +Example usage:: + + import network + + nic = network.USBD_NCM() + nic.active(True) + # wait for USB host to configure the NCM interface + while not nic.isconnected(): + pass + + print(nic.ipconfig("addr4")) + +Constructors +------------ + +.. class:: USBD_NCM() + + Create and return a USBD_NCM object. This initialises the NCM network + interface if it has not already been initialised. Only one instance + exists (singleton). + +Methods +------- + +.. method:: USBD_NCM.active([is_active]) + + Activate or deactivate the network interface. Without argument returns + current state as a bool. + + The interface is brought up automatically before USB enumeration, so this + returns ``True`` from boot. + +.. method:: USBD_NCM.isconnected() + + Returns ``True`` if the USB host has configured the NCM interface, + ``False`` otherwise. + + When USB is disconnected, this returns ``False`` and network traffic + stops. The interface remains registered with lwIP and can resume when + the host reconnects and re-enumerates the device. + +.. method:: USBD_NCM.status() + + Returns the link status as an integer: ``1`` if the interface is up, + ``0`` otherwise. + +.. method:: USBD_NCM.ipconfig('param') + USBD_NCM.ipconfig(param=value, ...) + + See `AbstractNIC.ipconfig`. + +.. method:: USBD_NCM.ifconfig([(ip, subnet, gateway, dns)]) + + See `AbstractNIC.ifconfig`. + +Notes +----- + +**Link-local IP address:** The device IP (169.254.x.1) is derived +deterministically from the device MAC address. RFC 3927 ARP probe/announce +(conflict detection) is not implemented, so if two devices happen to derive +the same address on the same network segment, the conflict will go undetected. + +**MAC address uniqueness:** The device and host-side MAC addresses are derived +from the value returned by ``mp_hal_get_mac()``. If two boards have the same +hardware MAC (e.g. the port does not use a hardware UID), they will present +the same network addresses and cause ARP conflicts. diff --git a/docs/library/network.rst b/docs/library/network.rst index d05d17132dc..3da27e39b2e 100644 --- a/docs/library/network.rst +++ b/docs/library/network.rst @@ -193,6 +193,7 @@ provide a way to control networking interfaces of various kinds. network.WIZNET5K.rst network.LAN.rst network.PPP.rst + network.USBD_NCM.rst Network functions ================= diff --git a/extmod/extmod.cmake b/extmod/extmod.cmake index 40ae717a54f..32534857790 100644 --- a/extmod/extmod.cmake +++ b/extmod/extmod.cmake @@ -53,6 +53,7 @@ set(MICROPY_SOURCE_EXTMOD ${MICROPY_EXTMOD_DIR}/network_lwip.c ${MICROPY_EXTMOD_DIR}/network_ninaw10.c ${MICROPY_EXTMOD_DIR}/network_ppp_lwip.c + ${MICROPY_EXTMOD_DIR}/network_usbd_ncm.c ${MICROPY_EXTMOD_DIR}/network_wiznet5k.c ${MICROPY_EXTMOD_DIR}/os_dupterm.c ${MICROPY_EXTMOD_DIR}/vfs.c diff --git a/extmod/extmod.mk b/extmod/extmod.mk index 961699f089e..da593b02abb 100644 --- a/extmod/extmod.mk +++ b/extmod/extmod.mk @@ -56,6 +56,7 @@ SRC_EXTMOD_C += \ extmod/network_lwip.c \ extmod/network_ninaw10.c \ extmod/network_ppp_lwip.c \ + extmod/network_usbd_ncm.c \ extmod/network_wiznet5k.c \ extmod/os_dupterm.c \ extmod/vfs.c \ diff --git a/extmod/modnetwork.c b/extmod/modnetwork.c index b6855fcaaab..952632c8b95 100644 --- a/extmod/modnetwork.c +++ b/extmod/modnetwork.c @@ -55,6 +55,11 @@ extern const struct _mp_obj_type_t mod_network_nic_type_nina; extern const struct _mp_obj_type_t mod_network_esp_hosted_type; #endif +#if MICROPY_PY_NETWORK_USBD_NCM +extern const struct _mp_obj_type_t mod_network_nic_type_ncm; +#include "extmod/network_usbd_ncm.h" +#endif + #ifdef MICROPY_PY_NETWORK_INCLUDEFILE #include MICROPY_PY_NETWORK_INCLUDEFILE #endif @@ -75,6 +80,11 @@ char mod_network_hostname_data[MICROPY_PY_NETWORK_HOSTNAME_MAX_LEN + 1] = MICROP void mod_network_init(void) { mp_obj_list_init(&MP_STATE_PORT(mod_network_nic_list), 0); + #if MICROPY_PY_NETWORK_USBD_NCM + // Initialise the USB NCM netif early so it is ready when TinyUSB starts + // receiving packets during USB enumeration (before any Python code runs). + ncm_auto_init(); + #endif } void mod_network_deinit(void) { @@ -205,6 +215,10 @@ static const mp_rom_map_elem_t mp_module_network_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_WLAN), MP_ROM_PTR(&mod_network_esp_hosted_type) }, #endif + #if MICROPY_PY_NETWORK_USBD_NCM + { MP_ROM_QSTR(MP_QSTR_USBD_NCM), MP_ROM_PTR(&mod_network_nic_type_ncm) }, + #endif + // Allow a port to take mostly full control of the network module. #ifdef MICROPY_PY_NETWORK_MODULE_GLOBALS_INCLUDEFILE #include MICROPY_PY_NETWORK_MODULE_GLOBALS_INCLUDEFILE diff --git a/extmod/network_usbd_ncm.c b/extmod/network_usbd_ncm.c new file mode 100644 index 00000000000..d6ae152a8e2 --- /dev/null +++ b/extmod/network_usbd_ncm.c @@ -0,0 +1,400 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "py/mperrno.h" +#include "py/mphal.h" + +#if MICROPY_PY_NETWORK_USBD_NCM + +// Include NCM configuration (MICROPY_PY_NETWORK_USBD_NCM_DHCP_SERVER). +#include "extmod/network_usbd_ncm.h" + +#ifndef NO_QSTR +#include "tusb.h" +#endif + +#include "lwip/ethip6.h" +#include "lwip/init.h" +#include "lwip/timeouts.h" +#include "lwip/etharp.h" +#include "lwip/dns.h" +#include "lwip/dhcp.h" +#include "netif/ethernet.h" +#include "lwip/apps/mdns.h" + +#include "extmod/modnetwork.h" +#include "shared/netutils/netutils.h" +#include "shared/netutils/dhcpserver.h" + +#define error_printf(...) mp_printf(&mp_plat_print, "network_usbd_ncm: " __VA_ARGS__) + +#if LWIP_IPV6 +#define IP(x) ((x).u_addr.ip4) +#else +#define IP(x) (x) +#endif + +const mp_obj_type_t mod_network_nic_type_ncm; + +typedef struct _ncm_obj_t { + mp_obj_base_t base; + + struct netif netif; + bool init; + + ip_addr_t ipaddr; + ip_addr_t netmask; + ip_addr_t gateway; + + #if MICROPY_PY_NETWORK_USBD_NCM_DHCP_SERVER + dhcp_server_t dhcp_server; + #endif +} ncm_obj_t; + +// Global object holding the usb net state +static ncm_obj_t ncm_obj; + +static mp_sched_node_t ncm_sched_node; + +#define IS_ACTIVE(self) ((self)->netif.flags & NETIF_FLAG_UP) + +/* This default mac will be updated during init from hardware unique ID (if available) */ +/* it is suggested that the first byte is 0x02 to indicate a link-local address */ +uint8_t tud_network_mac_address[6] = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00}; + +// Derive a link-local IPv4 address (169.254.X.1) from a MAC address. +// Note: no ARP probe/announce is performed (RFC 3927 collision detection is not +// implemented). The address is deterministic; if two devices share the same MAC, +// they will get the same link-local IP and ARP conflicts will go undetected. +// Assumes mp_hal_get_mac() returns a per-device unique value. +static void generate_linklocal_ip_from_mac(const uint8_t mac_addr[6], uint8_t ip_addr[4]) { + ip_addr[0] = 169; + ip_addr[1] = 254; + ip_addr[3] = 1; + + // Reuse the core string hash (djb2, the same hash() uses on bytes) to + // spread the MAC across the third octet, with no extra code compiled in. + size_t hash = qstr_compute_hash(mac_addr, 6); + uint8_t third_octet = (uint8_t)(hash ^ (hash >> 8)); + + // Avoid .0 and .255 + if (third_octet == 0) { + third_octet = 1; + } + if (third_octet == 255) { + third_octet = 254; + } + + ip_addr[2] = third_octet; +} + +static err_t linkoutput_fn(struct netif *netif, struct pbuf *p) { + (void)netif; + if (!tud_ready() || !tud_network_can_xmit(p->tot_len)) { + // Drop the frame while the link is down or a previous transmit is + // still in flight. An error return would propagate out of + // tcp_output() to the caller of socket.send(), even though tcp_write() + // has already queued that data, so the caller would resend bytes that + // are already in the stream. Dropping leaves recovery to TCP + // retransmission, as for any other lossy link. + return ERR_OK; + } + tud_network_xmit(p, 0); + return ERR_OK; +} + +static err_t netif_init_cb(struct netif *netif) { + LWIP_ASSERT("netif != NULL", (netif != NULL)); + netif->name[0] = 'u'; // lwIP short name "un" for USB Network + netif->name[1] = 'n'; + netif->mtu = CFG_TUD_NET_MTU; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP; + netif->state = NULL; + netif->linkoutput = linkoutput_fn; + netif->output = etharp_output; + #if LWIP_IPV6 + netif->output_ip6 = ethip6_output; + netif->flags |= NETIF_FLAG_MLD6; + #endif + return ERR_OK; +} + +static void ncm_init(void) { + // Init the NCM object + ncm_obj.base.type = (mp_obj_type_t *)&mod_network_nic_type_ncm; + + struct netif *netif = &(ncm_obj.netif); + + MICROPY_PY_LWIP_ENTER + + mp_hal_get_mac(MP_HAL_MAC_ETH0, tud_network_mac_address); + tud_network_mac_address[0] = 0x02; + + netif->hwaddr_len = sizeof(tud_network_mac_address); + memcpy(netif->hwaddr, tud_network_mac_address, sizeof(tud_network_mac_address)); + + // This USB Network essentially creates a link with two interfaces, one for the + // host and another for the micropython/lwip end of the connection. + // The MAC configured above is use for one end of the link, flip a bit for the + // MAC on the other end of the link. + netif->hwaddr[5] ^= 0x01; + + // Generate unique link-local IP address from MAC address + uint8_t ip_bytes[4]; + generate_linklocal_ip_from_mac(tud_network_mac_address, ip_bytes); + + // Convert to network byte order and set IP configuration + IP(ncm_obj.ipaddr).addr = PP_HTONL(((uint32_t)ip_bytes[0] << 24) | ((uint32_t)ip_bytes[1] << 16) | ((uint32_t)ip_bytes[2] << 8) | ip_bytes[3]); + IP(ncm_obj.netmask).addr = PP_HTONL(0xFFFF0000); // 255.255.0.0 for link-local + IP(ncm_obj.gateway).addr = 0; // No gateway for link-local + + netif = netif_add( + netif, + ip_2_ip4(&ncm_obj.ipaddr), + ip_2_ip4(&ncm_obj.netmask), + ip_2_ip4(&ncm_obj.gateway), + NULL, + netif_init_cb, + ethernet_input + ); + if (netif == NULL) { + MICROPY_PY_LWIP_EXIT + mp_raise_OSError(MP_ENOMEM); + } + #if LWIP_IPV6 + netif_create_ip6_linklocal_address(netif, 1); + netif_set_ip6_autoconfig_enabled(netif, 1); + #endif + #if LWIP_NETIF_HOSTNAME + netif_set_hostname(netif, mod_network_hostname_data); + #endif + if (netif_default == NULL) { + netif_set_default(netif); + } + + #if LWIP_MDNS_RESPONDER + mdns_resp_add_netif(netif, mod_network_hostname_data); + #endif + + #if MICROPY_PY_NETWORK_USBD_NCM_DHCP_SERVER + dhcp_server_init(&ncm_obj.dhcp_server, &ncm_obj.ipaddr, &ncm_obj.netmask); + // Don't advertise a default gateway -- this is a point-to-point USB link + // and advertising a router causes the host to route all traffic over USB. + ncm_obj.dhcp_server.send_router = false; + #endif + + // register with network module + mod_network_register_nic(&ncm_obj); + ncm_obj.init = true; + + MICROPY_PY_LWIP_EXIT +} + +static void _scheduled_tud_network_recv_renew(mp_sched_node_t *node) { + (void)node; + // Release the TinyUSB receive buffer and pick up the next datagram. + tud_network_recv_renew(); +} + +bool tud_network_recv_cb(const uint8_t *src, uint16_t size) { + if (!ncm_obj.init) { + return false; + } + struct netif *netif = &(ncm_obj.netif); + bool ret = true; + if (size) { + MICROPY_PY_LWIP_ENTER + + struct pbuf *p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL); + if (p == NULL) { + MICROPY_PY_LWIP_EXIT + // Return false without calling recv_renew: TinyUSB holds the buffer. + // NCM RX will stall until the host retransmits and memory is available. + return false; + } + + // Copy buf to pbuf + pbuf_take(p, src, size); + + if (netif->input(p, netif) != ERR_OK) { + pbuf_free(p); + ret = false; + } + + MICROPY_PY_LWIP_EXIT + } + // Defer tud_network_recv_renew(): calling it here would pull the next + // datagram, and its full lwIP input path, into this USB interrupt. + mp_sched_schedule_node(&ncm_sched_node, _scheduled_tud_network_recv_renew); + return ret; +} + +uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) { + // copy from network stack packet pointer to dst. + (void)arg; + MICROPY_PY_LWIP_ENTER + struct pbuf *p = (struct pbuf *)ref; + uint16_t len = pbuf_copy_partial(p, dst, p->tot_len, 0); + MICROPY_PY_LWIP_EXIT + return len; +} + +// Set the lwIP link state and tell the host to match, so that a deactivated +// interface shows up as disconnected rather than silently discarding traffic. +static void ncm_set_link(bool up) { + if (up) { + netif_set_link_up(&ncm_obj.netif); + } else { + netif_set_link_down(&ncm_obj.netif); + } + tud_network_link_state(TUD_OPT_RHPORT, up); +} + +// Called during netd_init() for the initial link state, which TinyUSB otherwise +// defaults to up. netd_init() also runs on every bus reset, so without this the +// host would see the link come back up after a replug while the netif is down. +bool tud_network_default_link_state_cb(void) { + return !ncm_obj.init || netif_is_link_up(&ncm_obj.netif); +} + +// Called from mod_network_init() to set up the NCM netif before USB starts. +// TinyUSB's NCM driver begins receiving as soon as the host sends +// SET_INTERFACE(alt=1), which happens during USB enumeration -- before any +// Python code runs. The netif must exist by then so tud_network_recv_cb() +// can deliver packets to lwIP. +// +// The netif is intentionally kept alive across MicroPython soft reset: lwIP +// is not re-initialised on soft reset, so the netif remains valid and TinyUSB +// can continue delivering packets. On re-entry we only re-register the singleton +// with the NIC list (which mod_network_init() cleared) rather than re-running +// netif_add (which must only be called once per netif). +void ncm_auto_init(void) { + if (!ncm_obj.init) { + ncm_init(); + } else { + // On soft-reset mod_network_init() clears the NIC list, so + // re-register the (still-live) singleton. + mod_network_register_nic(&ncm_obj); + } + // Bring the interface up here rather than leaving it to active(True): lwIP + // drops inbound packets on a down netif, and the host starts DHCP as soon + // as it enumerates. As such active() reads True from boot. + netif_set_up(&ncm_obj.netif); + ncm_set_link(true); +} + +/*******************************************************************************/ +// MicroPython bindings + +// Create and return a USBD_NCM object. +static mp_obj_t ncm_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, 0, false); + if (!ncm_obj.init) { + ncm_init(); + } + // Return NCM object + return MP_OBJ_FROM_PTR(&ncm_obj); +} + +static mp_obj_t ncm_status(mp_obj_t self_in) { + ncm_obj_t *self = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_NEW_SMALL_INT(IS_ACTIVE(self) ? 1 : 0); +} +static MP_DEFINE_CONST_FUN_OBJ_1(ncm_status_obj, ncm_status); + +static mp_obj_t ncm_isconnected(mp_obj_t self_in) { + ncm_obj_t *self = MP_OBJ_TO_PTR(self_in); + return mp_obj_new_bool(tud_connected() && netif_is_link_up(&self->netif)); +} +static MP_DEFINE_CONST_FUN_OBJ_1(ncm_isconnected_obj, ncm_isconnected); + +static mp_obj_t ncm_active(size_t n_args, const mp_obj_t *args) { + ncm_obj_t *self = MP_OBJ_TO_PTR(args[0]); + if (n_args == 1) { + return mp_obj_new_bool(IS_ACTIVE(self)); + } else { + if (mp_obj_is_true(args[1])) { + if (!IS_ACTIVE(self)) { + netif_set_up(&self->netif); + ncm_set_link(true); + } + } else { + if (IS_ACTIVE(self)) { + ncm_set_link(false); + netif_set_down(&self->netif); + // Note: We don't call ncm_deinit() here because that would + // completely remove the network interface. We just want to + // deactivate it so it can be reactivated later. + } + } + return mp_const_none; + } +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(ncm_active_obj, 1, 2, ncm_active); + +static mp_obj_t ncm_ifconfig(size_t n_args, const mp_obj_t *args) { + ncm_obj_t *self = MP_OBJ_TO_PTR(args[0]); + return mod_network_nic_ifconfig(&self->netif, n_args - 1, args + 1); +} +static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(ncm_ifconfig_obj, 1, 2, ncm_ifconfig); + +static mp_obj_t ncm_ipconfig(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) { + ncm_obj_t *self = MP_OBJ_TO_PTR(args[0]); + return mod_network_nic_ipconfig(&self->netif, n_args - 1, args + 1, kwargs); +} +static MP_DEFINE_CONST_FUN_OBJ_KW(ncm_ipconfig_obj, 1, ncm_ipconfig); + +static mp_obj_t ncm_config(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) { + if (n_args == 2 && kwargs->used == 0) { + const char *key = mp_obj_str_get_str(args[1]); + if (strcmp(key, "mac") == 0) { + return mp_obj_new_bytes(tud_network_mac_address, sizeof(tud_network_mac_address)); + } + } + mp_raise_ValueError(MP_ERROR_TEXT("unknown config param")); +} +static MP_DEFINE_CONST_FUN_OBJ_KW(ncm_config_obj, 1, ncm_config); + +static const mp_rom_map_elem_t ncm_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_status), MP_ROM_PTR(&ncm_status_obj) }, + { MP_ROM_QSTR(MP_QSTR_isconnected), MP_ROM_PTR(&ncm_isconnected_obj) }, + { MP_ROM_QSTR(MP_QSTR_active), MP_ROM_PTR(&ncm_active_obj) }, + { MP_ROM_QSTR(MP_QSTR_ifconfig), MP_ROM_PTR(&ncm_ifconfig_obj) }, + { MP_ROM_QSTR(MP_QSTR_ipconfig), MP_ROM_PTR(&ncm_ipconfig_obj) }, + { MP_ROM_QSTR(MP_QSTR_config), MP_ROM_PTR(&ncm_config_obj) }, +}; +static MP_DEFINE_CONST_DICT(ncm_locals_dict, ncm_locals_dict_table); + +MP_DEFINE_CONST_OBJ_TYPE( + mod_network_nic_type_ncm, + MP_QSTR_USBD_NCM, + MP_TYPE_FLAG_NONE, + make_new, ncm_make_new, + locals_dict, &ncm_locals_dict + ); + +#endif diff --git a/extmod/network_usbd_ncm.h b/extmod/network_usbd_ncm.h new file mode 100644 index 00000000000..0675ca294c2 --- /dev/null +++ b/extmod/network_usbd_ncm.h @@ -0,0 +1,40 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2026 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_EXTMOD_NETWORK_USBD_NCM_H +#define MICROPY_INCLUDED_EXTMOD_NETWORK_USBD_NCM_H + +// Start dhcp server on this interface by default as this allows the host computer +// to be automatically / quickly allocated a suitable ip address to be able to +// communicate over the usb network link. +#ifndef MICROPY_PY_NETWORK_USBD_NCM_DHCP_SERVER +#define MICROPY_PY_NETWORK_USBD_NCM_DHCP_SERVER (1) +#endif + +// Initialise the NCM netif early (before USB enumeration). +void ncm_auto_init(void); + +#endif // MICROPY_INCLUDED_EXTMOD_NETWORK_USBD_NCM_H From 0fd6c573ea815774668bbb16b8e197c8822368b2 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 24 Aug 2026 23:44:05 +1000 Subject: [PATCH 617/635] all: Bump version to 1.29.0. Signed-off-by: Damien George --- py/mpconfig.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py/mpconfig.h b/py/mpconfig.h index c146b76d0e9..c7c1efe40c0 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -41,7 +41,7 @@ #define MICROPY_VERSION_MAJOR 1 #define MICROPY_VERSION_MINOR 29 #define MICROPY_VERSION_MICRO 0 -#define MICROPY_VERSION_PRERELEASE 1 +#define MICROPY_VERSION_PRERELEASE 0 // Combined version as a 32-bit number for convenience to allow version // comparison. Doesn't include prerelease state. From 34f8568cdbb8b270c099bc3449d01ae9ae1433a0 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 25 Aug 2026 12:08:28 +1000 Subject: [PATCH 618/635] all: Bump version to 1.30.0-preview. Signed-off-by: Damien George --- py/mpconfig.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/py/mpconfig.h b/py/mpconfig.h index c7c1efe40c0..1edc0804eff 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -39,9 +39,9 @@ // as well as a fallback to generate MICROPY_GIT_TAG if the git repo or tags // are unavailable. #define MICROPY_VERSION_MAJOR 1 -#define MICROPY_VERSION_MINOR 29 +#define MICROPY_VERSION_MINOR 30 #define MICROPY_VERSION_MICRO 0 -#define MICROPY_VERSION_PRERELEASE 0 +#define MICROPY_VERSION_PRERELEASE 1 // Combined version as a 32-bit number for convenience to allow version // comparison. Doesn't include prerelease state. From 0c9b385d23dcbcd7a59a2e5500a255f6fd80434d Mon Sep 17 00:00:00 2001 From: Carlosgg Date: Sat, 6 Jan 2024 23:20:04 +0000 Subject: [PATCH 619/635] esp32/main: Execute _boot.py via MICROPY_BOARD_FROZEN_BOOT_FILE. This adds the option to execute custom frozen boot module by defining the macro `MICROPY_BOARD_FROZEN_BOOT_FILE`, which defaults to `_boot.py`. This feature is already available in stm32 and renesas-ra ports. Signed-off-by: Carlosgg Signed-off-by: Damien George --- ports/esp32/main.c | 7 +++++-- ports/esp32/mpconfigport.h | 4 ++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/ports/esp32/main.c b/ports/esp32/main.c index 697f4efde63..510ad6b7aaa 100644 --- a/ports/esp32/main.c +++ b/ports/esp32/main.c @@ -150,8 +150,11 @@ void mp_task(void *pvParameter) { machine_i2s_init0(); #endif - // run boot-up scripts - pyexec_frozen_module("_boot.py", false); + // Run optional frozen boot code. + #ifdef MICROPY_BOARD_FROZEN_BOOT_FILE + pyexec_frozen_module(MICROPY_BOARD_FROZEN_BOOT_FILE, false); + #endif + int ret = pyexec_file_if_exists("boot.py"); #if MICROPY_HW_ENABLE_USBDEV diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index 45d789f469b..8a38c5f48a2 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -425,6 +425,10 @@ typedef long mp_off_t; #define MICROPY_BOARD_STARTUP boardctrl_startup #endif +#ifndef MICROPY_BOARD_FROZEN_BOOT_FILE +#define MICROPY_BOARD_FROZEN_BOOT_FILE "_boot.py" +#endif + void boardctrl_startup(void); #ifndef MICROPY_PY_NETWORK_LAN From b9ebb3e58a383c2bf8df608a0fef3caf590f36e6 Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Fri, 14 Aug 2026 05:51:15 +0200 Subject: [PATCH 620/635] esp32/machine_sdcard: Move SDMMC default slot/width defines to header. Move MICROPY_HW_SDMMC_DEFAULT_SLOT and MICROPY_HW_SDMMC_DEFAULT_WIDTH out of mpconfigport.h and into machine_sdcard.h, next to the SD card SPI pin defaults. These defines are only used by machine_sdcard.c, so they belong with the rest of the SD card configuration. The defaults are now the conservative slot 1, 1-bit values, leaving per-board wiring to each board to override. Signed-off-by: Pavel Revak --- ports/esp32/machine_sdcard.h | 11 +++++++++++ ports/esp32/mpconfigport.h | 14 -------------- 2 files changed, 11 insertions(+), 14 deletions(-) diff --git a/ports/esp32/machine_sdcard.h b/ports/esp32/machine_sdcard.h index f54263b7750..9cdf7a03875 100644 --- a/ports/esp32/machine_sdcard.h +++ b/ports/esp32/machine_sdcard.h @@ -26,6 +26,17 @@ #ifndef MICROPY_INCLUDED_ESP32_MACHINE_SDCARD_H #define MICROPY_INCLUDED_ESP32_MACHINE_SDCARD_H +// Default slot and bus width for a native SD/MMC machine.SDCard(). These are +// conservative defaults (the historically usable slot 1, 1-bit); which slot is +// wired and how many data lines are routed is board specific, so a board should +// override these in its mpconfigboard.h to match its layout. +#ifndef MICROPY_HW_SDMMC_DEFAULT_SLOT +#define MICROPY_HW_SDMMC_DEFAULT_SLOT (1) +#endif +#ifndef MICROPY_HW_SDMMC_DEFAULT_WIDTH +#define MICROPY_HW_SDMMC_DEFAULT_WIDTH (1) +#endif + // Default pins for the primary SPI-mode SD card bus (slot 2). SPI mode is // available on every ESP32 variant, so a board may override these in its // mpconfigboard.h to make machine.SDCard(slot=2) work without explicit pins. diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h index 8a38c5f48a2..16e0bab0e1c 100644 --- a/ports/esp32/mpconfigport.h +++ b/ports/esp32/mpconfigport.h @@ -224,20 +224,6 @@ #ifndef MICROPY_HW_ENABLE_SDCARD #define MICROPY_HW_ENABLE_SDCARD (1) #endif -#ifndef MICROPY_HW_SDMMC_DEFAULT_SLOT -#if CONFIG_IDF_TARGET_ESP32P4 -#define MICROPY_HW_SDMMC_DEFAULT_SLOT (0) -#else -#define MICROPY_HW_SDMMC_DEFAULT_SLOT (1) -#endif -#endif -#ifndef MICROPY_HW_SDMMC_DEFAULT_WIDTH -#if CONFIG_IDF_TARGET_ESP32P4 -#define MICROPY_HW_SDMMC_DEFAULT_WIDTH (4) -#else -#define MICROPY_HW_SDMMC_DEFAULT_WIDTH (1) -#endif -#endif #define MICROPY_HW_SOFTSPI_MIN_DELAY (0) #define MICROPY_HW_SOFTSPI_MAX_BAUDRATE (esp_rom_get_cpu_ticks_per_us() * 1000000 / 200) // roughly #define MICROPY_PY_SSL (MICROPY_PY_NETWORK) From 4eb7e13b6c25971855c378adfe1e9c46cb3db2eb Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Fri, 14 Aug 2026 06:39:59 +0200 Subject: [PATCH 621/635] esp32/boards/ESP32_GENERIC_P4: Set default SDMMC slot and bus width. The ESP32-P4 has two equally capable SDMMC slots, so which slot is used and how many data lines are wired is a board property rather than a SoC one. This board connects the SD/MMC card to slot 0 with a full 4-bit bus, so set the default slot to 0 and the default bus width to 4. Signed-off-by: Pavel Revak --- ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h index 05805a5fbdd..60de3ccfdf8 100644 --- a/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h +++ b/ports/esp32/boards/ESP32_GENERIC_P4/mpconfigboard.h @@ -13,6 +13,9 @@ #define MICROPY_PY_MACHINE_SDCARD (1) #define MICROPY_HW_SDMMC_LDO_CHAN_ID (4) +// This board wires the SD/MMC card to SDMMC slot 0 with a full 4-bit bus. +#define MICROPY_HW_SDMMC_DEFAULT_SLOT (0) +#define MICROPY_HW_SDMMC_DEFAULT_WIDTH (4) #ifndef USB_SERIAL_JTAG_PACKET_SZ_BYTES #define USB_SERIAL_JTAG_PACKET_SZ_BYTES (64) From 8cf130db342eb5dafd43ad45a9b4f597512e82c0 Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Fri, 14 Aug 2026 05:33:48 +0200 Subject: [PATCH 622/635] esp32/modmachine: Use popcount to count wake pins. This commit introduces a minor optimisation when computing how much space to allocate to hold all the indices of the pins that triggered a wake event. Rather than looping through 64 bits to figure out how many bits are set (and therefore if there's anything to be done), do one popcount each on the two 32-bits halves of the source value and sum the results up. Saves 32 bytes on Xtensa and 16 bytes on RV32, not to mention being probably faster due to the fewer instructions being executed to compute the final value. Signed-off-by: Alessandro Gatti --- ports/esp32/modmachine.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/ports/esp32/modmachine.c b/ports/esp32/modmachine.c index 5fb9bf8f518..4da59a11f00 100644 --- a/ports/esp32/modmachine.c +++ b/ports/esp32/modmachine.c @@ -326,9 +326,7 @@ static mp_obj_t machine_wake_pins(void) { // Only a few (~8) pins might cause wakeup. // Therefore, we calculate the required space in a first pass. - for (index = 0, len = 0; index < 64; index++) { - len += (status & (1ULL << index)) ? 1 : 0; - } + len = mp_popcount(status >> 32) + mp_popcount(status & 0xFFFFFFFF); if (len) { mp_obj_tuple_t *tuple = MP_OBJ_TO_PTR(mp_obj_new_tuple(len, NULL)); From 3bd102dc2c001060d250366f1ce65564ddff09f6 Mon Sep 17 00:00:00 2001 From: Pavel Revak Date: Wed, 29 Jul 2026 11:40:02 +0200 Subject: [PATCH 623/635] esp32: Make ESP-IDF v5.5.5 the recommended version. Update the recommended (and CI newest) ESP-IDF version from v5.5.2 to v5.5.5, and bump the ESP-IDF version recorded in the component lockfiles accordingly. v5.5.5 supersedes the reasons the port was pinned to v5.5.2: the NimBLE host connection loss that broke v5.5.3 (espressif/esp-idf#18323) was fixed in v5.5.4, and the v5.5.4 stability report that motivated staying on v5.5.2 turned out to be a board-config issue rather than an IDF regression. The newer IDF also brings fixes relevant to SPIRAM boards: SD card reads and writes of PSRAM buffers now use multi-block DMA transfers via an internal bounce buffer (fixing very slow single-block SD writes), and the ESP32-S3 UART2 clock/reset register check is corrected upstream. Signed-off-by: Pavel Revak --- .github/workflows/ports_esp32.yml | 2 +- ports/esp32/README.md | 4 ++-- ports/esp32/lockfiles/dependencies.lock.esp32 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32c2 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32c3 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32c5 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32c6 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32h2 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32p4 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32s2 | 2 +- ports/esp32/lockfiles/dependencies.lock.esp32s3 | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) diff --git a/.github/workflows/ports_esp32.yml b/.github/workflows/ports_esp32.yml index 0df5d7584b8..e1b57a24b7b 100644 --- a/.github/workflows/ports_esp32.yml +++ b/.github/workflows/ports_esp32.yml @@ -20,7 +20,7 @@ concurrency: env: # Oldest and newest supported ESP-IDF versions, should match ports/esp32/README.md IDF_OLDEST_VER: &oldest "v5.3" - IDF_NEWEST_VER: &newest "v5.5.2" + IDF_NEWEST_VER: &newest "v5.5.5" jobs: build_idf: diff --git a/ports/esp32/README.md b/ports/esp32/README.md index 54dd192e9e8..dfa9cbeb4bd 100644 --- a/ports/esp32/README.md +++ b/ports/esp32/README.md @@ -52,8 +52,8 @@ manage the ESP32 microcontroller, as well as a way to manage the required build environment and toolchains needed to build the firmware. The ESP-IDF changes quickly and MicroPython only supports certain versions. The -current recommended version of ESP-IDF for MicroPython is v5.5.2. MicroPython -also supports v5.3, v5.4, v5.4.1, v5.4.2, v5.5.1 and v5.5.4. +current recommended version of ESP-IDF for MicroPython is v5.5.5. MicroPython +also supports v5.3, v5.4, v5.4.1, v5.4.2, v5.5.1, v5.5.2 and v5.5.4.

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zgZ9tf_yhkhfwAR_Az6lphj(^te0&~kZSA%3BFr!SSVZHLkf>WmEK%8J>H8r=fmslr1;TQIHZpN%kvE2jgXazZ-D z#;}r+&d;~o_4E1d%hVNFIsJduJeA+}&xRRk-rio%&euE7W@_*T7k&>)wk${h9wC~P zdg;l@)8RD&^7AhMd)ym=4U?Vj76WA;RuGjl=?U)}>N+GEX+ zAM1v#UKhI`eb}3UVL8`qU+MNzp37gQLSkdr_S)Lk-7@20&~pSkW-{;^E30QClk`3~0(5^>7oe=50T13NnzHxTcxWefcT!SelF{r5}E+I1N$EU literal 0 HcmV?d00001 diff --git a/docs/psoc-edge/installation.rst b/docs/psoc-edge/installation.rst new file mode 100644 index 00000000000..dd680e1543d --- /dev/null +++ b/docs/psoc-edge/installation.rst @@ -0,0 +1,62 @@ +.. _pse_mpy_install: + +Installing MicroPython +====================== + +To facilitate the installation of the MicroPython PSOC™ Edge port, the ``mp-ifx-flash.py`` Python script is +provided. It is compatible with Windows, Linux, and macOS. + +Prerequisites +------------- + +Before downloading and running the script, it is recommended to create a new folder to keep all the +related files together. For example: + +.. code-block:: bash + + $ mkdir mp-install + $ cd mp-install + +You can easily download the script from the terminal using the following command: + +.. code-block:: bash + + $ curl -s -L https://raw.githubusercontent.com/micropython/micropython/master/ports/psoc-edge/tools/mp-ifx-flash.py > mp-ifx-flash.py + +Ensure you have a recent version of `Python 3.x `_ and the +`pip `_ package installed. Then install the following packages: + +.. code-block:: bash + + $ pip install requests + +Getting the firmware +^^^^^^^^^^^^^^^^^^^^ + +Download the desired MicroPython firmware version for the PSOC™ Edge board from the `MicroPython download page `_. +The downloaded file is a ``.zip`` package containing the firmware binary and the necessary files for flashing. + +Flashing +-------- + +To flash the firmware, use the ``from-package`` command. +Specify the board using the ``--board`` flag and the path to the +downloaded ``.zip`` package using the ``--zip-package`` flag, as shown below: + +.. code-block:: bash + + $ python mp-ifx-flash.py from-package --board KIT_PSE84_AI --zip-package pathtodir/psoc-edge-package.zip + +Multiple connected devices +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +If you have multiple PSOC™ Edge boards connected to your computer, you can identify them by their +serial number and flash each one individually. To do so, use the ``-n`` flag to provide the serial number of +the target board as shown below: + +.. code-block:: bash + + $ python mp-ifx-flash.py from-package --board KIT_PSE84_AI --zip-package pathtodir/psoc-edge-package.zip -n 181F0D5A01212300 + + + diff --git a/docs/psoc-edge/links.rst b/docs/psoc-edge/links.rst new file mode 100644 index 00000000000..eccc46bb9d7 --- /dev/null +++ b/docs/psoc-edge/links.rst @@ -0,0 +1,6 @@ +.. _links.rst: + +.. _pse84_kit_ai_product_page: https://www.infineon.com/evaluation-board/KIT-PSE84-AI +.. _pse84_kit_ai_guide: https://www.infineon.com/assets/row/public/documents/30/44/infineon-kit-pse84-ai-user-guide-usermanual-en.pdf +.. _pse8x_consumer_datasheet: https://www.infineon.com/assets/row/public/documents/30/49/infineon-psoc-edge-e8x-consumer-datasheet-datasheet-en.pdf +.. _pse8x_arch_ref_manual: https://www.infineon.com/assets/row/public/documents/30/57/infineon-psoc-edge-e8x-architecture-reference-manual-additionaltechnicalinformation-en.pdf \ No newline at end of file diff --git a/docs/psoc-edge/quickref.rst b/docs/psoc-edge/quickref.rst new file mode 100644 index 00000000000..d592a7c7a07 --- /dev/null +++ b/docs/psoc-edge/quickref.rst @@ -0,0 +1,252 @@ +.. _psoc_edge_quickref: + +.. include:: links.rst + +Quick reference for the PSOC™ Edge +=================================== + +.. image:: img/kit-pse84-ai.png + :alt: KIT_PSE84_AI board + :width: 540px + +The `PSOC™ Edge E84 AI Kit `_. + +Below is a quick reference for PSOC™ Edge E84 boards. If it is your first time +working with this port it may be useful to get an overview of the microcontroller: + +.. toctree:: + :maxdepth: 1 + :includehidden: + + general.rst + installation.rst + +Pins and GPIO +------------- + +See :ref:`machine.Pin ` for the complete Pin API reference. +This section focuses on the specific PSOC™ Edge port variations and particularities. + +The constructor +^^^^^^^^^^^^^^^ + +The controller pin naming follows the nomenclature ``P_``, where: + + - ```` is a numeric identifier for the port (e.g., 0-21 for the PSOC™ Edge E84) + - ```` is the pin number within that port. + +Use the respective board pinout diagram to find the available pins and their locations. + +This is the ``id`` that needs to be passed to the constructor in one of the following formats: + + - As a **string label**, single or double quoted: ``'P_'`` or ``"P_"`` + - A **pre-instantiated object** ``Pin.cpu.`` or ``Pin.board.``. + +:: + + from machine import Pin + + p_in = Pin('P0_0', Pin.IN) + p_out = Pin("P7_0", Pin.OUT, value=False) + + p = Pin(Pin.cpu.P17_1, Pin.OPEN_DRAIN) + + +The pre-instantiated object can be used directly without calling the constructor. +Instead, you can use ``init()`` to configure it. + +:: + + from machine import Pin + + pin = Pin.cpu.P17_0 + pin.init(mode=Pin.IN) + + +.. tip:: + Use the REPL interface to discover the available user pins, using tab for completion: + + >>> from machine import Pin + >>> Pin.cpu.P + P10_5 P10_7 P11_3 P12_3 + P13_0 P13_1 P13_2 P13_3 + P13_4 P13_5 P13_6 P13_7 + P14_0 P14_1 P14_2 P14_3 + P14_4 P14_5 P14_6 P14_7 + P15_0 P15_1 P15_2 P15_3 + P15_4 P15_5 P15_6 P15_7 + P16_0 P16_1 P16_2 P16_3 + P16_4 P16_5 P16_6 P16_7 + P17_0 P17_1 P17_2 P17_3 + P17_4 P17_5 P17_7 P20_3 + P20_4 P20_5 P20_6 P20_7 + P21_1 P21_2 P21_3 P21_4 + P21_5 P21_6 P21_7 P3_0 + P3_1 P6_4 P6_6 P7_0 + P7_7 P8_0 P8_1 P8_5 + P8_6 P9_0 P9_1 P9_2 + P9_3 + + >>> from machine import Pin + >>> Pin.board. + AMIC1_CTB_INN AMIC1_CTB_INP AMIC1_CTB_OUT AMIC1_CTB_REF + AMIC2_CTB_INN AMIC2_CTB_INP AMIC2_CTB_OUT AMIC2_CTB_REF + I2C_SCL_1V8 I2C_SCL_3V3 I2C_SDA_1V8 I2C_SDA_3V3 + I2S_TX_FYSYNC I2S_TX_MCK I2S_TX_SCK I2S_TX_SD + I3C_SCL I3C_SDA IMU0_INT IMU1_INT + MAG_INT PDM_CLK PDM_DATA PRESS_SENS_INT + RADAR_INT RADAR_RESET RADAR_SPI_CLK RADAR_SPI_CS + RADAR_SPI_MISO RADAR_SPI_MOSI SERIAL_INT0 SERIAL_INT1 + SERIAL_INT2 SERIAL_INT3 USER_BUTTON USER_LED1 + USER_LED2 USER_LED_B USER_LED_G USER_LED_R + + + + + +The ``drive`` parameter accepts up to 8 levels, which set the following drive strength for the pin: + + - ``DRIVE_0``: 1mA/2mA drive current (normal/high speed IO) + - ``DRIVE_1``: 2mA/4mA drive current (normal/high speed IO) + - ``DRIVE_2``: 3mA/6mA drive current (normal/high speed IO) + - ``DRIVE_3``: 4mA/8mA drive current (normal/high speed IO) + - ``DRIVE_4``: 5mA/10mA drive current (normal/high speed IO) + - ``DRIVE_5``: 6mA/12mA drive current (normal/high speed IO) + - ``DRIVE_6``: 7mA/14mA drive current (normal/high speed IO) + - ``DRIVE_7``: 8mA/16mA drive current (normal/high speed IO) + +For more information about drive strength, check the PSOC™ Edge `Datasheet `_ and `Architecture Reference Manual `_. + +.. note:: + + The following constructor arguments and/or configuration values are NOT supported in this port: + + - ``alt``: Alternate functionality is not supported. + - ``mode``: ``Pin.ALT``, ``Pin.ALT_OPEN_DRAIN``, and ``Pin.ANALOG`` modes are not supported. + + The following ``mode``- ``pull`` combinations are not supported in this port: + + - ``Pin.OUT`` with ``Pin.PULL_UP`` or ``Pin.PULL_DOWN`` + - ``Pin.OPEN_DRAIN`` with ``Pin.PULL_DOWN`` + + +Methods +^^^^^^^ + +.. method:: Pin.irq(handler=None, trigger=(Pin.IRQ_FALLING | Pin.IRQ_RISING), priority=7) + +The following parameters have port-specific behavior: + + - ``priority``: Priority values range from 7 (lowest) to 0 (highest). Default is 7. + + .. note:: + + All pins on the same port share the same interrupt line. Therefore, only one priority can be set for all pins on the same port. + If multiple pins configure interrupts for the same port, the highest priority will be used. + If only one pin is configured for an interrupt, its priority can be reconfigured to any value. + +.. note:: + + The following ``irq()`` features are not supported in this port: + + - ``trigger``: The ``Pin.IRQ_LOW_LEVEL`` and ``Pin.IRQ_HIGH_LEVEL`` triggers are not supported. + - ``wake``: The wake parameter is currently not supported. + - ``hard``: This parameter is ignored. It can be passed but currently has no effect. + +.. note:: + + **None** of the non-core methods from the Pin API are currently implemented for this port. + + +Real time clock (RTC) +--------------------- + +See :ref:`machine.RTC `: :: + + from machine import RTC + import time + + irq_counter = 0 + + def cback(event): + global irq_counter + irq_counter += 1 + + rtc = RTC() + rtc.init((2023, 1, 1, 0, 0, 0, 0, 0)) # initialise rtc with specific date and time, + # eg. 2023/1/1 00:00:00 + rtc.datetime((2017, 8, 23, 2, 12, 48, 0, 0)) # set a specific date and + # time, eg. 2017/8/23 1:12:48 + rtc.datetime() # get date and time + + rtc.irq(trigger=RTC.ALARM0, handler=cback) + rtc.alarm(1000, repeat=False) # set one-shot short alarm in ms + rtc.alarm_left() # Read the time left for the alarm to expire + time.sleep_ms(1008) # wait sufficient time + print(irq_counter) # Check irq counter + + rtc.irq(trigger=RTC.ALARM0, handler=cback) + rtc.alarm(3000, repeat=True) # set periodic short alarm in ms + rtc.cancel() # cancel the alarm + + rtc.irq(trigger=RTC.ALARM0, handler=cback) + rtc.alarm((2023, 1, 1, 0, 0, 1, 0, 0), repeat=False) # set one-shot longer duration alarm + + rtc.memory(b"hello") # write bytes into RTC user memory + rtc.memory() # read bytes from RTC user memory + + +.. note:: + Setting a random week day in 'wday' field is not valid. The underlying library implements the logic to always + calculate the right weekday based on the year, date and month passed. However, datetime() will not raise an error + for this but rather re-write the field with the last calculated actual value. + +.. note:: + RTC API behavior on this port has the following specifics: + + - ``RTC()`` is a singleton constructor with no ``id`` or additional constructor arguments. + - ``rtc.irq()`` accepts alarm trigger ``0`` (``RTC.ALARM0``); ``wake`` is not implemented. + - ``rtc.alarm()`` accepts ``time`` and optional ``repeat``; no positional alarm ``id`` argument is used. + - Input ``weekday`` in datetime tuples is ignored and hardware computes the weekday from date fields. + - The current ``rtc.memory([data])`` maximum payload on KIT_PSE84_AI is 28 bytes. + +.. warning:: + RTC alarm timing on this port has second-level resolution. Millisecond alarm values are accepted, but are rounded + up to whole seconds internally. + +UART +---- + +See :ref:`machine.UART `. + +The following specialization applies to this port: + +Constructor +^^^^^^^^^^^^ + +.. class:: UART(id) + + The following parameters are supported with limited configuration: + + - ``bits``. Only 8 bits. + + These are planned for future implementation, but yet unavailable: + + - ``rts`` + - ``cts`` + - ``flow`` + +.. Note:: + + These parameters are not implemented: + + - ``txbuf`` + - ``invert`` + + +Methods +^^^^^^^ + +.. method:: UART.init(baudrate=9600, bits=8, parity=None, stop=1, *, ...) + + The same parameters as the constructor are supported, with the same limitations. \ No newline at end of file diff --git a/docs/templates/topindex.html b/docs/templates/topindex.html index e3bcd7cce14..344b971ea79 100644 --- a/docs/templates/topindex.html +++ b/docs/templates/topindex.html @@ -57,6 +57,10 @@